WO2023246909A1 - 布线基板及其制备方法、发光面板、显示装置 - Google Patents

布线基板及其制备方法、发光面板、显示装置 Download PDF

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Publication number
WO2023246909A1
WO2023246909A1 PCT/CN2023/101867 CN2023101867W WO2023246909A1 WO 2023246909 A1 WO2023246909 A1 WO 2023246909A1 CN 2023101867 W CN2023101867 W CN 2023101867W WO 2023246909 A1 WO2023246909 A1 WO 2023246909A1
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WO
WIPO (PCT)
Prior art keywords
substrate
opening
layer
metal
photoresist
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Application number
PCT/CN2023/101867
Other languages
English (en)
French (fr)
Inventor
胡海峰
Original Assignee
京东方科技集团股份有限公司
合肥京东方瑞晟科技有限公司
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Publication of WO2023246909A1 publication Critical patent/WO2023246909A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a wiring substrate and a preparation method thereof, a light-emitting panel, and a display device.
  • LED Light-Emitting Diode, light-emitting diode
  • the LED backlight may include a wiring substrate and LEDs, and the LEDs are connected to the wiring substrate.
  • Embodiments of the present disclosure provide a wiring substrate and a preparation method thereof, a light-emitting panel, and a display device.
  • the embodiment of the present disclosure provides a wiring substrate, including:
  • the insulating layer is located on the same side of the substrate as the plurality of metal traces.
  • the insulating layer is located in the area outside the metal traces and part of the surface of the metal traces.
  • the surface of the insulating layer away from the substrate is in contact with the substrate. The distance between the bottoms is greater than the distance between the surface of the metal trace away from the substrate and the substrate.
  • the surface of the insulating layer away from the substrate can reflect light.
  • the insulating layer has a first opening. Expose part of the surface of the metal trace.
  • the insulating layer is made of white ink, and the insulating layer covers the metal traces outside the first opening.
  • the insulating layer includes a photoresist layer and a reflective layer, the photoresist layer is located in an area outside the metal traces, the first opening includes a first sub-opening, and the first sub-opening Penetrating the photoresist layer; the reflective layer is at least located on the surface of the photoresist layer away from the substrate.
  • the reflective layer covers the photoresist layer and the metal traces
  • the first opening includes a second sub-opening
  • the second sub-opening penetrates the reflective layer
  • the second sub-opening is on the substrate There is an overlapping area between the orthographic projection on the substrate and the orthographic projection of the first sub-opening on the substrate.
  • the reflective layer is made of white ink.
  • the metal traces include a stacked body metal layer and an alloy layer, and the alloy layer is located on a surface of the body metal layer away from the substrate.
  • the thickness of the metal trace ranges from 5 ⁇ m to 8.5 ⁇ m.
  • the wiring substrate also includes an oxidation protection layer.
  • the oxidation protection layer is located in the exposed area of the metal traces.
  • the oxidation protection layer is in direct contact with the metal traces.
  • the material of the oxidation protection layer includes nickel and gold.
  • the thickness of the oxidation protection layer ranges from 4 ⁇ m ⁇ 5 ⁇ m.
  • the wiring substrate further includes an inorganic protective layer.
  • the inorganic protective layer covers the metal traces and the exposed surface of the substrate.
  • the insulating layer is located on a side of the inorganic protective layer facing away from the substrate.
  • the inorganic protective layer is provided with a second opening. hole, there is an overlapping area between the orthographic projection of the second opening on the substrate and the orthographic projection of the first opening on the substrate.
  • the material of the inorganic protective layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
  • the plurality of metal traces include: power signal lines, address signal lines, common voltage signal lines, cascade lines and feedback signal lines.
  • the plurality of metal lines form a plurality of first pad groups and a plurality of second pad groups through the exposed surface of the first opening, and the first pad group is used to couple with the micro driver chip, so The second pad group is used for coupling with the light emitting element.
  • Each of the first pad groups includes a power supply pad, an output pad, an address pad and a ground pad.
  • the power supply pad is connected to the power signal line, and the ground pad is connected to the common voltage signal. Line connection, the output pad is connected to at least one pad in the second pad group.
  • the plurality of first pad groups are cascaded.
  • the address pad of the first first pad group is connected to the address signal line, and the last first pad group is connected to the address signal line.
  • the output pad is connected to the feedback signal line, and the output pad of the n-th level first pad group is connected to the address pad of the (n+1)-th level first pad group through one of the cascade lines. , where n is a positive integer.
  • the embodiment of the present disclosure provides a method for preparing a wiring substrate, including:
  • An insulating layer is formed on the side of the substrate where the metal traces are formed.
  • the insulating layer is located in the area outside the metal traces and part of the surface of the metal traces.
  • the surface of the insulating layer away from the substrate is between between The distance is greater than the distance between the surface of the metal trace away from the substrate and the substrate.
  • the surface of the insulating layer away from the substrate can reflect light.
  • the insulating layer has a first opening, and the first opening exposes the metal trace. part of the surface.
  • forming multiple metal traces on one side of the substrate includes:
  • a first photoresist is coated on the side of the metal film facing away from the substrate, and a first mask is used to expose and develop the first photoresist to form a plurality of first photoresists arranged at intervals. colloid;
  • the metal film outside the first photoresist is etched, and the first photoresist is peeled off to obtain the plurality of metal traces.
  • forming a body metal film with a preset thickness on one side of the substrate includes:
  • the main metal film includes a stacked first metal film. metal film and a second metal film.
  • the insulating layer is white ink, and the insulating layer is formed on the side of the substrate facing the metal traces, including:
  • An inorganic protective layer is deposited on the side of the substrate facing the metal traces, and the inorganic protective layer covers the metal traces and substrate;
  • white ink is formed on the side of the inorganic protective layer facing away from the substrate, and the white ink is provided with a first opening;
  • a screen printing wet engraving process is used to form a second opening in the inorganic protective layer.
  • the insulating layer includes a photoresist layer and a reflective layer
  • the first opening includes a first sub-opening and a second sub-opening, and is formed on a side of the substrate facing the metal traces.
  • Insulation layers including:
  • a reflective layer is formed on the side of the photoresist layer away from the substrate.
  • the reflective layer is provided with a second sub-opening.
  • the orthographic projection of the second sub-opening on the substrate is the same as the first sub-opening.
  • the orthographic projection of the second sub-opening on the substrate is located at the position of the first sub-opening on the substrate. In orthographic projection.
  • the insulating layer includes a photoresist layer and a reflective layer
  • the first opening includes a first sub-opening and a second sub-opening, and is formed on a side of the substrate facing the metal wiring.
  • Insulation layers including:
  • An inorganic protective layer is deposited on the side of the substrate facing the metal traces, and the inorganic protective layer covers the metal traces and substrate;
  • Coat a second photoresist on the side of the substrate facing the inorganic protective layer use the first mask to form a photoresist pattern area and a hollow area, and the second photoresist in the photoresist pattern area constitutes the photoresist layer , the hollow area constitutes the first sub-opening, one of the second photoresist and the first photoresist is a positive photoresist, and the other is a negative photoresist;
  • a reflective layer is formed on the side of the photoresist layer away from the substrate, and the reflective layer is provided with a second sub-opening.
  • the preparation method of the wiring substrate also includes: performing an electroless nickel gold process on the exposed surface of the metal trace.
  • the embodiments of the present disclosure provide a light-emitting panel, including the wiring substrate in any embodiment of the present disclosure and a plurality of light-emitting diode chips.
  • the plurality of light-emitting diode chips are connected to metal wires correspondingly. .
  • the embodiments of the disclosure provide a display device, including the light-emitting panel in any embodiment of the disclosure.
  • Figure 1 is a schematic cross-sectional structural diagram of a wiring substrate provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional structural diagram of another wiring substrate provided by an embodiment of the present disclosure.
  • Figure 3 is a schematic cross-sectional structural diagram of another wiring substrate provided by an embodiment of the present disclosure.
  • Figure 4 is a partial structural schematic diagram of a wiring substrate provided by an embodiment of the present disclosure.
  • Figure 5 is an enlarged schematic diagram of part M in Figure 4.
  • Figure 6 is a schematic diagram of a metal film formed on a wiring substrate according to an embodiment of the present disclosure.
  • Figure 7 is a schematic diagram after forming the first photoresist in the wiring substrate according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram after metal traces are formed in the wiring substrate according to an embodiment of the present disclosure.
  • Figure 9 is a schematic diagram after forming an inorganic protective layer on a wiring substrate according to an embodiment of the present disclosure.
  • Figure 10 is a schematic diagram after white ink is formed on the wiring substrate according to an embodiment of the present disclosure.
  • Figure 11 is a schematic diagram after forming second openings and white ink in the wiring substrate according to an embodiment of the present disclosure
  • Figure 12 is a schematic diagram of the wiring substrate after forming the second opening in the inorganic protective layer according to another embodiment of the present disclosure
  • Figure 13 is a schematic diagram after forming a photoresist layer in the wiring substrate according to an embodiment of the present disclosure
  • Figure 14 is a schematic diagram after forming a reflective layer in the wiring substrate according to an embodiment of the present disclosure.
  • Figure 15 is a schematic diagram after forming a photoresist layer in an embodiment of the present disclosure.
  • Figure 16 is a schematic diagram after forming second openings in the inorganic protective layer in the wiring substrate according to an embodiment of the present disclosure
  • Figure 17 is a schematic diagram after forming the reflective layer and the second opening in an embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram after forming a reflective layer in another embodiment of the present disclosure.
  • FIG. 1 is a schematic cross-sectional structural diagram of a wiring substrate provided by an embodiment of the present disclosure.
  • the wiring substrate includes a substrate 11 , a plurality of metal traces 12 and an insulating layer 15 .
  • a plurality of metal traces 12 are located on one side of the substrate 11 .
  • the insulating layer 15 is located on the side of the substrate 11 facing the metal traces 12 , that is, the insulating layer 15 and the metal traces 12 are located on the same side of the substrate 11 .
  • the insulating layer 15 is located at least in the area outside the metal traces 12 .
  • the insulating layer 15 is located in the area outside the metal trace 12 and on part of the surface of the metal trace 12 .
  • the distance between the surface of the insulating layer 15 away from the substrate 11 and the substrate 11 is greater than the distance between the surface of the metal trace 12 away from the substrate 11 and the substrate 11 .
  • the surface of the insulating layer 15 away from the substrate 11 can reflect Shoot light.
  • a first opening 150 is provided in the insulating layer 15 , and the first opening 150 exposes part of the surface of the metal trace 12 .
  • the exposed surfaces of metal traces 12 may be used to connect to electronic components.
  • the electronic components may include at least one of a light-emitting diode chip, a micro driver chip, a sensor chip, and the like.
  • the light-emitting diode chip may be a sub-millimeter light-emitting diode (Mini Light Emitting Diode, Mini LED for short) chip, or may be a Micro Light Emitting Diode (Micro LED for short) chip.
  • the metal trace 12 includes a stacked body metal layer 121 and an alloy layer 122 , and the alloy layer 122 is located on a surface of the body metal layer 121 away from the substrate 11 .
  • the alloy layer 122 is a corrosion-resistant alloy layer.
  • the alloy layer 122 can protect the main metal layer 121 and prevent the main metal layer 121 from being corroded by water and oxygen during the manufacturing process; the insulating layer 15 can protect the side walls of the metal traces 12 and prevent the metal traces from being corroded. 12 is corroded by water and oxygen during the manufacturing process.
  • the alloy layer 122 and the insulating layer 15 can be fully protected, preventing the metal wiring 12 from being oxidized and corroded during the manufacturing process, and improving product performance.
  • the surface of the insulating layer 15 can reflect light. When a light-emitting device is installed on the wiring substrate, the light emitted by the light-emitting device to the surface of the wiring substrate can be reflected by the insulating layer 15 to the light-emitting side, thereby improving the light efficiency.
  • the material of the substrate 11 may include glass or resin (or other base materials of PCB (Printed Circuit Board, printed circuit board)), etc.
  • the material of the main metal layer 121 includes but is not limited to copper. Copper metal has the characteristics of low resistivity and good conductivity.
  • the material of the alloy layer 122 may include nickel and copper.
  • the material of the alloy layer 122 may be a nickel-copper alloy, a nickel-vanadium alloy, a nickel-tungsten alloy, or a tungsten-nickel alloy.
  • the metal wiring 121 may also have a single-layer structure.
  • the metal wiring 121 may be a single-layer metal layer or alloy layer.
  • the wiring substrate may further include an inorganic protective layer 14 .
  • the inorganic protective layer 14 is located on a side of the metal trace 12 facing away from the substrate 11 .
  • the inorganic protective layer 14 covers the metal trace 12 and the exposed surface of the substrate 11 (ie, the surface not covered by the metal trace 12 ).
  • the insulating layer 15 is located on the side of the inorganic protective layer 14 facing away from the substrate 11 .
  • the inorganic protective layer 14 can further protect the metal wiring 12 from water and oxygen erosion, and prevent water and oxygen from intruding into the metal wiring 12 during the manufacturing process of the insulating layer 15 .
  • the inorganic protective layer 14 is provided with a second opening 140 , and the second opening 140 is on the substrate 11 There is an overlapping area between the orthographic projection on the substrate 11 and the orthographic projection of the first opening 150 on the substrate 11 .
  • the overlapping area of the second opening 140 and the first opening 150 may expose part of the surface of the metal trace 12 .
  • the material of the inorganic protective layer 14 may include any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).
  • the inorganic protective layer 14 may be a single layer, multiple layers or a composite layer.
  • the thickness of the inorganic protective layer 14 can be set as needed.
  • the thickness of the inorganic protective layer 14 is 8% to 12.5% of the thickness of the metal trace 12 .
  • the thickness of the inorganic protective layer 14 is no greater than 10% of the thickness of the metal trace 12 .
  • the material of the insulating layer 15 may be white ink, and the insulating layer 15 covers the metal traces 12 outside the first opening 150 .
  • the white ink can protect both the side walls and the upper surface of the metal trace 12 , further preventing water and oxygen from corroding the metal trace 12 .
  • the white ink also has a reflective function, which can reflect the light irradiating the surface of the white ink toward the light exit side.
  • FIG. 2 is a schematic cross-sectional structural diagram of another wiring substrate provided by an embodiment of the present disclosure.
  • the structure of the wiring substrate in Figure 2 is the same as that of the wiring substrate in Figure 1.
  • the insulating layer 15 includes a photoresist layer 151 and a reflective layer 152.
  • the photoresist layer 151 is located on the metal trace. Area outside line 12.
  • the first opening 150 includes a first sub-opening 151a, and the first sub-opening 151a penetrates the photoresist layer 151.
  • the first sub-opening 151a may expose the entire surface of the metal trace 12 away from the substrate 11.
  • the reflective layer 152 is at least disposed on a surface of the photoresist layer 151 away from the substrate 11 .
  • Such insulating layer 15 is a composite layer of photoresist layer 151 and reflective layer 152, which can play a dual protection role and further prevent water and oxygen from corroding metal traces 12.
  • the reflective layer 152 may cover the metal traces 12 and the photoresist layer 151 .
  • the first opening 150 includes a second sub-opening 152a, and the second sub-opening 152a penetrates the reflective layer 152.
  • the orthographic projection of the second sub-opening 152a on the substrate 11 is located within the orthographic projection of the first sub-opening 151a on the substrate 11. Therefore, part of the surface of the metal trace 12 is exposed through the second sub-opening 152a.
  • the reflective layer 152 is made of white ink.
  • FIG. 3 is a schematic cross-sectional structural diagram of yet another wiring substrate provided by an embodiment of the present disclosure.
  • the structure of the wiring substrate in FIG. 3 is the same as that of the wiring substrate in FIG. 2 , except that the wiring substrate in FIG. 3 also includes an inorganic protective layer 14 .
  • the inorganic protective layer 14 please refer to the relevant embodiment in FIG. 1, and the detailed description is omitted here.
  • the thickness of the metal trace 12 may range from 5 ⁇ m to 8.5 ⁇ m (endpoint values included).
  • the thickness of the metal trace 12 may be 5 ⁇ m, 5.5 ⁇ m, 6 ⁇ m, 6.5 ⁇ m, 7 ⁇ m, or 7.5 ⁇ m.
  • the thickness of the metal trace 12 is large enough to reduce the resistance of the metal trace 12 .
  • the wiring substrate may further include an oxidation protection layer 16 , the oxidation protection layer 16 is located in the exposed area of the metal trace 12 , and the oxidation protection layer 16 is in direct contact with the metal trace 12 .
  • oxidation protection layer 16 covers exposed areas of metal traces 12 . The oxidation protection layer 16 can prevent the exposed areas of the metal traces 12 from being oxidized.
  • the material of the oxidation protection layer 16 includes nickel and gold.
  • the thickness of the oxidation protection layer 16 ranges from 4 ⁇ m to 5 ⁇ m. It should be noted that through the die-bonding process, the light-emitting diode chip or the micro driver chip is connected to the metal wiring 12 through the oxidation protection layer 16 .
  • Such an oxidation protection layer 16 can not only better prevent the metal traces 12 from being oxidized and corroded, but also improve the die-solid yield.
  • the step difference d between the surface of the insulating layer 15 away from the substrate 11 and the surface of the metal trace 12 away from the substrate 11 is less than or equal to 10 ⁇ m. Such a setting is beneficial to the subsequent die-bonding or bonding process and improves the yield.
  • each area of the metal trace 12 covered by the oxidation protection layer 16 and the oxidation protection layer 16 above the corresponding area may constitute a bonding pad.
  • each pad can be electrically connected to a pin of the electronic component by soldering metal.
  • Welding metal may include tin, etc.
  • the electronic component may include at least one of a light-emitting diode chip, a micro driver chip, a sensor chip, and the like.
  • FIG. 4 is a partial structural schematic diagram of a wiring substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is an enlarged schematic diagram of part M in FIG. 4 .
  • the aforementioned Figures 1 to 3 are respectively schematic cross-sectional structural diagrams taken at A-A in Figure 4 .
  • the wiring substrate may include a first pad group 102 and a second pad group 104 .
  • the first pad group 102 is coupled to the micro driver chip.
  • the second pad group 104 is coupled to the LED chip.
  • each first pad group 102 may be coupled with one micro driver chip, and each second pad group 104 may be coupled with multiple LED chips.
  • the metal traces 12 include power signal lines 103 .
  • the first pad group 102 includes a power supply pad Pwr and an output pad Out.
  • the power signal line 103 is coupled to the power supply pad Pwr.
  • the second pad group 104 includes a plurality of sub-pad groups 104' electrically connected to each other, and each sub-pad group 104' includes at least a first sub-pad 41 and a second sub-pad 42. Each sub-pad group 104' is coupled to one LED chip.
  • the first sub-pad 41 of at least one sub-pad group 104' included in each second pad group 104 is coupled to the power signal line 103.
  • Each second pad group The second sub-pad 42 of at least one sub-pad group 104' included in 104 is coupled to an output pad Out in the first pad group 102.
  • the second pad group 104 includes four sub-pad groups 104 ′.
  • the first sub-pad 41 of the sub-pad group 104' in the lower left corner is coupled to the power signal line 103, and the second sub-pad 42 of the sub-pad group 104' in the lower right corner is connected to the output of the first pad group 102.
  • the second sub-pad 42 of the previous sub-pad group 104' is connected to the first sub-pad 41 of the next sub-pad group 104'.
  • Line 43 is connected.
  • the first pad group 102 and the second pad group 104 are connected to the same power supply signal line 103 .
  • the metal trace 12 may also include a first connection lead 106 .
  • a power signal line 103 includes multiple sub-segments 103 ′. Two adjacent sub-segments 103 ′ may pass through a first connection lead 106 Connect with each other.
  • the metal trace 12 may also include a second connection lead 107 .
  • the second connection lead 107 and the first connection lead 106 have an integrated structure.
  • the second connection lead 107 is used to connect the power signal line 103 and the second pad group 104 .
  • the first pad group 102 further includes an address pad Di and a ground pad Gnd.
  • the address pad Di and the power supply pad Pwr belonging to the same first pad group 102 are spaced apart in the first direction X, and are spaced apart from the output pad Out in the second direction Y.
  • the second direction Y is separated from the first direction X vertical.
  • the ground pad Gnd is spaced apart from the power supply pad Pwr in the second direction Y, and is spaced apart from the output pad Out in the first direction X.
  • the output pad Out is located at the upper left corner of the first pad group 102
  • the address pad Di is located at the lower left corner of the first pad group 102
  • the ground pad Gnd is located at the upper right corner of the first pad group 102
  • Electrical pad Pwr is located at the lower right corner of the first pad group 102 .
  • the address pad Di can receive an address signal for strobing the micro driver chip of the corresponding address.
  • the power supply pad Pwr can provide the first operating voltage and communication data to the micro driver chip, and the communication data can be used to control the luminous brightness of the corresponding light-emitting element (that is, the LED chip).
  • the output pad Out can output the relay signal and the driving signal respectively in different periods of time.
  • the relay signal is an address signal provided to the address pad Di in the first pad group 102 of the next level, and the drive signal is a drive current, used to drive the first pad group where the output pad Out is located.
  • the light-emitting element coupled to 102 emits light.
  • the ground pad Gnd receives the common voltage signal.
  • the number of first pad groups 102 is multiple. Multiple first pad groups 102 may be cascaded. As shown in Figure 4, the metal trace 12 also includes an address signal line 108. One address signal line 108 It may be coupled to the address pad Di of the first first pad group 102 in the multi-level first pad group 102 .
  • the metal traces 12 also include cascade lines 109 .
  • the cascade line 109 is configured to connect the output pad Out of the n-th level first pad group 102 belonging to the same pad area and the address pad Di of the (n+1)-th level first pad group 102 to pass
  • the cascade line 109 provides the relay signal output by the output pad Out of the n-th stage first pad group 102 to the address pad Di of the (n+1)-th stage first pad group 102 .
  • n is a positive integer.
  • the metal trace 12 also includes a feedback signal line 110 , and one feedback signal line 110 is coupled to the output pad Out of the last first pad group 102 in the multi-level first pad group 102 .
  • the metal traces 12 may also include a common voltage signal line 111 , and a common voltage signal line 111 is coupled to the ground pads Gnd of all the first pad groups 102 in a pad area.
  • the line width W 2 of the common voltage signal line 111 may be greater than 1 mm and less than or equal to 2.5 mm.
  • the power signal line 103, the first connection lead 106, the second connection lead 107, the address signal line 108, the cascade line 109, the feedback signal line 110 and the common voltage signal line 111, these different metal Trace 12 is shown with different padding. It should be noted that the power signal line 103, the first connection lead 106, the second connection lead 107, the address signal line 108, the cascade line 109, the feedback signal line 110 and the common voltage signal line 111 are formed simultaneously using the same process. , that is, formed using the same composition process.
  • the metal traces 12 also include anti-static (Electro-Static discharge, ESD) traces 112 located on the periphery for anti-static protection of the wiring substrate.
  • ESD Electro-Static discharge
  • the anti-static wiring 112 is located on the periphery of any signal line, any connection line, any wiring and the first pad group 102 and the second pad group 104, and forms a ring structure.
  • An embodiment of the present disclosure also provides a light-emitting panel.
  • the light-emitting panel may include the wiring substrate and a light-emitting diode chip in any embodiment of the present disclosure.
  • the light-emitting diode chip is connected to the corresponding metal trace 12 .
  • An embodiment of the present disclosure also provides a display device, which includes the light-emitting panel in any embodiment of the present disclosure.
  • the light-emitting panel in the embodiment of the present disclosure can be installed in a display device as a display panel, or can also be installed in a display device as a light source.
  • the display device can be any product or component with a display function such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, wearable display devices, etc.
  • the light-emitting panel in the embodiment of the present disclosure can also be used as a light-emitting light source in lighting products.
  • Embodiments of the present disclosure also provide a method for preparing a wiring substrate.
  • the method for preparing a wiring substrate can be The method includes: forming a plurality of metal traces on one side of the substrate; and forming an insulating layer on the side of the substrate on which the metal traces are formed.
  • the insulation layer is at least in the area outside the metal traces.
  • the distance between the surface of the insulating layer on the side away from the substrate and the substrate is greater than the distance between the surface of the metal trace on the side away from the substrate and the substrate.
  • the surface of the insulating layer away from the substrate can reflect light.
  • the insulating layer is provided with a first opening, and the first opening exposes part of the surface of the metal trace.
  • the technical solution of the embodiment of the present disclosure will be further described below through the preparation process of the wiring substrate in an embodiment of the present disclosure.
  • the "patterning" mentioned in this article when the patterned material is an inorganic material or metal, includes coating of photoresist, mask exposure, development, etching, and stripping lithography. Glue and other processes.
  • the patterned material is an organic material
  • "patterning” includes mask exposure, development and other processes.
  • the evaporation, deposition, coating, coating, etc. mentioned in this article are all mature in related technologies. Preparation Process.
  • a body metal film 121' of a predetermined thickness is formed on one side of the substrate 11.
  • the preset thickness is 5 ⁇ m to 8.5 ⁇ m
  • this step may include: using a deposition process multiple times to form a body metal film 121' with a preset thickness on one side of the substrate 11.
  • a layer of sub-body metal film can be formed on one side of the substrate 11 using one deposition process.
  • the thickness of the sub-body metal film obtained by each deposition is relatively thin. Therefore, in order to obtain The main body metal film with a preset thickness can be deposited multiple times to obtain two or more layers of sub-body metal films stacked in order to obtain a main body metal film 121' with a preset thickness.
  • this step may include: depositing a first metal film on one side of the substrate 11, using the first metal film as a seed layer, and using an electroplating process to A second metal film (also called an electroplated metal film) is formed on the surface of a metal film away from the substrate 11 .
  • a second metal film with an ideal thickness can be obtained by using an electroplating process.
  • the main metal film 121' of thickness 121' includes a first metal film and a second metal film that are stacked.
  • a buffer layer (not shown in the figure) may be formed on one side of the substrate 11, and then the main metal film 121' is formed on the buffer layer.
  • the buffer layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or a composite layer.
  • the buffer layer can improve the water and oxygen resistance of the substrate 11 .
  • an alloy film 122' is deposited on the surface of the main metal film 121' away from the substrate 11 to obtain a metal film 12'.
  • Figure 6 is a schematic diagram of a metal film formed on a wiring substrate according to an embodiment of the present disclosure.
  • a deposition process can be used to deposit an alloy film 122' on the surface of the main metal film away from the substrate 11 to obtain a metal film.
  • the thin film 12' and the metal thin film 12' include a stacked main metal thin film 121' and an alloy thin film 122'.
  • a first photoresist is coated on the side of the metal film facing away from the substrate 11, and a first mask is used to expose and develop the first photoresist to form a plurality of first photoresist bodies arranged at intervals. 13.
  • the first photoresist 13 is located at the position of the metal trace 12 .
  • FIG. 7 is a schematic diagram after the first photoresist is formed in the wiring substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram after forming metal traces in the wiring substrate according to an embodiment of the present disclosure.
  • only one mask (Mask) is used to obtain the metal trace 12 with a preset thickness.
  • Mosk only one mask
  • at least about 5 masks are saved, and the number of masks is greatly reduced. Reduce costs and improve product competitiveness.
  • the insulating layer 15 may be white ink, and S50 may include:
  • an inorganic protective layer 14 is deposited on the side of the substrate 11 facing the metal traces 12.
  • the inorganic protective layer 14 covers the metal traces 12 and the substrate 11, as shown in Figure 9.
  • Figure 9 is an implementation of the present disclosure. Schematic diagram of an example after forming an inorganic protective layer on a wiring substrate.
  • the thickness of the inorganic protective layer 14 can be set as needed. For example, the thickness of the inorganic protective layer 14 is 8% to 12.5% of the thickness of the metal traces 12 . For example, the thickness of the inorganic protective layer 14 is no greater than the thickness of the metal traces 12 . 10%.
  • the inorganic protective layer 14 can protect the metal wiring 12 and prevent the metal wiring 12 from being corroded by water and oxygen in subsequent processes.
  • a screen printing process is used to form white ink on the side of the inorganic protective layer 14 facing away from the substrate 11.
  • the white ink is provided with a first opening 150, as shown in Figure 10.
  • Figure 10 is an implementation of the present disclosure. Schematic diagram of an example after white ink is formed on a wiring substrate.
  • the first opening 150 may expose part of the surface of the inorganic protective layer 14 .
  • the white ink can cover the top of the inorganic protective layer 14 , so that the white ink and the inorganic protective layer 14 can play a dual role in protecting the metal traces 12 , further preventing the metal traces 12 from being damaged. Water and oxygen erosion.
  • white ink and the first opening 150 can be formed at one time, avoiding the use of a mask for exposure, saving masks and reducing costs.
  • white ink can be coated on the inorganic protective layer 14 using a mask. The film is exposed and developed to form first openings 150 .
  • a screen printing wet engraving process is used to form the second opening 140 in the inorganic protective layer 14, as shown in Figure 11.
  • Figure 11 shows the second opening and white ink in the wiring substrate according to an embodiment of the present disclosure. Schematic diagram.
  • a screen can be used to print a wet etching paste on the inorganic protective layer 14 exposed through the first opening 150 , and the wet etching paste can chemically react with the inorganic protective layer 14 to cause the inorganic protective layer to 14 is etched away, so that the inorganic protective layer 14 forms a second opening 140 in the area corresponding to the first opening 150 , and the second opening 140 exposes part of the surface of the metal trace 12 .
  • Using a screen printing wet engraving process to form the second opening 140 can avoid applying a mask and further reduce costs.
  • the insulating layer 15 is white ink
  • S50 may include:
  • an inorganic protective layer 14 is deposited on the side of the substrate 11 facing the metal traces 12 , and the inorganic protective layer 14 covers the metal traces 12 and the substrate 11 , as shown in FIG. 9 .
  • a screen printing wet etching process is used to form a second opening 140 in the inorganic protective layer 14, as shown in Figure 12.
  • Figure 12 shows the formation of a second opening in the inorganic protective layer in a wiring substrate according to another embodiment of the present disclosure. Schematic diagram after. For example, as shown in FIG. 12 , a wet etching paste can be printed on the inorganic protective layer 14 above the metal trace 12 using a screen. The wet etching paste can react chemically with the inorganic protective layer 14 to cause the inorganic protective layer 14 to be The second opening 140 is etched away to form a second opening 140 in the inorganic protective layer 14 , and the second opening 140 exposes part of the surface of the metal trace 12 .
  • a screen printing process is used to form white ink on the side of the inorganic protective layer 14 facing away from the substrate 11 .
  • the white ink is provided with a first opening 150 , as shown in FIG. 11 .
  • white ink is formed on the side of the inorganic protective layer 14 facing away from the substrate 11 .
  • the white ink is provided with a first opening 150 , and the first opening 150 intersects with the second opening 140 .
  • the overlap area of the first opening 150 and the second opening 140 exposes part of the surface of the metal trace 12 .
  • the orthographic projection of the first opening 150 on the substrate 11 may coincide with the orthographic projection of the second opening 140 on the substrate 11 .
  • the insulating layer 15 includes a photoresist layer 151 and a reflective layer 152
  • the first opening 150 includes a first sub-opening 151a and a second sub-opening 152a.
  • S50 can include:
  • a second photoresist is coated on the side of the substrate 11 facing the metal traces 12, and a first mask is used to form a photoresist pattern area and a hollow area, and the second photoresist is performed on the photoresist pattern area.
  • the glue constitutes the photoresist layer 151, and the hollow area constitutes the first sub-opening 151a, as shown in Figure 13.
  • Figure 13 is a schematic diagram after the photoresist layer is formed in the wiring substrate according to an embodiment of the present disclosure.
  • a second photoresist can be coated on the side of the substrate 11 on which the metal traces 12 are formed, and a first mask is used to expose and develop the second photoresist to form photoresist pattern area and Hollow area. Since this process uses the same first mask as in the process of FIGS. 6 to 8 , the photoresist pattern area is located outside the metal trace 12 and the hollow area is located above the metal trace 12 .
  • the second photoresist in the photoresist pattern area constitutes the photoresist layer 151, and the hollow area constitutes the first sub-opening 151a.
  • the first sub-opening 151 a may expose the entire surface of the metal trace 12 on the side away from the substrate 11 .
  • one of the second photoresist and the first photoresist is a positive photoresist, and the other is a negative photoresist.
  • the same mask can be used, reducing the number of masks and further reducing costs.
  • the thickness of the photoresist layer 151 can be set as needed, and the thickness of the photoresist layer 151 can be equal to or greater than the thickness of the metal traces 12 .
  • a screen printing process is used to form a reflective layer 152 on the side of the photoresist layer 151 away from the substrate 11.
  • the reflective layer 152 is provided with a second sub-opening 152a.
  • the second sub-opening 152a is located on the substrate.
  • the orthographic projection of the second sub-opening 152a on the substrate 11 is located at In the orthographic projection, the second sub-opening 152a can expose part of the surface of the metal trace 12, as shown in FIG. 14.
  • FIG. 14 is a schematic diagram after the reflective layer is formed in the wiring substrate according to an embodiment of the present disclosure.
  • the overlapping area of the first sub-opening 151a and the second sub-opening 152a constitutes the first opening 150.
  • the insulating layer 15 includes a photoresist layer 151 and a reflective layer 152
  • the first opening 150 includes a first sub-opening 151a and a second sub-opening 152a.
  • S50 can include:
  • an inorganic protective layer 14 is deposited on the side of the substrate 11 facing the metal traces 12 , and the inorganic protective layer 14 covers the metal traces 12 and the substrate 11 , as shown in FIG. 9 .
  • a second photoresist is coated on the side of the substrate 11 facing the inorganic protective layer 14, a first mask is used to form a photoresist pattern area and a hollow area, and the second photolithography of the photoresist pattern area is
  • the glue constitutes the photoresist layer 151, and the hollow area constitutes the first sub-opening 151a, as shown in Figure 15.
  • Figure 15 is a schematic diagram after forming a photoresist layer in an embodiment of the present disclosure.
  • a second photoresist is coated on the inorganic protective layer 14, and a first mask is used to expose and develop the second photoresist to form a photoresist pattern area and a hollow area.
  • the photoresist pattern area is located outside the metal trace 12
  • the hollow area is located above the metal trace 12 .
  • the second photoresist in the photoresist pattern area constitutes the photoresist layer 151
  • the hollow area constitutes the first sub-opening 151a.
  • the first sub-opening 151a can expose the entire surface of the metal trace 12 on the side away from the substrate 11 .
  • one of the second photoresist and the first photoresist is a positive photoresist, and the other is a negative photoresist.
  • a screen printing wet etching process is used to remove at least part of the exposed inorganic protective layer 14 to form a second opening 140, as shown in FIG. 16 .
  • FIG. 16 is a schematic diagram after forming second openings in the inorganic protective layer in the wiring substrate according to an embodiment of the present disclosure.
  • a screen can be used to print a wet etching paste on the inorganic protective layer 14 exposed through the first sub-opening 151 a .
  • the wet etching paste can chemically react with the inorganic protective layer 14 to make the inorganic protection layer 14 .
  • the layer 14 is etched away, so that the inorganic protective layer 14 forms a second opening 140 in the area corresponding to the first sub-opening 151a, and the second opening 140 exposes part of the surface of the metal trace 12.
  • Using a screen printing wet etching process to form the second opening 140 can avoid using a photolithography mask and further reduce costs.
  • a screen printing process is used to form a reflective layer 152 on the side of the photoresist layer 151 away from the substrate 11.
  • the reflective layer 152 is provided with a second sub-opening 152a, as shown in Figure 17.
  • FIG. 17 is a schematic diagram after forming the reflective layer and the second opening in an embodiment of the present disclosure.
  • a screen printing process is used to form a reflective layer 152 on a side of the photoresist layer 151 away from the substrate 11 , and the reflective layer 152 is provided with a second sub-opening 152 a.
  • the orthographic projection of the second sub-opening 152a on the substrate 11 may coincide with the orthographic projection of the second opening 140 on the substrate 11.
  • the insulating layer 15 includes a photoresist layer 151 and a reflective layer 152, and the first opening 150 includes a first sub-opening 151a and a second sub-opening 152a.
  • S50 can include:
  • an inorganic protective layer 14 is deposited on the side of the substrate 11 facing the metal traces 12 , and the inorganic protective layer 14 covers the metal traces 12 and the substrate 11 , as shown in FIG. 9 .
  • a second photoresist is coated on the side of the substrate 11 facing the inorganic protective layer 14, a first mask is used to form a photoresist pattern area and a hollow area, and the second photolithography of the photoresist pattern area is
  • the glue constitutes the photoresist layer 151, and the hollow area constitutes the first sub-opening 151a, as shown in Figure 15.
  • a screen printing process is used to form a reflective layer 152 on the side of the photoresist layer 151 away from the substrate 11.
  • the reflective layer 152 is provided with a second sub-opening 152a, as shown in Figure 18.
  • FIG. 18 is a schematic diagram after forming a reflective layer in another embodiment of the present disclosure.
  • a screen printing process is used to form a reflective layer 152 on the side of the photoresist layer 151 away from the substrate 11 .
  • the reflective layer 152 is provided with a second sub-opening 152 a .
  • the orthographic projection of the second sub-opening 152a on the substrate 11 is located at the first sub-opening.
  • the hole 151a is in the orthographic projection on the substrate 11, and the second sub-opening 152a exposes part of the surface of the inorganic protective layer 14.
  • a screen printing wet etching process is used to remove at least a part of the exposed inorganic protective layer 14 to form a second opening 140, as shown in FIG. 17 .
  • the distance between the surface of the insulating layer 15 on the side away from the substrate 11 and the substrate 11 is equal to or greater than the distance on the side of the metal trace 12 away from the substrate 11
  • the distance between the surface of the insulating layer 15 and the substrate 11 is such that the surface of the insulating layer 15 away from the substrate 11 can reflect light.
  • the material of the insulating layer 15 is white ink, and the surface of the white ink can reflect light.
  • the reflective layer 152 in the insulating layer 15 can reflect light.
  • the preparation method of the wiring substrate may further include: performing an electroless nickel gold process on the exposed surface of the metal trace 12 .
  • This step may include: growing a nickel-gold layer on the exposed surface of the metal trace 12, and the nickel-gold layer may serve as the oxidation protection layer 16, as shown in FIG. 11, FIG. 14, and FIG. 17.
  • a nickel (Ni) layer is first formed on the surface of the exposed metal trace 12 by electroless plating, and the thickness of the nickel layer is 3 ⁇ m to 5 ⁇ m; and then a gold (Au) layer is plated on the surface of the nickel layer through a substitution reaction.
  • the thickness of the layer is approximately 0.03 ⁇ m, resulting in an oxidation protection layer 16, which includes a nickel layer and a gold layer.
  • the orthographic projection of the oxidation protection layer 16 on the wiring substrate 11 is located within the range of the orthographic projection of the metal trace 12 on the wiring substrate 11 , and the oxidation protection layer 16 passes through the first opening 150 and is directly connected to the metal trace 12 Contact connection.
  • the material of the oxidation protection layer 16 may include nickel.
  • the material of the oxidation protection layer 16 may be a nickel gold (NiAu) layer.
  • the thickness of the oxidation protection layer 16 may be 4 ⁇ m to 5 ⁇ m (inclusive).
  • the preparation method of the wiring substrate may further include: using an pickling process to clean the surface of the metal trace 12 exposed through the first opening 150 Carry out pickling.
  • the pickling time By controlling the pickling time, the thickness of the reaction between the acid and the metal traces 12 can be controlled, so that the components on the surface of the metal traces 12 that are oxidized due to exposure to the air can be removed, which is beneficial to ensuring the reliable electrical connection of the metal traces 12 properties and low resistance.
  • the thickness of the alloy layer is relatively thin. After the pickling process, all or part of the alloy layer 122 exposed by the first opening in the metal trace 12 may be removed by corrosion, thus The oxidation protection layer 16 may be directly in contact with the main metal layer 121 .
  • only one mask is needed to form the wiring substrate, which not only obtains metal traces with a predetermined thickness, but also provides at least two layers of protection to the metal traces, avoiding water damage to the metal traces during the manufacturing process. Oxygen erosion improves product performance and reduces costs.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • “plurality” means two or more than two, unless otherwise expressly and specifically limited.
  • connection In this disclosure, unless otherwise explicitly stated and limited, the terms “installation”, “connection”, “connection”, “fixing” and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two elements or an interaction between two elements .
  • fixing and other terms should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. , or integrated; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, or an internal connection between two elements or an interaction between two elements .
  • the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.
  • a first feature "on” or “below” a second feature may include the first and second features in direct contact, or may include the first and second features. Not in direct contact but through additional characteristic contact between them.
  • the terms “above”, “above” and “above” a first feature on a second feature include the first feature being directly above and diagonally above the second feature, or simply mean that the first feature is higher in level than the second feature.
  • “Below”, “below” and “beneath” the first feature of the second feature includes the first feature being directly above and diagonally above the second feature, or simply means that the first feature has a smaller horizontal height than the second feature.

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Abstract

本公开实施例提供一种布线基板及其制备方法、发光面板、显示装置。布线基板包括：衬底、多条金属走线和绝缘层；金属走线和绝缘层位于衬底的同一侧，绝缘层位于金属走线之外的区域和所述金属走线的部分表面，绝缘层的上表面与衬底之间的距离大于金属走线的上表面与衬底之间的距离，绝缘层的上表面能够反射光线，绝缘层设置有第一开孔，第一开孔暴露金属走线的部分表面。通过设置绝缘层，可以对金属走线起到防护作用，防止金属走线在制程中被氧化腐蚀，提高产品性能，另外，绝缘层的表面可以反射光线，提高了光效。

Description

布线基板及其制备方法、发光面板、显示装置
本申请要求于2022年6月24日提交的申请号为202210731172.0、发明名称为“一种发光面板及其制备方法、发光面板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种布线基板及其制备方法、发光面板、显示装置。
背景技术
随着技术的突破，LED(Light-Emitting Diode，发光二极管)背光可以应用于电视、监视器、电脑等显示产品。LED背光可以包括布线基板和LED，LED与布线基板相连。
发明内容
本公开实施例提供一种布线基板及其制备方法、发光面板、显示装置。
作为本公开实施例的第一个方面，本公开实施例提供一种布线基板，包括：
衬底；
多条金属走线，位于衬底的一侧；
绝缘层，与所述多条金属走线位于衬底的同一侧，绝缘层位于金属走线之外的区域和所述金属走线的部分表面，绝缘层的远离衬底一侧的表面与衬底之间的距离大于金属走线的远离衬底一侧的表面与衬底之间的距离，绝缘层的远离衬底的表面能够反射光线，绝缘层中具有第一开孔，第一开孔暴露金属走线的部分表面。
在一种可能的实施方式中，绝缘层的材质为白色油墨，绝缘层在第一开孔之外的位置覆盖金属走线。
在另一种可能的实施方式中，绝缘层包括光刻胶层和反射层，光刻胶层位于金属走线之外的区域，第一开孔包括第一子开孔，第一子开孔贯穿光刻胶层；反射层至少位于光刻胶层的远离衬底一侧的表面。
在又一种可能的实施方式中，反射层覆盖光刻胶层和金属走线，第一开孔包括第二子开孔，第二子开孔贯穿反射层，第二子开孔在衬底上的正投影与于第一子开孔在衬底上的正投影存在交叠区域。
在一个实施例中，反射层的材质为白色油墨。
可选地，所述金属走线包括层叠设置的主体金属层和合金层，所述合金层位于所述主体金属层的远离所述衬底的表面。
可选地，金属走线的厚度的范围为5μm～8.5μm。
可选地，布线基板还包括氧化防护层，氧化防护层位于金属走线的暴露区域，氧化防护层与金属走线直接接触，氧化防护层的材质包括镍和金，氧化防护层的厚度范围为4μm～5μm。
在一个实施例中，布线基板还包括无机保护层，无机保护层覆盖金属走线和衬底的外露表面，绝缘层位于无机保护层的背离衬底的一侧，无机保护层设置有第二开孔，第二开孔在衬底上的正投影与第一开孔在衬底上的正投影存在交叠区域。
可选地，无机保护层的材质包括硅氧化物、硅氮化物和氮氧化硅中的一种或多种。
可选地，所述多条金属走线包括：电源信号线、地址信号线、公共电压信号线、级联线和反馈信号线。所述多条金属线通过所述第一开孔暴露的表面形成多个第一焊盘组和多个第二焊盘组，所述第一焊盘组用于与微型驱动芯片耦接，所述第二焊盘组用于与发光元件耦接。每个所述第一焊盘组包括供电焊盘、输出焊盘、地址焊盘和接地焊盘，所述供电焊盘与所述电源信号线连接，所述接地焊盘与所述公共电压信号线连接，所述输出焊盘与一个所述第二焊盘组中的至少一个焊盘连接。所述多个第一焊盘组级联，多级所述第一焊盘组中，第一个第一焊盘组的地址焊盘与所述地址信号线连接，最后一个第一焊盘组的输出焊盘与所述反馈信号线连接，第n级第一焊盘组的输出焊盘与第(n+1)级第一焊盘组的地址焊盘通过一根所述级联线连接，其中，n为正整数。
作为本公开实施例的第二方面，本公开实施例提供一种布线基板的制备方法，包括：
在衬底的一侧形成多条金属走线；
在衬底的形成有金属走线的一侧形成绝缘层，绝缘层位于金属走线之外的区域和所述金属走线的部分表面，绝缘层的远离衬底一侧的表面与衬底之间的 距离大于金属走线的远离衬底一侧的表面与衬底之间的距离，绝缘层的远离衬底的表面能够反射光线，绝缘层中具有第一开孔，第一开孔暴露金属走线的部分表面。
可选地，所述在衬底的一侧形成多条金属走线，包括：
在所述衬底的一侧形成预设厚度的主体金属薄膜；
在所述主体金属薄膜远离所述衬底的表面沉积合金薄膜，得到包括所述主体金属薄膜和所述合金薄膜的金属薄膜；
在所述金属薄膜的背离所述衬底的一侧涂覆第一光刻胶，采用第一掩膜对所述第一光刻胶进行曝光和显影，形成间隔设置的多个第一光刻胶体；
对所述第一光刻胶体之外的金属薄膜进行刻蚀，并剥离所述第一光刻胶体，得到所述多条金属走线。
可选地，在衬底的一侧形成预设厚度的主体金属薄膜，包括：
多次采用沉积工艺，在衬底的一侧形成预设厚度的主体金属薄膜；或者，
在衬底的一侧沉积第一金属薄膜，采用电镀工艺在第一金属薄膜的远离衬底的表面形成第二金属薄膜，得到预设厚度的主体金属薄膜，主体金属薄膜包括层叠设置的第一金属薄膜和第二金属薄膜。
在一种可能的实施方式中，绝缘层为白色油墨，在衬底的朝向金属走线的一侧形成绝缘层，包括：
在衬底的朝向金属走线的一侧沉积无机保护层，无机保护层覆盖金属走线和衬底；
采用网版印刷工艺，在无机保护层的背离衬底的一侧形成白色油墨，白色油墨设置有第一开孔；
采用网印湿刻工艺，在无机保护层形成第二开孔。
在另一种可能的实施方式中，绝缘层包括光刻胶层和反射层，第一开孔包括第一子开孔和第二子开孔，在衬底的朝向金属走线的一侧形成绝缘层，包括：
在衬底的朝向金属走线的一侧涂覆第二光刻胶，采用第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层，镂空区构成第一子开孔，第二光刻胶与第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶；
采用网版印刷工艺，在光刻胶层的远离衬底的一侧形成反射层，反射层设置有第二子开孔，第二子开孔在衬底上的正投影与第一子开孔在衬底上的正投影存在交叠区域，例如第二子开孔在衬底上的正投影位于第一子开孔在衬底上的 正投影内。
在又一种可能的实施方式中，绝缘层包括光刻胶层和反射层，第一开孔包括第一子开孔和第二子开孔，在衬底的朝向金属走线的一侧形成绝缘层，包括：
在衬底的朝向金属走线的一侧沉积无机保护层，无机保护层覆盖金属走线和衬底；
在衬底的朝向无机保护层的一侧涂覆第二光刻胶，采用第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层，镂空区构成第一子开孔，第二光刻胶与第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶；
采用网印湿刻工艺，去除暴露出的无机保护层的至少一部分而形成第二开孔；
采用网版印刷工艺，在光刻胶层的远离衬底的一侧形成反射层，反射层设置有第二子开孔。
可选地，布线基板的制备方法还包括：对金属走线暴露的表面进行化学镍金工艺。
作为本公开实施例的第三个方面，本公开实施例提供一种发光面板，包括本公开任一实施例中的布线基板和多个发光二极管芯片，多个发光二极管芯片与金属走线对应连接。
作为本公开实施例的第四个方面，本公开实施例提供一种显示装置，包括本公开任一实施例中的发光面板。
附图说明
在附图中，除非另外规定，否则贯穿多个附图相同的附图标记表示相同或相似的部件或元素。这些附图不一定是按照比例绘制的。应该理解，这些附图仅描绘了根据本公开的一些实施方式，而不应将其视为是对本公开范围的限制。
图1为本公开实施例提供的一种布线基板的截面结构示意图；
图2为本公开实施例提供的另一种布线基板的截面结构示意图；
图3为本公开实施例提供的另一种布线基板的截面结构示意图；
图4为本公开实施例提供的一种布线基板的局部结构示意图；
图5为图4中的M部分的放大示意图；
图6为本公开一实施例布线基板中形成金属薄膜后的示意图；
图7为本公开一实施例布线基板中形成第一光刻胶体后的示意图；
图8为本公开一实施例布线基板中形成金属走线后的示意图；
图9为本公开一实施例布线基板中形成无机保护层后的示意图；
图10为本公开一实施例布线基板中形成白色油墨后的示意图；
图11为本公开一实施例布线基板中形成第二开孔和白色油墨后的示意图；
图12为本公开另一实施例布线基板中在无机保护层形成第二开孔后的示意图；
图13为本公开一实施例布线基板中形成光刻胶层后的示意图；
图14为本公开一实施例布线基板中形成反射层后的示意图；
图15为本公开一个实施例中形成光刻胶层后的示意图；
图16为本公开一实施例布线基板中在无机保护层形成第二开孔后的示意图；
图17为本公开一实施例中形成反射层和第二开孔后的示意图；
图18为本公开另一实施例中形成反射层后的示意图。
附图标记说明：
11、衬底；12、金属走线；121、主体金属层；122、合金层；13、第一光刻胶体；14、无机保护层；140、第二开孔；15、绝缘层；150、第一开孔；151、光刻胶层；151a、第一子开孔；152、反射层；152a、第二子开孔；16、氧化防护层。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本公开的精神或范围的情况下，可通过各种不同方式修改所描述的实施例，不同的实施例在不冲突的情况下可以任意结合。因此，附图和描述被认为本质上是示例性的而非限制性的。
图1为本公开实施例提供的一种布线基板的截面结构示意图。如图1所示，布线基板包括衬底11、多条金属走线12和绝缘层15。多条金属走线12位于衬底11的一侧。
绝缘层15位于衬底11的朝向金属走线12的一侧，即绝缘层15与金属走线12位于衬底11的同一侧。绝缘层15至少位于金属走线12之外的区域。例如绝缘层15位于金属走线12之外的区域和金属走线12的部分表面。绝缘层15的远离衬底11的表面与衬底11之间的距离大于金属走线12的远离衬底11的表面与衬底11之间的距离。示例性地，绝缘层15的远离衬底11的表面能够反 射光线。绝缘层15中设置有第一开孔150，第一开孔150暴露金属走线12的部分表面。
示例性地，金属走线12的暴露的表面可以用于与电子元件连接。电子元件可以包括发光二极管芯片、微型驱动芯片和传感器芯片等中的至少一种。
示例性地，发光二极管芯片可以为次毫米发光二极管(Mini Light Emitting Diode，简称Mini LED)芯片，或者，可以为微型发光二极管(Micro Light Emitting Diode，简称Micro LED)芯片。
示例性地，金属走线12包括层叠设置的主体金属层121和合金层122，合金层122位于主体金属层121的远离衬底11的表面。合金层122为耐蚀合金层。
本公开实施例的布线基板，合金层122可以保护主体金属层121，防止主体金属层121在制程中被水氧侵蚀；绝缘层15可以对金属走线12的侧壁形成保护，防止金属走线12在制程中被水氧侵蚀。通过设置合金层122和绝缘层15，可以对金属走线12起到全面防护，防止金属走线12在制程中被氧化腐蚀，提高产品性能。另外，绝缘层15的表面可以反射光线，当布线基板上设置发光器件后，发光器件发射到布线基板表面的光线可以被绝缘层15反射至出光侧，提高光效。
示例性地，衬底11的材质可以包括玻璃或者树脂(或者PCB(Printed Circuit Board，印刷电路板)的其他基材)等。
示例性地，主体金属层121的材质包括但不限于铜。铜金属具有电阻率低、导电性好的特点。合金层122的材质可以包括镍和铜，例如，合金层122的材质可以为镍铜合金、镍钒合金、镍钨合金或者钨镍合金等。
需要说明的是，在其他实施例中，金属走线121还可以为单层结构，例如，金属走线121为单层的金属层或者合金层等。
在一种实施方式中，如图1所示，布线基板还可以包括无机保护层14。无机保护层14位于金属走线12的背离衬底11的一侧，无机保护层14覆盖金属走线12和衬底11的外露表面(即未被金属走线12覆盖的表面)。绝缘层15位于无机保护层14背离衬底11的一侧。无机保护层14可以对金属走线12进一步起到保护作用，防止水氧侵蚀，避免在绝缘层15的制程中水氧侵入金属走线12。
示例性地，无机保护层14中设置有第二开孔140，第二开孔140在衬底11 上的正投影与第一开孔150在衬底11上的正投影存在交叠区域。第二开孔140和第一开孔150的交叠区域可以暴露金属走线12的部分表面。
示例性地，无机保护层14的材质可以包括硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种。无机保护层14可以是单层、多层或复合层。
无机保护层14的厚度可以根据需要设置。示例性地，无机保护层14的厚度为金属走线12的厚度的8％～12.5％。例如，无机保护层14的厚度不大于金属走线12厚度的10％。
在一种实施方式中，如图3所示，绝缘层15的材质可以为白色油墨，绝缘层15在第一开孔150之外的位置覆盖金属走线12。这样，在第一开孔150之外，白色油墨对金属走线12的侧壁和上表面均可以起到保护的作用，进一步防止水氧侵蚀金属走线12。另外，白色油墨还具有反射功能，可以将照射到白色油墨的表面的光线朝向出光侧反射。采用白色油墨作为绝缘层15，可以一步获得具有反射功能的绝缘层，有利于提高生产效率、降低成本。
图2为本公开实施例提供的另一种布线基板的截面结构示意图。图2中的布线基板的结构与图1中的布线基板的结构基板相同，不同之处在于，图2中绝缘层15包括光刻胶层151和反射层152，光刻胶层151位于金属走线12之外的区域。第一开孔150包括第一子开孔151a，第一子开孔151a贯穿光刻胶层151。示例性地，第一子开孔151a可以暴露金属走线12的远离衬底11的全部表面。示例性地，反射层152至少设置于光刻胶层151的远离衬底11的表面。这样的绝缘层15为光刻胶层151和反射层152的复合层，可以起到双重保护的作用，进一步防止水氧侵蚀金属走线12。
在一种实施方式中，反射层152可以覆盖金属走线12和光刻胶层151。第一开孔150包括第二子开孔152a，第二子开孔152a贯穿反射层152。第二子开孔152a在衬底11上的正投影位于第一子开孔151a在衬底11上的正投影内，从而，金属走线12的部分表面通过第二子开孔152a暴露。
示例性地，反射层152的材质为白色油墨。
图3为本公开实施例提供的又一种布线基板的截面结构示意图。图3中的布线基板的结构与图2中的布线基板的结构基板相同，不同之处在于，图3中布线基板还包括无机保护层14。无机保护层14的相关内容可以参见图1相关实施例，在此省略详细描述。
在一种实施方式中，金属走线12的厚度的范围可以为5μm～8.5μm(包括端点值)，例如，金属走线12的厚度可以为5μm、5.5μm、6μm、6.5μm、7μm、7.5μm、8μm、8.5μm中的一个。金属走线12的厚度足够大，可以降低金属走线12的电阻。
在一种实施方式中，如图1～图3所示，布线基板还可以包括氧化防护层16，氧化防护层16位于金属走线12的暴露区域，氧化防护层16与金属走线12直接接触。示例性地，氧化防护层16覆盖金属走线12的暴露区域。氧化防护层16可以防止金属走线12的暴露区域被氧化。
示例性地，氧化防护层16的材质包括镍和金。氧化防护层16的厚度范围为4μm～5μm。需要说明的是，通过固晶工艺，发光二极管芯片或微型驱动芯片通过氧化防护层16与金属走线12连接。这样的氧化防护层16不仅可以更好地防止金属走线12被氧化侵蚀，而且还可以提高固晶良率。
在一种实施方式中，如图1～图3所示，绝缘层15的远离衬底11的表面与金属走线12的远离衬底11的表面之间的段差d小于或等于10μm。这样的设置，有利于之后的固晶或绑定工艺，提高良率。
需要说明的是，金属走线12被氧化防护层16覆盖的各个区域以及对应区域上方的氧化防护层16可以构成焊盘。经过回流焊工艺后，每个焊盘可以通过焊接金属与电子元件的一个引脚实现电连接。焊接金属可以包括锡等。可选地，电子元件可以包括发光二极管芯片、微型驱动芯片、传感器芯片等中的至少一种。
图4为本公开实施例提供的一种布线基板的局部结构示意图。图5为图4中的M部分的放大示意图。前述图1～图3分别为图4中A-A处的截面结构示意图。
在一种实施方式中，如图4和图5所示，布线基板可以包括第一焊盘组102和第二焊盘组104，可选地，第一焊盘组102与微型驱动芯片耦接。第二焊盘组104与LED芯片耦接。可选地，每个第一焊盘组102可以与一个微型驱动芯片耦接，每个第二焊盘组104与多个LED芯片耦接。
金属走线12包括电源信号线103。第一焊盘组102包括供电焊盘Pwr和输出焊盘Out。电源信号线103与供电焊盘Pwr耦接。第二焊盘组104包括相互电连接的多个子焊盘组104'，每个子焊盘组104'至少包括第一子焊盘41和第二子焊盘42。每个子焊盘组104'与一个LED芯片耦接。每个第二焊盘组104所含至少一个子焊盘组104'的第一子焊盘41与电源信号线103耦接，每个第二焊盘组 104所含至少一个子焊盘组104'的第二子焊盘42与一个第一焊盘组102中的输出焊盘Out耦接。
例如，图4中，第二焊盘组104包括4个子焊盘组104'。左下角的子焊盘组104'的第一子焊盘41与电源信号线103耦接，右下角的子焊盘组104'的第二子焊盘42与第一焊盘组102中的输出焊盘Out耦接。按照顺时针方向，相邻的两个子焊盘组104'中，前一个子焊盘组104'的第二子焊盘42与下一个子焊盘组104'的第一子焊盘41通过连接线43连接。
在图4所示布线基板中，第一焊盘组102和第二焊盘组104连接同一根电源信号线103。
如图4和图5所示，金属走线12还可以包括第一连接引线106，一条电源信号线103包括多个子段103'，相邻的两个子段103'可以通过一个第一连接引线106相互连接。
如图4和图5所示，金属走线12还可以包括第二连接引线107。可选地，第二连接引线107与第一连接引线106为一体结构。该第二连接引线107用于将电源信号线103与第二焊盘组104连接。
示例性地，如图5所示，第一焊盘组102还包括地址焊盘Di和接地焊盘Gnd。属于同一第一焊盘组102的地址焊盘Di与供电焊盘Pwr在第一方向X上间隔设置、并与输出焊盘Out在第二方向Y上间隔设置，第二方向Y与第一方向X垂直。接地焊盘Gnd与供电焊盘Pwr在第二方向Y上间隔设置、并与输出焊盘Out在第一方向X上间隔设置。示例性地，输出焊盘Out位于第一焊盘组102的左上角，地址焊盘Di位于第一焊盘组102的左下角，接地焊盘Gnd位于第一焊盘组102的右上角，供电焊盘Pwr位于第一焊盘组102的右下角。
在一些实施例中，地址焊盘Di可接收地址信号，以用于选通相应地址的微型驱动芯片。供电焊盘Pwr可为微型驱动芯片提供第一工作电压和通信数据，该通信数据可用于控制相应发光元件(即LED芯片)的发光亮度。输出焊盘Out可在不同的时段内分别输出中继信号和驱动信号。可选地，中继信号为提供给下一级第一焊盘组102中的地址焊盘Di的地址信号，驱动信号为驱动电流，用于驱动与该输出焊盘Out所在第一焊盘组102耦接的发光元件发光。接地焊盘Gnd接收公共电压信号。
在一些实施例中，第一焊盘组102的数量为多个。多个第一焊盘组102可以级联。如图4所示，金属走线12还包括地址信号线108，一条地址信号线108 可以与多级第一焊盘组102中第一个第一焊盘组102的地址焊盘Di耦接。
如图5所示，金属走线12还包括级联线109。级联线109被配置为连接属于同一焊盘区的第n级第一焊盘组102的输出焊盘Out和第(n+1)级第一焊盘组102的地址焊盘Di，以通过级联线109将第n级第一焊盘组102的输出焊盘Out输出的中继信号提供给第(n+1)级第一焊盘组102的地址焊盘Di。其中，n为正整数。
如图4所示，金属走线12还包括反馈信号线110，一条反馈信号线110与多级第一焊盘组102中最后一个第一焊盘组102的输出焊盘Out耦接。
如图4和图5所示，金属走线12还可以包括公共电压信号线111，一条公共电压信号线111与一个焊盘区内全部第一焊盘组102的接地焊盘Gnd耦接。公共电压信号线111的线宽W2可以大于1mm且小于或者等于2.5mm。
在图4和图5中，电源信号线103、第一连接引线106、第二连接引线107、地址信号线108、级联线109、反馈信号线110和公共电压信号线111，这些不同的金属走线12采用了不同的填充进行了表示。需要说明的是，电源信号线103、第一连接引线106、第二连接引线107、地址信号线108、级联线109、反馈信号线110和公共电压信号线111是采用同样的工艺同时形成的，即采用同一构图工艺形成。
示例性地，如图4所示，金属走线12还包括位于外围的防静电(Electro-Static discharge，ESD)走线112，用于对布线基板进行防静电保护。具体的，防静电走线112位于任意信号线、任意连接线、任意走线以及第一焊盘组102、第二焊盘组104的外围，并构成环状结构。
本公开实施例还提供一种发光面板，发光面板可以包括本公开任一实施例中的布线基板和发光二极管芯片，发光二极管芯片与对应的金属走线12连接。
本公开实施例还提供一种显示装置，该显示装置包括本公开任一实施例中的发光面板。
本公开实施例中的发光面板可以作为显示面板装配于显示装置中，也可以作为光源装配于显示装置中。该显示装置可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、可穿戴显示设备等任何具有显示功能的产品或部件。
本公开实施例中的发光面板还可以作为发光光源使用在照明产品中。
本公开实施例还提供一种布线基板的制备方法，布线基板的制备方法可以 包括：在衬底的一侧形成多条金属走线；在衬底的形成有金属走线的一侧形成绝缘层。
绝缘层至少位于金属走线之外的区域。绝缘层的远离衬底一侧的表面与衬底之间的距离大于金属走线的远离衬底一侧的表面与衬底之间的距离。绝缘层的远离衬底的表面能够反射光线，绝缘层中设置有第一开孔，第一开孔暴露金属走线的部分表面。
下面通过本公开一实施例中布线基板的制备过程进一步说明本公开实施例的技术方案。可以理解的是，本文中所说的“图案化”，当图案化的材质为无机材质或金属时，“图案化”包括涂覆光刻胶、掩膜曝光、显影、刻蚀、剥离光刻胶等工艺，当图案化的材质为有机材质时，“图案化”包括掩模曝光、显影等工艺，本文中所说的蒸镀、沉积、涂覆、涂布等均是相关技术中成熟的制备工艺。
在S10中，在衬底11的一侧形成预设厚度的主体金属薄膜121’。
在一个实施例中，预设厚度为5μm～8.5μm，该步骤可以包括：多次采用沉积工艺，在衬底11的一侧形成预设厚度的主体金属薄膜121’。可以理解的是，采用一次沉积工艺可以在衬底11的一侧形成一层子主体金属薄膜，鉴于沉积工艺的局限性，每次沉积得到的子主体金属薄膜的厚度较薄，因此，为了得到预设厚度的主体金属薄膜，可以多次采用沉积工艺，得到两层或两层以上层叠设置子主体金属薄膜，进而得到预设厚度的主体金属薄膜121’。
在一个实施例中，为了得到预设厚度的主体金属薄膜121’，该步骤可以包括：在衬底11的一侧沉积第一金属薄膜，将第一金属薄膜作为种子层，采用电镀工艺在第一金属薄膜的远离衬底11的表面形成第二金属薄膜(也可以叫做电镀金属薄膜)。采用电镀工艺可以获得理想厚度的第二金属薄膜，通过控制电镀工艺的时间可以控制第二金属薄膜的厚度，从而可以控制第一金属薄膜和第二金属薄膜的厚度之和，进而可以得到预设厚度的主体金属薄膜121’，主体金属薄膜121’包括层叠设置的第一金属薄膜和第二金属薄膜。
示例性地，在形成主体金属薄膜121’之前，可以在衬底11的一侧形成缓冲(Buffer)层(图中未示出)，然后在缓冲层上形成主体金属薄膜121’。缓冲层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。缓冲层可以提高衬底11的抗水氧能力。
在S20中，在主体金属薄膜121’远离衬底11的表面沉积合金薄膜122’，得到金属薄膜12’。
图6为本公开一实施例布线基板中形成金属薄膜后的示意图，示例性地，如图6所示，可以采用沉积工艺在主体金属薄膜远离衬底11的表面沉积合金薄膜122’，得到金属薄膜12’，金属薄膜12’包括层叠设置的主体金属薄膜121’和合金薄膜122’。
在S30中，在金属薄膜的背离衬底11的一侧涂覆第一光刻胶，采用第一掩膜对第一光刻胶进行曝光和显影，形成间隔设置的多个第一光刻胶体13，第一光刻胶体13位于金属走线12的位置。如图7所示，图7为本公开一实施例布线基板中形成第一光刻胶体后的示意图。
在S40中，对第一光刻胶体13之外的金属薄膜进行刻蚀，并剥离第一光刻胶体13，得到多条金属走线12，金属走线12包括层叠设置的主体金属层121和合金层122，合金层122位于主体金属层121的远离衬底11的表面。如图8所示，图8为本公开一实施例布线基板中形成金属走线后的示意图。
本公开实施例中，只采用了一个掩膜(Mask)就得到了预设厚度的金属走线12，相比于现有技术至少约节约了5张掩膜，大大减少了掩膜的数量，降低了成本，提升了产品竞争力。
示例性地，绝缘层15可以为白色油墨，S50可以包括：
第一步，在衬底11的朝向金属走线12的一侧沉积无机保护层14，无机保护层14覆盖金属走线12和衬底11，如图9所示，图9为本公开一实施例布线基板中形成无机保护层后的示意图。无机保护层14的厚度可以根据需要设置，示例性地，无机保护层14的厚度为金属走线12厚度的8％～12.5％，例如，无机保护层14的厚度不大于金属走线12厚度的10％。形成无机保护层14后，无机保护层14可以对金属走线12起到保护的作用，防止金属走线12在后续制程中被水氧侵蚀。
第二步，采用网版印刷工艺，在无机保护层14的背离衬底11的一侧形成白色油墨，白色油墨设置有第一开孔150，如图10所示，图10为本公开一实施例布线基板中形成白色油墨后的示意图。示例性地，如图10所示，第一开孔150可以暴露无机保护层14的部分表面。在第一开孔150之外的位置，白色油墨可以覆盖在无机保护层14的上方，从而白色油墨和无机保护层14可以对金属走线12起到双重保护作用，进一步防止金属走线12被水氧侵蚀。采用网版印刷工艺，可以一次性形成白色油墨以及第一开孔150，避免采用掩膜曝光，节省了掩膜，降低了成本。示例性地，可以在无机保护层14上涂覆白色油墨，采用掩 膜、曝光并显影来形成第一开孔150。
第三步，采用网印湿刻工艺，在无机保护层14形成第二开孔140，如图11所示，图11为本公开一实施例布线基板中形成第二开孔和白色油墨后的示意图。示例性地，如图11所示，可以利用网版在通过第一开孔150暴露的无机保护层14上印刷湿刻膏，湿刻膏可以与无机保护层14发生化学反应而使无机保护层14被刻蚀掉，从而，无机保护层14在第一开孔150对应的区域形成第二开孔140，第二开孔140暴露金属走线12的部分表面。采用网印湿刻工艺形成第二开孔140，可以避免适用掩膜，进一步降低成本。
在另一个实施例中，绝缘层15为白色油墨，S50可以包括：
第一步，在衬底11的朝向金属走线12的一侧沉积无机保护层14，无机保护层14覆盖金属走线12和衬底11，如图9所示。
第二步，采用网印湿刻工艺，在无机保护层14形成第二开孔140，如图12所示，图12为本公开另一实施例布线基板中在无机保护层形成第二开孔后的示意图。示例性地，如图12所示，可以利用网版在金属走线12上方的无机保护层14上印刷湿刻膏，湿刻膏可以与无机保护层14发生化学反应而使无机保护层14被刻蚀掉，从而，在无机保护层14中形成第二开孔140，第二开孔140暴露金属走线12的部分表面。
第三步，采用网版印刷工艺，在无机保护层14的背离衬底11的一侧形成白色油墨，白色油墨设置有第一开孔150，如图11所示。示例性地，如图11所示，在无机保护层14的背离衬底11的一侧形成白色油墨，白色油墨设置有第一开孔150，第一开孔150与第二开孔140存在交叠区域，第一开孔150与第二开孔140的交叠区域暴露金属走线12的部分表面。示例性地，第一开孔150在衬底11上的正投影可以与第二开孔140在衬底11上的正投影重合。
在另一些实施例中，绝缘层15包括光刻胶层151和反射层152，第一开孔150包括第一子开孔151a和第二子开孔152a。S50可以包括：
第一步，在衬底11的朝向金属走线12的一侧涂覆第二光刻胶，采用第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层151，镂空区构成第一子开孔151a，如图13所示，图13为本公开一实施例布线基板中形成光刻胶层后的示意图。
示例性地，如图13所示，可以在衬底11的形成有金属走线12的一侧涂覆第二光刻胶，采用第一掩膜对第二光刻胶进行曝光和显影，形成光刻胶图案区和 镂空区。由于该过程采用与图6～图8过程中相同的第一掩膜，因此，光刻胶图案区位于金属走线12之外的区域，镂空区位于金属走线12的上方。光刻胶图案区的第二光刻胶构成光刻胶层151，镂空区构成第一子开孔151a。第一子开孔151a可以暴露金属走线12的远离衬底11一侧的全部表面。示例性地，第二光刻胶与第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶。通过选择与第一光刻胶相反的第二光刻胶，可以采用同一个掩膜，减少了掩膜数量，进一步降低成本。光刻胶层151的厚度可以根据需要设置，光刻胶层151的厚度可以等于或大于金属走线12的厚度。
第二步，采用网版印刷工艺，在光刻胶层151的远离衬底11的一侧形成反射层152，反射层152设置有第二子开孔152a，第二子开孔152a在衬底上的正投影与第一子开孔151a在衬底上的正投影存在交叠区域，例如第二子开孔152a在衬底11上的正投影位于第一子开孔151a在衬底11上的正投影内，第二子开孔152a可以暴露金属走线12的部分表面，如图14所示，图14为本公开一实施例布线基板中形成反射层后的示意图。示例性地，第一子开孔151a和第二子开孔152a的交叠区域构成第一开孔150。
在另一些实施例中，绝缘层15包括光刻胶层151和反射层152，第一开孔150包括第一子开孔151a和第二子开孔152a。S50可以包括：
第一步，在衬底11的朝向金属走线12的一侧沉积无机保护层14，无机保护层14覆盖金属走线12和衬底11，如图9所示。
第二步，在衬底11的朝向无机保护层14的一侧涂覆第二光刻胶，采用第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层151，镂空区构成第一子开孔151a，如图15所示。
图15为本公开一个实施例中形成光刻胶层后的示意图。示例性地，如图15所示，在无机保护层14的上涂覆第二光刻胶，采用第一掩膜对第二光刻胶进行曝光和显影，形成光刻胶图案区和镂空区，光刻胶图案区位于金属走线12之外的区域，镂空区位于金属走线12的上方。光刻胶图案区的第二光刻胶构成光刻胶层151，镂空区构成第一子开孔151a，第一子开孔151a可以暴露金属走线12的远离衬底11一侧的全部表面。示例性地，第二光刻胶与第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶。
第三步，采用网印湿刻工艺，去除暴露出的无机保护层14的至少一部分而形成第二开孔140，如图16所示。
图16为本公开一实施例布线基板中在无机保护层形成第二开孔后的示意图。示例性地，如图6所示，可以利用网版在通过第一子开孔151a暴露的无机保护层14上印刷湿刻膏，湿刻膏可以与无机保护层14发生化学反应而使无机保护层14被刻蚀掉，从而，无机保护层14在第一子开孔151a对应的区域形成第二开孔140，第二开孔140暴露金属走线12的部分表面。采用网印湿刻工艺形成第二开孔140，可以避免使用光刻掩膜版，进一步降低成本。
第三步，采用网版印刷工艺，在光刻胶层151的远离衬底11的一侧形成反射层152，反射层152设置有第二子开孔152a，如图17所示。
图17为本公开一实施例中形成反射层和第二开孔后的示意图。示例性地，如图17所示，采用网版印刷工艺，在光刻胶层151的远离衬底11的一侧形成反射层152，反射层152设置有第二子开孔152a。第二子开孔152a与第二开孔140存在交叠区域，第二子开孔152a与第二开孔140的交叠区域暴露金属走线12的部分表面。示例性地，第二子开孔152a在衬底11上的正投影可以与第二开孔140在衬底11上的正投影重合。
在又一些实施例中，绝缘层15包括光刻胶层151和反射层152，第一开孔150包括第一子开孔151a和第二子开孔152a。S50可以包括：
第一步，在衬底11的朝向金属走线12的一侧沉积无机保护层14，无机保护层14覆盖金属走线12和衬底11，如图9所示。
第二步，在衬底11的朝向无机保护层14的一侧涂覆第二光刻胶，采用第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层151，镂空区构成第一子开孔151a，如图15所示。
第三步，采用网版印刷工艺，在光刻胶层151的远离衬底11的一侧形成反射层152，反射层152设置有第二子开孔152a，如图18所示。
图18为本公开另一实施例中形成反射层后的示意图。示例性地，如图18所示，采用网版印刷工艺，在光刻胶层151的远离衬底11的一侧形成反射层152，反射层152设置有第二子开孔152a，第二子开孔152a在衬底上的正投影与第一子开孔151a在衬底上的正投影存在交叠区域，例如，第二子开孔152a在衬底11上的正投影位于第一子开孔151a在衬底11上的正投影内，第二子开孔152a暴露无机保护层14的部分表面。
第四步，采用网印湿刻工艺，去除暴露出的无机保护层14的至少一部分而形成第二开孔140，如图17所示。
示例性地，如图11、图14和图17所示，绝缘层15的远离衬底11一侧的表面与衬底11之间的距离等于或大于金属走线12的远离衬底11一侧的表面与衬底11之间的距离，绝缘层15的远离衬底11的表面能够反射光线。在图11中，绝缘层15的材质为白色油墨，白色油墨的表面可以反射光线。在图14和17中，绝缘层15中的反射层152可以反射光线。
在一种实施方式中，布线基板的制备方法还可以包括：对金属走线12暴露的表面进行化学镍金工艺。该步骤可以包括：在金属走线12的暴露表面生长镍金层，镍金层可以作为氧化防护层16，如图11、图14和图17所示。例如，在暴露的金属走线12的表面上先通过化学镀的方式制作镍(Ni)层，镍层的厚度为3μm～5μm；然后通过置换反应在镍层的表面镀金(Au)层，金层的厚度约为0.03μm，从而得到氧化防护层16，氧化防护层16包括镍层和金层。氧化防护层16在布线基板衬底11上的正投影位于金属走线12在布线基板衬底11上的正投影的范围内，氧化防护层16穿过第一开孔150与金属走线12直接接触连接。氧化防护层16的材质可以包括镍，例如，氧化防护层16的材质可以为镍金(NiAu)层。氧化防护层16的厚度可以为4μm～5μm(包括端点值)。
在一个实施例中，在对金属走线12暴露的表面进行化学镍金工艺之前，布线基板的制备方法还可以包括：采用酸洗制程，对通过第一开孔150暴露的金属走线12表面进行酸洗。通过控制酸洗的时间，可以控制酸与金属走线12反应的厚度，这样就可以去除金属走线12表面因为暴露在空气中而被氧化的成分，有利于确保金属走线12的电气连接可靠性和低电阻特性。在图1～图3所示的实施例中，合金层的厚度较薄，采用酸洗制程后，金属走线12中被第一开孔暴露的合金层122可能全部或部分被腐蚀去除，从而氧化防护层16可以直接与主体金属层121接触连接。
本公开实施例中，形成布线基板只需要采用一个掩膜，不仅得到了预设厚度的金属走线，而且对金属走线起到了至少两重保护，避免了金属走线在制程过程中的水氧侵蚀，提高了产品性能、降低了成本。
在本说明书的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”、“轴向”、“径向”、“周向”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特 定的方位构造和操作，因此不能理解为对本公开的限制。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者多个该特征。在本公开的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接，还可以是通信；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
上文的公开提供了许多不同的实施方式或例子用来实现本公开的不同结构。为了简化本公开，上文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本公开。此外，本公开可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到其各种变化或替换，这些都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (20)

  1. 一种布线基板，包括：
    衬底；
    多条金属走线，位于所述衬底的一侧；
    绝缘层，与所述多条金属走线位于所述衬底的同一侧，所述绝缘层位于所述金属走线之外的区域和所述金属走线的部分表面，所述绝缘层的远离所述衬底的表面与所述衬底之间的距离大于所述金属走线的远离所述衬底的表面与所述衬底之间的距离，所述绝缘层的远离所述衬底的表面能够反射光线，所述绝缘层中具有第一开孔，所述第一开孔暴露所述金属走线的部分表面。
  2. 根据权利要求1所述的布线基板，其中，所述绝缘层的材质为白色油墨，所述绝缘层在所述第一开孔之外的位置覆盖所述金属走线。
  3. 根据权利要求1所述的布线基板，其中，所述绝缘层包括光刻胶层和反射层，所述光刻胶层位于所述金属走线之外的区域，所述第一开孔包括第一子开孔，所述第一子开孔贯穿所述光刻胶层；
    所述反射层至少位于所述光刻胶层的远离所述衬底一侧的表面。
  4. 根据权利要求3所述的布线基板，其中，所述反射层覆盖所述光刻胶层和所述金属走线，所述第一开孔包括第二子开孔，所述第二子开孔贯穿所述反射层，所述第二子开孔在所述衬底上的正投影与所述第一子开孔在所述衬底上的正投影存在交叠区域。
  5. 根据权利要求4所述的布线基板，其中，所述反射层的材质为白色油墨。
  6. 根据权利要求1所述的布线基板，其中，所述金属走线包括层叠设置的主体金属层和合金层，所述合金层位于所述主体金属层的远离所述衬底的表面。
  7. 根据权利要求1所述的布线基板，其中，所述金属走线的厚度的范围为5μm～8.5μm。
  8. 根据权利要求1所述的布线基板，还包括氧化防护层，所述氧化防护层位于所述金属走线的暴露区域，所述氧化防护层与所述金属走线直接接触，所述氧化防护层的材质包括镍和金，所述氧化防护层的厚度范围为4μm～5μm。
  9. 根据权利要求1所述的布线基板，还包括无机保护层，所述无机保护层覆盖所述金属走线和所述衬底的外露表面，所述绝缘层位于所述无机保护层的背离所述衬底的一侧，所述无机保护层中具有第二开孔，所述第二开孔在所述衬 底上的正投影与所述第一开孔在所述衬底上的正投影存在交叠区域。
  10. 根据权利要求9所述的布线基板，其中，所述无机保护层的材质包括硅氧化物、硅氮化物和氮氧化硅中的一种或多种。
  11. 根据权利要求1至10任一项所述的布线基板，其中，所述多条金属走线包括：电源信号线、地址信号线、公共电压信号线、级联线和反馈信号线；
    所述多条金属线通过所述第一开孔暴露的表面形成多个第一焊盘组和多个第二焊盘组，所述第一焊盘组用于与微型驱动芯片耦接，所述第二焊盘组用于与发光元件耦接；
    每个所述第一焊盘组包括供电焊盘、输出焊盘、地址焊盘和接地焊盘，所述供电焊盘与所述电源信号线连接，所述接地焊盘与所述公共电压信号线连接，所述输出焊盘与一个所述第二焊盘组中的至少一个焊盘连接；
    所述多个第一焊盘组级联，多级所述第一焊盘组中，第一个第一焊盘组的地址焊盘与所述地址信号线连接，最后一个第一焊盘组的输出焊盘与所述反馈信号线连接，第n级第一焊盘组的输出焊盘与第(n+1)级第一焊盘组的地址焊盘通过一根所述级联线连接，其中，n为正整数。
  12. 一种布线基板的制备方法，包括：
    在衬底的一侧形成多条金属走线；
    在所述衬底的形成有所述金属走线的一侧形成绝缘层，所述绝缘层位于所述金属走线之外的区域和所述金属走线的部分表面，所述绝缘层的远离所述衬底一侧的表面与所述衬底之间的距离大于所述金属走线的远离所述衬底一侧的表面与所述衬底之间的距离，所述绝缘层的远离所述衬底的表面能够反射光线，所述绝缘层中具有第一开孔，所述第一开孔暴露所述金属走线的部分表面。
  13. 根据权利要求12所述的方法，其中，所述在衬底的一侧形成多条金属走线，包括：
    在所述衬底的一侧形成预设厚度的主体金属薄膜；
    在所述主体金属薄膜远离所述衬底的表面沉积合金薄膜，得到包括所述主体金属薄膜和所述合金薄膜的金属薄膜；
    在所述金属薄膜的背离所述衬底的一侧涂覆第一光刻胶，采用第一掩膜对所述第一光刻胶进行曝光和显影，形成间隔设置的多个第一光刻胶体；
    对所述第一光刻胶体之外的金属薄膜进行刻蚀，并剥离所述第一光刻胶体， 得到所述多条金属走线。
  14. 根据权利要求13所述的方法，其中，所述在所述衬底的一侧形成预设厚度的主体金属薄膜，包括：
    多次采用沉积工艺，在所述衬底的一侧形成预设厚度的主体金属薄膜；或者，
    在所述衬底的一侧沉积第一金属薄膜，采用电镀工艺在所述第一金属薄膜的远离所述衬底的表面形成第二金属薄膜，得到预设厚度的主体金属薄膜，所述主体金属薄膜包括层叠设置的第一金属薄膜和第二金属薄膜。
  15. 根据权利要求13或14所述的方法，其中，所述绝缘层为白色油墨，在所述衬底的朝向所述金属走线的一侧形成绝缘层，包括：
    在所述衬底的朝向所述金属走线的一侧沉积无机保护层，所述无机保护层覆盖所述金属走线和所述衬底；
    采用网版印刷工艺，在所述无机保护层的背离所述衬底的一侧形成白色油墨，所述白色油墨设置有所述第一开孔；
    采用网印湿刻工艺，在所述无机保护层形成第二开孔。
  16. 根据权利要求13或14所述的方法，其中，所述绝缘层包括光刻胶层和反射层，所述第一开孔包括第一子开孔和第二子开孔，在所述衬底的朝向所述金属走线的一侧形成绝缘层，包括：
    在所述衬底的朝向所述金属走线的一侧涂覆第二光刻胶，采用所述第一掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层，所述镂空区构成第一子开孔，所述第二光刻胶与所述第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶；
    采用网版印刷工艺，在所述光刻胶层的远离所述衬底的一侧形成反射层，所述反射层设置有第二子开孔，所述第二子开孔在所述衬底上的正投影与所述第一子开孔在所述衬底上的正投影存在交叠区域。
  17. 根据权利要求13或14所述的方法，其中，所述绝缘层包括光刻胶层和反射层，所述第一开孔包括第一子开孔和第二子开孔，在所述衬底的朝向所述金属走线的一侧形成绝缘层，包括：
    在所述衬底的朝向所述金属走线的一侧沉积无机保护层，所述无机保护层覆盖所述金属走线和所述衬底；
    在所述衬底的朝向所述无机保护层的一侧涂覆第二光刻胶，采用所述第一 掩膜形成光刻胶图案区和镂空区，光刻胶图案区的第二光刻胶构成光刻胶层，所述镂空区构成所述第一子开孔，所述第二光刻胶与所述第一光刻胶中的一个为正性光刻胶，另一个为负性光刻胶；
    采用网印湿刻工艺，去除暴露出的无机保护层的至少一部分而形成第二开孔；
    采用网版印刷工艺，在所述光刻胶层的远离所述衬底的一侧形成反射层，所述反射层设置有所述第二子开孔。
  18. 根据权利要求12至14任一项所述的方法，还包括：
    对所述金属走线暴露的表面进行化学镍金工艺。
  19. 一种发光面板，包括权利要求1-11中任一项所述的布线基板、以及多个发光二极管芯片，所述多个发光二极管芯片与所述金属走线对应连接。
  20. 一种显示装置，包括权利要求19所述的发光面板。
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