WO2021199681A1 - 受光素子および電子機器 - Google Patents

受光素子および電子機器 Download PDF

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Publication number
WO2021199681A1
WO2021199681A1 PCT/JP2021/004523 JP2021004523W WO2021199681A1 WO 2021199681 A1 WO2021199681 A1 WO 2021199681A1 JP 2021004523 W JP2021004523 W JP 2021004523W WO 2021199681 A1 WO2021199681 A1 WO 2021199681A1
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WIPO (PCT)
Prior art keywords
region
photoelectric conversion
semiconductor substrate
light receiving
receiving element
Prior art date
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Ceased
Application number
PCT/JP2021/004523
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English (en)
French (fr)
Japanese (ja)
Inventor
英訓 前田
健三 石橋
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Filing date
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Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Priority to CN202180016543.0A priority Critical patent/CN115191034A/zh
Priority to US17/910,920 priority patent/US20230178576A1/en
Priority to EP21781024.1A priority patent/EP4131430A4/en
Priority to JP2022511608A priority patent/JPWO2021199681A1/ja
Publication of WO2021199681A1 publication Critical patent/WO2021199681A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/807Pixel isolation structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/18Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/811Interconnections
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/812Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/199Back-illuminated image sensors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80Constructional details of image sensors
    • H10F39/809Constructional details of image sensors of hybrid image sensors

Definitions

  • This disclosure relates to light receiving elements and electronic devices. More specifically, the present invention relates to a light receiving element that detects light from an object and an electronic device that uses the light receiving element.
  • a light receiving element configured by arranging a plurality of pixels including a photoelectric conversion unit for detecting light from an object.
  • This light receiving element is used, for example, in a distance measuring device that measures a distance to an object. The distance to the object is measured by irradiating the object with light from the attached light source, detecting the light reflected from the object, and measuring the time it takes for the light from the light source to reciprocate between the object and the object. It can be done by doing.
  • a light receiving element used for measuring the distance to such an object needs to detect light with high sensitivity and high speed, and an avalanche photodiode (APD), which is a kind of photodiode as a photoelectric conversion unit, is used.
  • APD avalanche photodiode
  • Diode and Single Photon Avalanche Diode (SPAD) are used. These diodes are photodiodes that perform photoelectric conversion in a state where a reverse bias voltage near the breakdown voltage is applied, and are capable of high-sensitivity and high-speed response.
  • a light receiving element for example, a photodetector in which an APD is arranged on a pixel as a photoelectric conversion unit, a separation region for separating adjacent pixels is provided, and a hole accumulation region is arranged on a side wall of the separation region is used.
  • a photodetector in which an APD is arranged on a pixel as a photoelectric conversion unit, a separation region for separating adjacent pixels is provided, and a hole accumulation region is arranged on a side wall of the separation region is used.
  • the electrons emitted from the interface state formed on the end face of the semiconductor substrate at the boundary of the pixels are captured by the hole storage region, and the dark current caused by the electrons from the interface state can be reduced.
  • the dark current is a current based on the electric charge generated regardless of the incident light, and causes an error (noise) in the sensor output.
  • the above-mentioned conventional technology has a problem of causing crosstalk.
  • the above-mentioned separation region reduces crosstalk by blocking light obliquely incident from adjacent pixels.
  • the separation region is formed on the semiconductor substrate, when the incident light or the light generated by the self-emission of the photoelectric conversion unit is reflected by the wiring layer adjacent to the semiconductor substrate and is incident on the adjacent pixels, these lights are emitted. It cannot block light and causes crosstalk. Therefore, the above-mentioned conventional technique has a problem that a malfunction occurs due to noise.
  • This disclosure was made in view of the above-mentioned problems, and aims to reduce crosstalk.
  • the present disclosure has been made to solve the above-mentioned problems, and the first aspect thereof is a pixel provided on a semiconductor substrate and provided with a photoelectric conversion unit that performs photoelectric conversion of incident light, and the above-mentioned photoelectric conversion.
  • a wiring layer that is connected to the unit to transmit a signal and an insulating layer that insulates the wiring layer are provided and arranged adjacent to a surface of the semiconductor substrate that is the opposite surface of the back surface to which the incident light is incident.
  • the wiring region is arranged on the semiconductor substrate at the boundary between the pixels and penetrates the semiconductor substrate, and the width on the front surface side is wider than the width on the back surface side to separate the photoelectric conversion unit. It is a light receiving element including a separation region.
  • the separation region is formed in a wall shape surrounding the photoelectric conversion portion and has a width in a direction parallel to the surface of the semiconductor substrate whose front surface side is wider than the back surface side. May be done.
  • the separation region may include a wiring region adjacent portion which is arranged adjacent to the wiring region and is formed to have a width wider than the width of the surface side.
  • the separation region may include the wiring region adjacent portion having an inverted tapered cross section.
  • the separation region may include the wiring region adjacent portion having a hemispherical cross section.
  • the separation region may include the wiring region adjacent portion formed from the surface side of the semiconductor substrate.
  • the separation region may be configured in a shape adjacent to the wiring layer.
  • the wiring layer protective film arranged between the separation region and the wiring layer is further provided, and the separation region is adjacent to the wiring layer via the wiring layer protection film. You may.
  • the separation region may be arranged and configured in the groove portion formed in the semiconductor substrate.
  • the separation region may be arranged in the groove portion having a shape in which the width on the front surface side of the semiconductor substrate is wider than the width on the back surface side.
  • the separation region may be formed by arranging a metal in the groove.
  • the separation region may further include an insulating film arranged between the semiconductor substrate and the separation region.
  • the separation region may include the insulating film having a shape in which the film thickness on the front surface side of the semiconductor substrate is thicker than the film thickness on the back surface side.
  • the photoelectric conversion unit may be configured by a photodiode.
  • the photoelectric conversion unit may be composed of the photodiode that multiplies the charge generated by the photoelectric conversion of the incident light by a high reverse bias voltage.
  • the photoelectric conversion unit may be multiplied by the generated charge in a pn junction composed of a p-type semiconductor region and an n-type semiconductor region.
  • the photoelectric conversion unit may include a cathode region composed of the n-type semiconductor region.
  • the photoelectric conversion unit may include the cathode region arranged on the surface side of the semiconductor substrate.
  • the separation region is configured to have a width wider than the width on the back surface side adjacent to the wiring region, and the wiring region is larger than the region in which the charge is multiplied in the photodiode.
  • a wiring region adjacent portion arranged in a region close to the wiring region may be provided.
  • the generated charge is multiplied in the pn junction composed of the p-type semiconductor region and the n-type semiconductor region, and the separation region is the above-mentioned separation region.
  • the wiring region adjacent portion configured at a height from the surface side of the semiconductor substrate lower than the pn junction region may be provided.
  • the photoelectric conversion unit may include an anode region arranged in the vicinity of the separation region on the surface side of the semiconductor substrate.
  • the wiring region may include the wiring layer arranged in the vicinity of the separation region and connected to the anode region.
  • a second aspect of the present disclosure is a pixel provided with a photoelectric conversion unit arranged on a semiconductor substrate and performing photoelectric conversion of incident light, a wiring layer connected to the photoelectric conversion unit to transmit a signal, and the wiring layer.
  • a wiring region provided adjacent to a surface which is a surface opposite to the back surface of the semiconductor substrate to which the incident light is incident, and the semiconductor substrate at the boundary of the pixels.
  • a separation region that is arranged to penetrate the semiconductor substrate and has a width on the front surface side wider than the width on the back surface side to separate the photoelectric conversion unit, and a signal generated based on the photoelectric conversion. It is an electronic device including a processing circuit that performs processing.
  • the photoelectric conversion unit performs photoelectric conversion of the incident light that is reflected by the subject and incident on itself, and the processing circuit performs the photoelectric conversion of the incident light from the light source.
  • the above process for measuring the distance to the subject may be performed by measuring the time from the irradiation of light to the generation of the signal.
  • the processing circuit may perform the above processing for detecting the amount of change in the signal.
  • the processing circuit may detect the amount of change by comparing with a predetermined threshold value.
  • the processing circuit may be arranged on the semiconductor substrate bonded to the semiconductor substrate.
  • FIG. 1 is a diagram showing a configuration example of a light receiving element according to the first embodiment of the present disclosure.
  • FIG. 3 is a plan view showing a configuration example of the light receiving element 2, and is a plan view showing the configuration of a light receiving surface which is a surface on which incident light of the light receiving element 2 is irradiated.
  • the pixel array unit 10 is arranged on the light receiving surface of the light receiving element 2.
  • the pixel array unit 10 is a region arranged in the central portion of the light receiving element 2 and in which pixels for detecting incident light (pixels 100 described later) are arranged in a two-dimensional grid pattern.
  • a photoelectric conversion unit photoelectric conversion unit 101, which will be described later
  • a light receiving signal corresponding to the electric charge generated by the photoelectric conversion of the photoelectric conversion unit 101 is generated and output from the pixel 100.
  • the incident light can be detected by this received signal.
  • a plurality of pad openings 180 are arranged at the end of the light receiving element 2.
  • An electrode pad (electrode pad 148 described later) is arranged at the bottom of the pad opening 180.
  • the light receiving element 2 is configured by laminating two semiconductor chips.
  • FIG. 2 is a diagram showing a configuration example of pixels according to the first embodiment of the present disclosure.
  • FIG. 6 is a plan view showing a configuration example of the pixel 100.
  • the pixels 100 in the figure include semiconductor regions (semiconductor regions 111 and 113) formed on the semiconductor substrate 110, separation regions 150 arranged at the boundary of the pixels 100 and penetrating the semiconductor substrate 110, and wiring layers 122 to 124. Was described.
  • the separation region 150 can be formed in a wall shape.
  • the region with dot hatching represents the semiconductor region 111 and the like
  • the region with hatched diagonal lines represents the wiring layer 122 and the like.
  • the semiconductor region 111 is arranged in the central portion of the pixel 100 and constitutes a cathode region.
  • the semiconductor region 113 is arranged on the peripheral edge of the pixel 100 and constitutes an anode region.
  • the wiring layer 122 constitutes the anode wiring and is connected to the semiconductor region 113.
  • the wiring layer 123 constitutes the cathode wiring and is connected to the semiconductor region 111.
  • the wiring layer 124 is a ground wire for a shield. This shield suppresses the influence of electrical noise.
  • the wiring layer 124 is arranged in the region between the wiring layers 122 and 123.
  • FIG. 3 is a cross-sectional view showing a configuration example of a pixel according to the first embodiment of the present disclosure.
  • FIG. 1 is a cross-sectional view taken along the line aa'in FIG. 1, and is a cross-sectional view showing a configuration example of the light receiving element 2 and the pixel 100.
  • the light receiving element 2 is configured by laminating a sensor chip 191 and a logic chip 192.
  • the sensor chip 191 is a semiconductor chip in which the photoelectric conversion unit 101 described later is arranged.
  • the logic chip 192 is a semiconductor chip in which a processing circuit for processing a signal generated by the photoelectric conversion unit 101 is arranged.
  • the pixel 100 in the figure includes a semiconductor substrate 110, a wiring region 120, a semiconductor substrate 130, a wiring region 140, a separation region 150, a protective film 171 and an on-chip lens 172.
  • the semiconductor substrate 110, the insulating layer 121, and the wiring layers 122 to 124 are arranged on the sensor chip 191.
  • the semiconductor substrate 130, the insulating layer 141, and the wiring layer 142 are arranged on the logic chip 192.
  • the semiconductor substrate 110 is a semiconductor substrate on which a photoelectric conversion unit 101 that performs photoelectric conversion of incident light is arranged.
  • a semiconductor substrate made of silicon (Si) can be used for the semiconductor substrate 110.
  • the photoelectric conversion unit 101 in the figure shows an example configured by SPAD.
  • the photoelectric conversion unit 101 is composed of a well region 111 of the semiconductor substrate 110, an n-type semiconductor region 112 arranged in the well region 111, a p-type semiconductor region 113, and a semiconductor region 114.
  • the n-type semiconductor region 112 constituting the cathode region constitutes a pn junction together with the p-type semiconductor region 113.
  • a reverse bias voltage is applied to this pn junction via the well region 111 to form a depletion layer.
  • the photoelectric conversion of the photoelectric conversion unit 101 in the figure is performed in the well region 111.
  • the electrons of the charge generated by the photoelectric effect reach the depletion layer of the pn junction by drifting, they are accelerated by an electric field based on the reverse bias voltage.
  • a reverse bias voltage exceeding the breakdown voltage is applied to the photoelectric conversion unit 101 constituting the SPAD.
  • a reverse bias voltage of approximately 20 V is applied.
  • the strong electric field due to this reverse bias voltage causes electron avalanche, and electron avalanche occurs continuously, and the electric charge increases sharply. Therefore, the photoelectric conversion unit 101 can detect the incident of a single photon. By arranging such a photoelectric conversion unit 101, a highly sensitive pixel 100 can be configured.
  • the region near the pn junction at the interface between the semiconductor regions 112 and 113 is a region in which charge multiplication is performed, and is referred to as a multiplication region.
  • the p-type semiconductor region 114 is arranged adjacent to the well region 111 and constitutes an anode region.
  • the p-type semiconductor region 114 is configured to surround the well region 111 in the vicinity of the n-type semiconductor region 112.
  • the semiconductor substrate 110 is configured to have a relatively thick film thickness. This is to improve the sensitivity of the photoelectric conversion unit 101 by forming the well region 111 constituting the SPAD thickly.
  • the semiconductor substrate 110 can be configured to have a thickness of, for example, several ⁇ m.
  • the well region 111 is arranged on the back surface side of the semiconductor substrate 110, and the incident light is incident from the back surface side of the semiconductor substrate 110.
  • the back surface of the semiconductor substrate 110 corresponds to a light incident surface.
  • a wiring region 120 which will be described later, is arranged on the surface opposite to the back surface of the semiconductor substrate 110.
  • the semiconductor regions 112 and 114 constituting the cathode region and the anode region, respectively, are arranged on the surface side of the semiconductor substrate 110.
  • the configuration of the photoelectric conversion unit 101 is not limited to this example.
  • the conductive types of the semiconductor regions 112, 113, and 114 may be interchanged. Specifically, a configuration using the p-type semiconductor region 112 and the n-type semiconductor regions 113 and 114 can be adopted. In this case, the semiconductor region 112 becomes the anode region, and the semiconductor region 114 becomes the cathode region. Further, the hole storage area 115, which will be described later, is changed to the electron storage area 115.
  • the electron storage region 115 is a region formed of an n-type semiconductor to store electrons.
  • the conductive type in the semiconductor region may be described as a first conductive type and a second conductive type instead of the p-type and the n-type.
  • a hole storage region 115 can be arranged on the semiconductor substrate 110 adjacent to the separation region 150, which will be described later.
  • the hole storage region 115 captures electrons emitted from the interface state formed on the end face of the semiconductor substrate.
  • the hole storage region 115 can be configured by a p-type semiconductor region. Electrons from the interface state are captured by recombination with holes accumulated in the hole storage region 115.
  • the hole storage region 115 By arranging the hole storage region 115, the dark current caused by electrons from the interface state can be reduced. In addition, if the electrons from the interface state are accelerated and multiplied, a malfunction occurs.
  • the hole storage region 115 in the figure is arranged adjacent to the semiconductor region 114 constituting the anode and is electrically connected to the anode.
  • the hole storage region can be further arranged at the interface on the back surface side of the semiconductor substrate 110.
  • the wiring area 120 is an area arranged on the surface side of the semiconductor substrate 110 and where the wiring for transmitting a signal to the photoelectric conversion unit 101 or the like is arranged.
  • An insulating layer 121 and wiring layers 122 to 124 are arranged in the wiring region 120.
  • the wiring layers 122 to 124 are wirings for transmitting signals and the like of the photoelectric conversion unit 101.
  • the wiring layer 122 or the like can be made of a metal such as copper (Cu).
  • the insulating layer 121 insulates the wiring layer 122 and the like.
  • the insulating layer 121 can be made of, for example, silicon oxide (SiO 2 ).
  • a contact plug 125 for connecting the semiconductor region of the semiconductor substrate 110 and the wiring layer 122 is further arranged in the wiring region 120.
  • the wiring layer 122 is connected to the semiconductor region 114 constituting the anode region of the photoelectric conversion unit 101 via the contact plug 125.
  • the wiring layer 123 is connected to the semiconductor region 112 that constitutes the cathode region.
  • the contact plug 125 can be made of, for example, tungsten (W).
  • the wiring layer 122 in the figure shows an example in which the wiring layer 122 is arranged in the wiring region 120 directly below the separation region 150.
  • Pad 127 and via plug 126 are further arranged in the wiring area 120.
  • the pad 127 is an electrode arranged on the surface of the wiring region 120.
  • the pad 127 can be made of, for example, Cu.
  • the via plug 126 connects the wiring layer 122 and the like and the pad 127.
  • the via plug 126 can be made of, for example, Cu. Note that the figure shows an example in which the wiring layers 122 to 124 are arranged in the same layer of the wiring area 120.
  • the wiring area 120 can have a configuration having a plurality of wiring layers, and the wiring layers 122 to 124 can be arranged in different layers of the wiring area 120. Wirings arranged in different layers can be connected by via plugs.
  • the semiconductor substrate 130 is a semiconductor substrate bonded to the semiconductor substrate 110.
  • the semiconductor substrate 130 can be formed with a diffusion region of an element such as a processing circuit that processes a signal generated by the photoelectric conversion unit 101.
  • the wiring area 140 is a wiring area arranged on the surface side of the semiconductor substrate 130.
  • a wiring layer 142 and an insulating layer 141 are arranged in the wiring region 140.
  • a pad 147 is arranged on the surface of the wiring region 140 and is connected to the wiring layer 142 by a via plug 146. Further, the wiring layer 142 and the semiconductor substrate 130 are connected by a contact plug 145.
  • the sensor chip 191 is attached to the logic chip 192, the pad 147 and the pad 127 are joined. Signals can be exchanged between the elements arranged on the semiconductor substrates 110 and 130 via the pads 147 and 127. It is possible to configure the wiring that connects the photoelectric conversion unit and the above-mentioned processing circuit.
  • the wiring that electrically connects the photoelectric conversion unit 101 and the circuit can be arranged in the wiring areas 120 and 140. Further, in the wiring regions 120 and 140, wiring layers constituting an optical shield that reflects the incident light transmitted through the semiconductor substrate 110 and causes the incident light to enter the semiconductor substrate 110 again can be arranged.
  • the separation region 150 is arranged on the semiconductor substrate 110 at the boundary of the pixel 100 to separate the photoelectric conversion unit 101.
  • the separation region 150 is formed in a wall shape surrounding the pixel 100, and separates the photoelectric conversion unit 101 between the adjacent pixels 100. Further, the separation region 150 is formed in the shape of a wall whose width in the direction parallel to the surface of the semiconductor substrate 110 is wider on the front surface side than on the back surface side. Further, the separation region 150 further shields the incident light. The incident light obliquely incident through the adjacent pixels 100 is blocked by the separation region 150. Thereby, the occurrence of crosstalk can be reduced. As described in FIG. 2, the separation regions 150 are arranged in a grid pattern.
  • the separation region 150 can be formed by embedding a metal film such as W or aluminum (Al) in a groove formed through the semiconductor substrate 110.
  • the protective film 171 is arranged on the back surface side of the semiconductor substrate 110 to protect the semiconductor substrate 110.
  • the protective film 171 can be made of, for example, SiO 2 .
  • a fixed charge film can also be arranged between the semiconductor substrate 110 and the protective film 171.
  • This fixed charge film is a film having a fixed charge that is arranged on the surface of the semiconductor substrate 110 and pins the interface state of the semiconductor substrate 110.
  • the fixed charge film may be composed of, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ) and titanium oxide (TIO 2 ). can.
  • a fixed charge film can also be arranged in the groove of the semiconductor substrate 110 in which the separation region 150 is arranged. Further, an insulating film that insulates the separation region 150 made of metal can be arranged adjacent to the separation region 150. This insulating film can also be formed at the same time as the protective film 171 described above.
  • the on-chip lens 172 is a lens that collects incident light.
  • the on-chip lens 172 is formed in a hemispherical shape and is arranged on the back surface side of the semiconductor substrate 110, and collects the incident light on the photoelectric conversion unit 101.
  • the on-chip lens 172 can be made of an inorganic material such as silicon nitride (SiN) or an organic material such as an acrylic resin.
  • An electrode pad 148 and a pad opening 180 are arranged at the end of the light receiving element 2.
  • the electrode pad 148 is an electrode for transmitting a signal between the light receiving element 2 and an electronic circuit outside the light receiving element 2.
  • the electrode pad 148 is arranged in the wiring region of the logic chip 192 and is connected to the wiring layer 142.
  • the pad opening 180 is formed in a hole shape penetrating the surface side of the insulating layer 141 of the sensor chip 191 and the logic chip 192, and is configured to reach the surface of the electrode pad 148 from the light receiving surface of the light receiving element 2. By wire bonding to the electrode pad 148 via the pad opening 180, the electrode pad 148 and an external electronic circuit can be electrically connected.
  • the electrode pad 148 can be made of, for example, a metal such as Al or Au.
  • a separation region 150a can be arranged around the pad opening 180.
  • the separation region 150a is configured to surround the pad opening 180 and separates the pad opening 180.
  • the separation region 150b can be arranged on the semiconductor substrate 110 at the end of the sensor chip 191.
  • the separation region 150b is a separation region arranged along the outer circumference of the semiconductor substrate 110.
  • the configuration of the pixel 100 is not limited to this example.
  • a separation region for separating each photoelectric conversion unit can be arranged inside the pixel 100.
  • the separation region that separates the photoelectric conversion unit can be configured to penetrate the semiconductor substrate 110.
  • a separation region can be arranged between the semiconductor substrate 110 at the boundary of the plurality of photoelectric conversion units and the on-chip lens 172. This separation region is a separation region that shields the boundary region of the photoelectric conversion unit from light, and can be formed of a metal film or the like.
  • the separation region is arranged only at the boundary of the pixel 100.
  • FIG. 4 is a cross-sectional view showing a configuration example of a separation region according to the first embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view showing a configuration example of the separation region 150 described in FIG. The details of the configuration of the separation region 150 will be described with reference to the figure.
  • the separation region 150 separates the photoelectric conversion unit 101 arranged at the boundary of the pixel 100 and arranged on the semiconductor substrate 110.
  • the separation region 150 in the figure is composed of a metal film 154 arranged in the groove portion 151 formed in the semiconductor substrate 110.
  • the metal film 154 can be formed of W or the like.
  • the metal film 154 in the figure shows an example in which a gap 155 is formed in the central portion.
  • the groove portion 151 is configured such that the width of the semiconductor substrate 110 on the front surface side is wider than the width on the back surface side.
  • the groove portion 151 is configured to penetrate from the back surface side to the front surface side of the semiconductor substrate 110.
  • the groove portion 151 can be formed by etching the semiconductor substrate 110 from the back surface side toward the front surface side. This etching can be performed by, for example, anisotropic dry etching.
  • the fixed charge film 152 is arranged on the back surface side of the semiconductor substrate 110 and the wall surface of the groove portion 151 in the figure.
  • the fixed charge film 152 can be formed by forming a material film such as HfO 2 into a film by, for example, ALD (Atomic Layer Deposition).
  • An insulating film 153 is arranged between the fixed charge film 152 and the metal film 154.
  • the insulating film 153 can be formed by forming, for example, a material film such as SiO 2 by CVD (Chemical Vapor Deposition).
  • the groove portion 151 in the figure is configured so that the width on the front surface side and the width on the back surface side of the semiconductor substrate 110 are different. Specifically, the width of the semiconductor substrate 110 on the front surface side is wider than the width on the back surface side. Therefore, also in the insulating film 153 and the metal film 154 in the figure, the width on the front surface side and the width on the back surface side are configured to be different, and the width on the front surface side of the semiconductor substrate 110 is configured to be wider than the width on the back surface side. Will be done.
  • the shape of the groove portion 151 in the figure can be formed by increasing the amount of overetching when etching the vicinity of the surface side of the semiconductor substrate 110.
  • the incident light 401 in the figure represents the incident light that is blocked at the bottom of the separation region 150.
  • a region having a width wider than the back surface side of the semiconductor substrate 110 adjacent to the wiring region 120 of the separation region 150 will be referred to as a wiring region adjacent portion 160.
  • the incident light 401 is shielded by the wiring region adjacent portion 160.
  • the incident light 401 is shielded from light by reflecting or absorbing the incident light by the insulating film 153 or the metal film 154. As a result, crosstalk can be reduced.
  • the dotted arrow in the figure shows the locus of the incident light 401 when there is no wiring area adjacent portion 160.
  • the light obliquely incident on the bottom of the separation region 150 is reflected by the wiring layer 122 immediately below the separation region 150 and incident on the photoelectric conversion portion 101 of the adjacent pixel 100.
  • This causes crosstalk between adjacent pixels 100.
  • the wiring area adjacent portion 160 in the figure represents an example of the wiring region adjacent portion 160 having an inverted tapered cross section.
  • the wiring region adjacent portion 160 can also be arranged in the separation regions 150a and 150b described with reference to FIG.
  • FIG. 5 is a cross-sectional view showing another configuration example of the separation region according to the first embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. It differs from the separation region 150 in FIG. 4 in that the wiring region adjacent portion 160 is formed in a hemispherical shape.
  • the light-shielding area can be widened, and crosstalk can be further reduced.
  • the shape of the groove portion 151 in the figure can be formed by further increasing the amount of overetching when etching the vicinity of the surface side of the semiconductor substrate 110.
  • the separation region 150 is arranged in the groove portion 151 formed from the back surface side of the semiconductor substrate 110.
  • the separation region 150 is arranged in the grooves formed on the front surface side and the back surface side of the semiconductor substrate 110, and the above-mentioned first embodiment is described above. It is different from the form of.
  • FIG. 6 is a cross-sectional view showing a configuration example of the separation region according to the second embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. It differs from the separation region 150 described with reference to FIG. 4 in that the wiring region adjacent portion 161 is arranged instead of the wiring region adjacent portion 160.
  • the wiring region adjacent portion 161 in the figure is arranged in the groove portion 162 formed from the surface side of the semiconductor substrate 110.
  • the groove portion 162 is configured to have a width wider than that of the groove portion 151.
  • the wiring region adjacent portion 161 can be formed.
  • the insulating layer 121, the wiring layer 122, and the like are formed to arrange the wiring region 120.
  • the separation region 150 in the figure can be formed by forming the groove portion 151 having a depth reaching the metal film 164 from the back surface side of the semiconductor substrate 110 and arranging the insulating film 153 and the metal film 154.
  • the groove portion 162 is formed in a process different from that of the groove portion 151, the groove portion 162 having an arbitrary width can be formed. Compared with the case where the groove portions 151 having different widths are formed by adjusting the amount of overetching, the manufacturing process of the groove portion 162 of the wiring region adjacent portion 161 can be simplified.
  • the configuration of the light receiving element 2 other than this is the same as the configuration of the light receiving element 2 described in the first embodiment of the present disclosure, the description thereof will be omitted.
  • the groove portion 162 of the wiring region adjacent portion 161 is formed from the surface side of the semiconductor substrate 110, so that the manufacturing process can be simplified. ..
  • the bottom portion of the separation region 150 is arranged on the surface side of the semiconductor substrate 110.
  • the light receiving element 2 of the third embodiment of the present disclosure is different from the above-described first embodiment in that the bottom portion of the separation region 150 is arranged inside the wiring region 120.
  • FIG. 7 is a cross-sectional view showing a configuration example of a separation region according to a third embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. It differs from the separation region 150 described in FIG. 4 in that the bottom of the separation region 150 is arranged adjacent to the wiring layer 122.
  • the separation region 150 in the figure has a configuration in which the insulating film 153 is arranged between the wiring layer 122 and the metal film 154. As a result, the wiring region adjacent portion 161 can be brought close to the wiring layer 122 while insulating between the wiring layer 122 and the metal film 154. Leakage of incident light via the wiring layer 122 can be further reduced.
  • FIG. 8 is a cross-sectional view showing another configuration example of the separation region according to the third embodiment of the present disclosure.
  • FIG. 7 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. 7. It differs from the separation region 150 described with reference to FIG. 7 in that the wiring layer protective film 156 is arranged between the bottom of the separation region 150 and the wiring layer 122.
  • the wiring layer protective film 156 is arranged between the separation region 150 and the wiring layer 122 to protect the wiring layer 122. As described above, the groove portion 151 is formed by etching the semiconductor substrate 110. The wiring layer protective film 156 protects the wiring layer 122 by suppressing etching of the insulating layer 121 adjacent to the wiring layer 122 during this etching.
  • the wiring layer protective film 156 can be composed of a member called an etching stopper, which has a high selection ratio with respect to SiO 2, which is an object to be etched.
  • the wiring layer protective film 156 is composed of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), carbon (C), W, titanium (Ti), titanium nitride (TiN) and the like. can do.
  • the separation region 150 in the figure is arranged adjacent to the wiring layer 122 via the wiring layer protective film 156.
  • the configuration of the light receiving element 2 other than this is the same as the configuration of the light receiving element 2 described in the first embodiment of the present disclosure, the description thereof will be omitted.
  • the separation region 150 is arranged adjacent to the wiring layer 122. As a result, leakage of incident light via the wiring layer 122 can be further reduced.
  • the wiring region adjacent portion 160 is arranged at the bottom of the separation region 150.
  • the light receiving element 2 of the fourth embodiment of the present disclosure is different from the above-described first embodiment in that the region of the wiring region adjacent portion 160 is limited.
  • FIG. 9 is a cross-sectional view showing a configuration example of a separation region according to a fourth embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. It differs from the separation region 150 of FIG. 4 in that the wiring region adjacent portion 160 is arranged in a region closer to the wiring region 120 than the charge multiplication region in the photoelectric conversion unit 101.
  • the description of the semiconductor region 114 and the hole storage region 115 is omitted.
  • the wiring region adjacent portion 160 in the figure can be configured so that the height from the surface side of the semiconductor substrate 110 is lower than the semiconductor region 113 of the photoelectric conversion unit 101 constituting the SPAD.
  • the wiring region adjacent portion 160 is configured to have a height lower than the interface on the side where the incident light of the semiconductor region 113 is incident, preferably a height lower than the pn junction region of the interfaces of the semiconductor regions 112 and 113. can do.
  • the n-type semiconductor region 112 and the p-type semiconductor region 113 constituting the cathode region form a pn junction. When a reverse bias voltage is applied to this pn junction, a depletion layer is formed in the region of the semiconductor region 113, and the charge is multiplied.
  • the wiring region adjacent portion 160 When the wiring region adjacent portion 160 is arranged in the vicinity of such a multiplication region, the semiconductor region that contributes to the charge multiplication becomes narrow. Therefore, the sensitivity of the pixel 100 is lowered. Therefore, it is possible to prevent a decrease in the sensitivity of the pixel 100 by configuring the wiring region adjacent portion 160 so as not to cover the multiplication region.
  • the configuration of the light receiving element 2 other than this is the same as the configuration of the light receiving element 2 described in the first embodiment of the present disclosure, the description thereof will be omitted.
  • the pixel 100 is arranged by arranging the wiring region adjacent portion 160 in a region closer to the wiring region 120 than the multiplication region of the photoelectric conversion portion 101. It is possible to prevent a decrease in the sensitivity of the.
  • the width of the front surface side of the semiconductor substrate 110 of the metal film 154 of the separation region 150 is wider than that of the back surface side, but the width is the same as that of the back surface side. You may.
  • FIG. 10 is a cross-sectional view showing a configuration example of a separation region according to a modified example of the embodiment of the present disclosure.
  • FIG. 4 is a cross-sectional view showing a configuration example of the separation region 150, as in FIG. It differs from the separation region 150 of FIG. 4 in that a metal film 154 having the same width is arranged on the front surface side and the back surface side of the semiconductor substrate 110. Further, the insulating film 153 is configured such that the film thickness on the front surface side is thicker than the film thickness on the back surface side.
  • the metal film 154 may have a configuration in which the width of the front surface side of the semiconductor substrate 110 is narrower than that of the back surface side.
  • the configuration of the light receiving element 2 other than this is the same as the configuration of the light receiving element 2 described in the first embodiment of the present disclosure, the description thereof will be omitted.
  • a photoelectric conversion unit 101 composed of a photodiode that multiplies the charge generated by photoelectric conversion such as SPAD or APD by a reverse bias voltage is used.
  • the light receiving element 2 of the fifth embodiment of the present disclosure is different from the above-described first embodiment in that a photoelectric conversion unit composed of a normal photodiode is used.
  • FIG. 11 is a cross-sectional view showing a configuration example of a pixel according to a fifth embodiment of the present disclosure. Similar to FIG. 3, FIG. 3 is a cross-sectional view showing a configuration example of the pixel 100. It differs from the pixel 100 in FIG. 3 in that the photoelectric conversion unit 201 composed of the photodiode is arranged.
  • the photoelectric conversion unit 201 in the figure is composed of a p-type well region 111 of the semiconductor substrate 110 and an n-type semiconductor region 116 arranged in the well region 111.
  • a photodiode composed of a pn junction at the interface between the n-type semiconductor region 116 and the surrounding p-type well region 111 corresponds to the photoelectric conversion unit 201.
  • the well region 111 and the semiconductor region 116 form an anode region and a cathode region, respectively.
  • the semiconductor region 117 and the semiconductor region 118 are further arranged on the semiconductor substrate 110 in the figure.
  • the semiconductor region 117 is an n-type semiconductor region having a relatively high impurity concentration, and is a semiconductor region arranged adjacent to the semiconductor region 116 and electrically connected.
  • a contact plug 125 is connected to the semiconductor region 117.
  • the semiconductor region 118 is a semiconductor region composed of a p-type relatively high impurity concentration, and is a semiconductor region arranged adjacent to a well region and electrically connected.
  • the contact plug 125 is also connected to the semiconductor region 118.
  • the semiconductor region 118 is a semiconductor region that constitutes a so-called well contact.
  • Wiring layers 122 and 123 are arranged in the wiring area 120.
  • the wiring layer 122 is connected to the well region 111 forming the anode region via the contact plug 125 and the semiconductor region 118.
  • the wiring layer 123 is connected to the semiconductor region 116 constituting the cathode region via the contact plug 125 and the semiconductor region 117. Further, the wiring layer 124 is omitted.
  • the wiring region adjacent portion 160 wiring layer protective film 156 described in FIG. 4 is arranged, and crosstalk is reduced.
  • the configuration of the light receiving element 2 other than this is the same as the configuration of the light receiving element 2 described in the first embodiment of the present disclosure, the description thereof will be omitted.
  • the width of the separation region 150 on the surface side is widened. , The light leaking to the adjacent pixel 100 can be shielded. As a result, crosstalk can be reduced.
  • the technology according to the present disclosure can be applied to various products.
  • the technique according to the present disclosure may be applied to a distance measuring device.
  • the distance measuring device is a device that measures the distance to an object.
  • FIG. 12 is a diagram showing a configuration example of a light receiving element according to a distance measuring device to which the technique according to the present disclosure can be applied.
  • the light receiving element 2 in the figure includes a pixel array unit 10, a bias power supply unit 20, and a light receiving signal processing unit 30.
  • the pixel array unit 10 is configured by arranging a plurality of pixels 100 having a photoelectric conversion unit that performs photoelectric conversion of incident light in a two-dimensional grid pattern.
  • the pixel 100 detects incident light and outputs a received signal as a detection result.
  • APD or SPAD can be used for the photoelectric conversion unit.
  • SPAD is arranged in the pixel 100 as a photoelectric conversion unit.
  • Signal lines 21 and 31 are connected to each pixel 100.
  • the signal line 21 is a signal line that supplies the bias voltage of the pixel 100.
  • the signal line 31 is a signal line that transmits a received signal from the pixel 100.
  • the pixel array unit 10 in the figure describes an example in which the pixels 100 are arranged in 4 rows and 5 columns, the number of pixels 100 arranged in the pixel array unit 10 is not limited.
  • the bias power supply unit 20 is a power supply that supplies a bias voltage to the pixel 100.
  • the bias power supply unit 20 supplies a bias voltage via the signal line 21.
  • the light receiving signal processing unit 30 processes the light receiving signals output from the plurality of pixels 100 arranged in the pixel array unit 10.
  • the process of the light receiving signal processing unit 30 corresponds to, for example, a process of detecting the distance to the object based on the incident light detected by the pixel 100.
  • the light receiving signal processing unit 30 can perform a ToF (Time of Flight) type distance detection process used when measuring a distance to a distant object in an imaging device such as an in-vehicle camera. ..
  • the light source arranged in the image pickup apparatus irradiates the object with light, detects the light reflected by the object, and measures the time for the light from the light source to reciprocate between the object and the object. This is a process of detecting the distance.
  • SPAD capable of high-speed light detection is used.
  • the light receiving signal processing unit 30 is an example of the processing circuit described in the claims.
  • FIG. 13 is a circuit diagram showing a configuration example of pixels according to a distance measuring device to which the technique according to the present disclosure can be applied.
  • FIG. 12 is a circuit diagram showing a configuration example of the pixel 100 described with reference to FIG.
  • the pixel 100 in the figure includes a photoelectric conversion unit 101, a resistor 102, and an inverting buffer 103.
  • the signal line 21 in the figure is composed of a signal line Vbd that applies the yield voltage of the photoelectric conversion unit 101 and a signal line Vd that supplies power for detecting the yield state of the photoelectric conversion unit 101.
  • the anode of the photoelectric conversion unit 101 is connected to the signal line Vbd.
  • the cathode of the photoelectric conversion unit 101 is connected to one end of the resistor 102 and the input of the inverting buffer 103.
  • the other end of the resistor 102 is connected to the signal line Vd.
  • the output of the inverting buffer 103 is connected to the signal line 31.
  • a reverse bias voltage is applied to the photoelectric conversion unit 101 in the figure by the signal line Vbd and the signal line Vd.
  • the resistor 102 is a resistor for performing quenching. This quenching is a process of returning the photoelectric conversion unit 101 in the yield state to the steady state.
  • This quenching is a process of returning the photoelectric conversion unit 101 in the yield state to the steady state.
  • a sudden reverse current flows through the photomultiplier tube 101.
  • the terminal voltage of the resistor 102 increases due to this reverse current. Since the resistor 102 is connected in series with the photoelectric conversion unit 101, a voltage drop is caused by the resistor 102, and the terminal voltage of the photoelectric conversion unit 101 becomes lower than the voltage capable of maintaining the breakdown state. As a result, the photoelectric conversion unit 101 can be returned from the yield state to the steady state.
  • a constant current circuit using a MOS transistor can also be used.
  • the inverting buffer 103 is a buffer that shapes the pulse signal based on the transition and return of the photoelectric conversion unit 101 to the yield state.
  • the inverting buffer 103 generates a light receiving signal based on the current flowing through the photoelectric conversion unit 101 according to the irradiated light and outputs it to the signal line 31.
  • FIG. 14 is a diagram showing a configuration example of an imaging device according to a distance measuring device to which the technique according to the present disclosure can be applied.
  • the figure is a block diagram showing a configuration example of the image pickup device 1 constituting the distance measuring device.
  • the image pickup device 1 in the figure includes a light receiving element 2, a control unit 3, a light source device 4, and a lens 5.
  • the object 601 for distance measurement is shown.
  • the lens 5 is a lens that forms an image of an object on the light receiving element 2.
  • the light receiving element 2 the light receiving element 2 described with reference to FIG. 8 can be used.
  • the light source device 4 emits light to an object for distance measurement.
  • a laser light source that emits infrared light can be used.
  • the control unit 3 controls the entire image pickup apparatus 1. Specifically, the control unit 3 controls the light source device 4 to emit the emitted light 602 to the object 601 and notifies the light receiving element 2 of the start of the emission.
  • the light receiving element 2 notified of the emission of the emitted light 602 detects the reflected light 603 from the object 601 and measures the time from the emission of the emitted light 602 to the detection of the reflected light 603, and the distance to the object 601. To measure.
  • the measured distance is output to the outside of the image pickup apparatus 1 as distance data.
  • the image pickup device 1 is an example of the electronic device described in the claims.
  • DVS Dynamic Vision Sensor
  • FIG. 15 is a diagram showing a configuration example of a light receiving element according to DVS to which the technique according to the present disclosure can be applied.
  • the light receiving element 2 in the figure includes a pixel array unit 10, a row drive circuit 50, a column drive circuit 60, and a signal processing circuit 70.
  • the pixel array unit 10 is configured by arranging a plurality of pixels 100 having a photoelectric conversion unit that performs photoelectric conversion of incident light in a two-dimensional grid pattern.
  • the pixel 100 detects incident light and outputs a detection signal when the detected incident light changes.
  • a photodiode is arranged in the pixel 100 as a photoelectric conversion unit.
  • Signal lines 51, 61 and 71 are connected to each pixel 100.
  • the signal line 51 is a signal line that transmits a row drive signal.
  • the signal line 51 is a signal line that transmits a column drive signal.
  • the signal line 71 is a signal line that transmits a detection signal from the pixel 100.
  • the pixel array unit 10 in the figure describes an example in which the pixels 100 are arranged in 4 rows and 4 columns, the number of pixels 100 arranged in the pixel array unit 10 is not limited.
  • the row drive circuit 50 is a circuit that selects the row address of the pixel array unit 10 and outputs a detection signal to the pixel 100 corresponding to the selected row address.
  • the row drive circuit 50 outputs a control signal (row drive signal) to the signal line 51.
  • the column drive circuit 60 is a circuit that selects the column address of the pixel array unit 10 and outputs a detection signal to the pixel 100 corresponding to the selected column address.
  • the row drive circuit 60 outputs a control signal (row drive signal) to the signal line 61.
  • the signal processing circuit 70 executes predetermined signal processing on the detection signal from the pixel 100.
  • the signal processing circuit 70 generates two-dimensional image data by associating the detection signal with the arrangement of the pixels 100 of the pixel array unit 10, and performs processing such as image recognition.
  • the signal processing circuit 70 is an example of the processing circuit described in the claims.
  • FIG. 16 is a diagram showing a configuration example of pixels according to DVS to which the technique according to the present disclosure can be applied.
  • the pixel 100 in the figure includes a photoelectric conversion unit 201, a current-voltage conversion circuit 210, a buffer 220, a diffifier 230, a quantizer 240, and a transfer circuit 250.
  • the photoelectric conversion unit 201 detects incident light.
  • the photoelectric conversion unit 201 outputs a sink current corresponding to the incident light to the current / voltage conversion circuit 210 in the subsequent stage. Twice
  • the current-voltage conversion circuit 210 is a circuit that converts the output current from the photoelectric conversion unit 201 into a voltage. During this conversion, logarithmic compression is performed and the compressed voltage signal is output to the buffer 220.
  • the buffer 220 is a buffer that amplifies the voltage signal of the current-voltage conversion circuit 210 and outputs it to the differentialr 230 in the subsequent stage.
  • the diffifier 230 detects the amount of change in the voltage signal by detecting the difference in the voltage signal output from the buffer 220.
  • the differencer 230 starts detecting the amount of change in the voltage signal after the row drive signal is input from the row drive circuit 50.
  • the amount of change in the detected voltage signal is output via the signal line 239.
  • the quantizer 240 quantizes the voltage signal from the diffifier 230 and outputs it as a detection signal.
  • the detection signal is output via the signal line 249.
  • the transfer circuit 250 is a circuit that outputs a detection signal to the signal processing circuit 70 based on the column drive signal from the column drive circuit 60.
  • FIG. 17 is a diagram showing a configuration example of a current-voltage conversion circuit according to DVS to which the technique according to the present disclosure can be applied.
  • the figure is a circuit diagram showing a configuration example of the current-voltage conversion circuit 210.
  • the current-voltage conversion circuit 210 in the figure includes MOS transistors 211 to 213 and a capacitor 214.
  • An n-channel MOS transistor can be used for the MOS transistors 211 and 213.
  • a p-channel MOS transistor can be used as the MOS transistor 212.
  • the power supply line Vdd and the power supply line Vbias are arranged in the current-voltage conversion circuit 210 in the figure.
  • the power supply line Vdd is a power supply line that supplies power to the current-voltage conversion circuit 210.
  • the power supply line Vbias is a power supply line that supplies a bias voltage.
  • the photoelectric conversion unit 201 is also shown in the figure.
  • the anode of the photoelectric conversion unit 201 is grounded, and the cathode is connected to the source of the MOS transistor 211, the gate of the MOS transistor 213, and one end of the capacitor 214.
  • the other end of the capacitor 214 is connected to the gate of the MOS transistor 211, the drain of the MOS transistor 212, the drain of the MOS transistor 213, and the signal line 219.
  • the source of the MOS transistor 211 is connected to the power supply line Vdd, and the source of the MOS transistor 213 is grounded.
  • the gate of the MOS transistor 212 is connected to the power supply line Vbias, and the source is connected to the power supply line Vdd.
  • the MOS transistor 211 is a MOS transistor that supplies a current to the photoelectric conversion unit 201.
  • a sink current corresponding to the incident light flows through the photoelectric conversion unit 201.
  • the MOS transistor 211 supplies this sink current.
  • the gate of the MOS transistor 211 is driven by the output voltage of the MOS transistor 213, which will be described later, and outputs a source current equal to the sink current of the photoelectric conversion unit 201. Since the gate-source voltage Vgs of the MOS transistor becomes a voltage corresponding to the source current, the source voltage of the MOS transistor becomes a voltage corresponding to the current of the photoelectric conversion unit 201. As a result, the current of the photoelectric conversion unit 201 is converted into a voltage signal.
  • the MOS transistor 213 is a MOS transistor that amplifies the source voltage of the MOS transistor 211. Further, the MOS transistor 212 constitutes a constant current load of the MOS transistor 213. An amplified voltage signal is output to the drain of the MOS transistor 213. This voltage signal is output to the signal line 219 and fed back to the gate of the MOS transistor 211.
  • the Vgs of the MOS transistor 211 is equal to or less than the threshold voltage
  • the source current changes exponentially with respect to the change of Vgs. Therefore, the output voltage of the MOS transistor 213 fed back to the gate of the MOS transistor 211 becomes a voltage signal in which the output current of the photoelectric conversion unit 201 equal to the source current of the MOS transistor 211 is logarithmically compressed.
  • Capacitor 214 is a capacitor for phase compensation.
  • the capacitor 214 is connected between the drain and the gate of the MOS transistor 213 to perform phase compensation of the MOS transistor 213 constituting the amplifier circuit.
  • FIG. 18 is a diagram showing a configuration example of a diff and a quantizer according to DVS to which the technique according to the present disclosure can be applied.
  • the figure is a circuit diagram showing a configuration example of the difference device 230 and the quantizer 240.
  • the differencer 230 in the figure includes an inverting amplifier 231, capacitors 232 and 233, and a switch 234.
  • the capacitor 232 is connected between the signal line 229 and the input of the inverting amplifier 231.
  • the output of the inverting amplifier 231 is connected to the signal line 239.
  • Capacitors 233 and switches 234 connected in parallel are connected between the inputs and outputs of the inverting amplifier 231.
  • the control input of the switch 234 is connected to the signal line 51.
  • Capacitor 232 is a coupling capacitor that removes the DC component of the voltage signal output from the buffer 220. A signal corresponding to the amount of change in the voltage signal is transmitted by the capacitor 232.
  • the inverting amplifier 231 is an amplifier that charges the capacitor 233 according to the amount of change in the voltage signal transmitted by the capacitor 232.
  • the inverting amplifier 231 and the capacitor 232 form an amplifier circuit, and integrate the amount of change in the voltage signal transmitted by the capacitor 232.
  • the switch 234 is a switch that discharges the capacitor 233. This switch 234 becomes conductive, discharges the capacitor 232, and resets the amount of change in the voltage signal integrated in the capacitor 232 to 0V.
  • the switch 234 is controlled by a row drive signal transmitted by the signal line 51.
  • the diffifier 230 integrates and outputs the amount of change in the voltage signal according to the incident light in the period after being reset by the row drive signal. Thereby, the influence of noise can be reduced.
  • the quantizer 240 includes comparators 241 and 242.
  • the signal line 239 is connected to the non-inverting input of the comparator 241 and the inverting input of the comparator 242.
  • a predetermined threshold voltage Vth1 is applied to the inverting input of the comparator 241, and a predetermined threshold voltage Vth2 is applied to the non-inverting input of the comparator 242.
  • the outputs of the comparators 241 and 242 form a signal line 249, respectively.
  • the comparator 241 compares the threshold voltage Vth1 with the output voltage from the diffifier 230. When the output voltage from the diffifier 230 is higher than the threshold voltage Vth1, the value "1" is output. Twice
  • the comparator 242 compares the threshold voltage Vth2 with the output voltage from the diffifier 230. When the output voltage from the diffifier 230 is lower than the threshold voltage Vth2, the value "1" is output.
  • the signal quantized by the quantizer 240 is input to the transfer circuit 250.
  • the transfer circuit 250 can transfer to the signal processing circuit 70 as a detection signal that the change in the amount of incident light exceeds a predetermined threshold value.
  • the signal processing circuit 70 holds the transfer of the signal as an address event, and causes the row drive unit 50 to output the row drive signal to the pixel 100 to make a differencer. Reset 230.
  • the integration of the amount of change in the voltage signal according to the incident light is restarted.
  • FIG. 19 is a diagram showing a configuration example of an image pickup apparatus according to DVS to which the technique according to the present disclosure can be applied.
  • the figure is a block diagram showing a configuration example of the image pickup apparatus 1 constituting the DVS.
  • the image pickup device 1 in the figure includes a light receiving element 2, a control unit 3, a lens 5, and a recording unit 6.
  • the lens 5 is a lens that forms an image of an object on the light receiving element 2.
  • the light receiving element 2 the light receiving element 2 described with reference to FIG. 11 can be used.
  • the control unit 3 controls the light receiving element 2 to capture image data.
  • the recording unit 6 records image data by the light receiving element 2.
  • the light receiving element 2 can detect a region where the brightness has changed by acquiring the pixel 100 that has detected the address event. By updating only the image data in the region and generating the image data, high-speed imaging can be performed.
  • the image pickup device 1 is an example of the electronic device described in the claims.
  • separation regions 150 of FIGS. 5, 7, 8 and 10 may be applied to the pixel 100 of FIG.
  • the present technology can have the following configurations. (1) A pixel arranged on a semiconductor substrate and having a photoelectric conversion unit that performs photoelectric conversion of incident light, and Adjacent to the surface of the semiconductor substrate, which is the surface opposite to the back surface, which is the surface on which the incident light is incident, is provided with a wiring layer connected to the photoelectric conversion unit to transmit signals and an insulating layer to insulate the wiring layer. And the wiring area to be arranged It is arranged on the semiconductor substrate at the boundary of the pixels, penetrates the semiconductor substrate, and has a shape in which the width on the front surface side is wider than the width on the back surface side, and includes a separation region for separating the photoelectric conversion unit. Light receiving element.
  • the separation region is formed in a wall shape surrounding the photoelectric conversion portion, and has a width in a direction parallel to the surface of the semiconductor substrate whose front surface side is wider than the back surface side (1).
  • the light receiving element according to. (3) The light receiving element according to (1) or (2) above, wherein the separation region includes a wiring region adjacent portion arranged adjacent to the wiring region and having a width wider than the width on the surface side.
  • the separation region includes a portion adjacent to the wiring region having an inverted tapered cross section.
  • the light receiving element according to (9), wherein the separation region is arranged in the groove portion having a shape in which the width of the front surface side of the semiconductor substrate is wider than the width of the back surface side.
  • the separation region is formed by arranging a metal in the groove.
  • the separation region further includes an insulating film arranged between the semiconductor substrate and the separation region.
  • the separation region includes the insulating film having a shape in which the film thickness on the front surface side of the semiconductor substrate is thicker than the film thickness on the back surface side.
  • the photoelectric conversion unit is composed of the photodiode that multiplies the charge generated by the photoelectric conversion of incident light by a high reverse bias voltage.
  • the photoelectric conversion unit is the photomultiplier of the generated charge in a pn junction composed of a p-type semiconductor region and an n-type semiconductor region.
  • the photoelectric conversion unit includes a cathode region composed of the n-type semiconductor region.
  • the separation region is arranged adjacent to the wiring region to have a width wider than the width on the back surface side and is arranged in a region closer to the wiring region than the region in which the charge is multiplied in the photodiode.
  • the photoelectric conversion unit is multiplied by the generated charge in a pn junction composed of a p-type semiconductor region and an n-type semiconductor region.
  • the photoelectric conversion unit includes an anode region arranged in the vicinity of the separation region on the surface side of the semiconductor substrate.
  • the wiring region includes the wiring layer arranged in the vicinity of the separation region and connected to the anode region.
  • the wiring area to be arranged A separation region that is arranged on the semiconductor substrate at the boundary of the pixels, penetrates the semiconductor substrate, and has a shape in which the width of the front surface side is wider than the width of the back surface side to separate the photoelectric conversion unit.
  • An electronic device including a processing circuit that processes a signal generated based on the photoelectric conversion.
  • the photoelectric conversion unit performs photoelectric conversion of the incident light that is reflected by the subject and incident on itself from the light emitted from the light source.
  • the processing circuit detects the amount of change by comparing with a predetermined threshold value.
  • Imaging device 2 Light receiving element 10 Pixel array unit 30
  • Light receiving signal processing unit 70 Signal processing circuit 100 pixels 101, 201 Photoelectric conversion unit 110, 130 Semiconductor substrate 120, 140 Wiring area 121, 141 Insulation layer 122 to 124, 142 Wiring layer 150 , 150a, 150b Separation area 151, 162 Groove 153, 163 Insulation film 154, Metal film 156 Wiring layer protection film 160, 161 Wiring area adjacent part

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PCT/JP2021/004523 2020-03-31 2021-02-08 受光素子および電子機器 Ceased WO2021199681A1 (ja)

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US17/910,920 US20230178576A1 (en) 2020-03-31 2021-02-08 Light receiving element and electronic equipment
EP21781024.1A EP4131430A4 (en) 2020-03-31 2021-02-08 LIGHT RECEIPT ELEMENT AND ELECTRONIC DEVICE
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259639A (zh) * 2022-01-20 2023-06-13 台湾积体电路制造股份有限公司 半导体器件和半导体结构及其形成方法
JP2025513418A (ja) * 2022-04-18 2025-04-24 深▲セン▼鋭視智芯科技有限公司 Evs画素の動作方法及び関連装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12218165B2 (en) * 2021-06-18 2025-02-04 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor image sensor and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006190891A (ja) * 2005-01-07 2006-07-20 Sony Corp 固体撮像素子及び固体撮像素子の製造方法
WO2018150902A1 (ja) * 2017-02-17 2018-08-23 ソニーセミコンダクタソリューションズ株式会社 撮像素子および電子機器
JP2018201005A (ja) 2016-10-18 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 光検出器
WO2019138923A1 (ja) * 2018-01-11 2019-07-18 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、電子機器
WO2019146527A1 (ja) * 2018-01-23 2019-08-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2019155782A1 (ja) * 2018-02-09 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319784A (ja) * 2003-04-16 2004-11-11 Sanyo Electric Co Ltd 固体撮像素子及びその製造方法
KR101232282B1 (ko) * 2011-04-27 2013-02-12 에스케이하이닉스 주식회사 이미지 센서 및 그 제조방법
US9484376B2 (en) * 2014-05-30 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor isolation structure and manufacturing method thereof
CN107949913B (zh) * 2015-09-09 2019-04-19 松下知识产权经营株式会社 固体摄像元件
US10418407B2 (en) * 2015-11-06 2019-09-17 Artilux, Inc. High-speed light sensing apparatus III
KR102430496B1 (ko) * 2017-09-29 2022-08-08 삼성전자주식회사 이미지 센싱 장치 및 그 제조 방법
JP7250427B2 (ja) * 2018-02-09 2023-04-03 キヤノン株式会社 光電変換装置、撮像システム、および移動体
KR102553314B1 (ko) * 2018-08-29 2023-07-10 삼성전자주식회사 이미지 센서
KR102646903B1 (ko) * 2018-09-04 2024-03-12 삼성전자주식회사 이미지 센서

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006190891A (ja) * 2005-01-07 2006-07-20 Sony Corp 固体撮像素子及び固体撮像素子の製造方法
JP2018201005A (ja) 2016-10-18 2018-12-20 ソニーセミコンダクタソリューションズ株式会社 光検出器
WO2018150902A1 (ja) * 2017-02-17 2018-08-23 ソニーセミコンダクタソリューションズ株式会社 撮像素子および電子機器
WO2019138923A1 (ja) * 2018-01-11 2019-07-18 ソニーセミコンダクタソリューションズ株式会社 固体撮像装置、電子機器
WO2019146527A1 (ja) * 2018-01-23 2019-08-01 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子、撮像装置、および、固体撮像素子の制御方法
WO2019155782A1 (ja) * 2018-02-09 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259639A (zh) * 2022-01-20 2023-06-13 台湾积体电路制造股份有限公司 半导体器件和半导体结构及其形成方法
US20230230993A1 (en) * 2022-01-20 2023-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Uniform trenches in semiconductor devices and manufacturing method thereof
US12563852B2 (en) * 2022-01-20 2026-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Uniform trenches in semiconductor devices and manufacturing method thereof
JP2025513418A (ja) * 2022-04-18 2025-04-24 深▲セン▼鋭視智芯科技有限公司 Evs画素の動作方法及び関連装置

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