WO2021190406A1 - 半导体刻蚀方法 - Google Patents

半导体刻蚀方法 Download PDF

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WO2021190406A1
WO2021190406A1 PCT/CN2021/081738 CN2021081738W WO2021190406A1 WO 2021190406 A1 WO2021190406 A1 WO 2021190406A1 CN 2021081738 W CN2021081738 W CN 2021081738W WO 2021190406 A1 WO2021190406 A1 WO 2021190406A1
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ion implantation
mask layer
layer
etching method
etched
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PCT/CN2021/081738
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English (en)
French (fr)
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杨蕾
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长鑫存储技术有限公司
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Publication of WO2021190406A1 publication Critical patent/WO2021190406A1/zh
Priority to US17/501,164 priority Critical patent/US20220037161A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/3115—Doping the insulating layers
    • H01L21/31155—Doping the insulating layers by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Definitions

  • This application relates to the field of semiconductor technology, in particular to a semiconductor etching method.
  • the etching width often ranges from ten nanometers to several hundred nanometers. This leads to the existence of a load effect (aspect ratio dependent etching, ARDE) related to the etching aspect ratio during the etching process of the material layer to be etched, which is mainly manifested in that the material layer to be etched is different
  • ARDE a load effect
  • the etching depth of the pattern of the size is different, the wide pattern is etched deeper, and the narrow pattern is etched shallow.
  • a semiconductor etching method is provided.
  • a semiconductor etching method includes:
  • the ion implantation concentration in each region is proportional to the width of the region, and the material etching removal rate of the region after ion implantation is proportional to The ion implantation concentration in the region is inversely proportional;
  • the region after ion implantation is etched based on the opening pattern into the material layer to be etched to form trenches with the same size as the opening pattern, and the depth of each trench is approximately or the same.
  • the ion implantation concentration in each region is proportional to the width, and after ion implantation
  • the etching removal rate of the region is inversely proportional to the ion implantation concentration, that is, the ion implantation concentration in the region with a larger width is greater than the ion implantation concentration in the region with a smaller width, and the etching removal rate in the region with a larger width
  • the etching removal rate is smaller than the area with a smaller width, which can ensure the uniformity of the etching of the material layer to be etched, so that trenches with different widths but the same depth can be formed in the material layer to be etched.
  • the second mask layer includes a silicon oxynitride layer; the first mask layer includes an amorphous carbon layer, and the implanted ions include carbon-like ions.
  • ion implantation is performed on each of the exposed regions, and the ion implantation time of each of the regions is the same.
  • performing ion implantation on the exposed region based on the opening pattern includes the following steps:
  • a first ion implantation is performed on the exposed region based on the opening pattern, and the first ion implantation process includes performing ion implantation at a first incident angle along a first direction, and the angle of the first incident angle is Is the size of the included angle between the first direction and the normal direction;
  • a second ion implantation is performed on the exposed region based on the opening pattern, and the second ion implantation process includes performing ion implantation at a second incident angle along a second direction, and the second incident angle is Is the angle between the second direction and the normal direction, where,
  • the first direction is different from the second direction, and the angle of the first incident angle is equal to the angle of the second incident angle.
  • the angle of the first incident angle and the angle of the second incident angle are both greater than ⁇ ;
  • h is the thickness of the patterned second mask layer
  • d is the width of the opening pattern with the smallest width.
  • the ion implantation of the exposed region based on the opening pattern includes the following steps:
  • each time a preset time has elapsed, shielding the regions that reach the required ion implantation concentration until all the regions reach the required ion implantation concentration, and ending the ion implantation process includes:
  • the region with the largest opening pattern size reaches the required ion implantation concentration, and the ion implantation process ends.
  • the step of sequentially forming the first mask layer and the second mask layer on the material layer to be etched includes:
  • the above-mentioned semiconductor etching method further includes the step of removing the patterned hard mask layer.
  • the patterned hard mask layer is removed separately or consumed and removed during the patterning process.
  • the hard mask layer includes a tetraethyl orthosilicate hard mask layer.
  • An etch stop layer is provided under the material layer to be etched, and the etch stop layer is adjacent to the material layer to be etched.
  • the material layer to be etched includes a tungsten layer, the etch stop layer includes a silicon nitride layer, and the etching of the trench stops in the silicon nitride layer.
  • the flow rate of the doping gas during the ion implantation process is 10 to 500 sccm.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor structure including a patterned hard mask layer, a mask layer, an amorphous carbon layer, and a material layer to be etched before etching in the prior art;
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure including a patterned mask layer, an amorphous carbon layer, and a material layer to be etched during an etching process in the prior art;
  • FIG. 3 is a schematic cross-sectional view of a material layer to be etched after etching in the prior art
  • FIG. 5 is a schematic cross-sectional structure diagram of a structure obtained by forming a patterned hard mask layer, a second mask layer, a first mask layer, and a material layer to be etched in a semiconductor etching method provided in an embodiment of the application;
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a patterned mask layer, a first mask layer, and a material layer structure to be etched obtained after patterning the cross-sectional structure obtained in FIG. 5 in an embodiment of the application;
  • FIG. 7 is a schematic diagram of a cross-sectional structure when ion implantation is performed on the cross-sectional structure obtained in FIG. 6 in an embodiment of the application;
  • FIG. 8A is a partial structural diagram of the relationship between the ion implantation angle and the minimum opening pattern size width and the thickness of the patterned mask layer when the first ion implantation is performed on the region in an embodiment of the application;
  • 8B is a partial structural schematic diagram of the relationship between the ion implantation angle and the minimum opening pattern size width and the thickness of the patterned mask layer when the second ion implantation is performed on the region in an embodiment of the application;
  • FIG. 9 is a schematic cross-sectional structure diagram of a structure obtained by forming a patterned mask layer, a first mask layer, and a material layer to be etched in a semiconductor etching method provided in an embodiment of the application after ion implantation;
  • FIG. 10 is a schematic diagram of the relationship between the ion implantation concentration and the size and width of the region in the semiconductor etching method provided in an embodiment of the application;
  • FIG. 11 is a material layer to be etched with trenches of the same depth obtained after etching in the semiconductor etching method provided in an embodiment of the application.
  • FIGS. 1 to 3 the conventional semiconductor etching Several schematic cross-sectional structure diagrams of the etching process of the first metal layer in the process.
  • Figure 1 shows a schematic cross-sectional structure diagram of the semiconductor before etching, including the material layer to be etched silicon nitride 10' (SiN), metal Tungsten 20' (W), an amorphous carbon layer 30' (Armorphous Carbon Layer, ACL), a mask layer 40', silicon oxynitride (SiON), and a patterned hard mask layer 50 are sequentially formed on the material layer to be etched 'Tetra-Ethyl-Ortho-Silicate (TEOS), shown in Figure 2, is a schematic diagram of the cross-sectional structure of the semiconductor during the etching process.
  • TEOS tetra-Ethyl-Ortho-Silicate
  • the etching removal rate at the opening of the wider size pattern is relatively narrower
  • the etching removal rate at the pattern opening is faster, which makes the groove depth etched at the opening of the wider pattern always deeper than the groove depth etched at the opening of the narrow pattern during the etching process.
  • the situation is shown in Figure 3.
  • the trenches etched in the material layers 10' and 20' to be etched have obvious patterns in the wide areas and deep in the narrow areas due to the load effect. Shallow etching unevenness problem.
  • the present application provides a semiconductor etching method, which can ensure the etching uniformity of the material layer to be etched.
  • a semiconductor etching method proposed in this application includes:
  • S10 Provide a material layer to be etched
  • S11 sequentially forming a first mask layer and a second mask layer covering the first mask layer on the material layer to be etched; patterning the second mask layer to form openings of different sizes A pattern, the opening pattern enables the first mask layer to expose areas with different sizes;
  • S12 Perform ion implantation on the exposed region based on the opening pattern, the ion implantation concentration in each region is proportional to the width of the region, and the material in the region after ion implantation is etched and removed The rate is inversely proportional to the ion implantation concentration in the region;
  • the ion implantation concentration of each region in the first mask layer is configured to achieve the purpose of adjusting the etching removal rate of each region, so that the etching removal rate of regions with different opening sizes becomes controllable.
  • the size of the opening pattern is divided into three types. Specifically, they can be divided into three widths: large, medium, and small. However, it should be noted that this application does not limit the size of the opening pattern.
  • the second mask layer 40 may include but is not limited to a silicon oxynitride layer (SiON); the first mask layer 30 may include but is not limited to an amorphous carbon layer (ACL), undoped poly layer (un-doped poly), the implanted ions include but are not limited to carbon-like ions (C-like ion).
  • ACL amorphous carbon layer
  • un-doped poly un-doped poly
  • the implanted ions include but are not limited to carbon-like ions (C-like ion).
  • C-like ion carbon-like ions
  • ion implantation is performed on each of the exposed regions at the same time, and the ion implantation time of each region is the same, so that the ion implantation process is simple and efficient.
  • the ion implantation process should preferably be completed in two oblique implants.
  • the ion implantation of the exposed region based on the opening pattern may include the following steps:
  • a first ion implantation is performed on the exposed region based on the opening pattern, and the first ion implantation process includes performing ion implantation at a first incident angle along a first direction, The angle ⁇ 1 of the first incident angle is the angle between the first direction and the normal direction; the exposed area is subjected to a second ion implantation based on the opening pattern, and the second ion implantation
  • the implantation process includes ion implantation at a second incident angle along a second direction, and the angle ⁇ 2 of the second incident angle is the angle between the second direction and the normal direction; wherein, the first direction and the The second direction is different, and the angle of the first incident angle and the angle of the second incident angle may be equal or unequal.
  • the distribution of implanted ions in the same area is more uniform.
  • the normal line here refers to the dashed line perpendicular to the surface plane of the second mask layer 40.
  • the ion implantation angle mentioned here takes the ion emitter as the origin for consideration.
  • the ion implantation concentration is between the two; through two different angles of implantation, the effect that the ion implantation concentration in each area is proportional to the width can be achieved, and the uniformity of the ion implantation concentration can be ensured at the same time.
  • FIG. 10 a schematic diagram illustrating the relationship between the ion implantation concentration and the size and width of the region in the semiconductor etching method of the present application is shown.
  • the abscissa is the ion implantation concentration
  • the ordinate is the size and width of the opening pattern.
  • the ion implantation concentration should be proportional to the width of each region. That is, in this embodiment, the etching rate of the region with a small opening size>the etching rate of the region with a medium opening size>the etching rate of the region with a large opening size, so that the etching rate of the region with a small opening size is relatively higher. Fast, and the etching rate of the area with a large opening size is relatively slow, so as to make up for the difference in the etching removal rate between the pattern openings of different sizes in the etching process in the prior art.
  • the ion implantation process can also be achieved by time and region.
  • this method of time-division and region-division ion implantation is more complicated than the above-mentioned method of subdivision and tilt implantation, but it can achieve higher accuracy requirements, and it can also meet the requirements of ion implantation in each region.
  • the density is proportional to the width of the area.
  • the region that reaches the required ion implantation concentration is shielded, until the ion implantation concentration in all regions meets the requirement, and the ion implantation process ends.
  • the above ion implantation process may specifically include:
  • the region with the largest opening pattern size also reaches the required ion implantation concentration.
  • the ion implantation is stopped. So far, the ion implantation concentration in all regions meets the requirements.
  • the process of performing ion implantation on the exposed region based on the opening pattern may also be a combined ion implantation method of vertical ion implantation and inclined ion implantation, wherein the inclined ion implantation may also be re-implanted. Subdivided into multiple oblique ion implantation.
  • the flow rate of the doping gas during the ion implantation process is 10-500 sccm.
  • the step of sequentially forming the first mask layer and the second mask layer on the material layer to be etched specifically includes:
  • the patterned hard mask layer 50 is removed. It is worth noting that the patterned hard mask layer 50 can be removed separately or consumed during the patterning process.
  • the patterned hard mask layer 50 includes, but is not limited to, an ethyl orthosilicate hard mask layer (TEOS).
  • TEOS ethyl orthosilicate hard mask layer
  • An etch stop layer is provided under the material layer to be etched, and the etch stop layer is adjacent to the material layer to be etched.
  • the patterned hard mask layer 50 can be patterned by photoresist coating, exposure, and development, and then the pattern is transferred to the hard mask layer by etching to obtain the patterned hard mask layer. ⁇ 50 ⁇ Mold layer 50.
  • an exposure-etch-exposure-etch (Litho-Etch-Litho-Etch, LELE) process can also be used to form a finer pattern in the hard mask layer. This process can be more The pattern that originally needed to be formed in the same photoresist is well decomposed to solve the problem of too dense photolithography patterns.
  • the material layer to be etched includes a tungsten layer 20 (W), the etch stop layer includes a silicon nitride layer 10 (SiN), and the etching of the trench stops at the silicon nitride layer 10 is shown in Figure 11.

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Abstract

本申请提供一种半导体刻蚀方法，其包括: 提供待刻蚀材料层; 于所述待刻蚀材料层上依次形成第一掩膜层及覆盖所述第一掩膜层的第二掩膜层; 图形化所述第二掩膜层，以形成不同尺寸的开口图形，所述开口图形使得所述第一掩膜层暴露出具有不同尺寸的区域; 基于所述开口图形对被暴露出的所述区域进行离子注入，各所述区域内的离子注入浓度与所述区域的宽度成正比，且离子注入后的所述区域的材料刻蚀去除速率与所述区域内的离子注入浓度成反比; 基于所述开口图形刻蚀经离子注入后的所述区域至所述待刻蚀材料层内形成与所述开口图形尺寸一致的沟槽，各所述沟槽的深度近似或相同。

Description

半导体刻蚀方法
相关申请的交叉引用
本申请要求于2020年3月23日提交中国专利局、申请号为2020102063284、发明名称为“半导体刻蚀方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别是涉及一种半导体刻蚀方法。
技术背景
现有的半导体制备工艺中，连接盘层(Landing Pad Layout)由于图形设计复杂，刻蚀宽度往往从十纳米到几百纳米不等。这就导致了在对待刻蚀材料层进行刻蚀的过程中，存在着与刻蚀深宽比相关的负载效应(aspect ratio dependent etching，ARDE)，这主要表现在，待刻蚀材料层上不同尺寸的图形刻蚀深度不同，宽的图形刻蚀深，窄的图形刻蚀浅。
因此，需要寻求一种可以解决上述不同宽度图形因负载效应引起的刻蚀均匀性(etch uniformity)问题的办法。
发明内容
根据本申请的各种实施例，提供一种半导体刻蚀方法。
一种半导体刻蚀方法，包括：
提供待刻蚀材料层；
于所述待刻蚀材料层上依次形成第一掩膜层及覆盖所述第一掩膜层的第二掩膜层；图形化所述第二掩膜层，以形成不同尺寸的开口图形，所述开口图形使得所述第一掩膜层暴露出具有不同尺寸的区域；
基于所述开口图形对被暴露出的所述区域进行离子注入，各所述区域内 的离子注入浓度与所述区域的宽度成正比，且离子注入后的所述区域的材料刻蚀去除速率与所述区域内的离子注入浓度成反比；
基于所述开口图形刻蚀经离子注入后的所述区域至所述待刻蚀材料层内形成与所述开口图形尺寸一致的沟槽，各所述沟槽的深度近似或相同。
在上述半导体刻蚀方法中，通过先对第一掩膜层中的不同宽度的所述区域进行不同浓度的离子注入，使得各所述区域内的离子注入浓度与宽度成正比，且离子注入后的所述区域的刻蚀去除速率与离子注入浓度成反比，即宽度较大的区域内的离子注入浓度大于宽度较小的区域内的离子注入浓度，且宽度较大的区域的刻蚀去除速率小于宽度较小的区域的刻蚀去除速率，可以确保对待刻蚀材料层的刻蚀均匀性，使得待刻蚀材料层内可以形成不同宽度但相同深度的沟槽。
上述的半导体刻蚀方法，其中：
所述第二掩膜层包括氮氧化硅层；所述第一掩膜层包括非晶碳层，注入的离子包括类碳离子。
上述的半导体刻蚀方法，其中：
同时对被暴露出的各所述区域进行离子注入，且各所述区域的离子注入的时间相同。
上述的半导体刻蚀方法，其中：基于所述开口图形对被暴露出的所述区域进行离子注入包括如下步骤：
基于所述开口图形对被暴露出的所述区域进行第一次离子注入，所述第一次离子注入过程包括沿第一方向进行第一入射角的离子注入，所述第一入射角的角度为所述第一方向与法线方向的夹角大小；
基于所述开口图形对被暴露出的所述区域进行第二次离子注入，所述第二次离子注入过程包括沿第二方向进行第二入射角的离子注入，所述第二入射角的角度为所述第二方向与法线方向的夹角大小，其中，
所述第一方向与所述第二方向不同，所述第一入射角的角度与所述第二入射角的角度相等。
上述的半导体刻蚀方法，其中：
所述第一入射角的角度和所述第二入射角的角度均大于α；
Figure PCTCN2021081738-appb-000001
其中，h为所述图形化后的第二掩膜层的厚度，d为宽度最小的所述开口图形的宽度。
上述的半导体刻蚀方法，其中，基于所述开口图形对被暴露出的所述区域进行离子注入包括如下步骤：
基于所述开口图形对被暴露出的所述区域进行离子注入，所述离子注入过程中离子的注入方向为垂直于所述第二掩膜层；
每经过预设时间，对达到所需离子注入浓度的所述区域进行屏蔽，直到所有所述区域达到所需离子注入浓度，结束离子注入过程。
上述的半导体刻蚀方法，其中，每经过预设时间，对达到所需离子注入浓度的所述区域进行屏蔽，直到所有所述区域达到所需离子注入浓度，结束离子注入过程包括：
经过第一时间后，对达到所需离子注入浓度的开口图形尺寸最小的区域进行屏蔽；
经过第二时间后，对达到所需离子注入浓度的开口图形尺寸中等的区域进行屏蔽；及
经过第三时间后，开口图形尺寸最大的区域达到所需离子注入浓度，结束离子注入过程。
上述的半导体刻蚀方法，其中，于所述待刻蚀材料层上依次形成所述第一掩膜层及所述第二掩膜层包括：
于所述待刻蚀材料层的表面形成所述第一掩膜层；
于所述第一掩膜层的表面形成所述第二掩膜层；
于所述第二掩膜层的表面形成图形化硬掩膜层；
基于所述图形化硬掩膜层对所述第二掩膜层进行图形化处理，以得到所述图形化后的第二掩膜层。
上述的半导体刻蚀方法，还包括去除所述图形化硬掩膜层的步骤。
上述的半导体刻蚀方法，其中所述图形化硬掩膜层单独去除或在图形化过程中消耗去除。
上述的半导体刻蚀方法，其中：
所述的硬掩膜层包括正硅酸乙酯硬掩膜层。
上述的半导体刻蚀方法，其中：
在所述待刻蚀材料层下设置有刻蚀停止层，所述刻蚀停止层与所述待刻蚀材料层相邻。
上述的半导体刻蚀方法，其中：
所述的待刻蚀材料层包括钨层，所述刻蚀停止层包括氮化硅层，所述沟槽的刻蚀停止于所述氮化硅层中。
上述的半导体刻蚀方法，其中：
所述的离子注入过程中掺杂气体流量为10～500sccm。
上述的半导体刻蚀方法，其中，所述第一入射角的角度和所述第二入射角的角度为5°至25°。
附图说明
通过附图中所示的本申请的优选实施例的更具体说明，本申请的上述及其它目的、特征和优势将变得更加清晰。在全部附图中相同的附图标记指示相同的部分，且并未刻意按实际尺寸等比例缩放绘制附图，重点在于示出本申请的主旨。
图1为现有技术的刻蚀前的包含图形化硬掩膜层、掩膜层、非晶碳层及待刻蚀材料层的半导体结构的截面示意图；
图2为现有技术的刻蚀过程中包含图形化掩膜层、非晶碳层及待刻蚀材料层的半导体结构的截面示意图；
图3为现有技术的刻蚀完毕的待刻蚀材料层的截面示意图；
图4为本申请一种半导体刻蚀方法的流程图；
图5为本申请一实施例中提供的半导体刻蚀方法中形成有图形化硬掩膜层、第二掩膜层、第一掩膜层及待刻蚀材料层所得结构的截面结构示意图；
图6为本申请一实施例中对图5所得截面结构进行图形化处理后得到的图形化掩膜层、第一掩膜层及待刻蚀材料层结构的截面结构示意图；
图7为本申请一实施例中对图6所得截面结构进行离子注入时的截面结构示意图；
图8A为本申请一实施例中对区域进行第一次离子注入时离子注入角度与最小开口图形尺寸宽度及图形化掩膜层厚度关系的局部结构示意图；
图8B为本申请一实施例中对区域进行第二次离子注入时离子注入角度与最小开口图形尺寸宽度及图形化掩膜层厚度关系的局部结构示意图；
图9为本申请一实施例中提供的半导体刻蚀方法中形成有图形化掩膜层、第一掩膜层及待刻蚀材料层所得结构在离子注入后的截面结构示意图；
图10为本申请一实施例中提供的半导体刻蚀方法中离子注入浓度与区域的尺寸宽度关系的示意图；
图11为本申请一实施例中提供的半导体刻蚀方法中刻蚀后所得到的具有相同深度的沟槽的待刻蚀材料层。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施的限制。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体地实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组 合。
本申请的发明人在工作中发现，在对第一金属层的刻蚀过程中存在着刻蚀不均匀性的问题，具体的，如图1～图3所示，为现有的半导体刻蚀工艺中对第一金属层的刻蚀过程的几幅截面结构示意图，其中，图1所示为刻蚀前的半导体截面结构示意图，包括待刻蚀材料层氮化硅10’(SiN)、金属钨20’(W)，在待刻蚀材料层上依次形成有非晶碳层30’(Armorphous Carbon Layer,ACL)、掩膜层40’氮氧化硅(SiON)以及图形化硬掩膜层50’硅酸四乙酯(Tetra-Ethyl-Ortho-Silicate,TEOS)，图2所示，为刻蚀过程中的半导体截面结构示意图，可见，较宽尺寸图形开口处的刻蚀去除速率比较窄尺寸图形开口处的刻蚀去除速率要快，这使得在刻蚀过程中，较宽尺寸图形开口处刻蚀的沟槽深度总是比较窄尺寸图形开口处刻蚀的沟槽深度要更深一些，当刻蚀完毕以后，情况如图3所示，在待刻蚀材料层10’、20’中刻蚀出来的沟槽由于负载效应，存在着明显的宽处图形刻蚀深，窄处图形刻蚀浅的刻蚀不均匀性问题。
因此，基于发明人发现的上述问题，本申请提供一种半导体刻蚀方法，可以保证待刻蚀材料层的刻蚀均匀性。
为使本申请的上述目的、特征和优点能够更为明显易懂，下面结合附图对本申请的具体实施例作详细的说明。
请参阅图4，具体而言，本申请所提出的一种半导体刻蚀方法包括：
S10：提供待刻蚀材料层；
S11：于所述待刻蚀材料层上依次形成第一掩膜层及覆盖所述第一掩膜层的第二掩膜层；图形化所述第二掩膜层，以形成不同尺寸的开口图形，所述开口图形使得所述第一掩膜层暴露出具有不同尺寸的区域；
S12：基于所述开口图形对被暴露出的所述区域进行离子注入，各所述区域内的离子注入浓度与所述区域的宽度成正比，且离子注入后的所述区域的材料刻蚀去除速率与所述区域内的离子注入浓度成反比；
S13：基于所述开口图形刻蚀经离子注入后的所述区域，至所述待刻蚀材 料层内形成与所述开口图形尺寸一致的沟槽，各所述沟槽的深度近似或相同，值得注意的是，这里所说的近似是指各沟槽的深度均在一定范围内，工艺上可认为是具有近似的深度。
本申请通过对第一掩膜层中各区域的离子注入浓度进行配置，以达到调整各区域的刻蚀去除速率的目的，使得不同开口尺寸区域的刻蚀去除速率变的可控。
为了便于说明，本实施例中，将所述开口图形的尺寸大小分为三种，具体的，可分为大、中、小三个宽度。但是需要说明的是，本申请对开口图形的尺寸大小并不作限定。
请参阅图5～图8，作为示例，所述的第二掩膜层40可以包括但不仅限于氮氧化硅层(SiON)；所述第一掩膜层30可以包括但不限于非晶碳层(ACL)、未掺杂poly层(un-doped poly)，注入的离子包括但不限于类碳离子(C-like ion)。如此选择的原因是，由于非晶碳层其它离子不影响碳离子浓度，且类碳离子为中性4价不具有极性，因此类碳离子注入时不会改变之前材料的特性。
作为示例，较佳的，选择同时对被暴露出的各所述区域进行离子注入，各所述区域的离子注入时间相同，以使得离子注入过程简单高效。
作为示例，如图7所示，应当说明的是，为了达到不同开口尺寸区域中离子注入浓度不同的效果，在离子注入过程优选的应当采用分两次倾斜注入的方式来完成，具体的，所述的基于所述开口图形对被暴露出的所述区域进行离子注入可以包括如下步骤：
如图8A，8B所示，基于所述开口图形对被暴露出的所述区域进行第一次离子注入，所述第一次离子注入过程包括沿第一方向进行第一入射角的离子注入，所述第一入射角的角度α1为所述第一方向与法线方向的夹角大小；基于所述开口图形对被暴露出的所述区域进行第二次离子注入，所述第二次离子注入过程包括沿第二方向进行第二入射角的离子注入，所述第二入射角的角度α2为所述第二方向与法线方向的夹角大小；其中，所述第一方向与所 述第二方向不同，所述第一入射角的角度与所述第二入射角的角度可以相等或不等，相等时同一区域内的注入离子分布更均匀。值得注意的是，这里的法线是指垂直于所述第二掩膜层40表平面的虚线。此外，这里提到的离子注入角度是以离子发射器为原点进行考量的。
在另一个示例中，如图8A，8B所示，其中：设所述第一入射角的角度α1和所述第二入射角的角度α2均大于α，
Figure PCTCN2021081738-appb-000002
h为图形化后的所述第二掩膜层的厚度，d为宽度最小的所述开口图形的宽度，这样设计使得开口图形宽度最小处的地方离子无法注入。所述入射角的大范围为5°～25°。
如图9所示，上述两次倾斜的离子注入过程中，由于开口尺寸小的区域离子大部分都被打到第二掩膜层40的侧壁上，不能达到第一掩膜层30，所以开口尺寸小的区域的第一掩膜层30内离子无法注入因此注入浓度最小，而开口区域大的区域离子则能达到第一掩膜层30内，故离子注入浓度大，开口区域中等的区域离子注入浓度则介于两者之间；通过两次不同角度的注入，可以达到各区域内的离子注入浓度与宽度成正比的效果，并可以同时保证离子注入浓度的均匀性。
结合参考图10，示意了本申请半导体刻蚀方法中离子注入浓度与区域的尺寸宽度关系的示意图，横坐标为离子注入浓度，纵坐标为开口图形尺寸宽度。从图中可以看出，为了达到本申请的刻蚀均匀性目的，离子注入浓度与各区域的宽度应成正比关系。即，在本实施例中，开口尺寸小的区域的刻蚀速率＞开口尺寸中等的区域的刻蚀速率＞开口尺寸大的区域的刻蚀速率，这样开口尺寸小的区域的刻蚀速率相对较快，而开口尺寸大的区域的刻蚀速率则相对较慢，以此弥补现有技术在刻蚀过程中不同尺寸图形开口之间刻蚀去除速率之间的差值。
作为示例，为了达到不同开口尺寸区域中离子注入浓度不同的效果，在所述的离子注入过程中除了可以采用上述的分次倾斜注入的方式来实现之外，还可以通过分时间分区域的方式来实现离子注入，这种分时间分区域离 子注入的方式，虽然较上述分次倾斜注入的方式复杂，却能达到更高的精度要求，并且，同样可以满足使各所述区域内的离子注入浓度与所述区域的宽度成正比的技术效果。具体的，在一示例中，所述的基于所述开口图形对被暴露出的所述区域进行离子注入可以包括如下步骤：
基于所述开口图形对各所述区域进行离子注入，离子注入过程中离子的注入方向为垂直于所述第二掩膜层40，即沿着法线方向注入；
每经过一定时间，对达到所需离子注入浓度的区域进行屏蔽，直到所有区域的离子注入浓度均达到要求，离子注入过程结束。
以本实施例中，所述开口图形的尺寸为大、中、小三种情况为例，上述离子注入过程具体可以包括：
经过第一时间后，对达到所需离子注入浓度的开口图形尺寸最小的区域进行屏蔽；
再经过第二时间后，对达到所需离子注入浓度的开口图形尺寸中等的区域进行屏蔽；
再经过第三时间后，开口图形尺寸最大的区域也达到所需离子注入浓度，此时，停止离子注入。至此，所有区域的离子注入浓度均满足要求。
作为示例，所述的基于所述开口图形对被暴露出的所述区域进行离子注入的过程还可以是采用上述垂直离子注入与倾斜离子注入的组合离子注入方式，其中倾斜离子注入还可被再细分成多份倾斜离子注入。
较佳的，在一个示例中，所述的离子注入过程中掺杂气体流量为10～500sccm。
作为示例，于所述待刻蚀材料层上依次形成所述第一掩膜层及所述第二掩膜层的步骤具体包括：
于所述待刻蚀材料层的表面形成第一掩膜层30；
于所述第一掩膜层30的表面形成第二掩膜层40；
于所述第二掩膜层40的表面形成图形化硬掩膜层50；
基于所述图形化硬掩膜层50对所述第二掩膜层40进行图形化处理，以 得到所述图形化后的第二掩膜层40；
去除所述图形化硬掩膜层50，值得注意的是，图形化硬掩膜层50的去除方式可以为单独去除，也可以为在图形化过程中被消耗完。
作为示例，所述的图形化硬掩膜层50包括但不限于正硅酸乙酯硬掩膜层(TEOS)。在所述待刻蚀材料层下设置有刻蚀停止层，所述刻蚀停止层与所述待刻蚀材料层相邻。
作为示例，所述的图形化硬掩模层50可以通过光阻涂布、曝光、显影来形成所需图案，再通过刻蚀将图案转移到硬掩模层以得到所述的图形化硬掩模层50。较佳的，还可以采用曝光-刻蚀-曝光-刻蚀(Litho-Etch-Litho-Etch，LELE)的工艺，以在所述硬掩模层中形成较为精细的图案，这种工艺可以较好地将原本需要形成在同一光刻胶中的图案分解，以解决光刻图案过于密集的问题。
作为示例，所述的待刻蚀材料层包括钨层20(W)，所述刻蚀停止层包括氮化硅层10(SiN)，所述沟槽的刻蚀停止于所述氮化硅层10中如图11所示。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体刻蚀方法，包括：
    提供待刻蚀材料层；
    于所述待刻蚀材料层上依次形成第一掩膜层及覆盖所述第一掩膜层的第二掩膜层；图形化所述第二掩膜层，以形成不同尺寸的开口图形，所述开口图形使得所述第一掩膜层暴露出具有不同尺寸的区域；
    基于所述开口图形对被暴露出的所述区域进行离子注入，各所述区域内的离子注入浓度与所述区域的宽度成正比，且离子注入后的所述区域的材料刻蚀去除速率与所述区域内的离子注入浓度成反比；
    基于所述开口图形刻蚀经离子注入后的所述区域至所述待刻蚀材料层内形成与所述开口图形尺寸一致的沟槽，各所述沟槽的深度近似或相同。
  2. 根据权利要求1所述的半导体刻蚀方法，其中，
    所述第二掩膜层包括氮氧化硅层；所述第一掩膜层包括非晶碳层，注入的离子包括类碳离子。
  3. 根据权利要求1所述的半导体刻蚀方法，其中同时对被暴露出的所述区域进行离子注入，各所述区域的离子注入时间相同。
  4. 根据权利要求1所述的半导体刻蚀方法，其中基于所述开口图形对被暴露出的所述区域进行离子注入包括如下步骤：
    基于所述开口图形对被暴露出的所述区域进行第一次离子注入，所述第一次离子注入过程包括沿第一方向进行第一入射角的离子注入，所述第一入射角的角度为所述第一方向与法线方向的夹角大小；
    基于所述开口图形对被暴露出的所述区域进行第二次离子注入，所述第二次离子注入过程包括沿第二方向进行第二入射角的离子注入，所述第二入射角的角度为所述第二方向与法线方向的夹角大小，其中，
    所述第一方向与所述第二方向不同，所述第一入射角的角度与所述第二入射角的角度相等。
  5. 根据权利要求4所述的半导体刻蚀方法，其中，
    所述第一入射角的角度和所述第二入射角的角度均大于α；
    Figure PCTCN2021081738-appb-100001
    其中，h为所述图形化后的第二掩膜层的厚度，d为宽度最小的所述开口图形的宽度。
  6. 根据权利要求1所述的半导体刻蚀方法，其中基于所述开口图形对被暴露出的所述区域进行离子注入包括如下步骤：
    基于所述开口图形对被暴露出的所述区域进行离子注入，所述离子注入过程中离子的注入方向为垂直于所述第二掩膜层；
    每经过预设时间，对达到所需离子注入浓度的所述区域进行屏蔽，直到所有所述区域达到所需离子注入浓度，结束离子注入过程。
  7. 根据权利要求6所述的半导体刻蚀方法，其中每经过预设时间，对达到所需离子注入浓度的所述区域进行屏蔽，直到所有所述区域达到所需离子注入浓度，结束离子注入过程包括：
    经过第一时间后，对达到所需离子注入浓度的开口图形尺寸最小的区域进行屏蔽；
    经过第二时间后，对达到所需离子注入浓度的开口图形尺寸中等的区域进行屏蔽；及
    经过第三时间后，开口图形尺寸最大的区域达到所需离子注入浓度，结束离子注入过程。
  8. 根据权利要求1所述的半导体刻蚀方法，其中于所述待刻蚀材料层上依次形成所述第一掩膜层及所述第二掩膜层包括：
    于所述待刻蚀材料层的表面形成所述第一掩膜层；
    于所述第一掩膜层的表面形成所述第二掩膜层；
    于所述第二掩膜层的表面形成图形化硬掩膜层；
    基于所述图形化硬掩膜层对所述第二掩膜层进行图形化处理，以得到所述图形化后的第二掩膜层。
  9. 根据权利要求8所述的半导体刻蚀方法，还包括去除所述图形化硬掩膜层的步骤。
  10. 根据权利要求9所述的半导体刻蚀方法，其中所述图形化硬掩膜层单独去除或在图形化过程中消耗去除。
  11. 根据权利要求8所述的半导体刻蚀方法，其中，
    所述的硬掩膜层包括正硅酸乙酯硬掩膜层。
  12. 根据权利要求1所述的半导体刻蚀方法，其中，
    在所述待刻蚀材料层下设置有刻蚀停止层，所述刻蚀停止层与所述待刻蚀材料层相邻。
  13. 根据权利要求12所述的半导体刻蚀方法，其中，
    所述的待刻蚀材料层包括钨层，所述刻蚀停止层包括氮化硅层，所述沟槽的刻蚀停止于所述氮化硅层中。
  14. 根据权利要求4所述的半导体刻蚀方法，其中，
    所述的离子注入过程中掺杂气体流量为10～500sccm。
  15. 根据权利要求4所述的半导体刻蚀方法，其中所述第一入射角的角度和所述第二入射角的角度为5°至25°。
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