WO2022257323A1 - 离子注入方法 - Google Patents

离子注入方法 Download PDF

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Publication number
WO2022257323A1
WO2022257323A1 PCT/CN2021/125442 CN2021125442W WO2022257323A1 WO 2022257323 A1 WO2022257323 A1 WO 2022257323A1 CN 2021125442 W CN2021125442 W CN 2021125442W WO 2022257323 A1 WO2022257323 A1 WO 2022257323A1
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Prior art keywords
opening
ion implantation
oxide layer
layer
photoresist
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PCT/CN2021/125442
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English (en)
French (fr)
Inventor
周俊
孙鹏
杨道虹
魏丹清
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武汉新芯集成电路制造有限公司
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Publication of WO2022257323A1 publication Critical patent/WO2022257323A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/317—Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks

Definitions

  • the invention relates to semiconductor technology, in particular to an ion implantation method.
  • Ion implantation is a common process in the manufacturing process of semiconductor devices.
  • Ion implantation equipment usually implants dopant ions from the front or back of the semiconductor substrate to a preset area in the substrate according to a certain energy and implantation density, forming ions in the semiconductor structure. doped region.
  • dopant ions are, for example, n-type dopant ions (such as phosphorus (P) or arsenic (As)) or p-type dopant ions (such as boron (B) or boron difluoride (BF 2 )) .
  • a patterned photoresist is usually used as an implantation mask (ie, a barrier layer for ion implantation) during ion implantation.
  • the device structure is advancing towards a more highly integrated design, and the requirements for the minimum line width (or critical dimension, CD) that can be achieved by the process are getting higher and higher (for example, it needs to be below 0.35 microns).
  • CD critical dimension
  • the device structure of single-photon avalanche diodes has gradually developed from a planar structure to a vertical structure. The device size is reduced under the vertical structure.
  • the PN junction is designed on a deep silicon substrate.
  • a deep well region needs to be formed in the substrate, and the well region may require high-energy ion implantation above 1000keV. In this case, it is not easy to continue to use only photoresist to make the implantation mask to meet the requirements for the quality of ion implantation.
  • the reasons are: on the one hand, for a photoresist layer whose thickness can meet the ion implantation barrier requirements, the After patterning through the exposure and development process, the verticality of the sidewall of the photoresist layer relative to the substrate surface is not good, and the pattern accuracy is poor, resulting in poor precision of the defined ion implantation area, which is not conducive to meeting the line width requirements ; On the other hand, when carrying out high-energy ion implantation, the thickness of the photoresist layer as the implantation mask increases with the increase of the implantation depth, and the formation of a stable thick photoresist layer is very demanding on the material properties of the photoresist.
  • the quality of ion implantation is very critical to the quality of the manufactured devices.
  • the method of only using photoresist as an implant mask can no longer meet the process requirements of small line width and/or high energy ion implantation, which restricts the quality of devices. improvement.
  • the invention provides an ion implantation method, which can better meet the technological requirements of small line width and/or high-energy ion implantation and help to improve device quality compared with the method of only using photoresist as an implant mask.
  • the ion implantation method provided by the present invention includes the step of forming an implant mask on a semiconductor substrate, and the step of forming the implant mask includes:
  • the ONO stack including a first oxide layer, a nitride layer and a second oxide layer stacked sequentially from bottom to top;
  • the second opening penetrates the second oxide layer and the nitride layer and exposes the first oxide layer;
  • the ONO stack with the second opening is used as the implantation mask.
  • the thickness of the nitride layer and/or the second oxide layer is adjusted so that the depth of the second opening meets the requirements of ion implantation.
  • the thickness of the nitride layer is 1 ⁇ m to 2 ⁇ m
  • the thickness of the second oxide layer is
  • the thickness of the nitride layer is The thickness of the second oxide layer is 1 ⁇ m ⁇ 4 ⁇ m.
  • the thickness of the first oxide layer is
  • the step of forming the implantation mask further includes: forming a photoresist on the semiconductor substrate layer, the photoresist layer fills the second opening and the upper surface is higher than the upper surface of the second oxide layer; the photoresist layer is subjected to exposure and development treatment, so that based on the second opening forming a third opening, the third opening penetrates through the photoresist layer, the second oxide layer and the nitride layer and exposes the first oxide layer; wherein, adjusting the thickness of the photoresist layer The depth of the third opening meets the requirements of ion implantation, and the whole of the ONO stack with the third opening and the photoresist layer is used as the implantation mask.
  • the third opening includes a second opening located in the ONO stack and a photoresist hole communicating with the second opening and located in the photoresist layer, the photoresist hole The bottom of the bottom exposes at least part of the upper surface of the second oxide layer.
  • the upper surface of the second oxide layer exposed at the bottom of the photoresist hole is an annular surface whose inner side is connected to the sidewall of the second opening.
  • the width of the annular surface is greater than and less than
  • the minimum inner diameter of the second opening is less than or equal to 0.5 ⁇ m.
  • the ion implantation method further includes the step of performing ion implantation on the semiconductor substrate using the implant mask, and the step of removing the implant mask after the ion implantation is completed.
  • the ONO stack in the process of forming the implant mask, is first formed on the semiconductor substrate, and then the second oxide layer and the nitride layer are sequentially etched to form a The second oxide layer and the nitride layer expose the second opening of the first oxide layer.
  • the ONO stack with the second opening is used as the implantation mask.
  • the second oxide layer is etched at an angle perpendicular to the upper surface of the semiconductor substrate, and then the nitride layer is etched, and the second oxide layer acts as a mask, thereby obtaining the first
  • the verticality of the two openings is good, and the shape is easy to control, which helps to improve the accuracy of ion implantation, and is convenient to meet the shape control requirements of small line width device design.
  • the ONO stacked film It has good stability, and it is not easy to collapse even when the thickness is set larger to meet high-energy ion implantation. It can meet the process requirements of small line width and/or high-energy ion implantation, and helps to improve device quality.
  • FIGS. 1A to 1E are schematic cross-sectional views of the formation process of an implantation mask in an ion implantation method according to an embodiment of the present invention.
  • FIG. 1F is a schematic cross-sectional view of ion implantation into a semiconductor substrate using the implantation mask shown in FIG. 1E .
  • FIG. 1G is a schematic cross-sectional view after removing the implant mask shown in FIG. 1E .
  • FIGS. 2A to 2F are schematic cross-sectional views of the formation process of the implantation mask in the ion implantation method according to an embodiment of the present invention.
  • FIG. 2G is a schematic cross-sectional view of ion implantation into a semiconductor substrate using the implantation mask shown in FIG. 2F .
  • FIG. 2H is a schematic cross-sectional view after removing the implant mask shown in FIG. 2F .
  • ions are implanted into the semiconductor substrate by ion implantation to form ion-doped regions with different functions.
  • the implanted region range, implantation depth and ion doping concentration of the ion-doped regions with different functions may be different. different.
  • the ONO stack structure is used to make the implantation mask, which has the advantages of good verticality and good film stability, and can meet the shape control requirements of small line width device design, and when the thickness is large It is not easy to collapse.
  • some embodiments may choose to only use the ONO stack with the following second opening as the implantation mask (such as the following embodiment 1). In this case, for example, by properly setting the ONO stack The thickness of the upper two layers makes the total thickness of the ONO stack meet the thickness required by ion implantation.
  • the latter implantation mask formation method can reduce the manufacturing difficulty of the ONO stack, improve the process efficiency, and is especially suitable for the high ion implantation energy to be carried out, thereby requiring the larger thickness of the implantation mask (such as the case of 3 ⁇ m or more).
  • the present invention does not limit the material and specific structure of the semiconductor substrate on which the implantation mask is to be formed.
  • the semiconductor substrate may be various substrates capable of forming an ion-doped region in a predetermined region by ion implantation.
  • the semiconductor base may be configured as or include a silicon- or germanium-containing substrate on which doped epitaxial layers, gradient semiconductor layers, and semiconductor layers on top of other semiconductor layers of different types (such as silicon-germanium layer on the silicon layer).
  • the semiconductor substrate may have been processed by semiconductor processes such as deposition, etching, and ion implantation, so several ion-doped regions may be formed in the semiconductor substrate, and another ion-doped region still needs to be formed through an ion implantation process.
  • the ion implantation to be performed may be an ion implantation that requires high ion implantation precision (such as the critical dimension (or minimum line width) of the ion implantation region is less than or equal to 0.8 ⁇ m, or even less than 0.5 ⁇ m, such as only 0.2 ⁇ m), or, High-energy implantation (such as implantation energy greater than or equal to 1000keV) is to be performed, so the thickness of the implantation mask is required to be relatively high, or the ion implantation to be performed is both high-energy implantation and the critical dimension of the implantation region (or ion implantation opening) smaller.
  • high ion implantation precision such as the critical dimension (or minimum line width) of the ion implantation region is less than or equal to 0.8 ⁇ m, or even less than 0.5 ⁇ m, such as only 0.2 ⁇ m
  • High-energy implantation such as implantation energy greater than or equal to 1000keV
  • the present invention is not limited thereto, the implantation mask obtained in the ion implantation method of the present invention can also be used for the formation of ion-doped regions whose implantation energy is not very high or the critical size of the implanted region is relatively large, and the implantation mask still has The advantages of high injection precision and not easy to collapse are helpful to improve the quality of the device.
  • FIG. 1A to 1E are schematic views of the formation process of the implantation mask in the ion implantation method according to an embodiment of the present invention.
  • the ion implantation method of this embodiment will be described below with reference to FIG. 1A to FIG. 1E .
  • FIG. 1A is a schematic cross-sectional view after forming an ONO stack on a semiconductor substrate.
  • an ONO stack 200 is first formed on a semiconductor substrate 100, and the ONO stack 200 includes a first oxide layer 210, a nitride layer stacked in sequence from bottom to top. 220 and the second oxide layer 230.
  • the first oxide layer 210 is, for example, silicon oxide
  • the nitride layer 220 is, for example, silicon nitride
  • the second oxide layer 230 is, for example, silicon oxide.
  • the first oxide layer 210, the nitride layer 220, and the second oxide layer 230 may be formed through a chemical vapor deposition process.
  • the first oxide layer 210 may also be formed through a thermal oxidation process.
  • the thickness of the first oxide layer 210 is about It is used to protect the surface of the semiconductor substrate 100 during subsequent etching and ion implantation, and the first oxide layer 210 can also be used as an etching stop layer in the process of etching the upper nitride layer 220 .
  • the nitride layer 220 For the nitride layer 220, its thickness can be grown a little thicker according to the requirements of ion implantation, so as to block the penetration of implanted ions.
  • the furnace tube is usually used for chemical vapor deposition, the film formation rate of silicon nitride is low, compared with the oxidation For silicon, it takes longer to form the same thick silicon nitride, and the stress of silicon nitride is much larger than that of silicon oxide. Too thick silicon nitride is easy to warp the underlying substrate. Therefore, the thickness of the nitride layer 220 can be set according to the requirements of the ion implantation on the implantation mask, film formation efficiency, stress and other factors.
  • the second oxide layer 230 covers the surface of the nitride layer 220, and the second oxide layer 230 can be used as a mask when etching the nitride layer 220, which helps to control the morphology of the nitride layer and improve the etching precision.
  • Layer 230 additionally serves to block ion implantation.
  • the thickness of the implantation mask can be set according to the requirements of the subsequent ion implantation to the implantation mask (referred to as ion implantation requirements), and the ion implantation requirements Including requirements on the thickness of the implantation mask (because it affects the ion barrier capability), the precision of the defined ion implantation area (because it affects the design of the minimum line width), etc.
  • setting the required thickness of the implant mask can be satisfied by setting an ONO stack with an appropriate thickness, and the silicon nitride layer therein basically does not cause the problem of too long film forming time or obvious substrate warpage.
  • the thickness of the nitride layer 220 and/or the second oxide layer 230 is adjusted so that the nitride layer 220 and the The total thickness of the second oxide layer 230 is greater than or equal to the mask thickness required for ion implantation, and the mask thickness required for ion implantation is, for example, 1 ⁇ m.
  • the thickness of the nitride layer 220 is about 1 ⁇ m to 2 ⁇ m, and the thickness of the second oxide layer 230 is about It can be seen that the nitride layer 220 plays a major role in blocking the implantation of spacers.
  • the present invention is not limited thereto.
  • the second oxide layer 230 may be set to have a thickness much greater than that of the nitride layer 220, so that the second oxide layer 230 is mainly used to block the implantation of spacers, or it may also be set
  • the thicknesses of the second oxide layer 230 and the nitride layer 220 are relatively close, so they both play an important role in blocking the implantation of insulators.
  • the process of forming the ion implantation opening is introduced, and the ion implantation opening refers to the region exposed by the implantation mask during ion implantation.
  • the ion implantation opening is formed by removing part of the second nitride layer 230 and the nitride layer 220 stacked up and down, so that the ion implantation opening penetrates the second oxide layer 230 and the nitride layer 220 and exposes the underlying The first oxide layer 210 (partial thickness of the first oxide layer 210 may also be removed).
  • FIG. 1B is a schematic cross-sectional view after forming a patterned photoresist on the ONO stack.
  • a photoresist is coated on the upper surface of the ONO stack 200 and developed by exposure to pattern the photoresist.
  • the patterned photoresist (such as the area where “PR” is located in FIG. 1B ) is used as a mask for etching the lower second oxide layer 230 .
  • the part of the second oxide layer exposed by the photoresist covers the range of the ion implantation opening to be formed.
  • FIG. 1C is a schematic cross-sectional view after etching the second oxide layer.
  • the second oxide layer 230 is etched at an angle perpendicular to the upper surface of the semiconductor substrate 100 to form a first opening 200 a penetrating through the second oxide layer 230 and exposing the nitride layer 220 .
  • a patterned photoresist on the second oxide layer 230 as shown in FIG.
  • the angle of the upper surface of the semiconductor substrate 100 is etched to ensure that the sidewall of the first opening 200a formed by etching is substantially perpendicular to the upper surface of the semiconductor substrate (the angle between the two is, for example, in the range of 89° to 90°), so that Help to improve the precision of ion implantation.
  • the nitride layer 220 can be used as an etching barrier layer in the process of etching the second oxide layer 230. Of course, it is not excluded that there may still be a smaller thickness.
  • the nitride layer 220 is removed during the process of etching the second oxide layer 230, especially when the process of etching the second oxide layer 230 is set with a long over-etching time.
  • FIG. 1D is a schematic cross-sectional view after removing the photoresist on the second oxide layer.
  • the photoresist on the second oxide layer 230 will also be consumed so that it is not enough to be used as a mask, and the photoresist is easy to form during the dry etching process.
  • the polymer reactants are unfavorable to subsequent processes, so before further etching the nitride layer 220 , the remaining photoresist and possible polymer reactants on the second oxide layer 230 are removed.
  • FIG. 1E is a schematic cross-sectional view after etching the nitride layer. Referring to FIG. 1E , then, continue to etch downward from the first opening 200a to form a second opening 200b based on the first opening 200a, the second opening 200b penetrates the second oxide layer 230 and the nitride layer 220 and exposes the first An oxide layer 210 .
  • the process of forming the second opening 200b is mainly the process of etching the nitride layer 220, and the patterned second oxide layer 230 can be used as a mask for the process of etching the nitride layer 220, and the first oxide layer 210 can be used as a mask for the process of etching the nitride layer 220.
  • As an etch barrier layer required for the process of etching the nitride layer 220 is mainly the process of etching the nitride layer 220, and the patterned second oxide layer 230 can be used as a mask for the process of etching the nitride layer 220, and the first oxide layer 210 can be used as a mask for the process of etching the nitride layer 220.
  • As an etch barrier layer required for the process of etching the nitride layer 220 is mainly the process of etching the nitride layer 220, and the patterned second oxide layer 230
  • dry etching in the process of forming the second opening 200b, specifically dry etching at an angle perpendicular to the upper surface of the semiconductor substrate 100, so as to ensure the second opening 200b formed by etching
  • the sidewalls of are substantially perpendicular to the upper surface of the semiconductor substrate 100 .
  • the dry etching for etching the second oxide layer 230 and the nitride layer 220 can be carried out in the same dry etching equipment chamber, only need to change the etching conditions (such as etching Gas type, flow rate, chamber pressure, etc.) can be converted into the etching conditions required for etching the nitride layer 220, so that the two etchings can be performed continuously to save process time.
  • the etching conditions such as etching Gas type, flow rate, chamber pressure, etc.
  • the second opening 200b is formed by etching directly using the patterned second oxide layer 230 as a mask, the size of the second opening 200b is basically the same as that of the first opening 200a, for example, the minimum inner diameter of the second opening 200b is below 0.8 ⁇ m, even Below 0.5 ⁇ m.
  • the first oxide layer 210 with a smaller thickness may also be removed, as long as the remaining first oxide layer 210 can protect the surface of the semiconductor substrate 100 during subsequent ion implantation.
  • the implantation mask of this embodiment is formed.
  • the ONO stack 200 having the second opening 200b is used as the implantation mask, and the second opening 200b is an ion implantation opening.
  • the ion implantation method of this embodiment may include the step of performing ion implantation using the above-mentioned implant mask.
  • FIG. 1F is a schematic cross-sectional view of ion implantation into the semiconductor substrate 100 using the implantation mask shown in FIG. 1E .
  • dopant ions enter the semiconductor substrate 100 through the second opening 200b.
  • the dopant ions are, for example, p-type or n-type.
  • FIG. 1F takes p-type ions as an example, and the letter p represents p-type ions .
  • the ion type, implantation energy, implantation density and other conditions used in the specific ion implantation can be set according to the requirements of the specific ion implantation, and will not be repeated here.
  • the ONO stack 200 is used to achieve a mask thickness that meets the requirements of ion implantation.
  • the verticality of the second opening 200b is good, which helps to improve the accuracy of ion implantation and facilitates the small line width.
  • the film stability of ONO stack 200 is better, and it is not easy to collapse even when the thickness is large, which helps to reduce the risk of device failure and improve device quality.
  • the ion implantation method of this embodiment may include a step of removing the implantation mask after the ion implantation is completed.
  • FIG. 1G is a schematic cross-sectional view after removing the implant mask shown in FIG. 1E .
  • the nitride layer 220 can be removed by wet etching for silicon nitride first, and the second oxide layer 230 on the nitride layer 220 is also removed.
  • the first oxide layer 210 The semiconductor substrate 100 can be protected.
  • the first oxide layer 210 is removed by dry etching or wet etching. Since the first oxide layer 210 is relatively thin, damage to the surface of the semiconductor substrate 100 can be avoided by controlling the etching time.
  • the ion implantation method may further include a step of performing an ion activation process to form an ion-doped region 100 a in the semiconductor substrate 100 .
  • the semiconductor substrate 100 can be annealed at a high temperature of about 800° C. to 1100° C. to activate the dopant ions in the semiconductor substrate 100 .
  • the dopant ions diffuse in the semiconductor substrate 100 and become gradually stable.
  • the difference between the ion implantation method of this embodiment and the first embodiment is mainly reflected in the formation process of the implantation mask.
  • this embodiment is based on ion implantation requirements, silicon nitride stress, and process efficiency considerations.
  • the thickness of the nitride layer 220 can be reduced.
  • a photoresist layer is added as a part of the implantation mask, and a third opening with a depth greater than the second opening is obtained, and the third opening is used as an ion implantation opening.
  • nitrogen can be used on the basis of ensuring the verticality of the entire implantation mask and film stability.
  • the deposition time required for the nitride layer is shortened, thereby improving process efficiency and reducing the risk of warping of the semiconductor substrate due to silicon nitride stress.
  • FIG. 2A to 2G are schematic cross-sectional views of the formation process of the implantation mask in the ion implantation method according to an embodiment of the present invention.
  • FIG. 2A is a schematic cross-sectional view after forming an ONO stack on a semiconductor substrate.
  • an ONO stack 202 is first formed on a semiconductor substrate 102, and the ONO stack 202 includes a first oxide layer 211, a nitride layer stacked in sequence from bottom to top. 221 and the second oxide layer 231.
  • the first oxide layer 211 is, for example, silicon oxide
  • the nitride layer 221 is, for example, silicon nitride
  • the second oxide layer 231 is, for example, silicon oxide.
  • the thickness of the first oxide layer 211 is about
  • the thickness of the nitride layer 221 is about
  • the thickness of the second oxide layer 231 is about 1 ⁇ m ⁇ 4 ⁇ m. More specifically, the thickness of the second oxide layer 231 is about 3 ⁇ m ⁇ 4 ⁇ m.
  • the thickness of the second oxide layer 231 is much greater than the thickness of the nitride layer 221, so the second oxide layer 231 plays a major blocking role during ion implantation, and the nitride layer 221 can be used for etching the second oxide layer. 231 as an etch stop layer.
  • 2B is a schematic cross-sectional view after forming a patterned photoresist on the ONO stack.
  • a photoresist PR
  • PR photoresist
  • the range of the portion of the second oxide layer exposed by the photoresist may be set as the range of the ion implantation opening to be formed.
  • FIG. 2C is a schematic cross-sectional view after etching the second oxide layer.
  • the second oxide layer 231 is etched at an angle perpendicular to the upper surface of the semiconductor substrate 102 to form a first opening 202 a penetrating through the second oxide layer 231 and exposing the nitride layer 221 .
  • the method for forming the first opening 202a is similar to that of the first embodiment, and will not be repeated here.
  • FIG. 2D is a schematic cross-sectional view after etching the nitride layer.
  • the first opening 202a is formed in the ONO stack 202
  • the remaining photoresist and possible polymer reactants on the second oxide layer 231 are removed, and then continue downward from the first opening 202a.
  • Etching to form a second opening 202b based on the first opening 202a the second opening 202b penetrates the second oxide layer 231 and the nitride layer 221 and exposes the first oxide layer 211 .
  • the method for forming the second opening 202b is similar to that of the first embodiment, and will not be repeated here.
  • FIG. 2E is a schematic cross-sectional view after forming a photoresist layer on the ONO stack with the second opening.
  • the ONO stack 202 with the second opening 202b is set to not meet the implantation mask thickness required for ion implantation. Therefore, a photoresist layer with a suitable thickness is also stacked on the ONO stack 202 to Increase the thickness of the implant mask.
  • a photoresist layer 300 is then formed on the semiconductor substrate 102. Before exposure, the photoresist layer 300 fills the second opening 202b and the upper surface is as high as on the upper surface of the second oxide layer 231 .
  • the upper surface of the photoresist layer 300 is, for example, parallel to the horizontal plane.
  • FIG. 2F is a schematic cross-sectional view of the patterned photoresist layer.
  • the photoresist layer 300 is exposed and developed to form a third opening 202c based on the second opening 202b, and the third opening 202c penetrates the photoresist layer 300, the second oxidation layer 231 and nitride layer 221 and expose the first oxide layer 211, wherein, by adjusting the thickness of the photoresist layer 300 in the step of forming the photoresist layer 300, the depth of the third opening 202c can meet the ion injection requirements.
  • the entirety of the ONO stack 202 having the third opening 202c and the photoresist layer 300 is used as an injection mask.
  • the third opening 202c includes a second opening 202b located in the ONO stack 202 and a photoresist hole (not shown).
  • the size of the second opening 202b is the same as that of the photoresist hole, and both are the size of an ion implantation opening.
  • the present invention is not limited thereto.
  • the second opening 202b located below the third opening 202c is set slightly smaller than the ion implantation opening, and the photoresist hole communicating with the second opening 202b It is formed according to the size of the ion implantation opening, that is, at least at a certain sidewall position, the photoresist hole is not flush with the sidewall of the second opening 202b, specifically at the third opening 202c, the ONO stack 202 is relatively
  • the photoresist layer 300 protrudes a certain distance toward the second opening 202b, so that the bottom of the photoresist hole exposes at least part of the upper surface of the second oxide layer 231 .
  • Such an arrangement of upper width and lower narrowness helps to prevent the patterned photoresist layer 300 from collapsing, and also helps to prevent the material of the photoresist layer 300 from falling into the second opening 202b to affect the ion implantation accuracy.
  • the upper surface of the second oxide layer 231 exposed at the bottom of the photoresist hole may be an annular surface whose inner side is connected to the sidewall of the second opening 202b.
  • the width of the annular surface may be uniform or variable. Because the too large width will increase the range of ion implantation, it may affect the minimum line width setting of the device; moreover, when ion implantation is performed later, the dopant ions implanted into the semiconductor substrate 102 from the annular surface region should be taken into account.
  • the concentration of the doped region formed by the dopant ions implanted into the semiconductor substrate 102 from the second opening 202b should be based on the thickness of the photoresist layer 300, the size of the ion implantation opening and The concentration of the doped region to be achieved is determined comprehensively.
  • the minimum inner diameter of the photoresist hole is less than or equal to 0.5 ⁇ m
  • the minimum inner diameter of the second opening 202b is less than 0.5 ⁇ m
  • the second oxide layer 231 exposed by the photoresist hole is
  • the width of the annular surface is, for example, greater than and less than
  • the implantation mask of this embodiment is formed.
  • the whole ONO stack 202 having the third opening 202c and the photoresist layer 300 are used as the implantation mask, and the third opening 202c is an ion implantation opening.
  • the ion implantation method of this embodiment may include the step of performing ion implantation using the above-mentioned implant mask.
  • FIG. 2G is a schematic cross-sectional view of ion implantation into a semiconductor substrate using the implantation mask shown in FIG. 2F .
  • dopant ions enter the semiconductor substrate 102 through the third opening 202c.
  • the dopant ions are, for example, p-type or n-type.
  • FIG. 2G takes p-type ions as an example, and the letter p represents p-type ions .
  • Conditions such as the ion type, implantation energy, and implantation density used in the specific ion implantation can be set according to the requirements of the specific ion implantation, and will not be repeated here.
  • the ONO stack 202 and the photoresist layer 300 are used to achieve a mask thickness that satisfies the requirements of ion implantation, and when performing ion implantation, due to the good verticality of the second opening 202b, the depth of the photoresist hole The photoresist layer 300 has little influence on the verticality of the sidewall of the third opening 202c.
  • the accuracy of ion implantation can be improved, and it is convenient to meet the requirement of small line width. Topography control requirements for device design.
  • the thickness of the photoresist layer 300 is small, it is not easy to collapse, and the risk of the photoresist layer 300 collapsing can be further reduced by exposing the photoresist hole to part of the upper surface of the second oxide layer 231, thereby Reduce the risk of defective devices and help improve device quality.
  • the thickness of the photoresist layer 300 is increased as a part of the implantation mask. Relatively speaking, using the implantation method of this embodiment is easier to achieve a deeper implantation depth than in the first embodiment.
  • the ion implantation method of this embodiment may include the step of removing the implantation mask after the ion implantation is completed.
  • FIG. 2H is a schematic cross-sectional view after removing the implant mask shown in FIG. 2F .
  • the nitride layer 221 can be removed by wet etching for silicon nitride first, and the second oxide layer 231 on the nitride layer 221 is also removed.
  • the first An oxide layer 211 can protect the semiconductor substrate 102; and then dry etching or wet etching is used to remove the first oxide layer 211. Since the first oxide layer is relatively thin, damage to the surface of the semiconductor substrate can be avoided by controlling the etching time.
  • the ion implantation method may further include a step of performing an ion activation process to form an ion-doped region 102 a in the semiconductor substrate 102 .
  • the semiconductor substrate 102 can be annealed at a high temperature of about 800° C. to 1100° C. to activate the dopant ions in the semiconductor substrate 102 .
  • the dopant ions diffuse in the semiconductor substrate 102 and become gradually stable.
  • the ONO stack in the process of forming the implant mask, is first formed on the semiconductor substrate, and then the second oxide layer and the nitride layer are sequentially etched to form a The second oxide layer and the nitride layer expose the second opening of the first oxide layer.
  • the ONO stack with the second opening is used as the implantation mask.
  • a photoresist layer with a certain thickness can also be formed on the ONO stack to increase the thickness of the implantation mask.
  • the second oxide layer is etched at an angle perpendicular to the upper surface of the semiconductor substrate, and then the nitride layer is etched, and the second oxide layer acts as a mask, thereby obtaining the first
  • the verticality of the two openings is good, and the shape is easy to control, which helps to improve the accuracy of ion implantation, and is convenient to meet the shape control requirements of small line width device design.
  • the ONO stacked film Good stability even if the thickness is set larger to meet high-energy ion implantation, it is not easy to collapse, so it can better meet the process requirements of small line width and/or high-energy ion implantation, and help to improve device quality.
  • the embodiment of the present invention may also include a method for forming a single photon avalanche diode device, wherein the above-mentioned ion implantation method of the present invention is used.
  • the single photon avalanche diode device includes a semiconductor substrate, an epitaxial layer disposed on the semiconductor substrate (the epitaxial layer is doped with p-type ions, for example, and has a lower concentration), and a PN junction disposed in the epitaxial layer,
  • the PN junction is a vertical structure (meaning that the p-type conductive region and the n-type conductive region forming the PN junction are arranged along the thickness direction of the semiconductor substrate).
  • the PN junction is set very deep.
  • a well region surrounding the PN junction is also provided in the epitaxial layer.
  • the well region is, for example, A deep p-well with a concentration greater than the original p-type doping concentration of the epitaxial layer.
  • the width of the well region is, for example, less than 0.8 ⁇ m, and the depth penetrates the thickness of the epitaxial layer (for example, about 6 ⁇ m).
  • the ion implantation method provided by the present invention forms the well region. Based on the advantages of the ion implantation method provided by the present invention, the quality and yield of the produced single photon avalanche diode device can be improved.

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Abstract

本发明涉及一种离子注入方法。所述离子注入方法在形成注入掩膜的过程中，在半导体基底上先形成ONO叠层，然后依次刻蚀其中的第二氧化层和氮化层而形成第二开口，当所述第二开口的深度满足离子注入要求时，以具有第二开口的ONO叠层作为注入掩膜。在获得第二开口的过程中，以垂直于半导体基底上表面的角度刻蚀第二氧化层和氮化层，从而得到的第二开口的垂直性好，形貌易于控制，有助于提高离子注入的精度，便于满足小线宽器件设计的形貌控制要求，而且，ONO叠层的膜稳定性好，即使为了满足高能离子注入而厚度设置得较大时也不容易倒塌，可以满足小线宽和/或高能离子注入的工艺需求。

Description

离子注入方法 技术领域
本发明涉及半导体工艺技术，尤其涉及一种离子注入方法。
背景技术
离子注入是半导体器件制程中的常用工艺，离子注入通常由离子注入设备按照一定能量以及注入密度从半导体基底的正面或者背面向基底内的预设区域注入掺杂物离子，在半导体结构中形成离子掺杂区。根据导电类型不同，掺杂物离子例如为n型掺杂离子(如磷(P)或砷(As))或者p型掺杂离子(如硼(B)或二氟化硼(BF 2))。为了限定离子注入的范围，通常在离子注入时采用图形化的光刻胶作为注入掩膜(即离子注入的阻挡层)。
然而，随着技术的发展，器件结构向集成度更高的设计推进，对工艺能实现的最小线宽(或称关键尺寸，CD)的要求越来越高(例如需在0.35微米以下)。在制作某些半导体器件时，还需采用高能离子注入以增加离子注入的深度。例如，单光子雪崩二极管的器件结构目前由平面结构逐步发展成垂直结构，垂直结构下器件尺寸减小，为了有效降低器件的暗计数率，提升器件性能，PN结被设计在很深的硅衬底中，为了隔开相邻的器件区，在衬底中需要形成很深的阱区，该阱区可能需要用到1000keV以上的高能离子注入。在这种情况下，继续仅采用光刻胶制作注入掩膜已不容易满足对离子注入品质的要求，原因在于：一方面，对于厚度能够满足离子注入阻挡需求的光刻胶层来说，在通过曝光和显影工序进行图形化后，光刻胶层的侧壁相对于基底表面的垂直度不好，图形精度较差，导致所限定的离子注入区域的精度较差，不利于满足线宽要求；另一方面，在进行高能离子注入时，作为注入掩膜的光刻胶层的厚度随着注入深度的提高而增加，而形成稳定的厚光刻胶层对光刻胶的材料特性要求很高，不仅容易因垂直度不好而影响离子注入区域的精度，而且在形成小线宽图形时，光刻胶层那些深宽比很大的部分容易发生倒塌，进而会引起器件缺陷。
可见，离子注入的质量对所制作的器件的品质来说非常关键，目前仅采 用光刻胶作为注入掩膜的方式已不能满足小线宽和/或高能离子注入的工艺需求，制约着器件品质的提升。
发明内容
本发明提供了一种离子注入方法，相对于仅利用光刻胶作为注入掩膜的方式来说，更能够满足小线宽和/或高能离子注入的工艺需求，有助于提升器件品质。
本发明提供的离子注入方法包括在半导体基底上形成注入掩膜的步骤，所述注入掩膜的形成步骤包括：
在所述半导体基底上形成ONO叠层，所述ONO叠层包括从下至上依次叠加的第一氧化层、氮化层和第二氧化层；
以垂直于所述半导体基底上表面的角度刻蚀所述第二氧化层，以在所述第二氧化层中形成贯穿所述第二氧化层且露出所述氮化层的第一开口；
从第一开口继续向下刻蚀以基于所述第一开口形成第二开口，所述第二开口贯穿所述第二氧化层和所述氮化层且露出所述第一氧化层；
其中，当所述第二开口的深度满足离子注入要求时，以具有所述第二开口的ONO叠层作为所述注入掩膜。
可选的，在形成所述ONO叠层的步骤中，调节所述氮化层和/或所述第二氧化层的厚度，使得所述第二开口的深度满足离子注入要求。
可选的，所述氮化层的厚度为1μm～2μm，所述第二氧化层的厚度为
Figure PCTCN2021125442-appb-000001
可选的，所述氮化层的厚度为
Figure PCTCN2021125442-appb-000002
所述第二氧化层的厚度为1μm～4μm。
可选的，所述第一氧化层的厚度为
Figure PCTCN2021125442-appb-000003
可选的，当所述第二开口的深度小于离子注入要求的深度时，在形成所述第二开口后，所述注入掩膜的形成步骤还包括：在所述半导体基底上形成光刻胶层，所述光刻胶层填满所述第二开口且上表面高于所述第二氧化层的上表面；对所述光刻胶层进行曝光和显影处理，以基于所述第二开口形成第三开口，所述第三开口贯穿所述光刻胶层、所述第二氧化层和所述氮化层且 露出所述第一氧化层；其中，调整所述光刻胶层的厚度使得所述第三开口的深度满足离子注入要求，以具有所述第三开口的所述ONO叠层和所述光刻胶层整体作为所述注入掩膜。
可选的，所述第三开口包括位于所述ONO叠层中的第二开口和与所述第二开口连通且位于所述光刻胶层中的光刻胶孔，所述光刻胶孔的底部至少露出部分所述第二氧化层的上表面。
可选的，所述光刻胶孔底部露出的所述第二氧化层的上表面为内侧与所述第二开口侧壁连接的环形面。
可选的，所述环形面的宽度大于
Figure PCTCN2021125442-appb-000004
且小于
Figure PCTCN2021125442-appb-000005
可选的，所述第二开口的最小内径小于或等于0.5μm。
可选的，所述离子注入方法还包括利用所述注入掩膜对所述半导体基底进行离子注入的步骤，以及在离子注入结束后去除所述注入掩膜的步骤。
如上所述，本发明提供的离子注入方法，在形成注入掩膜的过程中，在半导体基底上先形成ONO叠层，然后依次刻蚀其中的第二氧化层和氮化层，形成贯穿所述第二氧化层和所述氮化层且露出所述第一氧化层的第二开口，当所述第二开口的深度满足离子注入要求时，以具有所述第二开口的ONO叠层作为注入掩膜。在获得第二开口的过程中，以垂直于所述半导体基底上表面的角度刻蚀第二氧化层，接着刻蚀所述氮化层，第二氧化层起到了掩膜作用，从而得到的第二开口的垂直性好，形貌易于控制，有助于提高离子注入的精度，便于满足小线宽器件设计的形貌控制要求，而且，相对于光刻胶层来说，ONO叠层的膜稳定性好，即使为了满足高能离子注入而厚度设置得较大时也不容易倒塌，可以满足小线宽和/或高能离子注入的工艺需求，有助于提升器件品质。
附图说明
图1A至图1E是本发明一实施例的离子注入方法中注入掩膜的形成过程的剖面示意图。
图1F是利用图1E所示的注入掩膜对半导体基底实施离子注入的剖面示意图。
图1G是去除图1E所示的注入掩膜后的剖面示意图。
图2A至图2F是本发明一实施例的离子注入方法中注入掩膜的形成过程的剖面示意图。
图2G是利用图2F所示的注入掩膜对半导体基底实施离子注入的剖面示意图。
图2H是去除图2F所示的注入掩膜后的剖面示意图。
附图标记说明：
100、102-半导体基底；200、202-ONO叠层；210、211-第一氧化层；220、221-氮化层；230、231-第二氧化层；200a、202a-第一开口；200b、202b-第二开口；300-光刻胶层；202c-第三开口；100a、102a-离子掺杂区。
具体实施方式
以下结合附图和具体实施例对本发明的离子注入方法作进一步详细说明。根据下面的说明，本发明的优点和特征将更清楚。应当理解，说明书的附图均采用了非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
在半导体器件的制作过程中，通过离子注入向半导体基底中注入离子，以形成不同功能的离子掺杂区，功能不同的离子掺杂区的注入区范围、注入深度及离子掺杂浓度可能有所不同。在执行离子注入时，为了满足相应的注入区范围、注入深度及离子掺杂浓度的要求，需设置用来限定注入区范围的注入掩膜的图形以及注入能量、注入密度等参数，其中，注入掩膜需要依照注入能量的高低而形成为适合的厚度。本发明以下描述的实施例中，采用ONO叠层结构来制作注入掩膜，具有垂直性好和膜稳定性好的优点，可以满足小线宽器件设计的形貌控制要求，且厚度较大时也不容易倒塌。
根据离子注入要求，一些实施例可选择仅采用具有下述的第二开口的ONO叠层作为注入掩膜的方式(如下面的实施例一)，这种情况例如可通过适当设置ONO叠层的上面两层的厚度使得ONO叠层的总厚度满足离子注入要求的厚度。另外，还有一些情况，例如当要进行的离子注入需要的注入掩膜厚度较大或者ONO叠层的制作难度较高或耗时过长时，本发明另外的实施 例(如下面的实施例二)不是将具有所述第二开口的ONO叠层直接作为注入掩膜，而是在形成具有所述第二开口的ONO叠层后，再在上方形成一定厚度的光刻胶层，并且通过对光刻胶层进行图形化，使得在第二开口位置形成深度更大的第三开口，并将具有所述第三开口的所述ONO叠层和所述光刻胶层整体作为所述注入掩膜，其中通过调整所述光刻胶层的厚度可使得所述第三开口的深度满足离子注入要求。对于同样厚度的注入掩膜，后一种注入掩膜形成方法可以降低ONO叠层的制作难度，提高工艺效率，尤其适合于要进行的离子注入能量高、从而要求注入掩膜的厚度较大(如3μm以上)的情况。
本发明对于要在其上形成注入掩膜的半导体基底的材质和具体结构不作限定。所述半导体基底可以是各种能够通过离子注入在其中预设区域形成离子掺杂区的基底。所述半导体基底可以设置为或者包括含硅或锗的衬底，所述衬底上可形成有掺杂的外延层、梯度半导体层和位于不同类型的其它半导体层上面的半导体层(例如锗硅层上的硅层)。所述半导体基底可能已经过诸如沉积、刻蚀、离子注入等半导体工艺的处理，因而在半导体基底中可形成有若干离子掺杂区，且仍需要通过离子注入工艺形成另外的离子掺杂区。
待进行的离子注入可以是对离子注入精度要求较高(如离子注入区的关键尺寸(或者最小线宽)小于或等于0.8μm，甚至小于0.5μm，例如仅0.2μm)的离子注入，或者，要进行的是高能量注入(例如注入能量大于等于1000keV)故对注入掩膜的厚度要求较高，或者，待进行的离子注入既属于高能量注入而且注入区域(或者离子注入开口)的关键尺寸较小。但本发明不限于此，本发明的离子注入方法中得到的注入掩膜也可以用于注入能量不是很高或者注入区关键尺寸较大的离子掺杂区的形成，所述注入掩膜仍然具有注入精度高、不容易倒塌的优点，有助于器件品质的提升。
以下分别通过两个实施例对本方面的离子注入方法进行说明。需要说明的是，所述实施例仅是制造和应用本发明的示例性的具体实施方式，并不构成在制造和应用本发明时的范围限制。在某些实施方式下，下述实施例中的技术特征也可以相互关联、启发，以构成新的实施例。
实施例一
图1A至图1E是本发明一实施例的离子注入方法中注入掩膜的形成过程的示意图。以下先参照图1A至图1E对本实施例的离子注入方法进行说明。
图1A为在半导体基底上形成ONO叠层后的剖面示意图。参照图1A，在进行离子注入前，为了形成注入掩膜，首先在半导体基底100上形成ONO叠层200，所述ONO叠层200包括从下至上依次叠加的第一氧化层210、氮化层220和第二氧化层230。
第一氧化层210例如为氧化硅，氮化层220例如为氮化硅，第二氧化层230例如为氧化硅。第一氧化层210、氮化层220和第二氧化层230可以通过化学气相沉积工艺形成。第一氧化层210也可以通过热氧化工艺形成。第一氧化层210的厚度约
Figure PCTCN2021125442-appb-000006
用于在后续刻蚀以及离子注入时保护半导体基底100表面，并且，第一氧化层210还可用于在刻蚀上方的氮化层220的过程中作为刻蚀停止层。
对于氮化层220，其厚度可以根据离子注入要求生长的厚一点，以阻挡注入离子穿过，但是，由于通常利用炉管进行化学气相沉积时，氮化硅成膜速率较低，相对于氧化硅，形成同样较厚的氮化硅的时间更长，而且氮化硅的应力相较于氧化硅大很多，过厚的氮化硅容易使下方基底发生翘曲。故而，可根据要进行的离子注入对注入掩膜的要求以及成膜效率、应力等因素进行考量，设置氮化层220的厚度。
第二氧化层230覆盖在氮化层220表面，第二氧化层230可以作为刻蚀氮化层220时的掩膜，有助于控制氮化层的形貌，提高刻蚀精度，第二氧化层230另外也用于阻挡离子注入。
因为要进行的离子注入的预设深度是已知的，注入掩膜的厚度可根据后续要进行的离子注入对注入掩膜的要求(称为离子注入要求)来设定，所述离子注入要求包括对注入掩膜的厚度(因为影响离子阻隔能力)、限定出的离子注入区的精度(因为影响最小线宽设计)等的要求。本实施例中，设定注入掩膜需要达到的厚度可以通过设置合适厚度的ONO叠层满足，且其中的氮化硅层基本不会产生成膜时间过长或者明显的基底翘曲的问题。具体的，根据离子注入要求，在形成所述ONO叠层200的步骤中，调节所述氮化层220和/或所述第二氧化层230的厚度，使得所述氮化层220和所述第二氧化层230 的总厚度大于或等于离子注入要求的掩膜厚度，离子注入要求的掩膜厚度例如为1μm。作为示例，所述氮化层220的厚度约1μm～2μm，所述第二氧化层230的厚度约
Figure PCTCN2021125442-appb-000007
可见对阻隔离子注入起主要作用的是氮化层220。本发明不限于此，在另一实施例中，可以设置所述第二氧化层230具有远大于氮化层220的厚度，从而主要利用第二氧化层230阻隔离子的注入，或者，也可以设置第二氧化层230和氮化层220的厚度相对较为接近，从而均起到较为重要的阻隔离子注入的作用。
接下来介绍形成离子注入开口的过程，所述离子注入开口指的是在进行离子注入时被注入掩膜暴露出的区域。本实施例中，所述离子注入开口通过去除部分上下叠加的第二氮化层230和氮化层220形成，因而所述离子注入开口贯穿第二氧化层230和氮化层220且露出下方的第一氧化层210(第一氧化层210的部分厚度也可以被去除)。
图1B为在ONO叠层上形成图形化的光刻胶后的剖面示意图。参照图1B，为了限定要去除的第二氧化层230的范围，在ONO叠层200的上表面涂敷光刻胶并通过曝光显影，使光刻胶图形化。图形化后的光刻胶(如图1B中“PR”所在区域)作为刻蚀下方第二氧化层230的掩膜。本实施例中，被光刻胶暴露的第二氧化层部分覆盖要形成的离子注入开口的范围。
图1C为刻蚀第二氧化层后的剖面示意图。参照图1C，接着，以垂直于半导体基底100上表面的角度刻蚀第二氧化层230，以形成贯穿所述第二氧化层230且露出氮化层220的第一开口200a。为了确保刻蚀角度，在第二氧化层230上形成图形化的光刻胶后(如图1B所示)，利用各向异性的干法刻蚀刻蚀第二氧化层230，具体以垂直于所述半导体基底100上表面的角度进行刻蚀，以确保刻蚀形成的第一开口200a的侧壁基本垂直于半导体基底上表面(二者夹角例如在89°～90°的范围)，这样有助于提高离子注入的精度。由于氮化硅和氧化硅具有较高的刻蚀选择比，在刻蚀第二氧化层230的工艺中可利用氮化层220以作为刻蚀阻挡层，当然，不排除仍可能有较小厚度的氮化层220在刻蚀第二氧化层230的工艺中被去除，尤其是当刻蚀第二氧化层230的工艺设置了较长的过刻蚀时间的情况下。
图1D为去除第二氧化层上的光刻胶后的剖面示意图。参照图1D，在形 成第一开口200a的过程中，第二氧化层230上的光刻胶也会被损耗导致不足以再作为掩膜使用，而且光刻胶在干法刻蚀过程中容易形成聚合物反应物，对后续工艺不利，故在进一步刻蚀氮化层220之前，将第二氧化层230上残留的光刻胶及可能存在的聚合物反应物去除。
图1E为刻蚀氮化层后的剖面示意图。参照图1E，接着，从第一开口200a继续向下刻蚀以基于所述第一开口200a形成第二开口200b，所述第二开口200b贯穿第二氧化层230和氮化层220且露出第一氧化层210。
形成第二开口200b的过程主要是刻蚀氮化层220的过程，而图形化后的第二氧化层230可作为刻蚀氮化层220的工艺的掩膜使用，第一氧化层210则可作为刻蚀氮化层220的工艺需要的刻蚀阻挡层。为了确保刻蚀的垂直度，优选形成第二开口200b的过程仍然采用干法刻蚀，具体以垂直于半导体基底100上表面的角度进行干法刻蚀，以确保刻蚀形成的第二开口200b的侧壁基本垂直于半导体基底100的上表面。进一步的，刻蚀第二氧化层230和氮化层220的干法刻蚀可以在同一干刻设备腔体内进行，只需要在第二氧化层230刻蚀结束后将刻蚀条件(如刻蚀气体种类、流量、腔内压强等)转换为刻蚀氮化层220所需的刻蚀条件即可，使两次刻蚀连续进行可以节约工艺时间。
在刻蚀氮化层220的工艺结束后，原来第一开口200a位置形成了更深的开口，称为第二开口200b。由于直接以图形化的第二氧化层230作为掩膜刻蚀形成第二开口200b，第二开口200b与第一开口200a的尺寸基本一致，例如第二开口200b的最小内径在0.8μm以下，甚至0.5μm以下。在刻蚀氮化层220的过程中，仍可能有较小厚度的第一氧化层210也被去除，只要剩余的第一氧化层210可以在后续离子注入时保护半导体基底100表面即可。
经过上述步骤，形成了本实施例的注入掩膜，此处以具有所述第二开口200b的ONO叠层200作为所述注入掩膜，第二开口200b为离子注入开口。
本实施例的离子注入方法可包括利用上述注入掩膜进行离子注入的步骤。图1F是利用图1E所示的注入掩膜对半导体基底100实施离子注入的剖面示意图。参照图1F，在离子注入时，掺杂物离子通过第二开口200b进入半导体基底100内，掺杂离子例如是p型或者n型，图1F以p型离子为例，字母p表示p型离子。具体离子注入时采用的离子类型、注入能量大小、注入 密度等条件可根据具体离子注入的需求设置，此处不再赘述。本实施例中，利用ONO叠层200达到满足离子注入要求的掩膜厚度，在进行离子注入时，由于第二开口200b的垂直性好，有助于提高离子注入的精度，便于满足小线宽器件设计的形貌控制要求，此外，相对于光刻胶，ONO叠层200的膜稳定性更好，即使厚度较大时也不容易倒塌，有助于降低器件不良风险，提升器件品质。
本实施例的离子注入方法可包括在离子注入完成后去除注入掩膜的步骤。图1G是去除图1E所示的注入掩膜后的剖面示意图。作为示例，可以先采用针对氮化硅的湿法蚀刻去除氮化层220，同时氮化层220上的第二氧化层230也被去除，在蚀刻氮化硅的过程中，第一氧化层210可以保护半导体基底100。然后，再利用干法蚀刻或者湿法蚀刻去除第一氧化层210，由于第一氧化层210较薄，通过控制蚀刻时间可以避免损伤半导体基底100表面。
此外，参照图1G，在去除注入掩膜后，所述离子注入方法还可包括进行离子激活处理而在半导体基底100中形成离子掺杂区100a的步骤。具体可以通过在800℃～1100℃左右的高温下对半导体基底100进行退火，以将半导体基底100内的掺杂离子激活，通过激活处理，掺杂离子在半导体基底100内扩散并逐渐稳定。
实施例二
本实施例的离子注入方法相对于实施例一的差异主要体现于注入掩膜的形成过程。具体而言，本实施例基于离子注入要求、氮化硅的应力以及工艺效率的考量，相对于实施例一的方案，氮化层220的厚度可以降低，另外在形成位于ONO叠层中的第二开口的基础上，增加光刻胶层作为注入掩膜的一部分，并得到较第二开口深度更大的第三开口，以第三开口作为离子注入开口。在离子注入需要的注入掩膜的深度不变的情况下，相对于仅利用ONO叠层作为注入掩膜的情形，可以在确保注入掩膜整体的垂直性及膜稳定性的基础上，使氮化层需要的沉积时间缩短，从而提高工艺效率，而且可以降低由于氮化硅应力而导致半导体基底发生翘曲的风险。以下结合附图对本实施例的离子注入方法作具体说明。
图2A至图2G是本发明一实施例的离子注入方法中注入掩膜的形成过程的剖面示意图。具体的，图2A为在半导体基底上形成ONO叠层后的剖面示意图。参照图2A，在进行离子注入前，为了形成注入掩膜，首先在半导体基底102上形成ONO叠层202，所述ONO叠层202包括从下至上依次叠加的第一氧化层211、氮化层221和第二氧化层231。第一氧化层211例如为氧化硅，氮化层221例如为氮化硅，第二氧化层231例如为氧化硅。所述第一氧化层211的厚度约
Figure PCTCN2021125442-appb-000008
所述氮化层221的厚度约
Figure PCTCN2021125442-appb-000009
所述第二氧化层231的厚度约1μm～4μm。更具体的，第二氧化层231的厚度约3μm～4μm。本实施例中，第二氧化层231的厚度远大于氮化层221的厚度，因而第二氧化层231在离子注入时起主要的阻挡作用，氮化层221可以于在刻蚀第二氧化层231时用作刻蚀停止层。
图2B为在ONO叠层上形成图形化的光刻胶后的剖面示意图。参照图2B，接着，在ONO叠层202上涂敷光刻胶(PR)并进行曝光显影，使光刻胶图形化，图形化后的光刻胶作为刻蚀下方第二氧化层231的掩膜。被光刻胶暴露的第二氧化层部分的范围可按照为要形成的离子注入开口的范围设置。然而，本实施例中，考虑到后续要在ONO叠层202上形成光刻胶层以增加注入掩膜的厚度，为了确保ONO叠层202上的光刻胶层在按照离子注入开口图形化后，不容易倒塌，如图2B所示，用来作为刻蚀第二氧化层231的掩膜的光刻胶在图形化时，按照较离子注入开口稍小的尺寸设置开口，相对于离子注入开口的设置范围，被光刻胶暴露的第二氧化层部分从外至内以均匀或者非均匀的宽度内缩适当距离，以防止后续位于ONO叠层202上的光刻胶层发生倒塌。
图2C为刻蚀第二氧化层后的剖面示意图。参照图2C，接着，以垂直于所述半导体基底102上表面的角度刻蚀第二氧化层231，以形成贯穿所述第二氧化层231且露出所述氮化层221的第一开口202a。形成所述第一开口202a的方法与实施例一类似，此处不再赘述。
图2D为刻蚀氮化层后的剖面示意图。参照图2D，在ONO叠层202中形成第一开口202a后，接着将第二氧化层231上残留的光刻胶及可能存在的聚合物反应物去除，然后，从第一开口202a继续向下刻蚀以基于所述第一开口202a形成第二开口202b，所述第二开口202b贯穿第二氧化层231和氮化层 221且露出第一氧化层211。第二开口202b的形成方法与实施例一类似，此处不再赘述。
图2E为在具有第二开口的ONO叠层上形成光刻胶层后的剖面示意图。参照图2E，本实施例中，设定具有第二开口202b的ONO叠层202不满足离子注入要求的注入掩膜厚度，因此通过在ONO叠层202上还叠加适合厚度的光刻胶层以增加注入掩膜的厚度。具体的，在形成上述第二开口202b后，接着在所述半导体基底102上形成光刻胶层300，未曝光前，所述光刻胶层300填满所述第二开口202b且上表面高于第二氧化层231的上表面。光刻胶层300的上表面例如与水平面平行。
图2F为图形化后的光刻胶层的剖面示意图。参照图2F，接着，对所述光刻胶层300进行曝光和显影处理，以基于所述第二开口202b形成第三开口202c，所述第三开口202c贯穿光刻胶层300、第二氧化层231和氮化层221且露出第一氧化层211，其中，通过在形成光刻胶层300的步骤中调整所述光刻胶层300的厚度可使得所述第三开口202c的深度满足离子注入要求。本实施例以具有所述第三开口202c的所述ONO叠层202和所述光刻胶层300整体作为注入掩膜。
参照图2D和图2F，所述第三开口202c包括位于ONO叠层202中的第二开口202b和与所述第二开口202b连通且位于所述光刻胶层300中的光刻胶孔(未示出)。一些实施例中，所述第二开口202b和光刻胶孔的大小相同，且均为离子注入开口的大小。然而，本发明不限于此，本实施例采用的优选方案中，第三开口202c中位于下方的第二开口202b设置得较离子注入开口略小，而与第二开口202b连通的光刻胶孔按照离子注入开口的大小形成，也即，至少在某一侧壁位置光刻胶孔与第二开口202b的侧壁是不齐平的，具体在第三开口202c处，ONO叠层202相对于光刻胶层300朝向第二开口202b突出一段距离，使得所述光刻胶孔的底部至少露出部分所述第二氧化层231的上表面。这样上宽下窄的设置有助于避免图形化后的光刻胶层300发生倒塌，也有助于避免光刻胶层300的材料掉入第二开口202b内影响离子注入精度。
参照图2F，为了确保图形化后光刻胶层300稳固，所述光刻胶孔底部露 出的第二氧化层231的上表面可以是内侧与所述第二开口202b侧壁连接的环形面。所述环形面的宽度可以是均一的或者是变化的。由于过大的宽度会增加离子注入的范围，可能会对器件的最小线宽设置造成影响；而且，后续在进行离子注入时，考虑到从环形面区域注入到半导体基底102中的掺杂物离子与从第二开口202b内注入到半导体基底102中的掺杂物离子形成的掺杂区浓度会存在差异，所述环形面的宽度应根据光刻胶层300的厚度、离子注入开口的尺寸以及要实现的掺杂区浓度综合决定。作为示例，本实施例中，所述光刻胶孔的最小内径小于或等于0.5μm，所述第二开口202b的最小内径小于0.5μm，所述光刻胶孔露出的第二氧化层231的环形面的宽度例如大于
Figure PCTCN2021125442-appb-000010
且小于
Figure PCTCN2021125442-appb-000011
经过上述步骤，形成了本实施例的注入掩膜，此处以具有所述第三开口202c的ONO叠层202和光刻胶层300整体作为注入掩膜，第三开口202c为离子注入开口。
本实施例的离子注入方法可包括利用上述注入掩膜进行离子注入的步骤。图2G是利用图2F所示的注入掩膜对半导体基底实施离子注入的剖面示意图。参照图2G，在离子注入时，掺杂物离子通过第三开口202c进入半导体基底102内，掺杂离子例如是p型或者n型，图2G以p型离子为例，字母p表示p型离子。具体离子注入时采用的离子类型、注入能量大小、注入密度等条件可根据具体离子注入的需求设置，此处不再赘述。本实施例中，利用ONO叠层202和光刻胶层300达到满足离子注入要求的掩膜厚度，并且在进行离子注入时，由于第二开口202b的垂直性好，而光刻胶孔的深度较小，光刻胶层300对第三开口202c侧壁垂直性的影响较小，因而相对于仅采用光刻胶层作为注入掩膜的情况，可以提高离子注入的精度，便于满足小线宽器件设计的形貌控制要求。此外，由于光刻胶层300厚度较小，不容易倒塌，并且还可通过使光刻胶孔露出第二氧化层231的部分上表面的方式，进一步降低光刻胶层300倒塌的风险，进而降低器件不良风险，有助于提升器件品质。本实施例由于较实施例一增加了光刻胶层300作为注入掩膜的一部分厚度，相对来说，利用本实施例的注入方法较实施例一容易实现更深的注入深度。
本实施例的离子注入方法可包括在离子注入完成后去除注入掩膜的步 骤。图2H是去除图2F所示的注入掩膜后的剖面示意图。参照图2H，作为示例，可以先采用针对氮化硅的湿法蚀刻去除氮化层221，同时氮化层221上的第二氧化层231也被去除，在蚀刻氮化硅的过程中，第一氧化层211可以保护半导体基底102；然后再利用干法蚀刻或者湿法蚀刻去除第一氧化层211，由于第一氧化层较薄，通过控制蚀刻时间可以避免损伤半导体基底表面。
此外，参照图2H，在去除注入掩膜后，所述离子注入方法还可包括进行离子激活处理而在半导体基底102中形成离子掺杂区102a的步骤。具体可以通过在800℃～1100℃左右的高温下对半导体基底102进行退火，以将半导体基底102内的掺杂离子激活，通过激活处理，掺杂离子在半导体基底102内扩散并逐渐稳定。
如上所述，本发明提供的离子注入方法，在形成注入掩膜的过程中，在半导体基底上先形成ONO叠层，然后依次刻蚀其中的第二氧化层和氮化层，形成贯穿所述第二氧化层和所述氮化层且露出所述第一氧化层的第二开口，当所述第二开口的深度满足离子注入要求时，以具有所述第二开口的ONO叠层作为注入掩膜。当所述第二开口的深度不满足离子注入要求时，还可以在ONO叠层上形成一定厚度的光刻胶层来增加注入掩膜的厚度。在获得第二开口的过程中，以垂直于所述半导体基底上表面的角度刻蚀第二氧化层，接着刻蚀所述氮化层，第二氧化层起到了掩膜作用，从而得到的第二开口的垂直性好，形貌易于控制，有助于提高离子注入的精度，便于满足小线宽器件设计的形貌控制要求，而且，相对于光刻胶层来说，ONO叠层的膜稳定性好，即使为了满足高能离子注入而厚度设置得较大时也不容易倒塌，因而更能够满足小线宽和/或高能离子注入的工艺需求，有助于提升器件品质。
本发明实施例还可以包括一种单光子雪崩二极管器件的形成方法，其中采用了上述的本发明的离子注入方法。所述单光子雪崩二极管器件包括半导体衬底、设置于半导体衬底上的外延层(所述外延层例如具有p型离子掺杂，浓度较低)以及在所述外延层中设置的PN结，PN结为垂直结构(指沿半导体衬底的厚度方向设置构成PN结的p型导电区和N型导电区)。为了有效降低器件的暗计数率，提升器件性能，PN结被设置得很深，为了与周围其它器件隔离，在外延层中还设置有包围所述PN结的阱区，所述阱区例如为深p阱 且浓度大于外延层原来的p型掺杂的浓度。所述阱区的宽度例如小于0.8μm，深度贯穿外延层的厚度(例如约6μm)，在形成所述阱区时，需要采用高能离子注入，且应避免注入掩膜倒塌造成缺陷，因此可以采用本发明提供的离子注入方法形成所述阱区，基于本发明提供的离子注入方法的优点，所制作的单光子雪崩二极管器件的质量及良率可以得到提高。
上述描述仅是对本发明较佳实施例的描述，并非对本发明权利范围的任何限定，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (11)

  1. 一种离子注入方法，其特征在于，包括在半导体基底上形成注入掩膜的步骤，形成所述注入掩膜的步骤包括：
    在所述半导体基底上形成ONO叠层，所述ONO叠层包括从下至上依次叠加的第一氧化层、氮化层和第二氧化层；
    以垂直于所述半导体基底上表面的角度刻蚀所述第二氧化层，以形成贯穿所述第二氧化层且露出所述氮化层的第一开口；
    从所述第一开口继续向下刻蚀，以基于所述第一开口形成第二开口，所述第二开口贯穿所述第二氧化层和所述氮化层且露出所述第一氧化层；
    其中，当所述第二开口的深度满足离子注入要求时，以具有所述第二开口的ONO叠层作为所述注入掩膜。
  2. 如权利要求1所述的离子注入方法，其特征在于，在形成所述ONO叠层的步骤中，调节所述氮化层和/或所述第二氧化层的厚度，使得所述第二开口的深度满足离子注入要求。
  3. 如权利要求2所述的离子注入方法，其特征在于，所述氮化层的厚度为1μm～2μm，所述第二氧化层的厚度为
    Figure PCTCN2021125442-appb-100001
  4. 如权利要求2所述的离子注入方法，其特征在于，所述氮化层的厚度为
    Figure PCTCN2021125442-appb-100002
    所述第二氧化层的厚度为1μm～4μm。
  5. 如权利要求1所述的离子注入方法，其特征在于，所述第一氧化层的厚度为
    Figure PCTCN2021125442-appb-100003
  6. 如权利要求1所述的离子注入方法，其特征在于，当所述第二开口的深度小于离子注入要求的深度时，在形成所述第二开口后，所述注入掩膜的形成步骤还包括：
    在所述半导体基底上形成光刻胶层，所述光刻胶层填满所述第二开口且上表面高于所述第二氧化层的上表面；
    对所述光刻胶层进行曝光和显影处理，以基于所述第二开口形成第三开口，所述第三开口贯穿所述光刻胶层、所述第二氧化层和所述氮化层且露出所述第一氧化层；
    其中，调整所述光刻胶层的厚度使得所述第三开口的深度满足离子注入要求，以具有所述第三开口的所述ONO叠层和所述光刻胶层整体作为所述注入掩膜。
  7. 如权利要求6所述的离子注入方法，其特征在于，所述第三开口包括位于所述ONO叠层中的第二开口和与所述第二开口连通且位于所述光刻胶层中的光刻胶孔，所述光刻胶孔的底部至少露出部分所述第二氧化层的上表面。
  8. 如权利要求7所述的离子注入方法，其特征在于，所述光刻胶孔底部露出的所述第二氧化层的上表面为内侧与所述第二开口的侧壁连接的环形面。
  9. 如权利要求8所述的离子注入方法，其特征在于，所述环形面的宽度大于
    Figure PCTCN2021125442-appb-100004
    且小于
    Figure PCTCN2021125442-appb-100005
  10. 如权利要求1至9任一项所述的离子注入方法，其特征在于，所述第二开口的最小内径小于或等于0.5μm。
  11. 如权利要求1至9任一项所述的离子注入方法，其特征在于，所述离子注入方法还包括利用所述注入掩膜对所述半导体基底进行离子注入的步骤，以及在离子注入结束后去除所述注入掩膜的步骤。
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