TW204409B - Fabrication improvement to the code implantation of Mask ROM - Google Patents

Abstract

A fabrication method for Mask ROM, which is the buried-in N+ bit line structure, to reduce the turn-around-time of product by shifting code implantation step to the latter part of fabrication, comprises: (1) After depositing polysilicon layer and N+ and P+ ion-implantation on the substrate of buried-in N+ bit line structure, deposits a SiO2 layer with thickness <1000Ax on the surround of polysilicon layer. (2) Deposits a Si3N4 layer with thickness >100Ax on the SiO2 layer. (3) Deposits a thick oxide layer on the Si3N4 layer by CVD method. (4) Proceeds contact alignment and etching fabrication. (5) Proceeds code alignment by sheltering the part required no code implantation, and selectively wet/dry etching the part required code implantation. (6) Proceeds code implantation. (7) Removes photo-resistor, deposits metal layer, and (8) Proceeds the ordinary MOSFET fabrication.

Description

04409 Λ 6 Π 6 V. Description of the invention (i) Printed by the Ministry of Economic Affairs, Bureau of Standards, A Industrial Consumers Cooperative Society Detailed description: The present invention is «in the code of a mask ROM (Mask ROM) ( code) Improvement of ion implantation process • In order to shorten the delivery time of the cover power ROM product by this special process. The mask ROM is currently the cheapest memory (calculated based on the price per bit). And because of its lack of market, it has always been the focus of competition among manufacturers at home and abroad. In addition to the new structure, The new manufacturing method and the newly designed cover-screen ROM are the main reasons for the competition of various manufacturers. Another very important factor is the delivery date of the product. As the name implies, the product delivery time refers to the time from the start of the production of different ROMs to the delivery of the product. Therefore, if the product delivery time is shortened, the market competitiveness will be greatly improved. In the current mask power ROM manufacturing process, this manufacturing method is based on accepting the form and function of the customer's commission. First, cut the 0 and 1 yards * and make the corresponding photomask, and then implant the cipher code ion. (Code implantation) Hit the male son into the memory film base layer. The next steps are like the general ROM process. A total of code etching / implantation is required. Thick oxide layer sinks, contact window alignment / etching, and gold wire connection Steps of Shen Dong, product testing, etc. Therefore, it takes at least 3-4 weeks from the date of acceptance of the customer's commission to produce the required ROM to the product delivery date. This time limit is a very unfavorable factor for today's Ben, which is highly competitive in product demand. In view of this, the purpose of the present invention is to solve the problem of delivery date. According to the structure of the traditional code ion implantation cover power-type read-only memory (ROM), the allowable code ion implantation step is limited by the contact layout, so it can only be used in contact ( contact) manufacturing process (please read the precautions ^ fill in this page) to install. Order _ This paper is used in the "8 home standards (CNS) T4 standard (210Χ297 public 3t)-204409 Λ 6 Π 6 V. Description of the invention (Part 1) The test department is approved by Shi Yang and printed by the A-Consumer Cooperative Society ^ Κ 前 輲 施, because in its traditional method, after making Ρ * and ίΤ ions, the semiconductor structure already has a long edge Therefore, high energy is required to make the ion implantation suitable for the insulating layer 1 when doing code ion implantation, so it has its problems in mass production. In view of the above limitations, the inventor is thinking about how to move the password implantation step in the later stage of the production S process. When the customer commissions the product, only add a little step to sleep (including the Jinyu line connection and the protective layer Steps such as deposition and product testing) can be made to achieve the purpose of reducing the time of product delivery. According to the principles of the present invention, the memory elegant structure must be one without a window near the memory unit (such as buried The structure of the type bit line), and cooperate with the special process can not be restricted by the connection point, and the time of product delivery is reduced. To illustrate the principles of the present invention, the description of the preferred real drag case KK and the following garden-style description are as follows: Circle 1 (A) -1 (E) shows the manufacturing process circle according to the real drag case of the present invention; Hehuan 2 (A) -2 (D) shows a manufacturing flowchart according to another embodiment of the present invention.囫 1 (A)-1 (E) shows the process circle of the first embodiment of the present invention. According to the principles of the present invention, the prerequisite for the postponement of the dark cell ion implantation step of the memory cell is that the memory cell must be an embedded N * bit structure, because in this structure, each memory cell is surrounded by There is no contact window, so there is no need to be limited by the contact window on the process. The manufacturing method of this first embodiment is as follows:-⑴ According to the general embedded type "bit-bit single-power R0H process *, proceed to the end (please first Please pay attention to the note ^ item write this page) Install-Line-This paper is used in the middle of the national standard (CNS) Ή regulations (210x29 / public category-Λ Λ ο 9 66 ΛΠ V. Invention description (3 ) The standard of the Ministry of Economic Affairs, Qin A Industrial Consumer Cooperative Cooperative, printed the 5i pole; ⑵Grow the calendar Si〇2 5 on the gate 1 • The embedded N * bit line 3 also grows an oxide layer 2 at the same time , Where the electrode can be made of polycrystalline silicon or other materials, (as shown in Figure 1 (A)); ⑶ in the structure shown in Na 1 (A) and then deposit a layer of thickness> 10〇A of SiaN * 6, as shown in Fig. 1 (B); ⑷M CVD (Chemical Vapor Deposition) method to grow an oxide layer 7 (BPSG or PSG) on the structure of Fig. 1 (B), as shown in Fig. 1 (C) ⑸ Perform contact window alignment and etching process (at this time, there is no contact window when the memory cell meets the surface); ⑹ Perform dark alignment, Κ 光 箪 8 covers the part that does not do dark ion implantation • Then do the selectivity Etching process, this etching step can be used by Mae etching or dry etching; ⑺ Perform code ion implantation step >> As shown in circle (D), the position of implanted ion is as shown by symbol 4; ⑻Remove photoresist, After sulphuric acid cleaning, metal deposition is performed; and ⑼ followed by quasi CMOS process. In the above example, the purpose of Si3IU 6 is to protect Si02® 5 from being etched, which is the step (6 ) The termination instruction of the etching process in the process, that is, the single step will stop after reaching the temple, and it will not be etched continuously. The Si〇2 layer, so the thickness of the polysilicon layer 1 can be accurately dug The system * enables the subsequent determination of the energy implantation of the code ion implantation to be accurately determined. In addition, the above “Examples can still use hot phosphoric acid etching to remove the Si3fU 6 of the dark mound implantation area as needed. This judgment depends on whether the thickness of Si3H4 will affect Go to (please pay attention to w3ft first Qiongxunyu this page ) The ft scale of the paper is used in the middle of the aa home sample standard (CNS) A 4 specifications (210x297 male 5 ^ 04409 Λ 6 Β 6 V. Description of the invention (+) The quasi-bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs β Industrial Consumer Cooperation Du Yin 5i code ion Depending on the energy required for implantation, the structure garden after Si3 »U calendar etching is as shown in Garden 1 (E &gt;. The method of the present invention can also be applied to the process of the second real example, and its steps include: (1) The steps are the same as in the first embodiment (1); (2) The steps are the same as in the first embodiment (2), but the 5 layer 2 is thermally grown Si 〇2, and its thickness must be controlled to a certain value, such as 800 A. At this time, the structure of the memory cell is as shown in Figure 2 (A); ⑶Rather than sink the Si3H4 layer 6, the KCVD method directly deposits a vaporized layer 7 (such as PSG) on the 5 calendar. 5 Above, as shown in circle 2 (B); ⑷ Same as the first embodiment step "⑸; ⑸ Same as the first K picking example step (Θ, as shown in the circle of sun 2 (C), but if you choose During wet etching, the etch rate of CVD oxide layer 7 is greater than the thermal growth rate of polysilicon, the etching rate of chemical layer Si〇2 5 is controlled by K time, so that the thickness of residual oxide layer 5 on polysilicon layer 1 is between 500- Between 800 Α ([Theta] password for ion implantation steps, such as undecided 2 (D) as shown; and a step ⑺ remainder of the first embodiment in ⑻ and (8) the same. The feature of this embodiment is that the CVD vaporization layer 7 and the thermal oxidation layer 5 on the polysilicon layer have different etching rates for the Mei etching, so that the thickness of the oxide layer on the polysilicon layer 1 can be properly controlled * In order to facilitate the subsequent code ion implantation. Compared with the method described in the first embodiment, this method is less easy to control the thickness of the oxide layer, but its manufacturing process is simpler. As mentioned above • Whether the first or second embodiment is used to make the present invention • Before implanting the coded carcass M, a number of processes have been carried out first, so it is up to the customer Page) Binding-Line · This paper is used in the thick-edged standard (CNS) f4 specifications (210x297 official history) 6-Λ 6 Π 6 ^ 〇44〇9_ V. Description of the invention ($) The commissioned design begins (ie From the code ion implantation step) to the completion of the entire process, the time on the κ can be reduced by about half compared to the traditional method. The above embodiments of the present invention can be modified and changed without departing from the scope of the present invention. The scope of the present invention should be as listed in the following patent application garden (please read j and note This page) The Ministry of Economic Affairs, the Central Bureau of Economics and Trade, the β-industrial instrument cooperation, the Duyin paper standard, and the Chinese National Standard (CNS) T4 standard (210x297 public if) 7

Claims (1)

M409 A7 B7 C7 D7 '、、 Apply for patents, the Ministry of Economics, the Central Bureau of Economic Development, Pui Gong Xiaozhi Cooperative printed 1'-a method of covering the power of only the SK (Hask ROM) • Use to make the code « The sub-implantation step is moved to the whole stage of the whole-memory «process, to shorten the delivery time of the product, in which the memory-only marrow is embedded N + bit line structure, the method includes the following steps: (1) in "Substrate in the buried IT bit line structure" (Substrate) After the polysilicon layer Shen Zhen and P + ion implantation is completed, deposit a Si〇2 calendar around the silicon layer * the layer thickness <1000 A; ⑵ deposit a layer of thickness> 100 A SUN4 on the S ί〇2 layer; ⑶ Li Liang CVD (chenical vapored deposition) method to deposit a thick oxide layer on the Si 3N4 layer; ⑷ to carry on the joint Point alignment and etching process; ⑸ Perform code alignment to cover the part that does not want to be implanted with photoresist, and selectively etch the area to be coded ion implanted by wet etching or dry etching; (6) Implant the coded plaque with the coded ion implantation; ⑺ remove the photoresist, and deposit it by gold; (8) followed by gold typically air semiconductive crystal field effect of the process. 2. According to the method of item 1 of the patent application, the SUM * is used. Terminate the employment as an etch of step ⑸. That is, the etching step is stopped until the layer is reached, so that the thickness of the dielectric layer on the polysilicon layer is accurately controlled by K, which results in the dark mound ion implantation that can accurately calculate the performance. The number of people needed at the time. 3. Based on the method of claim 2 of the patent scope of the application, in which the thickness of the SUH4 layer is still large before the step ⑹ is selected, it will affect the penetration energy required for the implantation of the password code. Use etching to remove the desired darkness (please read the precautions on the back and then write this page) ¾ .. hit. The ft scale of this paper is applicable to China ’s S4 standard (CNS) f4 specification (210x297 g *). 6. Apply for a patent Model A7 B7 C7 D7 Si3H4 printed on the code ion implantation area of the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 4. A mask ROM method is only used to remember the mask body (Mask ROM) * used to make the code carved into the step "Move to the next stage of the whole memory system process" to shorten the delivery time of the product. The read memory «is a buried H * bit structure, and the method includes the following steps: (1) The polysilicon Shen Shen and P and P * are completed in the substrate (Substrate) in the buried N + bit line structure After ion implantation, another Si02 «is deposited around the silicon calendar, the degree of this layer is about 800 Α; ⑵ deposit a thick oxide layer on the Si〇2 layer by CVD method; ⑶ Perform contact point alignment and Win engraving process; ⑷ Align the dark mound to cover the part where the dark mound ion implantation is not desired, and selectively touch the dark disk sickle from irrigation or dry etching. Area until the CVD oxide is etched away; ⑸ Implant the dark-sculpted carved implant in the area where the scythe implant is to be coded; ⑻ Remove the photoresist * Perform the gold layer deposition; and ⑺ Then proceed to the general gold-oxygen semiconductor The process of field effect electric crystal hip. 5. According to the method of item 4 of the patent application * in step ⑷, if you choose the wet etching method when the desired code is implanted in the sickle, control the etching rate of the CVD oxide layer to be greater than the poly The unique engraving rate of the thermally oxidized and grown oxide layer 5 on the silicon calendar is controlled by time so that the thickness of the thermally grown and grown oxide layer remaining on the polysilicon calendar is greater than 500 Α. (Please close the precautions on the back of the moraine first, and then fill out this page.) Use the Zhongyuan Yijia sample standard for paper size selection (CNS &gt; T4 specifications (210x297 公 嫠 &gt;