WO2021190294A1 - 字线结构及其制造方法、半导体存储器 - Google Patents

字线结构及其制造方法、半导体存储器 Download PDF

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Publication number
WO2021190294A1
WO2021190294A1 PCT/CN2021/079666 CN2021079666W WO2021190294A1 WO 2021190294 A1 WO2021190294 A1 WO 2021190294A1 CN 2021079666 W CN2021079666 W CN 2021079666W WO 2021190294 A1 WO2021190294 A1 WO 2021190294A1
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Prior art keywords
word line
line contact
contact structure
word
substrate
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PCT/CN2021/079666
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English (en)
French (fr)
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刘志拯
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长鑫存储技术有限公司
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Priority to EP21774339.2A priority Critical patent/EP3971966A4/en
Priority to US17/386,499 priority patent/US20210358916A1/en
Publication of WO2021190294A1 publication Critical patent/WO2021190294A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

Definitions

  • the invention relates to a word line structure, a manufacturing method thereof, and a semiconductor memory.
  • DRAM Dynamic Random Access Memory
  • the first aspect of the present application provides a word line structure, including:
  • the first word line array includes a plurality of first word lines extending in the X direction, the plurality of first word lines have the same length and are aligned in the Y direction;
  • the second word line array includes a plurality of second word lines extending along the X direction, the plurality of second word lines have the same length and are aligned along the Y direction;
  • the first word line array and the second word line array are not aligned in the Y direction, and the Y direction is perpendicular to the X direction.
  • a semiconductor memory including:
  • a memory cell including a storage capacitor and a transistor, the gate of the transistor is connected to a word line, the drain of the transistor is connected to a bit line, and the source of the transistor is connected to the storage capacitor;
  • a plurality of the memory cells are arranged in an array of M rows and N columns, the memory cells in the same row share one word line, the memory cells in the same column share one bit line, and the word line has the word Line structure, the M and N are both positive integers.
  • a third aspect of the present application provides a method for manufacturing a word line structure, including:
  • Patterning the hard mask layer wherein the pattern of the patterned hard mask layer is the same as the pattern of the word line;
  • a dielectric layer is filled in the word line trench, and the top of the dielectric layer is flush with the surface of the substrate; the dielectric layer and the substrate in the set area are etched to the first word line Or the second word line to form a word line contact groove, the word line contact groove is used to form a first word line contact structure and a second word line contact structure; in the first word line contact groove and Depositing a contact material layer in the second word line contact groove and the surface of the substrate; and removing the contact material layer on the substrate surface, and the remaining contact material layer serves as the first word line contact Structure and the second word line contact structure.
  • FIG. 1 is a schematic diagram of a word line contact structure of an embodiment
  • FIG. 2 is a schematic diagram of a first word line array according to an embodiment
  • FIG. 3 is a schematic diagram of a second word line array according to an embodiment
  • FIG. 4 is a schematic diagram of a T-shaped word line contact structure according to an embodiment
  • FIG. 5 is a schematic diagram of a semicircular word line contact structure according to an embodiment
  • FIG. 6 is a schematic diagram of an embodiment of the word line contact structure in a staggered arrangement of word lines
  • FIG. 7 is a schematic diagram of complementary shapes of adjacent word line contact structures according to an embodiment
  • FIG. 8 is a schematic diagram of complementary shapes of adjacent word line contact structures in another embodiment
  • FIG. 9 is a schematic diagram of a groove-type contact structure according to an embodiment.
  • FIG. 10 shows a method of manufacturing a word line structure according to an embodiment.
  • the dynamic random access memory includes multiple repeating memory cells. As the size of the dynamic random access memory continues to shrink and the integration level continues to increase, the feature size and cell area of the dynamic random access memory will decrease, so the area of the word line contact structure will also be reduced accordingly. If it is small, the contact resistance between the word line contact structure and the corresponding word line becomes larger, and the current flowing through the word line is too small, thereby reducing the opening and closing speed of the switch in the memory cell of the dynamic random access memory.
  • FIG. 1 is a schematic diagram of a word line contact structure according to an embodiment. As shown in FIG. 1, the word line structure includes a first word line array 100 and a second word line array 200.
  • the first word line array 100 includes a plurality of first word lines 110 extending along the X direction, the plurality of first word lines 110 have the same length and are aligned along the Y direction;
  • the second word line array 200 includes a plurality of second word lines 210 extending along the X direction, and the plurality of second word lines 210 have the same length and are aligned along the Y direction;
  • first word line array 100 and the second word line array 200 are not aligned in the Y direction, and the Y direction is perpendicular to the X direction.
  • the misalignment of the first word line array 100 and the second word line array 200 in the Y direction means that the first word line array 100 and the second word line array 200 are in different columns, that is, the first word line array 100 is in the Y direction.
  • the extended first axis of symmetry does not coincide with the second axis of symmetry extending in the Y direction of the second word line array 200.
  • the first word line 110 and the second word line 210 are both formed in a word line trench, a plurality of active regions 300 are provided in the substrate, and each active region 300 is used to form a memory cell, and each active region 300 is used to form a memory cell.
  • the projections of the first word line 110 and the second word line 210 on the substrate both pass through the multiple active regions 300, and the first word line 110 and the second word line 210 are used to control the turning on and off of the transistor of the memory cell.
  • the cross section in this embodiment refers to a cross section parallel to the surface of the substrate, and the cross section in the following embodiment is the same as the definition in this embodiment, and will not be repeated.
  • a plurality of first word lines 110 are arranged at a predetermined interval along the Y direction at equal intervals, and a plurality of second word lines 210 are arranged at a predetermined interval along the Y direction at an equal interval.
  • FIG. 2 is a schematic diagram of the first word line array 100 of this embodiment
  • FIG. 3 is a schematic diagram of the second word line array 200 of this embodiment.
  • the word line 110 and the plurality of equally spaced second word lines 210 can make the first word line 110 and the second word line 210 suitable for neatly arranged active regions.
  • the active area connected to the first word line 110 and the active area connected to the second word line 210 can be arranged more compatible on the substrate, thereby reducing the active area, Design difficulty and processing difficulty of the first word line 110 and the second word line 210.
  • a plurality of first word lines 110 and a plurality of second word lines 210 are arranged at intervals in the Y direction, that is, two words arranged adjacent to each first word line 110
  • the word lines are both the second word lines 210, and the two word lines adjacent to each second word line 210 are the first word lines 110.
  • this embodiment greatly improves the word line distribution density in the word line structure, thereby reducing the word line structure occupying in the Y direction.
  • the device area further improves the integration degree of the semiconductor device and reduces the area of the semiconductor device.
  • a plurality of first word lines 110 have a first word line contact structure 111 on the positive side in the X direction.
  • a plurality of second word lines 210 are A second word line contact structure 211 is provided on the negative side in the X direction.
  • the plurality of first word lines 110 have the first word line contact structure 111 on the negative side in the X direction, and the plurality of second word lines 210 have the second word on the positive side in the X direction. ⁇ 211 ⁇ Line contact structure 211.
  • first word line contact structure 111 and the second word line contact structure 211 are both arranged on the same side of the corresponding word line, for example, both are arranged on the positive side of the X direction or both are arranged on the negative side of the X direction. To one side, the setting space of the word line contact structure will be very limited.
  • each first word line contact structure 111 and the second word line contact structure 211 are respectively disposed on different sides of the corresponding word line
  • each first word line contact structure 111 and each The second word line contact structures 211 provide a larger arrangement space, thereby more effectively reducing the contact resistance of each word line contact structure.
  • the size of the first word line contact structure 111 and the second word line contact structure 211 in the Y direction can be 1.2 to 2 times the minimum process size.
  • the cross-sectional areas of the first word line contact structure 111 and the second word line contact structure 211 are the same.
  • each word line contact structure can have the same contact resistance with the corresponding word line.
  • the contact resistance is the same
  • the current flowing through each word line is the same, so that the opening and closing speeds of the switches in each memory cell are the same, thereby avoiding the performance difference between different memory cells, and improving the reliability of the overall performance of the device .
  • the cross-sectional shapes of the first word line contact structure 111 and the second word line contact structure 211 are both rectangular, T-shaped, and semicircular.
  • the first word line contact structure 111 and the second word line contact structure 211 are rectangular word line contact structures
  • FIG. 4 is a schematic diagram of a T-shaped word line contact structure of an embodiment
  • FIG. 5 is an implementation
  • a schematic diagram of the semicircular word line contact structure of the example, as shown in FIGS. 1, 4, and 5, the first word line contact structure 111 and the second word line contact structure 211 of any cross-sectional shape are applicable to the word line Structure, therefore, word line contact structures of other cross-sectional shapes not shown in this embodiment also belong to the protection scope of this embodiment.
  • FIG. 6 is a schematic diagram of a word line structure with a staggered arrangement of the word line contact structure of an embodiment.
  • a staggered arrangement the arrangement space of the first word line contact structure 111 in the X direction is enlarged, the size of the first word line contact structure 111 in the X direction is increased, and the first word line contact structure 111 and the The contact area between the corresponding first word lines 110 further reduces the contact resistance.
  • the length of the second word line 210 is extended, so that the plurality of second word line contact structures 211 are also arranged in a staggered manner, thereby expanding the space for the second word line contact structure 211 in the X direction.
  • the size of the second word line contact structure 211 in the X direction is increased, and the contact area between the second word line contact structure 211 and the corresponding first word line 110 is enlarged. It should be noted that the staggered word line contact structure will inevitably increase the size of the word line structure in the X direction, and thus need to occupy a larger device area. Therefore, it is necessary to select the appropriate first word line contact structure 111 and The size of the second word line contact structure 211 in the X direction is to achieve a balance between contact resistance and device size.
  • the shape of the first word line contact structure 111 is T-shaped, and the adjacent T-shaped first word line contacts The arrangement direction of the structure 111 is opposite.
  • the shapes of the adjacent T-shaped first word line contact structures 111 are complementary to each other to achieve The first word line contact structure 111 with a larger cross-sectional area.
  • the arrangement directions of the adjacent T-shaped second word line contact structures 211 are also opposite.
  • this embodiment does not specifically limit the shape and arrangement direction of the first word line contact structure 111 and the second word line contact structure 211, and other shapes that can realize adjacent word line contact structures as shown in FIG. 8 Complementary technical solutions also belong to the protection scope of this application.
  • both the first word line contact structure 111 and the second word line contact structure 211 are electrically connected to the gate of the transistor at one end, and electrically connected to the driving circuit at the other end.
  • the driving circuit is used to select the word line to achieve Access to the storage unit.
  • the first word line contact structure 111 and/or the second word line contact structure 211 is a groove type contact structure.
  • FIG. 9 is a schematic diagram of the groove type contact structure of this embodiment, as shown in FIG. 9
  • the groove type contact structure refers to etching the interlayer dielectric layer 410, and etching the word line 400 of a set depth to form a groove, and filling the groove with a conductive material to form the contact structure 430, so that the word line 400 is electrically connected to the metal layer 420.
  • the first word line contact structure 111 and/or the second word line contact structure 211 as a groove-type contact structure, it is possible to reduce the area of the word line contact structure while ensuring a larger contact area to prevent phase contact. Contacts and short circuits occur between adjacent contact structures, thereby improving the integration and reliability of the semiconductor device.
  • the materials of the first word line contact structure 111 and the second word line contact structure 211 are all one or more of tungsten, aluminum, copper, titanium, tantalum, and polysilicon.
  • the electrical conductivity therefore, can further reduce the contact resistance between the first word line contact structure 111 and the second word line contact structure 211 and the corresponding word line.
  • FIG. 10 is a manufacturing method of a word line structure according to an embodiment. As shown in FIG. 10, the manufacturing method of the word line structure includes steps S100 to S600.
  • S100 Provide a substrate in which an isolation structure and an active region are formed.
  • the substrate may be a silicon substrate or a germanium substrate, and an isolation structure is formed in the substrate.
  • the isolation structure is used to define an active area in the substrate. After the isolation structure is formed, the isolation structure is The method forms an active region in the substrate.
  • the isolation structure is a shallow trench isolation structure, and the steps of forming the shallow trench isolation structure are as follows: etching a trench in a substrate; filling a dielectric in the trench; using The chemical mechanical polishing method flattens the surface of the wafer. Wherein, a chemical vapor deposition method is used to fill the trench with a dielectric material such as silicon oxide.
  • the shallow trench isolation structure has a small surface area, is compatible with chemical mechanical polishing technology, can be applied to smaller line widths and higher integration requirements, and is a better isolation technology. It should be noted that the isolation structure in this embodiment is not limited to the shallow trench isolation structure, and other isolation structures that can achieve isolation performance are also possible.
  • the material of the hard mask layer may be at least one of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, and silicon carbon oxynitride.
  • the hard mask layer is used as a mask for etching. Substrate.
  • S300 a patterned hard mask layer, where the pattern of the patterned hard mask layer is the same as the pattern of the word line.
  • double-patterning technology Double-Patterning, DP
  • double-patterning technology includes but not limited to self-aligned double patterning (SADP), photolithography- Etching-lithography-etching technology (Litho-Etch-Litho-Etch, LELE) and freeze coating etching technology (Litho-Freeze-Litho, LFL)
  • SADP self-aligned double patterning
  • Litho-Etch-Litho-Etch LELE
  • freeze coating etching technology Litho-Freeze-Litho, LFL
  • S400 Etch the substrate through the patterned hard mask layer to form word line trenches.
  • S500 Fill the word line trench with a conductive material layer, and etch the conductive material layer so that the top of the conductive material layer is lower than the surface of the substrate, and the remaining conductive material layers serve as the first word line 110 and the second word line 210.
  • a plurality of first word lines 110 extend along the X direction, a plurality of the first word lines 110 have the same length, and are aligned along the Y direction; a plurality of second word lines 210 extend along the X direction, and The second word lines 210 have the same length and are aligned along the Y direction; wherein, the first word line array 100 and the second word line array 200 are not aligned in the Y direction, The Y direction is perpendicular to the X direction.
  • the material of the conductive material layer is one or more of tungsten, aluminum, titanium, tantalum, titanium nitride, and polysilicon.
  • S600 Fill a dielectric layer in the word line trench, the top of the dielectric layer is flush with the surface of the substrate; etching the dielectric layer and the substrate in the set area to the first word line 110 or the second word line 210 to form a word Line contact grooves.
  • the word line contact grooves are used to form the first word line contact structure 111 and the second word line contact structure 211; deposit a contact material layer in the word line contact groove and the surface of the substrate; remove the surface of the substrate The contact material layer, and the remaining contact material layers serve as the first word line contact structure 111 and the second word line contact structure 211.
  • steps in the flowchart of FIG. 10 are displayed in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless specifically stated in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least part of the steps in FIG. 10 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution of these sub-steps or stages The sequence is not necessarily performed sequentially, but may be performed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
  • a semiconductor memory including:
  • the storage unit includes a storage capacitor and a transistor, the gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the storage capacitor;
  • multiple memory cells are arranged in an array of M rows and N columns. Memory cells in the same row share a word line, and memory cells in the same column share a bit line.
  • the word line has a word line structure. M and N are both positive integers. .
  • the semiconductor memory of this embodiment is based on the first word line array 100 and the second word line array 200 that are not aligned in the Y direction, by setting the first word line contact structure 111 and the second word line contact structure 211 in the horizontal plane. Provides a larger arrangement space, expands the cross-sectional area of the first word line contact structure 111 and the second word line contact structure 211, thereby reducing the first word line contact structure 111 and the second word line contact structure 211 and the corresponding The contact resistance between the word lines improves the opening and closing speed of the switch in the memory cell of the semiconductor memory.

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Abstract

一种字线结构及其制造方法和半导体存储器，字线结构包括第一字线阵列和第二字线阵列，第一字线阵列包括沿X方向延伸的多条第一字线，多条所述第一字线具有相同的长度，且沿Y方向对齐排列；第二字线阵列包括沿所述X方向延伸的多条第二字线，多条所述第二字线具有相同的长度，且沿所述Y方向对齐排列；其中，所述第一字线阵列与所述第二字线阵列在所述Y方向上不对齐，所述Y方向与所述X方向垂直。

Description

字线结构及其制造方法、半导体存储器
相关申请交叉引用
本申请要求2020年03月25日递交的、标题为“字线结构和半导体存储器”、申请号为2020102160246的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及一种字线结构及其制造方法和半导体存储器。
背景技术
科学技术的不断发展使人们对半导体技术的要求越来越高，半导体器件的面积不断缩小，因此对半导体制造工艺的精密程度要求和精确程度提出了更高的要求。半导体存储器是一种利用半导体电路进行存取的存储器,其中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)以其快速的存储速度和高集成度被广泛应用于各个领域。
发明内容
根据多个实施例，本申请第一方面提供一种字线结构，包括：
第一字线阵列，包括沿X方向延伸的多条第一字线，多条所述第一字线具有相同的长度，且沿Y方向对齐排列；以及
第二字线阵列，包括沿所述X方向延伸的多条第二字线，多条所述第二字线具有相同的长度，且沿所述Y方向对齐排列；
其中，所述第一字线阵列与所述第二字线阵列在所述Y方向上不对齐，所述Y方向与所述X方向垂直。
T形
根据多个实施例，本申请第二方面提供一种半导体存储器，包括：
如上述的字线结构；以及
存储单元，包括存储电容和晶体管，所述晶体管的栅极连接至字线，所述晶体管的漏极连接至位线，所述晶体管的源极连接至所述存储电容；
其中，多个所述存储单元以M行N列的阵列进行布置，同一行的存储单元共用一条所述字线，同一列的存储单元共用一条所述位线，所述字线具有所述字线结构，所述M和N均为正整数。
根据多个实施例，本申请第三方面提供一种字线结构的制造方法，包括：
提供衬底，所述衬底中形成有隔离结构和有源区；
在所述衬底表面形成硬掩模层；
图形化所述硬掩模层，其中，图形化的所述硬掩模层的图形与字线的图形相同；
通过图形化的所述硬掩模层蚀刻所述衬底以形成字线沟槽；
在所述字线沟槽中填充导电材料层，并蚀刻所述导电材料层以使所述导电材料层的顶部低于所述衬底的表面，剩余的所述导电材料层作为第一字线和第二字线；以及
在所述字线沟槽中填充介质层，所述介质层的顶部与所述衬底的表面相齐平；蚀刻设定区域的所述介质层和所述衬底至所述第一字线或所述第二字线以形成字线接触凹槽，所述字线接触凹槽用于形成第一字线接触结构和第二字线接触结构；在所述第一字线接触凹槽和所述第二字线接触凹槽中和所述衬底表面沉积接触材料层；以及去除所述衬底表面的所述接触材料层，剩余的所述接触材料层作为所述第一字线接触结构和所述第二字线接触结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为一实施例的字线接触结构的示意图；
图2为一实施例的第一字线阵列的示意图；
图3为一实施例的第二字线阵列的示意图；
图4为一实施例的T形字线接触结构的示意图；
图5为一实施例的半圆形字线接触结构的示意图；
图6为一实施例的字线接触结构呈交错排列的字线结构的示意图；
图7为一实施例的相邻的字线接触结构的形状相互补的示意图；
图8为另一实施例的相邻的字线接触结构的形状相互补的示意图；
图9为一实施例的凹槽型接触结构的示意图；
图10为一实施例的字线结构的制造方法。
具体实施方式
动态随机存储器包括多个重复的存储单元，随着动态随机存储器的尺寸不断缩小、集成度不断提高，动态随机存储器的特征尺寸和单元面积都会减小，因此字线接触结构的面积也会相应减小，使得字线接触结构与相应字线之间的接触电阻变大，导致流经字线的电流过小，从而降低了动态随机存储器的存储单元中开关的打开和关断速度。
为了便于理解本发明，下面将参照相关附图对本发明进列更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所行项目的任意的和所有的组合。
图1为一实施例的字线接触结构的示意图，如图1所示，字线结构包括第一字线阵列100和第二字线阵列200。
第一字线阵列100，包括沿X方向延伸的多条第一字线110，多条第一字线110具有相同的长度，且沿Y方向对齐排列；
第二字线阵列200，包括沿X方向延伸的多条第二字线210，多条第二字线210具有相同的长度，且沿Y方向对齐排列；
其中，第一字线阵列100与第二字线阵列200在Y方向上不对齐，Y方向与X方向垂直。
其中，第一字线阵列100与第二字线阵列200在Y方向上不对齐是指第一字线阵列100与第二字线阵列200不同列，即第一字线阵列100的沿Y方向延伸的第一对称轴与第二字线阵列200的沿Y方向延伸的第二对称轴不重合。具体地，第一字线110和第二字线210均形成在字线沟槽中，衬底中设有多个有源区300，每个有源区300均用于形成存储单元，每条第一字线110和第二字线210在衬底上的投影都穿过多个有源区300，第一字线110和第二字线210用于控制存储单元的晶体管的开启和关闭。
参考图1可知，在本实施例中，由于第一字线阵列100和第二字线阵列200在Y方向上不对齐，为字线接触结构提供了更大的设置空间，从而可以扩大字线接触结构的横截面的面积，进而减小字线接触结构和相应字线之间的接触电阻，提高存储单元中开关的打开和关断速度，也同时避免了字线接触结构与字线在Y方向上发生位置偏移时，可能导致的接触电阻增大甚至器件失效的问题。需要说明的是，本实施例中的横截面是指平行于衬底表面的截面，以下实施例中的横截面与本实施例中的定义相同，将不再进行赘述。
在一实施例中，多条第一字线110沿Y方向以设定间距等距排列，多条第二字线210沿Y方向以设定间距等距排列。图2为本实施例的第一字线阵列100的示意图，图3为本实施例的第二字线阵列200的示意图，如图2和图3所示，设置多条等距排列的第一字线110和多条等距排列的第二字线210可以使第一字线110和第二字线210适用于整齐排列的有源区，同时，当第一字线110的排列间距和第二字线210的排列间距相同时，可以使第一字线110连接的有源区和第二字线210连接的有源区在衬底上更好地兼容排列，从而降低了有源区、第一字线110和第二字线210的设计难度和加工难度。
在一实施例中，如图1所示，多条第一字线110和多条第二字线210在Y方向上互相间隔设置，即与每条第一字线110相邻设置的两条字线均为第二字线210，且与每条第二字线210相邻设置的两条字线均为第一字线110。相比非间隔设置的第一字线110和第二字线210，本实施例极大程度上地提高了字线结构中的字线分布密度，从而缩小了字线结构在Y方向上占用的器件面积，进而提高了半导体器件的集成度，减小了半导体器件的面积。
在一实施例中，如图2所示，多条第一字线110在X方向的正向一侧具有第一字线接触结构111，如图3所示，多条第二字线210在X方向的负向 一侧具有第二字线接触结构211。在另一实施例中，多条第一字线110在X方向的负向一侧具有第一字线接触结构111，多条第二字线210在X方向的正向一侧具有第二字线接触结构211。可以理解的是，若第一字线接触结构111和第二字线接触结构211都设置于相应字线的同一侧，如都设置于X方向的正向一侧或都设置于X方向的负向一侧，则字线接触结构的设置空间将非常受限。
因此，在上述两个将第一字线接触结构111和第二字线接触结构211分别设置于相应字线的不同侧的实施例中，可以为每个第一字线接触结构111和每个第二字线接触结构211都提供较大的设置空间，从而更加有效地降低每个字线接触结构的接触电阻。进一步地，基于本实施例的字线结构，第一字线接触结构111和第二字线接触结构211在Y方向上的尺寸可以实现最小工艺尺寸的1.2倍至2倍。
在一实施例中，第一字线接触结构111与第二字线接触结构211的横截面的面积相同。通过设置横截面的面积相同的第一字线接触结构111和第二字线接触结构211，可以使每个字线接触结构与相应的字线之间具有相同的接触电阻，当接触电阻相同时，在相同条件下流经每条字线的电流相同，从而使每个存储单元中开关的打开和关断速度一致，进而避免了不同存储单元之间的性能差异，提高了器件整体性能的可靠性。
在一实施例中，第一字线接触结构111和第二字线接触结构211的横截面的形状均为矩形、T形、半圆形中的一种。参考图1实施例中的第一字线接触结构111和第二字线接触结构211为矩形字线接触结构，图4为一实施例的T形字线接触结构的示意图，图5为一实施例的半圆形字线接触结构的示意图，如图1、图4和图5所示，任一横截面形状的第一字线接触结构111和第二字线接触结构211都适用于字线结构，因此，本实施例未示出的其他横截面形状的字线接触结构也属于本实施例的保护范围。
图6为一实施例的字线接触结构呈交错排列的字线结构的示意图，如图6所示，本实施例通过延长第一字线110的长度，使多个第一字线接触结构111呈交错排列，从而扩宽了第一字线接触结构111在X方向上的设置空间，增大了第一字线接触结构111在X方向上的尺寸，扩大了第一字线接触结构111与相应的第一字线110之间的接触面积，进一步减小了接触电阻。进一步 地，本实施例还通过延长第二字线210的长度，使多个第二字线接触结构211也呈交错排列，从而扩宽了第二字线接触结构211在X方向上的设置空间，增大了第二字线接触结构211在X方向上的尺寸，扩大了第二字线接触结构211与相应的第一字线110之间的接触面积。需要说明的是，交错排列的字线接触结构必然会使字线结构在X方向上的尺寸变大，从而需要占据更大的器件面积，因此，需要选择恰当的第一字线接触结构111和第二字线接触结构211在X方向上的尺寸，以实现接触电阻和器件尺寸之间的平衡。
图7为一实施例的相邻的字线接触结构的形状相互补的示意图，在本实施例中，第一字线接触结构111的形状为T形，相邻的T形第一字线接触结构111的设置方向相反。如图7所示，在第一字线的长度和第二字线的长度相同的前提下，本实施例通过使相邻的T形第一字线接触结构111的形状相互补设置，可以实现更大的横截面面积的第一字线接触结构111。进一步地，本实施例中相邻的T形第二字线接触结构211的设置方向也相反。需要说明的是，本实施例不具体限定第一字线接触结构111和第二字线接触结构211的形状和设置方向，其他如图8所示的能够实现相邻的字线接触结构的形状相互补的技术方案也属于本申请的保护范围。
在一实施例中，第一字线接触结构111和第二字线接触结构211均一端与晶体管的栅极电连接，另一端与驱动电路电连接，其中，驱动电路用于选择字线以实现对存储单元的访问。
在一实施例中，第一字线接触结构111和/或第二字线接触结构211为凹槽型接触结构，图9为本实施例的凹槽型接触结构的示意图，如图9所示，凹槽型接触结构是指，刻蚀层间介质层410，并蚀刻设定深度的字线400以形成凹槽，并在凹槽中填入导电材料，以形成接触结构430，使得字线400与金属层420电连接。本实施例通过设置第一字线接触结构111和/或第二字线接触结构211为凹槽型接触结构，可以在保证较大的接触面积的同时减小字线接触结构的面积，防止相邻的接触结构之间发生接触和短路，从而提高了半导体器件的集成度和可靠性。
在一实施例中，第一字线接触结构111和第二字线接触结构211的材料均为钨、铝、铜、钛、钽、多晶硅中的一种或多种，上述材料具有较好的导电性能，因此，可以进一步降低第一字线接触结构111和第二字线接触结构 211与相应字线之间的接触电阻。
图10为一实施例的字线结构的制造方法，如图10所示，字线结构的制造方法包括步骤S100至S600。
S100：提供衬底，所述衬底中形成有隔离结构和有源区。
具体地，所述衬底可以为硅衬底或锗衬底，所述衬底中形成有隔离结构，隔离结构用于在衬底中界定出有源区，形成隔离结构后，通过离子注入的方法在所述衬底中形成有源区。
可选地，所述隔离结构为浅沟槽隔离结构，形成所述浅沟槽隔离结构的步骤如下：在衬底中刻蚀出沟槽；在所述沟槽中填入介电质；利用化学机械抛光的方法使晶片表面平坦化。其中，采用化学气相沉积的方法在所述沟槽中填入介电质，所述介电质的材料例如氧化硅。浅沟槽隔离结构的表面积较小，与化学机械抛光技术兼容，能够适用于更小的线宽和更高的集成度要求，是一种较好的隔离技术。需要说明的是，本实施例中的隔离结构不局限于浅沟槽隔离结构，其他可以实现隔离性能的隔离结构也可。
S200：在衬底表面形成硬掩模层。
具体地，硬掩模层的材料可以为氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氮氧化硅中的至少一种，硬掩模层用于作为掩膜蚀刻衬底。
S300：图形化硬掩模层，其中，图形化的硬掩模层的图形与字线的图形相同。
具体地，采用双图案技术(Double-Patterning，DP)形成图形化的硬掩模层，其中双图案技术包括但不限于自对准双图案技术(Self-aligned double patterning，SADP)、光刻-蚀刻-光刻-蚀刻技术(Litho-Etch-Litho-Etch，LELE)以及冻结涂层蚀刻技术(Litho-Freeze-Litho，LFL)，本实施例采用双图案技术以提高字线沟槽的密度和器件的集成度。
S400：通过图形化的硬掩模层蚀刻衬底以形成字线沟槽。
S500：在字线沟槽中填充导电材料层，并蚀刻导电材料层以使导电材料层的顶部低于衬底的表面，剩余的导电材料层作为第一字线110和第二字线210。
其中，多条第一字线110沿X方向延伸，多条所述第一字线110具有相同的长度，且沿Y方向对齐排列；多条第二字线210沿所述X方向延伸，多 条所述第二字线210具有相同的长度，且沿所述Y方向对齐排列；其中，所述第一字线阵列100与所述第二字线阵列200在所述Y方向上不对齐，所述Y方向与所述X方向垂直。可选地，导电材料层的材料为钨、铝、钛、钽、氮化钛、多晶硅中的一种或多种。
S600：在字线沟槽中填充介质层，介质层的顶部与衬底的表面相齐平；蚀刻设定区域的介质层和衬底至第一字线110或第二字线210以形成字线接触凹槽，字线接触凹槽用于形成第一字线接触结构111和第二字线接触结构211；在字线接触凹槽中和衬底表面沉积接触材料层；去除衬底表面的接触材料层，剩余的接触材料层作为第一字线接触结构111和第二字线接触结构211。
应该理解的是，虽然图10的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图10中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
在一实施例中，还提供了一种半导体存储器，包括：
如上述字线结构；以及
存储单元，包括存储电容和晶体管，晶体管的栅极连接至字线，晶体管的漏极连接至位线，晶体管的源极连接至存储电容；
其中，多个存储单元以M行N列的阵列进行布置，同一行的存储单元共用一条字线，同一列的存储单元共用一条位线，字线具有字线结构，M和N均为正整数。
本实施例的所述半导体存储器基于在Y方向上不对齐的第一字线阵列100和第二字线阵列200，通过为第一字线接触结构111和第二字线接触结构211在水平面内提供更大的设置空间，扩大了第一字线接触结构111和第二字线接触结构211的横截面面积，从而减小了第一字线接触结构111和第二字线接触结构211和相应字线之间的接触电阻，提高了半导体存储器的存储单 元中开关的打开和关断速度。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
以上所述实施例的各技术特征可以进列任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进列描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种字线结构，包括：
    第一字线阵列，包括沿X方向延伸的多条第一字线，多条所述第一字线具有相同的长度，且沿Y方向对齐排列；以及
    第二字线阵列，包括沿所述X方向延伸的多条第二字线，多条所述第二字线具有相同的长度，且沿所述Y方向对齐排列；
    其中，所述第一字线阵列与所述第二字线阵列在所述Y方向上不对齐，所述Y方向与所述X方向垂直。
  2. 根据权利要求1所述的字线结构，其中多条所述第一字线沿所述Y方向以设定间距等距排列，多条所述第二字线沿所述Y方向以所述设定间距等距排列。
  3. 根据权利要求2所述的字线结构，其中多条所述第一字线和多条所述第二字线在所述Y方向上互相间隔设置。
  4. 根据权利要求3所述的字线结构，其中多条所述第一字线在所述X方向的正向一侧具有第一字线接触结构，多条所述第二字线在所述X方向的负向一侧具有第二字线接触结构。
  5. 根据权利要求3所述的字线结构，其中多条所述第一字线在所述X方向的负向一侧具有第一字线接触结构，多条所述第二字线在所述X方向的正向一侧具有第二字线接触结构。
  6. 根据权利要求4或5所述的字线结构，其中所述第一字线接触结构与所述第二字线接触结构的横截面的面积相同。
  7. 根据权利要求4或5所述的字线结构，其中所述第一字线接触结构和所述第二字线接触结构的横截面的形状均为矩形、T形、半圆形中的一种。
  8. 根据权利要求7所述的字线结构，其中相邻的T形的所述第一字线接触结构的设置方向相反。
  9. 根据权利要求8所述的字线结构，其中相邻的T形的所述第二字线接触结构的设置方向相反。
  10. 根据权利要求4或5所述的字线结构，其中所述第一字线接触结构和所述第二字线接触结构均一端与晶体管的栅极电连接，另一端与驱动电路电连接。
  11. 根据权利要求4或5所述的字线结构，其中所述第一字线接触结构和/或所述第二字线接触结构为凹槽型接触结构。
  12. 根据权利要求4或5所述的字线结构，其中所述第一字线接触结构和所述第二字线接触结构的材料均为钨、铝、铜、钛、钽、多晶硅中的一种或多种。
  13. 一种半导体存储器，包括：
    如权利要求1至12中的任一项所述的字线结构；以及
    存储单元，包括存储电容和晶体管，所述晶体管的栅极连接至字线，所述晶体管的漏极连接至位线，所述晶体管的源极连接至所述存储电容；
    其中，多个所述存储单元以M行N列的阵列进行布置，同一行的存储单元共用一条所述字线，同一列的存储单元共用一条所述位线，所述字线具有所述字线结构，所述M和N均为正整数。
  14. 一种字线结构的制造方法，包括：
    提供衬底，所述衬底中形成有隔离结构和有源区；
    在所述衬底表面形成硬掩模层；
    图形化所述硬掩模层，其中，图形化的所述硬掩模层的图形与字线的图形相同；
    通过图形化的所述硬掩模层蚀刻所述衬底以形成字线沟槽；
    在所述字线沟槽中填充导电材料层，并蚀刻所述导电材料层以使所述导电材料层的顶部低于所述衬底的表面，剩余的所述导电材料层作为第一字线和第二字线；以及
    在所述字线沟槽中填充介质层，所述介质层的顶部与所述衬底的表面相齐平；蚀刻设定区域的所述介质层和所述衬底至所述第一字线或所述第二字线以形成字线接触凹槽，所述字线接触凹槽用于形成第一字线接触结构和第二字线接触结构；在所述第一字线接触凹槽和所述第二字线接触凹槽中和所述衬底表面沉积接触材料层；以及去除所述衬底表面的所述接触材料层，剩余的所述接触材料层作为所述第一字线接触结构和所述第二字线接触结构。
  15. 根据权利要求14所述的方法，其中形成所述隔离结构包括：
    在所述衬底中刻蚀出沟槽；
    在所述沟槽中填入介电质；以及
    利用化学机械抛光的方法使晶片表面平坦化。
  16. 根据权利要求14所述的方法，其中所述硬掩模层的材料为氧化硅、氮化硅、碳化硅、氮氧化硅、碳氮化硅、碳氮氧化硅中的至少一种。
  17. 根据权利要求14所述的方法，其中多条所述第一字线沿X方向延伸，多条所述第一字线具有相同的长度，且沿Y方向对齐排列；多条所述第二字线沿所述X方向延伸，多条所述第二字线具有相同的长度，且沿所述Y方向对齐排列；其中，所述第一字线阵列与所述第二字线阵列在所述Y方向上不对齐，所述Y方向与所述X方向垂直。
  18. 根据权利要求14所述的方法，其中所述导电材料层的材料为钨、铝、钛、钽、氮化钛、多晶硅中的一种或多种。
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