WO2021184202A1 - 发光基板及其驱动方法、显示装置 - Google Patents

发光基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2021184202A1
WO2021184202A1 PCT/CN2020/079734 CN2020079734W WO2021184202A1 WO 2021184202 A1 WO2021184202 A1 WO 2021184202A1 CN 2020079734 W CN2020079734 W CN 2020079734W WO 2021184202 A1 WO2021184202 A1 WO 2021184202A1
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WIPO (PCT)
Prior art keywords
light
emitting
line
circuit
signal
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PCT/CN2020/079734
Other languages
English (en)
French (fr)
Inventor
杨明
王飞飞
郝卫
玄明花
张振宇
陈小川
时凌云
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/426,939 priority Critical patent/US11651743B2/en
Priority to KR1020217038187A priority patent/KR20220155181A/ko
Priority to JP2021568846A priority patent/JP2023527096A/ja
Priority to CN202080000255.1A priority patent/CN113748453B/zh
Priority to PCT/CN2020/079734 priority patent/WO2021184202A1/zh
Priority to EP20925742.7A priority patent/EP4123631A4/en
Priority to TW109145945A priority patent/TWI767473B/zh
Publication of WO2021184202A1 publication Critical patent/WO2021184202A1/zh
Priority to US18/182,478 priority patent/US11881184B2/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G09G3/3426—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines the different display panel areas being distributed in two dimensions, e.g. matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/02—Networking aspects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes

Definitions

  • the embodiments of the present disclosure relate to a light-emitting substrate, a driving method thereof, and a display device.
  • At least one embodiment of the present disclosure provides a light-emitting substrate including a plurality of light-emitting units arranged in an array, wherein each light-emitting unit includes a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal, and the driving circuit includes a first input terminal , A second input terminal and an output terminal, the plurality of light emitting elements are serially connected in series and connected between the driving voltage terminal and the output terminal, and the driving circuit is configured to be configured according to the first input terminal received by the first input terminal.
  • An input signal and a second input signal received by the second input terminal output a relay signal through the output terminal during the first time period, and provide a drive signal through the output terminal to all serially connected signals during the second time period.
  • the multiple light-emitting elements includes a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal, and the driving circuit includes a first input terminal , A second input terminal and an output terminal, the plurality of light emit
  • the drive circuit further includes a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a drive signal generation circuit, and a relay signal generation circuit;
  • the demodulation circuit is electrically connected to the second input terminal and the physical layer interface circuit, and is configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit.
  • the physical layer interface circuit is also electrically connected to the data processing control circuit, and is configured to process the communication data to obtain a data frame, and transmit the data frame to the data processing control circuit;
  • the data processing control circuit is also electrically connected to the first input terminal, the pulse width modulation circuit, and the relay signal generating circuit, and is configured to generate a pulse width control signal based on the data frame and to set the pulse width
  • the control signal is transmitted to the pulse width modulation circuit, and a relay control signal is generated based on the first input signal and the relay control signal is transmitted to the relay signal generating circuit;
  • the pulse width modulation circuit is also connected with
  • the drive signal generation circuit is electrically connected, and is configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit;
  • the drive signal generation circuit is also connected to The output terminal is electrically connected and configured to generate the drive signal in response to the pulse width modulation signal and output the drive signal from the output terminal;
  • the second input signal is a power line carrier communication signal
  • the power line carrier communication signal includes information corresponding to the communication data
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a plurality of address transfer lines, wherein the plurality of address transfer lines extend in a first direction and are configured to transmit the first input signal, and the plurality of light-emitting units Arranged into N rows and M columns and divided into multiple groups, each group of light-emitting units includes X rows and M columns and a total of X*M light-emitting units.
  • the X*M light-emitting units are sequentially numbered according to the row and column distribution positions, the first input terminal of the driving circuit of the light-emitting unit numbered 1 is electrically connected to the address transfer line corresponding to the group of light-emitting units, and the light-emitting unit numbered P
  • the output terminal of the driving circuit is electrically connected to the first input terminal of the driving circuit of the light-emitting unit numbered P+1, and the first input terminal of the driving circuit of the light-emitting unit numbered P+1 receives the number P
  • the relay signal output by the output terminal of the driving circuit of the light-emitting unit is used as the first input signal, N is an integer greater than 0, M is an integer greater than 0, 0 ⁇ X ⁇ N and X is an integer, 0 ⁇ P ⁇ X*M and P is an integer.
  • the X*M light-emitting units are sequentially numbered row by row and column by row according to the Z shape, or numbered row by row and column by row according to the S shape.
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a plurality of voltage transfer lines, wherein the plurality of voltage transfer lines extend along the first direction and are configured to transmit the second input signal, and the plurality of voltage transfer lines
  • the voltage transfer line corresponds to the N rows of light-emitting units one-to-one
  • the second input terminal of the drive circuit is electrically connected to the voltage transfer line corresponding to the row of the light-emitting unit including the drive circuit.
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a plurality of source address lines and a plurality of source voltage lines extending in a second direction, wherein the plurality of source address lines and the plurality of address transfer lines are one-to-one.
  • the multiple source voltage lines correspond to the multiple groups of light-emitting units one-to-one, and each source voltage line corresponds to multiple voltages corresponding to the corresponding group of light-emitting units
  • the patch cord is electrically connected and configured to transmit the second input signal, and the first direction crosses the second direction.
  • the source address line and the source voltage line are located on the same layer, the voltage transfer line and the address transfer line are located on the same layer, and the source address line is on the same layer as the source address line.
  • the address transfer lines are located on different layers.
  • the light-emitting substrate further includes a plurality of first test points, a plurality of second test points, a plurality of third test points, and a plurality of fourth test points; wherein, the plurality of first test points Point is located at one end of the source address line and the source voltage line away from the light-emitting unit; the plurality of second test points are located at the connection of the source address line and the address transfer line, and located at the source The connection between the voltage line and the voltage transfer line that is farthest from the first test point in the voltage transfer line connected to the source voltage line; the plurality of third test points are located at both ends of the voltage transfer line, and Located at the end of the address transfer line away from the light-emitting unit; the plurality of fourth test points are located in the connection between the source voltage line and the voltage transfer line except for the connection of the second test point Place.
  • the plurality of source address lines are arranged along the first direction, and the lengths of the plurality of source address lines along the second direction are different from each other.
  • the length of the source address line that is closer to the gate drive circuit in the display panel stacked on the light-emitting substrate is less than that of the gate drive circuit.
  • the length of the source address lines that are far apart; the plurality of source voltage lines are arranged along the first direction, and the lengths of the plurality of source voltage lines along the second direction are different from each other.
  • the length of the source voltage line that is closer to the gate drive circuit is smaller than the length of the source voltage line that is farther away from the gate drive circuit.
  • the plurality of source address lines are parallel to each other, and the length of the plurality of source address lines arranged in sequence along the first direction changes monotonously;
  • the source voltage lines are parallel to each other, and the length of the plurality of source voltage lines arranged in sequence along the first direction changes monotonously.
  • source address lines and source voltage lines corresponding to the same group of light-emitting units are arranged adjacent to each other.
  • the source voltage line does not overlap the address transfer line.
  • the source address line and the source voltage line are located in the gaps of multiple columns of light-emitting cells.
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a plurality of first driving voltage lines and a plurality of first common voltage lines extending along the second direction, wherein the first driving voltage line is connected to each light-emitting
  • the driving voltage terminal of the unit is electrically connected and configured to transmit the driving voltage
  • the driving circuit further includes a common voltage terminal
  • the first common voltage line is electrically connected to the common voltage terminal of the driving circuit of each light-emitting unit, and is configured to Transmission of common voltage.
  • the first driving voltage line and the first common voltage line are located on the same layer, and are located on the same layer as the source address line and the source voltage line.
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a plurality of second driving voltage lines and a plurality of second common voltage lines extending along the first direction, wherein the second driving voltage line is connected to the first common voltage line.
  • a driving voltage line is electrically connected to form a grid-shaped wiring
  • the second common voltage line is electrically connected to the first common voltage line and forms a grid-shaped wiring
  • the second driving voltage line and the first common voltage line are electrically connected
  • the two common voltage lines are located on the same layer, and are located on the same layer as the address transfer line and the voltage transfer line.
  • the multiple light-emitting elements are arranged in an array, and the driving circuit is located in a gap of the array formed by the multiple light-emitting elements.
  • the light-emitting element is a micro light-emitting diode.
  • the light-emitting substrate provided by an embodiment of the present disclosure further includes a flexible printed circuit board, wherein the flexible printed circuit board overlaps and is electrically connected to the source address line and the source voltage line, and the first test point Located on the side of the flexible printed circuit board away from the light-emitting unit.
  • At least one embodiment of the present disclosure further provides a display device, including a display panel and the light-emitting substrate according to any embodiment of the present disclosure, wherein the display panel has a display side and a non-display side opposite to the display side
  • the light-emitting substrate is arranged on the non-display side of the display panel as a backlight unit.
  • At least one embodiment of the present disclosure further provides a method for driving a light-emitting substrate according to any one of the embodiments of the present disclosure, including: providing the first input signal and the second input signal so that the output terminal is at the The relay signal is output in the first period, and the output terminal is caused to provide the driving signal to the plurality of light-emitting elements connected in series in the second period, so that the plurality of light-emitting elements are In the second time period, light is emitted under the action of the driving signal.
  • FIG. 1 is a schematic diagram of a light-emitting substrate provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of the arrangement of light-emitting units of the light-emitting substrate shown in FIG. 1;
  • FIG. 3 is a schematic diagram of a light-emitting unit in the light-emitting substrate shown in FIG. 1;
  • FIG. 4 is a schematic diagram of the pins of the driving circuit in the light-emitting unit of the light-emitting substrate shown in FIG. 1;
  • FIG. 5 is a schematic diagram of the arrangement of light-emitting elements and driving circuits in the light-emitting unit of the light-emitting substrate shown in FIG. 1;
  • 6A is a schematic block diagram of a driving circuit in a light-emitting unit of a light-emitting substrate provided by some embodiments of the present disclosure
  • 6B is a waveform diagram of the second input signal in the driving circuit shown in FIG. 6A;
  • FIG. 6C is a schematic diagram of the working flow of the driving circuit shown in FIG. 6A;
  • FIG. 6D is a signal timing diagram of the driving circuit shown in FIG. 6A;
  • FIG. 7A and 7B are schematic diagrams of the numbering of the light-emitting units of the light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 8A is a schematic diagram of test points of a light-emitting substrate provided by some embodiments of the present disclosure.
  • 8B and 8C are schematic plan views of a single test point in a light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of wiring of a light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of wiring of another light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 11 is a schematic diagram of another light-emitting substrate provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic cross-sectional view of a display device provided by some embodiments of the present disclosure.
  • Mini Light Emitting Diode or Micro Light Emitting Diode (Micro-LED) is small in size and high in brightness, and can be widely used in display devices.
  • the backlight module the backlight is finely adjusted to realize the display of high-dynamic range images (High-Dynamic Range, HDR).
  • the typical size (e.g., length) of Micro-LED is less than 50 microns, such as 10 microns to 50 microns; the typical size (e.g., length) of Mini-LED is 50 microns to 150 microns, such as 80 microns to 120 microns.
  • the light-emitting diodes Due to the small size of the light-emitting diodes, when the light-emitting diodes are applied to the backlight module, a huge number of light-emitting diodes are required. Moreover, since the light emitting diode is a current driving element, the signal line needs to transmit the current signal from the driving chip to the light emitting diode. If you want to independently control each light-emitting diode in the backlight module, a large number of driving chips and dense signal lines need to be set accordingly, which leads to higher product costs. In addition, the chip area of the drive circuit is usually large, which will take up more space, which increases the difficulty of product design and processing.
  • At least one embodiment of the present disclosure provides a light-emitting substrate, a driving method thereof, and a display device.
  • the light-emitting substrate can realize sub-regional independent control of light-emitting brightness, has low power consumption, high integration, simple control mode, and can cooperate with liquid crystal display devices to realize high-contrast display.
  • At least one embodiment of the present disclosure provides a light-emitting substrate including a plurality of light-emitting units arranged in an array.
  • Each light-emitting unit includes a driving circuit, a plurality of light-emitting elements, and a driving voltage terminal.
  • the driving circuit includes a first input terminal, a second input terminal and an output terminal.
  • a plurality of light-emitting elements are connected in series and connected between the driving voltage terminal and the output terminal.
  • the driving circuit is configured to output a relay signal through the output terminal during the first period according to the first input signal received by the first input terminal and the second input signal received by the second input terminal, and to provide driving through the output terminal during the second period Signals to multiple light-emitting elements connected in series.
  • FIG. 1 is a schematic diagram of a light-emitting substrate provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic diagram of an arrangement of light-emitting units of the light-emitting substrate shown in FIG. 1.
  • the light-emitting substrate 10 includes a base substrate 01 and a plurality of light-emitting units 100 arranged in an array on the base substrate 01.
  • the plurality of light emitting units 100 are arranged in N rows and M columns, N is an integer greater than 0, and M is an integer greater than 0.
  • the number of light-emitting units 100 can be determined according to actual requirements, for example, according to the size of the light-emitting substrate 10 and the required brightness.
  • the base substrate 01 may be a plastic substrate, a silicon substrate, a ceramic substrate, a glass substrate, a quartz substrate, etc.
  • the base substrate 01 includes a single-layer or multi-layer circuit, which is not limited in the embodiment of the present disclosure.
  • each row of light emitting cells 100 is arranged along a first direction
  • each column of light emitting cells 100 is arranged along a second direction.
  • the first direction is the row direction
  • the second direction is the column direction.
  • the embodiments of the present disclosure are not limited to this, and the first direction and the second direction can be arbitrary directions, and the first direction and the second direction only need to be crossed.
  • the plurality of light emitting units 100 are not limited to being arranged along a straight line, and can also be arranged along a curve, in a circle, or in any manner, which may be determined according to actual needs, and the embodiment of the present disclosure does not limit this.
  • each light-emitting unit 100 includes a driving circuit 110, a plurality of light-emitting elements 120, and a driving voltage terminal Vled.
  • the driving circuit 110 includes a first input terminal Di, a second input terminal Pwr, an output terminal OT, and a common voltage terminal GND.
  • the first input terminal Di receives a first input signal
  • the first input signal is, for example, an address signal for strobing the driving circuit 110 of the corresponding address.
  • the addresses of different driving circuits 110 may be the same or different.
  • the first input signal may be an 8-bit address signal, and the address to be transmitted can be obtained by parsing the address signal.
  • the second input terminal Pwr receives a second input signal.
  • the second input signal is, for example, a power line carrier communication signal.
  • the second input signal not only provides power to the driving circuit 110, but also transmits communication data to the driving circuit 110.
  • the communication data can be used to control the light-emitting duration of the corresponding light-emitting unit 100, thereby controlling its visual light-emitting brightness.
  • the output terminal OT can respectively output different signals in different time periods, for example, output relay signals and drive signals respectively.
  • the relay signal is an address signal provided to other drive circuits 110, that is, the first input terminal Di of the other drive circuit 110 receives the relay signal as the first input signal, thereby obtaining the address signal.
  • the driving signal may be a driving current for driving the light-emitting element 120 to emit light.
  • the common voltage terminal GND receives a common voltage signal, such as a ground signal.
  • the driving circuit 110 is configured to output the relay signal through the output terminal OT in the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr, and to pass the relay signal in the second period
  • the output terminal OT provides a driving signal to a plurality of light-emitting elements 120 connected in series.
  • the output terminal OT outputs a relay signal, and the relay signal is provided to the other driving circuits 110 so that the other driving circuits 110 obtain address signals.
  • the output terminal OT outputs a driving signal, which is provided to a plurality of light-emitting elements 120 connected in series, so that the light-emitting elements 120 emit light in the second time period.
  • the first period and the second period are different periods, and the first period may be earlier than the second period, for example.
  • the first time period can be continuously connected to the second time period, and the end time of the first time period is the start time of the second time period; or, there can be other time periods between the first time period and the second time period, and the other time periods can be used to achieve
  • the other period can also be used only to separate the first period and the second period, so as to avoid the signal of the output terminal OT in the first period and the second period from interfering with each other.
  • the working principle of the driving circuit 110 will be described in detail later, and will not be repeated here.
  • the driving signal when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light-emitting element 120 or from the light-emitting element 120 to the output terminal OT.
  • the flow direction of the driving current can be determined according to actual needs. The embodiment does not limit this.
  • "the output terminal OT outputs a drive signal” means that the output terminal OT provides a drive signal, and the direction of the drive signal can either flow from the output terminal OT or flow into the output terminal OT.
  • each light-emitting element 120 includes a positive electrode (+) and a negative electrode (-) (or, it may also be referred to as an anode and a cathode), and the positive and negative electrodes of the multiple light-emitting elements 120 are connected in series end-to-end, so that the driving voltage terminals Vled and A current path is formed between the output terminals OT.
  • the driving voltage terminal Vled provides a driving voltage, for example, a high voltage during a period (the second period) in which the light-emitting element 120 needs to emit light, and a low voltage in other periods.
  • a driving signal e.g., a driving current
  • the multiple light-emitting elements 120 emit light when the driving current flows.
  • the duration of the driving current the light-emitting duration of the light-emitting elements 120 can be controlled, thereby controlling the visual light-emitting brightness.
  • one light emitting unit 100 includes 6 light emitting elements 120, and the 6 light emitting elements 120 are arranged in 2 rows and 3 columns.
  • the six light-emitting elements 120 are sequentially numbered as (1,1), (1,2), (1,3), (2,1), (2 ,2) and (2,3), the numbers are shown in Figure 3.
  • the light-emitting element 120 at position (2,1) is used as the starting point of the series, and (1,1), (2,2), (1,2), (2) are connected in sequence.
  • the light-emitting element 120 at positions (1, 3) and (1, 3) has the light-emitting element 120 at positions (1, 3) as the end point of the series connection.
  • the anode of the light emitting element 120 at the position (2, 1) is connected to the driving voltage terminal Vled, and the cathode of the light emitting element 120 at the position (1, 3) is connected to the output terminal OT of the driving circuit 110.
  • the use of this distribution method and series connection method can effectively avoid the overlapping of the wiring, which is convenient for design and preparation.
  • the bending shape and length of the wiring between any two adjacent light-emitting elements 120 on the series circuit are approximately the same.
  • the resistance of the circuit itself is more balanced, which can improve the load balance and improve the stability of the circuit.
  • FIG. 5 is a schematic diagram of the arrangement of light-emitting elements and driving circuits in the light-emitting unit of the light-emitting substrate shown in FIG. 1.
  • multiple (for example, 6) light-emitting elements 120 are arranged in an array, for example, arranged in multiple rows and multiple columns, so that the light emission can be more uniform.
  • the driving circuit 110 is located in the gap of the array formed by the plurality of light-emitting elements 120.
  • the number of light-emitting elements 120 in each light-emitting unit 100 is not limited, and can be any number such as 4, 5, 7, 8, etc., and is not limited to 6. .
  • the plurality of light-emitting elements 120 can be arranged in any manner, for example, arranged according to a required pattern, and is not limited to a matrix arrangement.
  • the placement position of the driving circuit 110 is not limited, and can be placed in any gap between the light-emitting elements 120, which may be determined according to actual requirements, which is not limited in the embodiment of the present disclosure.
  • the driving circuit 110 includes a demodulation circuit 111, a physical layer interface circuit 112, a data processing control circuit 113, a pulse width modulation circuit 114, a driving signal generation circuit 115, a relay signal generation circuit 116, and a power supply circuit 117.
  • the demodulation circuit 111 is electrically connected to the second input terminal Pwr and the physical layer interface circuit 112, and is configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit 112.
  • the second input signal input by the second input terminal Pwr is a power line carrier communication signal
  • the power line carrier communication signal contains information corresponding to the communication data.
  • the communication data is data reflecting the duration of light emission, which in turn represents the required light emission brightness.
  • the embodiments of the present disclosure adopt the power line carrier communication (Power Line Carrier Communication, PLC) protocol to superimpose the communication data on the power signal, thereby effectively reducing The number of signal lines.
  • PLC Power Line Carrier Communication
  • FIG. 6B is a waveform diagram of the second input signal in the driving circuit shown in FIG. 6A.
  • the dashed ellipse box represents an enlarged view of the corresponding waveform.
  • the demodulation circuit 111 filters out the DC power component of the second input signal, so that communication data can be obtained.
  • the second input signal please refer to the conventional power line carrier communication signal, which will not be described in detail here.
  • the detailed description of the demodulation circuit 111 can also refer to the conventional power line carrier communication signal demodulation circuit, which will not be described in detail here.
  • the physical layer interface circuit 112 is also electrically connected to the data processing control circuit 113, configured to process the communication data to obtain a data frame (for example, frame rate data), and transmit the data frame to the data processing control circuit 113.
  • the data frame obtained by the physical layer interface circuit 112 contains information that needs to be transmitted to the driving circuit 110, such as information related to the light-emitting time (for example, the specific duration of the light-emitting time).
  • the physical layer interface circuit 112 may be a common port physical layer (Physical, PHY), and the detailed description can refer to the conventional design, which will not be described in detail here.
  • the data processing control circuit 113 is also electrically connected to the first input terminal Di, the pulse width modulation circuit 114, and the relay signal generating circuit 116.
  • the data processing control circuit 113 is configured to generate a pulse width control signal based on the data frame and transmit the pulse width control signal to the pulse width modulation circuit 114, and generate a relay control signal based on the first input signal and transmit the relay control signal to Relay signal generating circuit 116.
  • the required light-emitting time length of the light-emitting element 120 connected to the driving circuit 110 can be obtained, so the corresponding pulse width control signal is generated based on the light-emitting time length.
  • the relay control signal is a signal generated after the data processing control circuit 113 processes the first input signal.
  • the address signal corresponding to the drive circuit 110 can be known, and a relay control signal corresponding to the subsequent address will be generated, and the subsequent address corresponds to Other driving circuits 110.
  • the data processing control circuit 113 may be implemented as a single-chip microcomputer, a central processing unit (CPU), a digital signal processor, and the like.
  • the pulse width modulation circuit 114 is also electrically connected to the drive signal generation circuit 115, and is configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the drive signal generation circuit 115.
  • the pulse width modulation signal generated by the pulse width modulation circuit 114 corresponds to the light emission duration required by the light emitting element 120, for example, the effective pulse width duration is equal to the light emission duration required by the light emitting element 120.
  • the detailed description of the pulse width modulation circuit 114 can refer to a conventional pulse width modulation circuit, which will not be described in detail here.
  • the driving signal generating circuit 115 is also electrically connected to the output terminal OT, and is configured to generate a driving signal in response to the pulse width modulation signal, and output the driving signal from the output terminal OT.
  • outputting the drive signal from the output terminal OT can mean that the drive signal (for example, drive current) flows from the output terminal OT to the light-emitting element 120, or it can mean that the drive signal (for example, drive current) flows from the light-emitting element 120 into the output terminal OT, specifically The direction of current is not restricted.
  • the driving signal generation circuit 115 may include a current source A and a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor (Field Effect Transistor, FET), which Metal oxide semiconductor field effect transistors are called MOS transistors.
  • MOS Metal Oxide Semiconductor
  • FET Field Effect Transistor
  • the control electrode of the MOS tube receives the pulse width modulation signal transmitted by the pulse width modulation circuit 114, and is turned on or off under the control of the pulse width modulation signal.
  • the first pole of the MOS tube is connected to the output terminal OT, the second pole of the MOS tube is connected to the first pole of the current source A, and the second pole of the current source A is connected to the common voltage terminal GND to receive the common voltage.
  • the current source A may be a constant current source.
  • the MOS tube When the pulse width modulation signal is at an effective level, the MOS tube is turned on, and the current source A provides a driving current through the output terminal OT. When the pulse width modulation signal is at an invalid level, the MOS tube is turned off, and the output terminal OT does not provide a driving current at this time.
  • the duration of the effective level of the pulse width modulation signal is equal to the on-duration of the MOS transistor, and the on-duration of the MOS transistor is equal to the duration of the drive current provided by the output terminal OT. In this way, the light-emitting duration of the light-emitting element 120 can be further controlled, and thus the visual light-emitting brightness can be controlled.
  • the driving current flows from the OT terminal into the driving circuit 110, flows through the MOS transistor and the current source A in turn, and then flows into the ground terminal (for example, the common voltage terminal GND).
  • the driving signal generating circuit 115 may also adopt other circuit structure forms, which are not limited by the embodiments of the present disclosure.
  • the relay signal generating circuit 116 is also electrically connected to the output terminal OT, and is configured to generate a relay signal based on the relay control signal, and output the relay signal from the output terminal OT.
  • the relay control signal corresponds to the subsequent address
  • the relay signal generated based on the relay control signal contains the subsequent address
  • the subsequent address corresponds to the other driving circuits 110.
  • the relay signal is output from the output terminal OT, it is provided to the first input terminal Di of the separately provided drive circuit 110, and the relay signal is input as the first input signal to the separately provided drive circuit 110, so that the separately provided drive circuit 110
  • the driving circuit 110 obtains the corresponding address signal.
  • the relay signal generating circuit 116 may be implemented by a latch, a decoder, an encoder, etc., which is not limited in the embodiment of the present disclosure.
  • both the drive signal generating circuit 115 and the relay signal generating circuit 116 are electrically connected to the output terminal OT, the drive signal generating circuit 115 and the relay signal generating circuit 116 are different from each other.
  • the drive signal and the relay signal are output in the period of time, and the drive signal and the relay signal are transmitted in a time-sharing manner through the output terminal OT, so they will not affect each other.
  • the power supply circuit 117 is electrically connected to the demodulation circuit 111 and the data processing control circuit 113, respectively, and is configured to receive electric energy and supply power to the data processing control circuit 113.
  • the second input signal is a power line carrier communication signal.
  • the DC power component (ie, electric energy) in the second input signal is transmitted to the power supply circuit 117, and then the power supply circuit 117 provides data to the data.
  • Processing control circuit 113 the embodiment of the present disclosure is not limited to this, and the power supply circuit 117 may also be electrically connected with other circuits in the driving circuit 110 to provide electric energy.
  • the power supply circuit 117 can be implemented by a switch circuit, a voltage conversion circuit, a voltage stabilizing circuit, etc., which is not limited in the embodiment of the present disclosure.
  • the driving circuit 110 may also include more circuits and components, and is not limited to the demodulation circuit 111, the physical layer interface circuit 112, the data processing control circuit 113, and the pulse width modulation circuit described above. 114.
  • the driving signal generating circuit 115, the relay signal generating circuit 116, and the power supply circuit 117 may be determined according to the functions that need to be implemented, which is not limited in the embodiment of the present disclosure.
  • FIG. 6C is a schematic diagram of the working flow of the driving circuit shown in FIG. 6A
  • FIG. 6D is a signal timing diagram of the driving circuit shown in FIG. 6A.
  • the driving circuit 110 when the driving circuit 110 is working, it is first powered on (that is, powered on) to complete the initialization, and then the address writing operation is performed in the period S1, that is, in the period S1, the first input signal Di_1 passes through the first input signal Di_1.
  • An input terminal Di is input to the driving circuit 110 to write an address.
  • the first input signal Di_1 is sent through a separately provided transmitter.
  • the drive configuration is performed, and the relay signal Di_2 is output through the output terminal OT.
  • the relay signal Di_2 is input as the first input signal to the first input terminal Di of the driving circuit 110 provided separately.
  • the aforementioned first period is period S2.
  • the driving voltage terminal Vled is energized.
  • the time interval S3 is entered after an interval of about 10 microseconds. At this time, the driving voltage provided by the driving voltage terminal Vled becomes a high level.
  • the driving circuit 110 is in a normal working mode, and the output terminal OT provides a driving signal (for example, a driving current) according to the required duration, so that the light-emitting element 120 connected to the driving circuit 110 emits light according to the required duration.
  • a driving signal for example, a driving current
  • the aforementioned second period is period S4.
  • the light-emitting substrate 10 adopting the driving circuit 110 operates in a local backlight adjustment (Local Dimming) mode, which can achieve a high dynamic range effect.
  • the system is shut down, that is, the driving circuit 110 is powered off, and the driving voltage provided by the driving voltage terminal Vled becomes a low level, and the light emitting element 120 stops emitting light.
  • VREG, POR, Vreg_1.8, OSC, and Reset_B are all internal signals of the driving circuit 110, which will not pass through the first input terminal Di, the second input terminal Pwr, the output terminal OT, and the common voltage terminal GND. Output.
  • Di_1 is the first input signal received by the driving circuit 110
  • Di_2 is the relay signal output by the driving circuit 110 (that is, the first input signal received by the next connected driving circuit 110)
  • Di_n is a plurality of connected sequentially The first input signal received by the n-th driving circuit 110 in the driving circuit 110.
  • control circuit 110 can be implemented as a chip, the chip size (for example, length) is tens of micrometers, and the chip area is about a few hundred square micrometers or even less.
  • the light-emitting substrate 10 (for example, soldered in the light-emitting substrate 10) does not need to be arranged outside the light-emitting substrate 10 by binding, which saves the installation space of the printed circuit board, simplifies the structure, and facilitates the realization of lightness and thinness.
  • Each control circuit 110 directly drives one light-emitting unit 100, which avoids problems such as complicated operation and easy flicker in the horizontal scanning control mode.
  • the driving circuit 110 has a small number of ports, a small number of required signals, a simple control method, a simple wiring method, and low cost.
  • the light-emitting substrate 10 further includes a plurality of address transfer wires 130, and the plurality of address transfer wires 130 extend along the first direction and are configured to transmit the first input signal.
  • the multiple light-emitting units 100 in the light-emitting substrate 10 are arranged in N rows and M columns and are divided into multiple groups.
  • Each group of light-emitting units 100 includes X rows and M columns, a total of X*M light-emitting units 100, and multiple address transfer lines 130 and The multiple groups of light emitting units 100 correspond one to one.
  • the light emitting unit 100 is divided into N/X groups.
  • each group of light-emitting units 100 includes 2 rows and 5 columns, a total of 10 light-emitting units 100.
  • every 2 rows of light-emitting units 100 corresponds to one address transfer line 130, and the address transfer in the light-emitting substrate 10
  • the number of wires 130 is N/2.
  • N is an integer greater than
  • M is an integer greater than
  • 0 ⁇ X ⁇ N is an integer.
  • X*M light-emitting units 100 are sequentially numbered according to the row and column distribution positions.
  • FIG. 7A X*M light-emitting units are numbered row by row in a Z-shape
  • each rectangle in FIG. 7A represents a light-emitting unit 100
  • the number of each light-emitting unit 100 is marked on each Rectangle.
  • FIG. 7B X*M light-emitting units are numbered row by row and column by row in an S shape.
  • each light-emitting unit 100 represents a light-emitting unit 100, and each light-emitting unit 100 The number is marked in each rectangle. It should be noted that the manner in which the light-emitting units 100 are numbered sequentially according to the row and column distribution positions is not limited to the manner described above, and may be numbered according to other methods, so that the connection manners of multiple light-emitting units 100 can be flexibly adjusted. The embodiments of the present disclosure There is no restriction on this.
  • the first input Di of the driving circuit 110 of the light-emitting unit 100 numbered 1 is electrically connected to the address transfer line 130 corresponding to the group of light-emitting units 100, and the number is
  • the output terminal OT of the drive circuit 110 of the light-emitting unit 100 of P is electrically connected to the first input terminal Di of the drive circuit 110 of the light-emitting unit 100 numbered P+1, and the drive circuit 110 of the light-emitting unit 100 numbered P+1
  • the first input terminal Di receives the relay signal output by the output terminal OT of the driving circuit 110 of the light-emitting unit 100 numbered P as the first input signal.
  • 0 ⁇ P ⁇ X*M and P is an integer.
  • the first group of light-emitting units 100 when the numbering method shown in FIG. 7A is used, for a group of light-emitting units 100 numbered 1 (that is, the group of light-emitting units 100 on the uppermost side of the light-emitting substrate 10, or referred to as the first group of light-emitting units 100), it is located at the first group of light-emitting units 100.
  • the first input terminal Di of the driving circuit 110 of the light-emitting unit 100 in the first column of the row is electrically connected to the address transfer line 130 corresponding to the group of light-emitting units 100, and the output terminal OT of the driving circuit 110 of each light-emitting unit 100 is connected to the next light-emitting unit 100.
  • the first input terminal Di of the driving circuit 110 of the unit 100 is electrically connected (the output terminal OT of the driving circuit 110 of the last light-emitting unit 100 is not connected to other driving circuits 110).
  • the light-emitting units 100 located in the third row and first column are driven
  • the first input terminal Di of the circuit 110 is electrically connected to the address transfer line 130 corresponding to the group of light-emitting units 100, and the output terminal OT of the driving circuit 110 of each light-emitting unit 100 is connected to the first input terminal of the driving circuit 110 of the subsequent light-emitting unit 100 Di is electrically connected, and its connection method is similar to that of the first group of light-emitting units 100.
  • each group of light-emitting units 100 only the first input terminal Di of the driving circuit 110 of the first light-emitting unit 100 is electrically connected to the address transfer line 130, and the first input terminal Di of the driving circuit 110 of the other light-emitting unit 100 is electrically connected.
  • the input terminal Di receives the relay signal output by the driving circuit 110 of the previous light-emitting unit 100 as the first input signal. Therefore, for a group of light-emitting units 100, only one first input signal (ie address signal) needs to be provided through one address transfer line 130, so that all light-emitting units 100 in the group of light-emitting units 100 can obtain their respective address signals. . This greatly reduces the number of signal lines, saves wiring space, and simplifies the control method.
  • the light-emitting substrate 10 further includes a plurality of voltage transfer wires 140.
  • the plurality of voltage transfer lines 140 extend along the first direction and are configured to transmit the second input signal, and the plurality of voltage transfer lines 140 correspond to the N rows of light-emitting units one-to-one.
  • each row of light-emitting units 100 corresponds to one voltage transfer line 140, and the number of voltage transfer lines 140 in the light-emitting substrate 10 is N.
  • the first row of light-emitting units 100, the second row of light-emitting units 100, and the third row of light-emitting units 100 respectively correspond to a voltage transfer line 140.
  • the second input terminal Pwr of the driving circuit 110 in the light-emitting unit 100 is electrically connected to the voltage transfer line 140 corresponding to the row of the light-emitting unit 100 including the driving circuit 110. That is, the second input terminals Pwr of all the driving circuits 110 in a row of light-emitting units 10 are electrically connected to the voltage transfer line 140 corresponding to the row to receive the second input signal.
  • the light-emitting substrate 10 further includes a plurality of source address lines 150 and a plurality of source voltage lines 160 extending in the second direction.
  • the multiple source address lines 150 are electrically connected to the multiple address transfer lines 130 in a one-to-one correspondence, and are configured to transmit the first input signal.
  • the number of source address lines 150 is equal to the number of address transfer lines 130, and both are equal to N/X, that is, when the light-emitting units 100 are divided into N/X groups, each group of light-emitting units 100 corresponds to one source address line 150
  • an address transfer line 130, the source address line 150 and the address transfer line 130 transmit the first input signal to the first light-emitting unit 100 in the group of light-emitting units 100.
  • the source address line xAddr1 transmits the first input signal for the first group of light-emitting units 100
  • the source address line xAddr2 transmits the first input signal for the second group of light-emitting units 100.
  • multiple source voltage lines 160 correspond to multiple groups of light-emitting units 100 one-to-one, and each source voltage line 160 is electrically connected to multiple voltage transfer wires 140 corresponding to a corresponding group of light-emitting units 100, and is configured to transmit the second input. Signal.
  • the number of source voltage lines 160 is N/X, that is, when the light-emitting units 100 are divided into N/X groups, each group of light-emitting units 100 corresponds to one source voltage line 160, and the source voltage line 160 connects the second input
  • the signal is transmitted to a plurality of voltage transfer wires 140 corresponding to the group of light-emitting units 100, so as to provide a second input signal for all the light-emitting units 100 in the group of light-emitting units 100.
  • the source address line 150 and the source voltage line 160 corresponding to the same group of light emitting cells 100 are arranged adjacent to each other.
  • the source voltage line xPwr1 is electrically connected to the two voltage transfer wires 140 corresponding to the first group of light-emitting units 100, so as to provide a second input signal for the first and second rows of light-emitting units 100; source voltage The line xPwr2 is electrically connected to the two voltage transfer lines 140 corresponding to the second group of light-emitting units 100, so as to provide a second input signal for the third and fourth rows of light-emitting units 100 (the fourth row of light-emitting units 100 and 100 are not shown in the figure).
  • the corresponding voltage transfer line 140 ).
  • the second input terminals Pwr of the driving circuits 110 of all the light-emitting units 100 are electrically connected to the corresponding voltage transfer lines 140, and these voltage transfer lines 140 are connected to the same source voltage line 160. . Therefore, for a group of light-emitting units 100, only one second input signal needs to be provided through one source voltage line 160, so that all the light-emitting units 100 in the group of light-emitting units 100 can obtain the second input signal. This greatly reduces the number of signal lines, saves wiring space, and simplifies the control method.
  • the number of source address lines 150 and the number of source voltage lines 160 are both N/X.
  • the source address line 150 and the source voltage line 160 are located on the same layer, the voltage transfer line 140 and the address transfer line 130 are located on the same layer, and the source address line 150 and the address transfer line 130 are located on the same layer. Located on different floors. That is, the source address line 150 and the source voltage line 160 are prepared by a patterning process (such as a photolithography process), and the voltage transfer line 140 and the address transfer line 130 are prepared by another patterning process.
  • a patterning process such as a photolithography process
  • the source address line 150 and the source voltage An insulating layer is provided between the film layer where the line 160 is located and the voltage transfer line 140 and the film layer where the address transfer line 130 is located, and the corresponding wiring is electrically connected through the via hole penetrating the insulating layer. In this way, the preparation process can be simplified, and the usual semiconductor film preparation process can be compatible, and the production efficiency can be improved.
  • the light-emitting units 100 are divided into multiple groups, and the above-mentioned connection manner is adopted so that the light-emitting brightness of each group of light-emitting units 100 can be independently controlled.
  • the light-emitting duration of each group of light-emitting units 100 can be the same Or different, this can be determined according to usage and needs.
  • the first input signals provided to each group of light emitting units 100 are independent of each other, and the second input signals provided to each group of light emitting units 100 are independent of each other, so the light emitting brightness of each group of light emitting units 100 can be independently controlled.
  • the light-emitting substrate 10 can realize sub-regional independent control of light-emitting brightness, and has a wide range of applications. In addition, the number of ports of the driving circuit 110 is small, and the required control signal is small, so the control method is simple, the power consumption is small, and the operation is convenient.
  • the light-emitting substrate 10 has a high degree of integration, and can cooperate with a liquid crystal display device to realize high-contrast display.
  • FIG. 8A is a schematic diagram of test points of a light-emitting substrate provided by some embodiments of the present disclosure.
  • the light-emitting substrate 10 further includes a plurality of first test points 181, a plurality of second test points 182, a plurality of third test points 183, and a plurality of fourth test points. 184.
  • a plurality of light emitting units 100 are mainly distributed in the area Q. It should be noted that all the light-emitting units 100 may be located in the area Q, or most of the light-emitting units 100 may be located in the area Q, and the remaining part of the light-emitting units 100 may be located around the area Q. That is, the area Q represents the approximate distribution area of the plurality of light emitting units 100 that exceeds at least 70% of the total number.
  • the plurality of first test points 181 are located at one end of the source address line 150 and the source voltage line 160 away from the light emitting unit 100.
  • a plurality of second test points 182 are located at the junction of the source address line 150 and the address transfer line 130, and located at the farthest distance from the first test point 181 among the source voltage line 160 and the voltage transfer line 140 connected to the source voltage line 160 The connection point of the voltage transfer line 140.
  • the plurality of third test points 183 are located at both ends of the voltage transfer line 140 and at the end of the address transfer line 130 far away from the light-emitting unit 100.
  • a plurality of fourth test points 184 are located at the connection points between the source voltage line 160 and the voltage transfer line 140 except for the position where the second test point 182 is located.
  • the first test point 181 is located on the first side F1 of the light-emitting substrate 10
  • the second test point 182 and the fourth test point 184 are located in the middle area of the light-emitting substrate 10
  • the third test point The points 183 are located on the second side F2 and the third side F3 of the light-emitting substrate 10.
  • the address transfer line 130 and the voltage transfer line 140 are located on the same layer, and the source address line 150 and the source voltage line 160 are located on the same layer.
  • the two film layers are different layers.
  • Corresponding traces are electrically connected.
  • there may be signal line open circuit and short circuit of each signal line which may cause the light-emitting substrate to fail to work normally, and the faulty light-emitting substrate is put into operation without testing. The follow-up process will cause a waste of production resources.
  • the first test point 181, the second test point 182, the third test point 183, and the fourth test point 184 it is possible to timely and conveniently detect the signal line open circuit and short circuit during the preparation process and before shipment.
  • each test point can be exposed metal in a certain process stage to facilitate the placement of probes (such as test probes) for testing, and during subsequent processes, the test points can be covered by subsequent layers (such as dielectric layers).
  • the insulating layer covers and is no longer exposed, or it can still be exposed.
  • each test point is electrically connected to the corresponding signal line, the test point and the corresponding signal line can be formed integrally, or the separately provided conductive pattern can be electrically connected to the signal line by welding, using conductive adhesive, etc.
  • the provided conductive pattern serves as a test point.
  • the embodiment of the present disclosure does not limit this.
  • the 8B and 8C are schematic plan views of a single test point in a light-emitting substrate provided by some embodiments of the present disclosure.
  • the test point Te1 overlaps with the signal line L1 and is electrically connected.
  • the test point Te1 can be any one of the first test point 181, the second test point 182, the third test point 183, and the fourth test point 184.
  • the signal line L1 can be the address extension cord 130, the voltage extension cord 140, and the source Any one of the address line 150 and the source voltage line 160.
  • the shape of the test point Te1 is a circle.
  • the diameter of the circle is greater than or equal to the line width of the signal line L1, thereby facilitating the placement of the probe, so that the probe and the signal line L1 can be electrically connected better.
  • the test point Te2 overlaps with the signal line L2 and is electrically connected.
  • the test point Te2 may be any one of the first test point 181, the second test point 182, the third test point 183, and the fourth test point 184
  • the signal line L2 may be an address transfer line 130, a voltage transfer line 140. Any one of the source address line 150 and the source voltage line 160.
  • the shape of the test point Te2 is a polygon, specifically, it may be a square.
  • the side length of the square is greater than or equal to the line width of the signal line L2, thereby facilitating the placement of the probe, so that the probe and the signal line L2 can be electrically connected better.
  • each test point is not limited to the circle and square described above, and can also be any regular or irregular shape such as hexagon, ellipse, trapezoid, rectangle, triangle, etc.
  • the shape can be determined according to actual requirements, which is not limited in the embodiments of the present disclosure.
  • the relationship between the size of the test point and the size of the signal line can also be determined according to actual requirements, which is not limited in the embodiment of the present disclosure.
  • the source address line 150 and the source voltage line 160 are In the previous process preparation, the address transfer line 130 and the voltage transfer line 140 are formed on the source address line 150 and the source voltage line 160 by a subsequent process. There is an insulating layer between the two film layers, and the corresponding Wire the electrical connection.
  • the first test point 181 and the second test point 182 can be used to detect whether the source address line 150 and the source voltage line 160 are disconnected.
  • a test probe can be used to apply a voltage across the same source address line 150 or the same source voltage line 160, that is, to apply a voltage between a first test point 181 and a second test point 182, and at the same time, Test whether there is current between these two test points. When a current is detected, there is no disconnection between the first test point 181 and the second test point 182, that is, the corresponding source address line 150 or the source voltage line 160 is not disconnected.
  • the resistance value between the first test point 181 and the second test point 182 can also be detected. When the resistance value is infinite, it indicates that there is an open circuit between the two. If the resistance value is within a reasonable range, it indicates that the two There is no disconnection between them. For example, in some examples, a signal may be applied between the first test point Addr1_D and the second test point Addr1_U to detect whether an open circuit occurs.
  • the first test point 181 and the third test point 183 can be used to test whether the line formed by the source address line 150 and the address transfer line 130 is open, and to test Whether the line formed by the source voltage line 160 and the voltage transfer line 140 is disconnected.
  • a test probe can be used to apply a voltage at both ends of the same circuit, that is, a voltage is applied between a first test point 181 and a third test point 183, and at the same time, whether there is a test point between the two test points. Current.
  • a signal may be applied between the first test point Addr1_D and the third test point Addr1_L to detect whether an open circuit occurs.
  • an open circuit when an open circuit occurs between the first test point Addr1_D and the third test point Addr1_L, it may be between the first test point Addr1_D and the second test point Addr1_U, and the second test point Addr1_U and the third test point.
  • a signal is applied between the points Addr1_L to detect whether each part is disconnected. The method of detecting the open circuit is as described above, and will not be repeated here.
  • the third test point 183 can be used to test whether the voltage transfer line 140 is open.
  • a test probe can be used to apply voltage on both ends of the same voltage transfer line 140, that is, at a third test point 183 (for example, the third test point 183 on the left) and another third test point 183 (for example, A voltage is applied between the third test point 183) on the right, and at the same time, it is tested whether there is a current between the two test points.
  • a signal may be applied between the third test point Pwr1_L and the third test point Pwr1_R to detect whether an open circuit occurs. The method of detecting the open circuit is as described above, and will not be repeated here.
  • the location where the disconnection occurs can be found.
  • a test probe can be used to apply a voltage between the second test point 182 and the fourth test point 184 corresponding to the same group of light-emitting units 100, and at the same time, test whether there is a current between the two test points, so as to determine which segment is There is an open circuit on the line. The method of detecting the open circuit is as described above, and will not be repeated here.
  • the first test point 181 can be used for detection after the source address line 150 and the source voltage line 160 are formed, and the first test point can also be used after the address transfer line 130 and the voltage transfer line 140 are formed. 181 was tested.
  • a test probe can be used to apply a voltage between the two first test points 181, and at the same time, to test whether there is a current between the two test points. When a current is detected, there is a short circuit between the two first test points 181, that is, a short circuit between the corresponding two lines. When it is detected that there is no current, it means that there is no short circuit between the two first test points 181, that is, there is no short circuit between the corresponding two lines.
  • the resistance value between the two first test points 181 can also be detected. When the resistance value is infinite, it means that there is no short circuit between the two. If the resistance value is within a certain range or smaller, it means that the resistance There is a short circuit between.
  • a signal may be applied between the first test point Addr1_D and the first test point Pwr1_D to detect whether a short circuit occurs.
  • the second test point 182 can also be used for short-circuit detection, that is, a signal is applied between two second test points 182 to detect whether a short-circuit occurs.
  • test points are not limited, which can be determined according to actual requirements. For example, it is not necessary to set test points on each signal line, but only set test points on certain signal lines that need attention, thereby simplifying the preparation process and improving production efficiency.
  • other test points may be provided in the light-emitting substrate 10 provided in the embodiment of the present disclosure, so as to meet diversified testing requirements.
  • the light-emitting substrate 10 further includes a flexible printed circuit board (Flexible Printed Circuit, FPC) 170.
  • the flexible printed circuit board 170 overlaps the source address line 150 and the source voltage line 160 and is electrically connected by bonding.
  • the first test point 181 is located on the side of the flexible printed circuit board 170 away from the light emitting unit 100.
  • the flexible printed circuit board 170 is also used for binding with other components, such as a light-emitting control circuit.
  • the light emission control circuit can provide a plurality of first input signals and a plurality of second input signals, and these first input signals and second output signals are transmitted to each source address line 150 and source voltage line 160 through the flexible printed circuit board 170, It is further transmitted to each group of light-emitting units 100 to control the light-emitting substrate 10 to emit light.
  • FIG. 9 is a schematic diagram of wiring of a light-emitting substrate provided by some embodiments of the present disclosure.
  • a plurality of source address lines 150 and a plurality of source voltage lines 160 are alternately arranged.
  • the source address line xAddr1 and the source voltage line xPwr1 on the leftmost side are used to provide the first input signal and the second input signal for the first group of light-emitting units 100. Since the first group of light-emitting units 100 are located on the uppermost side of the light-emitting substrate, the source address line xAddr1 and the source voltage line xPwr1 are longer, and the source address line xAddr1 is electrically connected to the address transfer line Addr1 to transmit the first input signal to the group
  • the first input terminal Di of the driving circuit 110 of the first light-emitting unit 100, the source voltage line xPwr1, and the plurality of address transfer lines Pwr1 corresponding to the group of light-emitting units 100 are electrically connected to transmit the second input signal to all of the group.
  • the second input terminal Pwr of the driving circuit 110 of the light-emitting unit 100 are electrically connected to transmit the second input signal to all of the group.
  • the source address line xAddrn and the source voltage line xPwrn on the rightmost side are used to provide the first input signal and the second input signal for the last group of light-emitting units 100. Since the last group of light-emitting units 100 is located on the lowermost side of the light-emitting substrate, the source address line xAddrn and the source voltage line xPwrn are shorter, and the source address line xAddrn is electrically connected to the address transfer line Addrn to transmit the first input signal to the group.
  • the first input terminal Di of the driving circuit 110 of the first light-emitting unit 100, the source voltage line xPwrn and the plurality of address transfer lines Pwrn corresponding to the group of light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the second input terminal Pwr of the driving circuit 110 of all the light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the second input terminal Pwr of the driving circuit 110 of all the light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the second input terminal Pwr of the driving circuit 110 of all the light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the second input terminal Pwr of the driving circuit 110 of all the light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the second input terminal Pwr of the driving circuit 110 of all the light-emitting units 100 are electrically connected to transmit the second input signal to the group
  • the leftmost source voltage line xPwr1 overlaps with other address transfer lines Addr2,..., Addrn-1, Addrn except for the address transfer line Addr1, and generates capacitances Cpa_1_2,..., Cpa_1_n-1, Cpa_1_n in sequence.
  • the source voltage line xPwr2 overlaps with other address transfer lines Addr3,..., Addrn-1, Addrn except for the address transfer lines Addr1 and Addr2, and generates capacitances Cpa_2_3,..., Cpa_2_n-1, Cpa_2_n in sequence.
  • the source voltage line xPwrn-1 overlaps with the address transfer line Addrn and generates a capacitance Cpa_n-1_n.
  • the aforementioned capacitance may be a parasitic capacitance generated between lines, rather than a separate capacitive device.
  • the load of the second input signal in the multiple source voltage lines xPwr1, xPwr2,..., xPwrn needs to be lower than a certain value, and the capacitance corresponding to the second input signal needs to be as small as possible.
  • the source voltage lines xPwr1, xPwr2,..., xPwrn-1 and the address transfer wires Addr2,..., Addrn-1, Addrn overlap the capacitance generated may cause additional load, so it may be
  • the optical performance of the backlight using the light-emitting substrate has an additional impact.
  • the backlight including the light-emitting substrate is usually stacked with a separately provided display panel, and the display panel is arranged on the backlight.
  • the display panel usually includes a gate driving circuit, for example, the gate driving circuit is formed on the left side of the display panel to form a GOA (Gate Driver On Array) circuit for providing row scanning signals for pixels in the display panel.
  • GOA Gate Driver On Array
  • the leftmost source address line xAddr1 and the source voltage line xPwr1 have a longer length in the second direction, so they may affect the GOA circuit in the display panel, and make the gap between the backlight source and the display panel Signal crosstalk occurs, which may have additional influence on the display effect of the display device.
  • FIG. 10 is a schematic diagram of wiring of another light-emitting substrate provided by some embodiments of the present disclosure, and the light-emitting substrate can effectively avoid the above-mentioned problems.
  • a plurality of source address lines 150 are arranged along a first direction, and the lengths of the plurality of source address lines 150 along the second direction are different from each other.
  • the length of the source address line 150 that is closer to the gate drive circuit in the display panel stacked on the light-emitting substrate 10 is shorter than that of the source address line 150 that is farther away from the gate drive circuit.
  • the plurality of source voltage lines 160 are arranged along the first direction, and the lengths of the plurality of source voltage lines 160 along the second direction are different from each other. The length of the source voltage line 160 that is closer is less than the length of the source voltage line 160 that is far away from the gate driving circuit.
  • One input signal, the light-emitting unit 100 is divided into 9 groups from top to bottom.
  • the source voltage line xPwr1 provides the second input signal for the light-emitting units 100 in rows 1-4
  • the source voltage line xPwr2 provides the second input signal for the light-emitting units 100 in rows 5-8, and so on.
  • the source address line xAddr1 is connected to the first input terminal Di of the driving circuit 110 of the light-emitting unit 100 in the first row and the first column
  • the source address line xAddr2 is connected to the first input terminal of the driving circuit 110 of the light-emitting unit 100 in the fifth row and the first column. Input Di, and so on.
  • the leftmost source address line xAddrn and source voltage line xPwrn are used to provide the first input signal and the second input signal for the last group of light-emitting units 100. Since the last group of light-emitting units 100 are located on the lowermost side of the light-emitting substrate, the source address line xAddrn and the source voltage line xPwrn are shorter.
  • the source address line xAddr1 and the source voltage line xPwr1 on the rightmost side are used to provide the first input signal and the second input signal for the first group of light-emitting units 100. Since the first group of light-emitting units 100 are located on the uppermost side of the light-emitting substrate, the source address line xAddr1 and the source voltage line xPwr1 are longer.
  • the multiple source address lines 150 are parallel to each other, and the lengths of the multiple source address lines 150 arranged in sequence along the first direction change monotonously, for example, from left to right; the multiple source voltage lines 160 are parallel to each other, along The lengths of the multiple source voltage lines 160 arranged sequentially in the first direction change monotonously, for example, the lengths sequentially increase from left to right.
  • the source address lines 150 and the source voltage lines 160 corresponding to the same group of light-emitting units 100 are arranged adjacently, and the source address lines 150 and the source voltage lines 160 are located in the gaps of multiple columns of light-emitting units 100. .
  • the source address line 150 and the source voltage line 160 are arranged in the gaps of the multiple columns of light emitting cells 100, instead of being arranged on the leftmost or rightmost side of the multiple columns of light emitting cells 100, which can avoid the source address lines 150 and the source voltage lines 160
  • the signal in the light-emitting substrate 10 has an impact on the display panel stacked on the light-emitting substrate 10.
  • the source voltage line 160 does not overlap any address transfer line 130. Therefore, no capacitance (such as parasitic capacitance) is generated between the source voltage line 160 and the address transfer line 130, and thus no additional load is caused, thereby improving the optical performance of the backlight using the light-emitting substrate 10.
  • capacitance such as parasitic capacitance
  • the gate driving circuit is usually arranged on the leftmost side of the display panel, the leftmost source address line xAddrn and the source voltage line xPwrn in the light-emitting substrate 10 have shorter lengths in the second direction, so the gate driving The influence of the circuit is small, and the crosstalk between the backlight source and the display panel can be reduced or avoided, thereby improving the display effect of the display device.
  • the location of the address transfer line 130, the voltage transfer line 140, the source address line 150, and the source voltage line 160 can be changed according to requirements, and are not limited to those shown in FIGS. 9 and 10. In order to better adapt to application scenarios and better meet application requirements.
  • FIG. 11 is a schematic diagram of another light-emitting substrate provided by some embodiments of the present disclosure.
  • the light-emitting substrate 10 further includes a plurality of first driving voltage lines 191 and a plurality of first common voltage lines 201 extending in the second direction, and further includes A plurality of second driving voltage lines 192 and a plurality of second common voltage lines 202 are extended.
  • the first driving voltage line 191 is electrically connected to the driving voltage terminal Vled of each light-emitting unit 100, and is configured to transmit a driving voltage.
  • the second driving voltage line 192 is electrically connected to the first driving voltage line 191 and forms a grid-like wiring to reduce the transmission resistance and improve the voltage uniformity in the light-emitting substrate 10.
  • the first common voltage line 201 is electrically connected to the common voltage terminal GND of the driving circuit 110 of each light-emitting unit 100, and is configured to transmit a common voltage (for example, a ground voltage).
  • the second common voltage line 202 is electrically connected to the first common voltage line 201 and forms a grid-like wiring to reduce the transmission resistance and improve the voltage consistency in the light-emitting substrate 10.
  • the first driving voltage line 191 and the first common voltage line 201 are located in the same layer, and are located in the same layer as the source address line 150 and the source voltage line 160. Since the first driving voltage line 191, the first common voltage line 201, the source address line 150, and the source voltage line 160 all extend in the second direction, the four can be arranged on the same layer without overlapping each other, thereby simplifying the structure. Simplify the preparation process.
  • the second driving voltage line 192 and the second common voltage line 202 are located on the same layer, and are located on the same layer as the address transfer line 130 and the voltage transfer line 140. Since the second driving voltage line 192, the second common voltage line 202, the address transfer line 130, and the voltage transfer line 140 all extend along the first direction, the four can be arranged on the same layer without overlapping each other, thereby simplifying the structure. Simplify the preparation process.
  • the film layer where the first driving voltage line 191 in FIG. 11 is located is under the light-emitting element 120. Therefore, the first driving voltage line 191 may extend below the anode of the light-emitting element 120 and pass through the via hole and the light-emitting element.
  • the positive electrode of 120 is electrically connected, that is, the first driving voltage line 191 transmits the driving voltage to the positive electrode of the light-emitting element 120 (that is, to the driving voltage terminal Vled).
  • the negative electrode of the light-emitting element 120 overlaps the first driving voltage line 191 in FIG. 11, since the two are located in different layers, the negative electrode of the light-emitting element 120 is not electrically connected to the first driving voltage line 191.
  • the film layer where the first common voltage line 201 is located is under the driving circuit 110, therefore, the first common voltage line 201 is located under the driving circuit 110 and is electrically connected to the common voltage terminal GND of the driving circuit 110 through a via hole.
  • the length and width of the first driving voltage line 191, the second driving voltage line 192, the first common voltage line 201, and the second common voltage line 202 can be set to arbitrary values.
  • the length can be the same or different, and the width can also be the same or different, which can be determined according to actual needs, which is not limited in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, which includes a display panel and the light-emitting substrate provided in any embodiment of the present disclosure.
  • the display device can realize sub-regional independent control of luminous brightness, has low power consumption, high integration, simple control mode, and can cooperate with liquid crystal display devices to realize high-contrast display.
  • FIG. 12 is a schematic cross-sectional view of a display device provided by some embodiments of the present disclosure.
  • the display device 20 includes a display panel 210 and a light-emitting substrate 220.
  • the light-emitting substrate 220 may be a light-emitting substrate provided by any embodiment of the present disclosure, such as the aforementioned light-emitting substrate 10.
  • the display panel 210 has a display side P1 and a non-display side P2 opposite to the display side P1, and the light-emitting substrate 220 is disposed on the non-display side P2 of the display panel 210 as a backlight unit.
  • the light-emitting substrate 220 may serve as a surface light source to provide backlight to the display panel 210.
  • the display panel 210 may be an LCD panel, an electronic paper display panel, etc., which is not limited in the embodiment of the present disclosure.
  • the display device 20 may be an LCD device, an electronic paper display device, etc., or may also be other devices with a display function, etc., which is not limited in the embodiments of the present disclosure.
  • the display device 20 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an e-book, etc., which is not limited in the embodiments of the present disclosure.
  • the light-emitting substrate 10 provided by the embodiments of the present disclosure can be applied to the above-mentioned display device 20 as a backlight unit, or can be used alone as a substrate with a display function or a light-emitting function, which is not limited by the embodiments of the present disclosure. .
  • the display device 20 may further include more components and structures, which may be determined according to actual requirements, which are not limited in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a method for driving the light-emitting substrate, by which the light-emitting substrate provided in any embodiment of the present disclosure can be driven.
  • this driving method it is possible to realize the sub-regional independent control of the luminous brightness, the control method is simple, and the high-contrast display can be realized in cooperation with the liquid crystal display device.
  • the driving method includes the following operations:
  • the output terminal OT Provide the first input signal and the second input signal, make the output terminal OT output the relay signal in the first period, and make the output terminal OT provide the driving signal to the multiple light-emitting elements 120 connected in series in the second period, so that The plurality of light-emitting elements 120 emit light under the action of the driving signal in the second period.
  • the driving method may further include more steps and operations, which may be determined according to actual requirements, which are not limited in the embodiments of the present disclosure.

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Abstract

一种发光基板及其驱动方法、显示装置，该发光基板(10)包括阵列排布的多个发光单元(100)。每个发光单元(100)包括驱动电路(110)、多个发光元件(120)和驱动电压端(Vled)。多个发光元件(120)依次串联，并且连接在驱动电压端(Vled)和驱动电路(110)的输出端(OT)之间。驱动电路(110)配置为根据第一输入端(Di)接收的第一输入信号和第二输入端(Pwr)接收的第二输入信号在第一时段内通过输出端(OT)输出中继信号，以及在第二时段内通过输出端(OT)提供驱动信号至依次串联的多个发光元件(120)。该发光基板(10)可以实现发光亮度的分区域独立控制，功耗小，集成度高，控制方式简单，可与液晶显示器件配合实现高对比度显示。

Description

发光基板及其驱动方法、显示装置 技术领域
本公开的实施例涉及一种发光基板及其驱动方法、显示装置。
背景技术
随着发光二极管技术的发展，采用亚毫米量级甚至微米量级的发光二极管的背光源得到了广泛的应用。由此，不仅可以使利用该背光源的例如透射式显示产品的画面对比度达到有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品的水平，还可以使产品保留液晶显示(Liquid Crystal Display，LCD)的技术优势，进而提升画面的显示效果，为用户提供更优质的视觉体验。
发明内容
本公开至少一个实施例提供一种发光基板，包括阵列排布的多个发光单元，其中，每个发光单元包括驱动电路、多个发光元件和驱动电压端，所述驱动电路包括第一输入端、第二输入端和输出端，所述多个发光元件依次串联，并且连接在所述驱动电压端和所述输出端之间，所述驱动电路配置为根据所述第一输入端接收的第一输入信号和所述第二输入端接收的第二输入信号在第一时段内通过所述输出端输出中继信号，以及在第二时段内通过所述输出端提供驱动信号至依次串联的所述多个发光元件。
例如，在本公开一实施例提供的发光基板中，所述驱动电路还包括解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路和中继信号生成电路；所述解调电路与所述第二输入端和所述物理层接口电路电连接，配置为对所述第二输入信号进行解调以得到通信数据，并将所述通信数据传输至所述物理层接口电路；所述物理层接口电路还与所述数据处理控制电路电连接，配置为对所述通信数据进行处理以得到数据帧，并将所述数据帧传输至所述数据处理控制电路；所述数据处理控制电路还与所述第一输入端、所述脉宽调制电路和所述中继信号生成电路电连接，配置为基于所述数据帧产生脉宽控制信号并将所述脉宽控制信号传输至所述脉宽调 制电路，以及基于所述第一输入信号产生中继控制信号并将所述中继控制信号传输至所述中继信号生成电路；所述脉宽调制电路还与所述驱动信号生成电路电连接，配置为响应于所述脉宽控制信号产生脉宽调制信号，并将所述脉宽调制信号传输至所述驱动信号生成电路；所述驱动信号生成电路还与所述输出端电连接，配置为响应于所述脉宽调制信号产生所述驱动信号，并将所述驱动信号从所述输出端输出；所述中继信号生成电路还与所述输出端电连接，配置为基于所述中继控制信号生成所述中继信号，并将所述中继信号从所述输出端输出。
例如，在本公开一实施例提供的发光基板中，所述第二输入信号为电力线载波通信信号，所述电力线载波通信信号包含对应于所述通信数据的信息。
例如，本公开一实施例提供的发光基板还包括多条地址转接线，其中，所述多条地址转接线沿第一方向延伸且配置为传输所述第一输入信号，所述多个发光单元排列为N行M列且划分为多组，每组发光单元包括X行M列共X*M个发光单元，所述多条地址转接线与多组发光单元一一对应，在同一组发光单元中，所述X*M个发光单元根据行列分布位置依次编号，编号为1的发光单元的驱动电路的第一输入端与该组发光单元对应的地址转接线电连接，编号为P的发光单元的驱动电路的输出端与编号为P+1的发光单元的驱动电路的第一输入端电连接，所述编号为P+1的发光单元的驱动电路的第一输入端接收所述编号为P的发光单元的驱动电路的输出端输出的所述中继信号以作为所述第一输入信号，N为大于0的整数，M为大于0的整数，0<X≤N且X为整数，0<P<X*M且P为整数。
例如，在本公开一实施例提供的发光基板中，在同一组发光单元中，所述X*M个发光单元按照Z形逐行逐列依次编号，或者按照S形逐行逐列依次编号。
例如，本公开一实施例提供的发光基板还包括多条电压转接线，其中，所述多条电压转接线沿所述第一方向延伸且配置为传输所述第二输入信号，所述多条电压转接线与N行发光单元一一对应，所述驱动电路的第二输入端与包括该驱动电路的发光单元所在行对应的电压转接线电连接。
例如，本公开一实施例提供的发光基板还包括沿第二方向延伸的多条源地址线和多条源电压线，其中，所述多条源地址线与所述多条地址转接线一一对应电连接，且配置为传输所述第一输入信号，所述多条源电压线与所述 多组发光单元一一对应，每条源电压线与对应的一组发光单元对应的多条电压转接线电连接，且配置为传输所述第二输入信号，所述第一方向与所述第二方向交叉。
例如，在本公开一实施例提供的发光基板中，所述源地址线与所述源电压线位于同一层，所述电压转接线与所述地址转接线位于同一层，所述源地址线与所述地址转接线位于不同层。
例如，本公开一实施例提供的发光基板还包括多个第一测试点、多个第二测试点、多个第三测试点和多个第四测试点；其中，所述多个第一测试点位于所述源地址线和所述源电压线远离所述发光单元的一端；所述多个第二测试点位于所述源地址线与所述地址转接线的连接处，以及位于所述源电压线与和该源电压线相连的电压转接线中距离所述第一测试点最远的电压转接线的连接处；所述多个第三测试点位于所述电压转接线的两端，以及位于所述地址转接线远离所述发光单元的一端；所述多个第四测试点位于所述源电压线与所述电压转接线的连接处中除所述第二测试点所在位置以外的连接处。
例如，在本公开一实施例提供的发光基板中，所述多条源地址线沿所述第一方向排布，所述多条源地址线沿所述第二方向的长度彼此不同，在沿所述第一方向相距最远的两条源地址线中，与叠置在所述发光基板上的显示面板中栅极驱动电路相距较近的源地址线的长度小于与所述栅极驱动电路相距较远的源地址线的长度；所述多条源电压线沿所述第一方向排布，所述多条源电压线沿所述第二方向的长度彼此不同，在沿所述第一方向相距最远的两条源电压线中，与所述栅极驱动电路相距较近的源电压线的长度小于与所述栅极驱动电路相距较远的源电压线的长度。
例如，在本公开一实施例提供的发光基板中，所述多条源地址线彼此平行，沿所述第一方向依序排布的所述多条源地址线的长度单调变化；所述多条源电压线彼此平行，沿所述第一方向依序排布的所述多条源电压线的长度单调变化。
例如，在本公开一实施例提供的发光基板中，对应于同一组发光单元的源地址线和源电压线相邻设置。
例如，在本公开一实施例提供的发光基板中，所述源电压线不与所述地址转接线相交叠。
例如，在本公开一实施例提供的发光基板中，所述源地址线与所述源电压线位于多列发光单元的空隙中。
例如，本公开一实施例提供的发光基板还包括沿所述第二方向延伸的多条第一驱动电压线和多条第一公共电压线，其中，所述第一驱动电压线与每个发光单元的驱动电压端电连接，且配置为传输驱动电压，所述驱动电路还包括公共电压端，所述第一公共电压线与每个发光单元的驱动电路的公共电压端电连接，且配置为传输公共电压。
例如，在本公开一实施例提供的发光基板中，所述第一驱动电压线和所述第一公共电压线位于同一层，且与所述源地址线和所述源电压线位于同一层。
例如，本公开一实施例提供的发光基板还包括沿所述第一方向延伸的多条第二驱动电压线和多条第二公共电压线，其中，所述第二驱动电压线与所述第一驱动电压线电连接且形成网格状走线，所述第二公共电压线与所述第一公共电压线电连接且形成网格状走线，所述第二驱动电压线和所述第二公共电压线位于同一层，且与所述地址转接线和所述电压转接线位于同一层。
例如，在本公开一实施例提供的发光基板中，在同一个发光单元中，所述多个发光元件阵列排布，所述驱动电路位于所述多个发光元件构成的阵列的空隙中。
例如，在本公开一实施例提供的发光基板中，所述发光元件为微型发光二极管。
例如，本公开一实施例提供的发光基板还包括柔性印刷电路板，其中，所述柔性印刷电路板与所述源地址线和所述源电压线交叠且电连接，所述第一测试点位于所述柔性印刷电路板远离所述发光单元的一侧。
本公开至少一个实施例还提供一种显示装置，包括显示面板和如本公开任一实施例所述的发光基板，其中，所述显示面板具有显示侧和与所述显示侧相对的非显示侧，所述发光基板设置在所述显示面板的非显示侧以作为背光单元。
本公开至少一个实施例还提供一种如本公开任一实施例所述的发光基板的驱动方法，包括：提供所述第一输入信号和所述第二输入信号，使所述输出端在所述第一时段内输出所述中继信号，并且使所述输出端在所述第二时段内提供所述驱动信号至依次串联的所述多个发光元件，从而使所述多个发 光元件在所述第二时段内在所述驱动信号的作用下发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种发光基板的示意图；
图2为图1所示的发光基板的发光单元的排列示意图；
图3为图1所示的发光基板中一个发光单元的示意图；
图4为图1所示的发光基板的发光单元中的驱动电路的引脚示意图；
图5为图1所示的发光基板的发光单元中发光元件和驱动电路的排列示意图；
图6A为本公开一些实施例提供的一种发光基板的发光单元中驱动电路的原理示意框图；
图6B为图6A所示的驱动电路中第二输入信号的波形图；
图6C为图6A所示的驱动电路的工作流程示意图；
图6D为图6A所示的驱动电路的信号时序图；
图7A和图7B为本公开一些实施例提供的发光基板的发光单元的编号方式示意图；
图8A为本公开一些实施例提供的一种发光基板的测试点示意图；
图8B和图8C为本公开一些实施例提供的一种发光基板中单个测试点的平面示意图；
图9为本公开一些实施例提供的一种发光基板的布线示意图；
图10为本公开一些实施例提供的另一种发光基板的布线示意图；
图11为本公开一些实施例提供的另一种发光基板的示意图；以及
图12为本公开一些实施例提供的一种显示装置的剖面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描 述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在采用发光二极管的显示产品中，迷你发光二极管(Mini Light Emitting Diode，Mini-LED)或微型发光二极管(Micro Light Emitting Diode，Micro-LED)的尺寸小且亮度高，可以大量应用于显示装置的背光模组中，并对背光进行精细调节，从而实现高动态范围图像(High-Dynamic Range，HDR)的显示。例如，Micro-LED的典型尺寸(例如长度)小于50微米，例如10微米～50微米；Mini-LED的典型尺寸(例如长度)为50微米～150微米，例如80微米～120微米。由于发光二极管的尺寸小，当将发光二极管应用到背光模组中时，需要巨大数量的发光二极管。而且，由于发光二极管是电流驱动元件，故信号线需要将电流信号从驱动芯片传输给发光二极管。如果想要独立控制背光模组中的每一个发光二极管，则需要相应设置大量的驱动芯片以及密集的信号线，从而导致产品成本较高。此外，驱动电路的芯片面积通常较大，会占用较多空间，提高了产品的设计和加工难度。
本公开至少一个实施例提供一种发光基板及其驱动方法、显示装置。该发光基板可以实现发光亮度的分区域独立控制，功耗小，集成度高，控制方式简单，可与液晶显示器件配合实现高对比度显示。
下面，将参考附图详细地说明本公开的实施例。应当注意的是，不同的附图中相同的附图标记将用于指代已描述的相同的元件。
本公开至少一个实施例提供一种发光基板，该发光基板包括阵列排布的多个发光单元。每个发光单元包括驱动电路、多个发光元件和驱动电压端。 驱动电路包括第一输入端、第二输入端和输出端，多个发光元件依次串联，并且连接在驱动电压端和输出端之间。驱动电路配置为根据第一输入端接收的第一输入信号和第二输入端接收的第二输入信号在第一时段内通过输出端输出中继信号，以及在第二时段内通过输出端提供驱动信号至依次串联的多个发光元件。
图1为本公开一些实施例提供的一种发光基板的示意图，图2为图1所示的发光基板的发光单元的排列示意图。如图1和图2所示，发光基板10包括衬底基板01和在衬底基板01上阵列排布的多个发光单元100。例如，多个发光单元100排列为N行M列，N为大于0的整数，M为大于0的整数。例如，发光单元100的数量可以根据实际需求而定，例如根据发光基板10的尺寸和所需要的亮度而定，虽然图1中仅示出了3行5列发光单元100，但是应当理解，发光单元100的数量不限于此。例如，该衬底基板01可以为塑料基板、硅基板、陶瓷基板、玻璃基板、石英基板等，衬底基板01中包括有单层或多层线路，本公开的实施例对此不作限制。
例如，每一行发光单元100沿第一方向排列，每一列发光单元100沿第二方向排列。例如，第一方向为行方向且第二方向为列方向。当然，本公开的实施例不限于此，第一方向和第二方向可以为任意的方向，只需使第一方向和第二方向交叉即可。并且，多个发光单元100也不限于沿直线排列，也可以沿曲线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
图3为图1所示的发光基板中一个发光单元的示意图，图4为图1所示的发光基板的发光单元中的驱动电路的引脚示意图。如图1、图3和图4所示，每个发光单元100包括驱动电路110、多个发光元件120和驱动电压端Vled。
驱动电路110包括第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND。第一输入端Di接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动电路110。例如，不同的驱动电路110的地址可以相同或不同。第一输入信号可以为8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入端Pwr接收第二输入信号，第二输入信号例如为电力线载波通信信号。例如，第二输入信号不仅为驱动电路110提供电能，还向驱动电路110传输通信数据，该通信数据可用于控制相应的发光单元100的发光时长，进而控制其视觉上的发光亮度。输出端OT可在不 同的时段内分别输出不同的信号，例如分别输出中继信号和驱动信号。例如，中继信号为提供给其他驱动电路110的地址信号，也即是，其他驱动电路110的第一输入端Di接收该中继信号以作为第一输入信号，从而获取地址信号。例如，驱动信号可以为驱动电流，用于驱动发光元件120发光。公共电压端GND接收公共电压信号，例如接地信号。
驱动电路110配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT提供驱动信号至依次串联的多个发光元件120。在第一时段内，输出端OT输出中继信号，该中继信号被提供给其他驱动电路110以使其他驱动电路110获得地址信号。在第二时段内，输出端OT输出驱动信号，该驱动信号被提供给依次串联的多个发光元件120，使得发光元件120在第二时段内发光。例如，第一时段与第二时段为不同的时段，第一时段例如可以早于第二时段。第一时段可以与第二时段连续相接，第一时段的结束时刻即为第二时段的开始时刻；或者，第一时段与第二时段中间还可以有其他时段，该其他时段可以用于实现其他需要的功能，该其他时段也可以仅用于使第一时段和第二时段间隔开，以避免输出端OT在第一时段和第二时段的信号彼此干扰。关于驱动电路110的工作原理将在后文进行详细说明，此处不再赘述。
需要说明的是，当驱动信号为驱动电流时，驱动电流可以从输出端OT流向发光元件120，也可以从发光元件120流入输出端OT，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。在本文中，“输出端OT输出驱动信号”表示输出端OT提供驱动信号，而驱动信号的方向既可以从输出端OT流出，也可以流入输出端OT。
例如，如图1和图3所示，多个发光元件120依次串联，并且串联连接在驱动电压端Vled和输出端OT之间。例如，发光元件120可以为微型发光二极管(Micro-LED)或迷你发光二极管(Mini-LED)。例如，每个发光元件120包括正极(+)和负极(-)(或者，也可称为阳极和阴极)，多个发光元件120的正极和负极依序首尾串联，从而在驱动电压端Vled和输出端OT之间形成电流路径。驱动电压端Vled提供驱动电压，例如在需要使发光元件120发光的时段(第二时段)内为高电压，而在其他时段内为低电压。由此，在第二时段内，驱动信号(例如驱动电流)从驱动电压端Vled依次流经多个发 光元件120，然后流入驱动电路110的输出端OT。多个发光元件120在驱动电流流过时发光，通过控制驱动电流的持续时间，可以控制发光元件120的发光时长，从而控制视觉上的发光亮度。
例如，如图1和图3所示，在一些示例中，一个发光单元100包括6个发光元件120，该6个发光元件120排列为2行3列。例如，按照从左至右、从上至下的方式给该6个发光元件120依次编号为(1,1)、(1,2)、(1,3)、(2,1)、(2,2)和(2,3)，编号在图3中示出。例如，将6个发光元件120串联时，以位置(2,1)处的发光元件120作为串联的起点，依次连接(1,1)、(2,2)、(1,2)、(2,3)和(1,3)位置处的发光元件120，以位置(1,3)处的发光元件120作为串联的终点。例如，位置(2,1)处的发光元件120的正极连接驱动电压端Vled，位置(1,3)处的发光元件120的负极连接驱动电路110的输出端OT。采用这种分布方式和串联方式，可以有效避免走线交叠，便于设计和制备，并且，串联线路上任意的相邻两个发光元件120之间的走线的弯折形状和长度大致相同，使得线路本身的电阻较为均衡，可以提高负载均衡性，提高电路的稳定性。
图5为图1所示的发光基板的发光单元中发光元件和驱动电路的排列示意图。如图5所示，在同一个发光单元100中，多个(例如6个)发光元件120阵列排布，例如排列为多行多列，这样可以使发光更为均为。驱动电路110位于多个发光元件120构成的阵列的空隙中。
需要说明的是，本公开的实施例中，每个发光单元100中的发光元件120的数量不受限制，可以为4个、5个、7个、8个等任意数量，而不限于6个。多个发光元件120可以采用任意的排列方式，例如按照所需要的图案排列，而不限于矩阵排列方式。驱动电路110的设置位置不受限制，可以设置在发光元件120彼此之间的任意空隙中，这可以根据实际需求而定，本公开的实施例对此不作限制。
下面对驱动电路110的工作原理进行简要说明。
图6A为本公开一些实施例提供的一种发光基板的发光单元中驱动电路的原理示意框图。如图6A所示，该驱动电路110包括解调电路111、物理层接口电路112、数据处理控制电路113、脉宽调制电路114、驱动信号生成电路115、中继信号生成电路116和电源供给电路117。
例如，解调电路111与第二输入端Pwr和物理层接口电路112电连接， 配置为对第二输入信号进行解调以得到通信数据，并将该通信数据传输至物理层接口电路112。例如，第二输入端Pwr输入的第二输入信号为电力线载波通信信号，该电力线载波通信信号包含对应于通信数据的信息。例如，通信数据为反映发光时长的数据，进而代表了所需要的发光亮度。相比于通常的串行外设接口(Serial Peripheral Interface，SPI)协议，本公开实施例通过采用电力线载波通信(Power Line Carrier Communication，PLC)协议，将通信数据叠加在电源信号上，从而有效减少信号线的数量。
图6B为图6A所示的驱动电路中第二输入信号的波形图。如图6B所示，虚线椭圆框表示相应波形的放大图，第二输入信号为高电平时，其高电平的幅值在阈值幅值Vth的附近波动，例如，在第一幅值V 1和第二幅值V 2之间变化，V 2<Vth<V 1。通过调制第一幅值V 1和第二幅值V 2的变化规律，可以将通信数据调制到第二输入信号中，从而使第二输入信号在传输电能的同时传输对应于通信数据的信息。例如，解调电路111将第二输入信号的直流电源成分滤掉，从而可以得到通信数据。关于第二输入信号的详细说明可以参考常规的电力线载波通信信号，此处不再详述。相应地，解调电路111的详细说明也可以参考常规的电力线载波通信信号的解调电路，此处不再详述。
例如，物理层接口电路112还与数据处理控制电路113电连接，配置为对通信数据进行处理以得到数据帧(例如帧频数据)，并将数据帧传输至数据处理控制电路113。物理层接口电路112得到的数据帧包含了需要传输给该驱动电路110的信息，例如与发光时间相关的信息(例如发光时间的具体时长)。例如，物理层接口电路112可以为通常的端口物理层(Physical，PHY)，详细说明可参考常规设计，此处不再详述。
例如，数据处理控制电路113还与第一输入端Di、脉宽调制电路114和中继信号生成电路116电连接。数据处理控制电路113配置为基于数据帧产生脉宽控制信号并将该脉宽控制信号传输至脉宽调制电路114，以及基于第一输入信号产生中继控制信号并将该中继控制信号传输至中继信号生成电路116。例如，根据数据帧可以获知与该驱动电路110相连的发光元件120所需要的发光时长，因此基于该发光时长产生对应的脉宽控制信号。例如，中继控制信号为数据处理控制电路113对第一输入信号处理之后产生的信号。通过对第一输入信号进行处理(例如解析、锁存、译码等)，可以获知对应于该驱动电路110的地址信号，并且会产生对应于后续地址的中继控制信号，该 后续地址对应于其他驱动电路110。例如，数据处理控制电路113可以实现为单片机、中央处理器(Central Processing Unit，CPU)、数字信号处理器等。
例如，脉宽调制电路114还与驱动信号生成电路115电连接，配置为响应于脉宽控制信号产生脉宽调制信号，并将脉宽调制信号传输至驱动信号生成电路115。例如，脉宽调制电路114产生的脉宽调制信号对应于发光元件120所需要的发光时长，例如有效脉宽时长等于发光元件120所需要的发光时长。例如，脉宽调制电路114的详细说明可以参考常规的脉宽调制电路，此处不再详述。
例如，驱动信号生成电路115还与输出端OT电连接，配置为响应于脉宽调制信号产生驱动信号，并将该驱动信号从输出端OT输出。这里，将驱动信号从输出端OT输出，可以表示驱动信号(例如驱动电流)从输出端OT流向发光元件120，也可以表示驱动信号(例如驱动电流)从发光元件120流入输出端OT，具体的电流方向不受限制。
例如，在一些示例中，当驱动信号为驱动电流时，驱动信号生成电路115可以包括电流源A和金属氧化物半导体(Metal Oxide Semiconductor，MOS)场效应晶体管(Field Effect Transistor，FET)，将该金属氧化物半导体场效应晶体管称为MOS管。MOS管的控制极接收脉宽调制电路114传输的脉宽调制信号，从而在脉宽调制信号的控制下导通或截止。MOS管的第一极与输出端OT连接，MOS管的第二极与电流源A的第一极连接，电流源A的第二极与公共电压端GND连接以接收公共电压。例如，电流源A可以为恒流源。
当脉宽调制信号为有效电平时，MOS管导通，电流源A通过输出端OT提供驱动电流。当脉宽调制信号为无效电平时，MOS管截止，此时输出端OT不提供驱动电流。脉宽调制信号的有效电平的时长等于MOS管的导通时长，MOS管的导通时长等于输出端OT提供驱动电流的时长。由此，可以进一步控制发光元件120的发光时长，进而控制视觉上的发光亮度。例如，在一些示例中，当MOS管导通时，驱动电流从OT端流入驱动电路110，并依次流经MOS管和电流源A，然后流入接地端(例如公共电压端GND)。需要说明的是，本公开的实施例中，驱动信号生成电路115还可以采用其他电路结构形式，本公开的实施例对此不作限制。
例如，中继信号生成电路116还与输出端OT电连接，配置为基于中继控制信号生成中继信号，并将中继信号从输出端OT输出。例如，中继控制信号 对应于后续地址，基于中继控制信号产生的中继信号包含了后续地址，该后续地址对应于其他驱动电路110。中继信号从输出端OT输出后，被提供给另行提供的驱动电路110的第一输入端Di，该中继信号作为第一输入信号输入到该另行提供的驱动电路110，从而使该另行提供的驱动电路110获取对应的地址信号。中继信号生成电路116可以通过锁存器、译码器、编码器等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，虽然驱动信号生成电路115和中继信号生成电路116均与输出端OT电连接，但是，驱动信号生成电路115和中继信号生成电路116分别在不同的时段输出驱动信号和中继信号，驱动信号和中继信号通过输出端OT分时传输，因此不会彼此影响。
例如，电源供给电路117分别与解调电路111和数据处理控制电路113电连接，配置为接收电能并给数据处理控制电路113供电。例如，第二输入信号为电力线载波通信信号，经过解调电路111解调后，第二输入信号中的直流电源成分(即电能)传输至电源供给电路117，再由电源供给电路117提供给数据处理控制电路113。当然，本公开的实施例不限于此，电源供给电路117还可以与驱动电路110中的其他电路电连接以提供电能。电源供给电路117可以通过开关电路、电压转换电路、稳压电路等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，驱动电路110还可以包括更多的电路和部件，不限于上述的解调电路111、物理层接口电路112、数据处理控制电路113、脉宽调制电路114、驱动信号生成电路115、中继信号生成电路116和电源供给电路117，这可以根据需要实现的功能而定，本公开的实施例对此不作限制。
图6C为图6A所示的驱动电路的工作流程示意图，图6D为图6A所示的驱动电路的信号时序图。
如图6C和图6D所示，驱动电路110工作时，首先上电(也即通电)完成初始化，接着在时段S1进行写地址操作，也即是，在时段S1，第一输入信号Di_1通过第一输入端Di输入驱动电路110，从而写入地址。例如，第一输入信号Di_1通过另行提供的发送器发送。
接着，在时段S2，进行驱动配置，并且，通过输出端OT输出中继信号Di_2。例如，中继信号Di_2作为第一输入信号被输入到另行提供的驱动电路 110的第一输入端Di。例如，前述的第一时段为时段S2。
然后，在时段S3，驱动电压端Vled通电。例如，当多个驱动电路110均获取到对应的地址后，大约间隔10微秒之后进入时段S3。此时，驱动电压端Vled提供的驱动电压变为高电平。
接着，在时段S4，驱动电路110处于正常工作模式，输出端OT根据所需要的时长提供驱动信号(例如驱动电流)，以使与该驱动电路110连接的发光元件120根据需要的时长发光。例如，前述的第二时段为时段S4。例如，在作为显示装置的背光单元的情形，采用该驱动电路110的发光基板10在局部背光调节(Local Dimming)模式下工作，可以实现高动态范围效果。
最后，在时段S5，系统关闭，也即是，该驱动电路110断电，且驱动电压端Vled提供的驱动电压变为低电平，发光元件120停止发光。
需要说明的是，上述工作流程仅为示意性的，而非限制性的，驱动电路110实际的工作流程可以根据实际需求而定，本公开的实施例对此不作限制。在图6D中，VREG、POR、Vreg_1.8、OSC、Reset_B均为驱动电路110的内部信号，不会经过第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND输入或输出。Di_1为该驱动电路110接收的第一输入信号，Di_2为该驱动电路110输出的中继信号(也即为相连的下一个驱动电路110接收的第一输入信号)，Di_n为依次连接的多个驱动电路110中第n个驱动电路110接收的第一输入信号。
例如，该控制电路110可以实现为芯片，芯片尺寸(例如长度)为几十微米，芯片面积约为几百平方微米甚至更小，与Mini-LED的大小相似，具有小型化特点，便于集成到发光基板10中(例如焊接在发光基板10中)，而无须通过绑定的方式设置在发光基板10之外，节省了印刷电路板的设置空间，简化了结构，有利于实现轻薄化。每一个控制电路110直接驱动一个发光单元100，避免了行扫描控制方式操作复杂且容易闪烁等问题。并且，该驱动电路110的端口数量少，所需信号数量少，控制方式简单，走线方式简单，成本低。
例如，如图1所示，该发光基板10还包括多条地址转接线130，多条地址转接线130沿第一方向延伸且配置为传输第一输入信号。
例如，发光基板10中的多个发光单元100排列为N行M列且划分为多组，每组发光单元100包括X行M列共X*M个发光单元100，多条地址转 接线130与多组发光单元100一一对应。此时，发光单元100划分为N/X组。例如，在图1所示的示例中，每组发光单元100包括2行5列共10个发光单元100，因此，每2行发光单元100对应一条地址转接线130，发光基板10中的地址转接线130的数量为N/2。例如，N为大于0的整数，M为大于0的整数，0<X≤N且X为整数。
例如，在同一组发光单元100中，X*M个发光单元100根据行列分布位置依次编号。例如，在一些示例中，如图7A所示，X*M个发光单元按照Z形逐行逐列依次编号，图7A中每个矩形表示一个发光单元100，各个发光单元100的编号标注在各个矩形中。例如，在另一些示例中，如图7B所示，X*M个发光单元按照S形逐行逐列依次编号，类似地，图7B中每个矩形表示一个发光单元100，各个发光单元100的编号标注在各个矩形中。需要说明的是，发光单元100根据行列分布位置依次编号的方式不限于上文描述的方式，也可以根据其他方式进行编号，使得多个发光单元100的连接方式可灵活调节，本公开的实施例对此不作限制。
例如，如图1所示，在同一组发光单元100中，编号为1的发光单元100的驱动电路110的第一输入端Di与该组发光单元100对应的地址转接线130电连接，编号为P的发光单元100的驱动电路110的输出端OT与编号为P+1的发光单元100的驱动电路110的第一输入端Di电连接，编号为P+1的发光单元100的驱动电路110的第一输入端Di接收编号为P的发光单元100的驱动电路110的输出端OT输出的中继信号以作为第一输入信号。例如，0<P<X*M且P为整数。
例如，当采用图7A所示的编号方式时，对于编号为1的一组发光单元100(即发光基板10最上侧的一组发光单元100，或者称为第一组发光单元100)，位于第一行第一列的发光单元100的驱动电路110的第一输入端Di与该组发光单元100对应的地址转接线130电连接，各个发光单元100的驱动电路110的输出端OT与后一个发光单元100的驱动电路110的第一输入端Di电连接(最后一个发光单元100的驱动电路110的输出端OT不与其他驱动电路110连接)。对于编号为2的一组发光单元100(即紧邻第一组发光单元100的一组发光单元100，或者称为第二组发光单元100)，位于第三行第一列的发光单元100的驱动电路110的第一输入端Di与该组发光单元100对应的地址转接线130电连接，各个发光单元100的驱动电路110的输出端OT 与后一个发光单元100的驱动电路110的第一输入端Di电连接，其连接方式与第一组发光单元100类似。
通过上述连接方式，在每组发光单元100中，只有第一个发光单元100的驱动电路110的第一输入端Di与地址转接线130电连接，而其他发光单元100的驱动电路110的第一输入端Di接收前一个发光单元100的驱动电路110输出的中继信号作为第一输入信号。由此，对于一组发光单元100，只需要通过一条地址转接线130提供一个第一输入信号(即地址信号)，便可以使该组发光单元100中的所有发光单元100均获得各自的地址信号。这样极大地减少了信号线的数量，节省了布线空间，并且简化了控制方式。
例如，如图1所示，该发光基板10还包括多条电压转接线140。多条电压转接线140沿第一方向延伸且配置为传输第二输入信号，多条电压转接线140与N行发光单元一一对应。例如，每行发光单元100对应一条电压转接线140，发光基板10中的电压转接线140的数量为N。例如，如图1所示，第一行发光单元100、第二行发光单元100、第三行发光单元100分别对应一条电压转接线140。
例如，对于一行发光单元100，发光单元100中的驱动电路110的第二输入端Pwr与包括该驱动电路110的发光单元100所在行对应的电压转接线140电连接。也即是，一行发光单元10中所有的驱动电路110的第二输入端Pwr均与该行对应的电压转接线140电连接，以接收第二输入信号。
例如，如图1所示，该发光基板10还包括沿第二方向延伸的多条源地址线150和多条源电压线160。
例如，多条源地址线150与多条地址转接线130一一对应电连接，且配置为传输第一输入信号。例如，源地址线150的数量与地址转接线130的数量相等，均等于N/X，也即是，当发光单元100划分为N/X组时，每组发光单元100对应一条源地址线150和一条地址转接线130，该源地址线150和地址转接线130将第一输入信号传输至该组发光单元100中的第一个发光单元100。例如，如图1所示，源地址线xAddr1为第一组发光单元100传输第一输入信号，源地址线xAddr2为第二组发光单元100传输第一输入信号。
例如，多条源电压线160与多组发光单元100一一对应，每条源电压线160与对应的一组发光单元100对应的多条电压转接线140电连接，且配置为传输第二输入信号。例如，源电压线160的数量为N/X，也即是，当发光单 元100划分为N/X组时，每组发光单元100对应一条源电压线160，该源电压线160将第二输入信号传输至与该组发光单元100对应的多条电压转接线140，从而为该组发光单元100中的所有发光单元100提供第二输入信号。例如，对应于同一组发光单元100的源地址线150和源电压线160相邻设置。
例如，如图1所示，源电压线xPwr1与第一组发光单元100对应的两条电压转接线140电连接，从而为第一行和第二行发光单元100提供第二输入信号；源电压线xPwr2与第二组发光单元100对应的两条电压转接线140电连接，从而为第三行和第四行发光单元100提供第二输入信号(图中未示出第四行发光单元100及相应的电压转接线140)。
需要说明的是，在同一组发光单元100中，所有发光单元100的驱动电路110的第二输入端Pwr与相应的电压转接线140电连接，这些电压转接线140连接到同一条源电压线160。由此，对于一组发光单元100，只需要通过一条源电压线160提供一个第二输入信号，便可以使该组发光单元100中的所有发光单元100均获得第二输入信号。这样极大地减少了信号线的数量，节省了布线空间，并且简化了控制方式。
例如，在该发光基板10中，源地址线150的数量和源电压线160的数量均为N/X。
例如，在一些示例中，在衬底基板01之上，源地址线150与源电压线160位于同一层，电压转接线140与地址转接线130位于同一层，源地址线150与地址转接线130位于不同层。也即是，源地址线150与源电压线160采用一次图案化工艺(例如光刻工艺)制备，电压转接线140与地址转接线130采用另一次图案化工艺制备，源地址线150与源电压线160所在的膜层和电压转接线140与地址转接线130所在的膜层之间设置有绝缘层，通过贯穿绝缘层的过孔使相应的走线电连接。通过这种方式，可以简化制备工艺，并且能够兼容通常的半导体膜层制备工艺，提高生产效率。
在本公开的实施例中，发光单元100被划分为多组，采用上述连接方式使得每组发光单元100的发光亮度可以分别独立控制。例如，通过设置提供给各组发光单元100的第一输入信号和第二输入信号分别控制各组发光单元100的发光时长，进而控制视觉上的发光亮度，各组发光单元100的发光时长可以相同或不同，这可以根据使用方式和需求而定。提供给各组发光单元100的第一输入信号彼此独立，提供给各组发光单元100的第二输入信号彼此独 立，因此各组发光单元100的发光亮度可独立控制。该发光基板10可以实现发光亮度的分区域独立控制，适用范围广。并且，驱动电路110的端口数量少，所需要的控制信号少，因此控制方式简单，功耗小，便于操作。该发光基板10的集成度高，可与液晶显示器件配合实现高对比度显示。
图8A为本公开一些实施例提供的一种发光基板的测试点示意图。例如，如图8A所示，在一些实施例中，该发光基板10还包括多个第一测试点181、多个第二测试点182、多个第三测试点183和多个第四测试点184。例如，多个发光单元100主要分布于区域Q中。需要注意的是，可以所有的发光单元100均位于区域Q中，也可以大部分发光单元100位于区域Q中，剩余的一部分发光单元100可以位于区域Q的周围。也即是，区域Q表示至少超过总数数量的70％的多个发光单元100的大致分布区域。
例如，多个第一测试点181位于源地址线150和源电压线160远离发光单元100的一端。多个第二测试点182位于源地址线150与地址转接线130的连接处，以及位于源电压线160与和该源电压线160相连的电压转接线140中距离第一测试点181最远的电压转接线140的连接处。多个第三测试点183位于电压转接线140的两端，以及位于地址转接线130远离发光单元100的一端。多个第四测试点184位于源电压线160与电压转接线140的连接处中除第二测试点182所在位置以外的连接处。例如，在一些示例中，如图8A所示，第一测试点181位于发光基板10的第一侧F1，第二测试点182和第四测试点184位于发光基板10的中间区域，第三测试点183位于发光基板10的第二侧F2和第三侧F3。
在Mini-LED背光源的制备过程中，地址转接线130和电压转接线140位于同一层，源地址线150与源电压线160位于同一层，这两个膜层为不同层，通过过孔使相应的走线电连接。然而，在制备过程中，由于工艺限制或其他因素，可能会存在信号线断路及各信号线短路的情况，从而导致发光基板无法正常工作，在不进行检测的情况下将存在故障的发光基板投入后续工艺，会造成生产资源的浪费。
为此，通过设置第一测试点181、第二测试点182、第三测试点183和第四测试点184，可以在制备过程中及出货前及时且方便地检测信号线断路和短路的情况，尽早发现存在故障的发光基板，存在故障的发光基板不再进行后续工艺制程，从而避免生产资源的浪费，有效监控相应的背光源工艺及背光 源产品的质量，提升产品品质。
例如，各个测试点可以在某一工艺阶段中为裸露的金属，以便于放置探针(例如测试表笔)进行检测，而进行后续工艺时，测试点可以被后续的膜层(例如介电层等绝缘层)覆盖而不再裸露，或者也可以仍然为裸露的状态。例如，各个测试点与相应的信号线电连接，测试点与相应的信号线可以一体形成，也可以采用焊接、利用导电胶粘接等方式将另行提供的导电图案与信号线电连接，该另行提供的导电图案作为测试点。关于测试点的结构形式和形成方式，本公开的实施例对此不作限制。例如，可以采用电压表、电流表、欧姆表或其他任意适用的测试仪器，并借助探针对测试点进行电压检测、电流检测或电阻检测，从而获知两个测试点之间的线路是否存在断路、短路等情况。关于断路、短路等情况的检测原理可以参考常规设计，此处不再详述。
图8B和图8C为本公开一些实施例提供的一种发光基板中单个测试点的平面示意图。如图8B所示，测试点Te1与信号线L1交叠并电连接。测试点Te1可以为第一测试点181、第二测试点182、第三测试点183和第四测试点184中的任意之一，信号线L1可以为地址转接线130、电压转接线140、源地址线150和源电压线160中的任意之一。例如，测试点Te1的形状为圆形。例如，该圆形的直径大于或等于信号线L1的线宽，从而便于放置探针，使探针与信号线L1更好地实现电连接。
如图8C所示，测试点Te2与信号线L2交叠并电连接。类似地，测试点Te2可以为第一测试点181、第二测试点182、第三测试点183和第四测试点184中的任意之一，信号线L2可以为地址转接线130、电压转接线140、源地址线150和源电压线160中的任意之一。例如，测试点Te2的形状为多边形，具体地，可以为正方形。例如，该正方形的边长大于或等于信号线L2的线宽，从而便于放置探针，使探针与信号线L2更好地实现电连接。
需要说明的是，本公开的实施例中，各个测试点的形状不限于上文描述的圆形和正方形，还可以为六边形、椭圆形、梯形、矩形、三角形等任意的规则或不规则形状，这可以根据实际需求而定，本公开的实施例对此不作限制。测试点的尺寸与信号线的尺寸关系也可以根据实际需求而定，本公开的实施例对此不作限制。
下面结合图8A对各个测试点的测试方式和用途进行简要说明。这里，以地址转接线130与电压转接线140位于同一层、源地址线150与源电压线160 位于同一层且这两个膜层为不同层为例，源地址线150和源电压线160采用在先的工艺制备，地址转接线130和电压转接线140采用后续的工艺形成在源地址线150和源电压线160之上，两个膜层之间具有绝缘层，并通过过孔使相应的走线电连接。
例如，在形成源地址线150和源电压线160之后，利用第一测试点181和第二测试点182，可以检测源地址线150和源电压线160各自是否存在断路的情况。例如，可以采用测试表笔在同一条源地址线150或同一条源电压线160的两端施加电压，也即，在一个第一测试点181和一个第二测试点182之间施加电压，同时，测试这两个测试点之间是否有电流。当检测到电流时，则该第一测试点181和该第二测试点182之间没有断路，也即，相应的源地址线150或源电压线160没有断路。当检测到没有电流存在时，则说明该第一测试点181和该第二测试点182之间存在断路，也即，相应的源地址线150或源电压线160存在断路的情况。例如，还可以检测第一测试点181和第二测试点182之间的电阻值，当电阻值无穷大时，则说明两者之间存在断路的情况，若电阻值在合理范围内，则说明两者之间没有断路。例如，在一些示例中，可以在第一测试点Addr1_D与第二测试点Addr1_U之间施加信号以检测是否发生断路。
例如，在形成地址转接线130和电压转接线140之后，利用第一测试点181和第三测试点183，可以测试源地址线150与地址转接线130形成的线路是否存在断路的情况，以及测试源电压线160与电压转接线140形成的线路是否存在断路的情况。例如，可以采用测试表笔在同一条线路的两端施加电压，也即，在一个第一测试点181和一个第三测试点183之间施加电压，同时，测试这两个测试点之间是否有电流。例如，在一些示例中，可以在第一测试点Addr1_D与第三测试点Addr1_L之间施加信号以检测是否发生断路。例如，在一些示例中，当第一测试点Addr1_D与第三测试点Addr1_L之间发生断路时，可以在第一测试点Addr1_D与第二测试点Addr1_U之间、第二测试点Addr1_U与第三测试点Addr1_L之间施加信号以检测各部分是否发生断路。检测断路的方式如上所述，此处不再赘述。
例如，利用第三测试点183，可以测试电压转接线140是否存在断路的情况。例如，可以采用测试表笔在同一条电压转接线140的两端施加电压，也即，在一个第三测试点183(例如左侧的第三测试点183)和另一个第三测试 点183(例如右侧的第三测试点183)之间施加电压，同时，测试这两个测试点之间是否有电流。例如，在一些示例中，可以在第三测试点Pwr1_L与第三测试点Pwr1_R之间施加信号以检测是否发生断路。检测断路的方式如上所述，此处不再赘述。
例如，利用第二测试点182和第四测试点184，可以在形成地址转接线130和电压转接线140之后且发生断路的情形下，寻找断路发生的位置。例如，可以采用测试表笔在同一组发光单元100对应的第二测试点182和第四测试点184之间施加电压，同时，测试这两个测试点之间是否有电流，从而可以判断是哪一段线路存在断路的情况。检测断路的方式如上所述，此处不再赘述。
例如，对于短路的情况，可以在形成源地址线150和源电压线160之后，利用第一测试点181进行检测，还可以在形成地址转接线130和电压转接线140之后，利用第一测试点181进行检测。例如，可以采用测试表笔在两个第一测试点181之间施加电压，同时，测试这两个测试点之间是否有电流。当检测到电流时，则这两个第一测试点181之间存在短路的情况，也即，相应的两条线路之间短路。当检测到没有电流存在时，则说明这两个第一测试点181之间不存在短路的情况，也即，相应的两条线路之间没有短路。例如，还可以检测这两个第一测试点181之间的电阻值，当电阻值无穷大时，则说明两者之间没有短路，若电阻值在一定范围内或者较小，则说明两者之间存在短路的情况。例如，在一些示例中，可以在第一测试点Addr1_D与第一测试点Pwr1_D之间施加信号以检测是否发生短路。类似地，还可以利用第二测试点182进行短路检测，也即，在两个第二测试点182之间施加信号以检测是否发生短路。
需要说明的是，本公开的各个实施例中，测试点的数量和结构形式不受限制，这可以根据实际需求而定。例如，可以不必在每条信号线上设置测试点，而仅在需要关注的某些信号线上设置测试点，从而简化制备工艺，提高生产效率。例如，除了上述测试点，还可以在本公开实施例提供的发光基板10中设置其他测试点，以便于满足多样化的检测需求。
例如，如图8A所示，在一些实施例中，发光基板10还包括柔性印刷电路板(Flexible Printed Circuit，FPC)170。柔性印刷电路板170与源地址线150和源电压线160交叠且通过绑定(bonding)而电连接，第一测试点181 位于柔性印刷电路板170远离发光单元100的一侧。例如，柔性印刷电路板170还用于与其他部件绑定，该其他部件例如为发光控制电路。该发光控制电路可以提供多个第一输入信号和多个第二输入信号，这些第一输入信号和第二输出信号通过柔性印刷电路板170传输至各条源地址线150和源电压线160，再进一步传输至各组发光单元100，以控制该发光基板10发光。
图9为本公开一些实施例提供的一种发光基板的布线示意图。例如，如图9所示，在该发光基板中，多条源地址线150和多条源电压线160交替设置。
例如，最左侧的源地址线xAddr1和源电压线xPwr1用于为第一组发光单元100提供第一输入信号和第二输入信号。由于第一组发光单元100位于发光基板的最上侧，因此该源地址线xAddr1和源电压线xPwr1较长，源地址线xAddr1与地址转接线Addr1电连接以将第一输入信号传输至该组中第一个发光单元100的驱动电路110的第一输入端Di，源电压线xPwr1和与该组发光单元100对应的多条地址转接线Pwr1电连接以将第二输入信号传输至该组中所有发光单元100的驱动电路110的第二输入端Pwr。
例如，最右侧的源地址线xAddrn和源电压线xPwrn用于为最后一组发光单元100提供第一输入信号和第二输入信号。由于最后一组发光单元100位于发光基板的最下侧，因此该源地址线xAddrn和源电压线xPwrn较短，源地址线xAddrn与地址转接线Addrn电连接以将第一输入信号传输至该组中第一个发光单元100的驱动电路110的第一输入端Di，源电压线xPwrn和与该组发光单元100对应的多条地址转接线Pwrn电连接以将第二输入信号传输至该组中所有发光单元100的驱动电路110的第二输入端Pwr。
例如，从左至右，多条源电压线xPwr1、xPwr2、…、xPwrn的长度依次减小，多条源地址线xAddr1、xAddr2、…、xAddrn的长度也依次减小。因此，最左侧的源电压线xPwr1与除了地址转接线Addr1之外的其他地址转接线Addr2、…、Addrn-1、Addrn均存在交叠并依次产生电容Cpa_1_2、…、Cpa_1_n-1、Cpa_1_n。类似地，源电压线xPwr2与除了地址转接线Addr1和Addr2之外的其他地址转接线Addr3、…、Addrn-1、Addrn均存在交叠并依次产生电容Cpa_2_3、…、Cpa_2_n-1、Cpa_2_n。类似地，源电压线xPwrn-1与地址转接线Addrn存在交叠并产生电容Cpa_n-1_n。例如，上述电容可以为线路之间产生的寄生电容，而并非单独的电容器件。
在设计和使用过程中，需要使多条源电压线xPwr1、xPwr2、…、xPwrn中的第二输入信号的负载低于一定数值，第二输入信号相应的电容需要尽量小。在图9所示的发光基板中，源电压线xPwr1、xPwr2、…、xPwrn-1与地址转接线Addr2、…、Addrn-1、Addrn交叠产生的电容可能会引起额外负载，因此可能会对采用该发光基板的背光源的光学性能产生额外影响。
并且，在将该发光基板应用到背光源并将该背光源应用于显示设备中时，包括该发光基板的背光源通常与另行提供的显示面板叠置，显示面板设置在背光源之上。显示面板通常包括栅极驱动电路，该栅极驱动电路例如形成在显示面板的左侧以构成GOA(Gate Driver On Array)电路，用于为显示面板中的像素提供行扫描信号。如图9所示，最左侧的源地址线xAddr1和源电压线xPwr1在第二方向上的长度较长，因此可能会对显示面板中的GOA电路产生影响，使背光源与显示面板之间发生信号串扰，从而可能对显示设备的显示效果产生额外影响。
图10为本公开一些实施例提供的另一种发光基板的布线示意图，该发光基板可以有效避免上述问题。
例如，如图10所示，在一些实施例中，多条源地址线150沿第一方向排布，多条源地址线150沿第二方向的长度彼此不同，在沿第一方向相距最远的两条源地址线150中，与叠置在发光基板10上的显示面板中栅极驱动电路相距较近的源地址线150的长度小于与栅极驱动电路相距较远的源地址线150的长度。多条源电压线160沿第一方向排布，多条源电压线160沿第二方向的长度彼此不同，在沿第一方向相距最远的两条源电压线160中，与栅极驱动电路相距较近的源电压线160的长度小于与栅极驱动电路相距较远的源电压线160的长度。
例如，在该示例中，N＝36，X＝4，N/X＝36/4＝9，即每4行发光单元100共用一个第二输入信号，每4行发光单元100需要被提供一个第一输入信号，发光单元100被划分为从上至下的9组。例如，源电压线xPwr1为第1-4行发光单元100提供第二输入信号，源电压线xPwr2为第5-8行发光单元100提供第二输入信号，以此类推。相应地，源地址线xAddr1连接至第一行第一列发光单元100的驱动电路110的第一输入端Di，源地址线xAddr2连接至第五行第一列发光单元100的驱动电路110的第一输入端Di，以此类推。
例如，最左侧的源地址线xAddrn和源电压线xPwrn用于为最后一组发光 单元100提供第一输入信号和第二输入信号。由于最后一组发光单元100位于发光基板的最下侧，因此该源地址线xAddrn和源电压线xPwrn较短。最右侧的源地址线xAddr1和源电压线xPwr1用于为第一组发光单元100提供第一输入信号和第二输入信号。由于第一组发光单元100位于发光基板的最上侧，因此该源地址线xAddr1和源电压线xPwr1较长。
例如，多条源地址线150彼此平行，沿第一方向依序排布的多条源地址线150的长度单调变化，例如从左至右依次变长；多条源电压线160彼此平行，沿第一方向依序排布的多条源电压线160的长度单调变化，例如从左至右依次变长。例如，如图1和图10所示，对应于同一组发光单元100的源地址线150和源电压线160相邻设置，源地址线150与源电压线160位于多列发光单元100的空隙中。将源地址线150与源电压线160设置于多列发光单元100的空隙中，而不设置在多列发光单元100的最左侧或最右侧，可以避免源地址线150与源电压线160中的信号对叠置在发光基板10上的显示面板产生影响。
例如，源电压线160不与任意一条地址转接线130相交叠。因此，源电压线160与地址转接线130之间不会产生电容(例如寄生电容)，因而不会引起额外负载，从而提高采用该发光基板10的背光源的光学性能。
并且，由于栅极驱动电路通常设置在显示面板的最左侧，该发光基板10中最左侧的源地址线xAddrn和源电压线xPwrn在第二方向上的长度较短，因此对栅极驱动电路产生的影响较小，可以减小或避免背光源与显示面板之间的串扰，从而提高显示设备的显示效果。
需要说明的是，本公开的实施例中，地址转接线130、电压转接线140、源地址线150和源电压线160的设置位置可以根据需求而变化，而不限于图9和图10中所示的方式，从而更好地适应应用场景，更好地满足应用需求。
图11为本公开一些实施例提供的另一种发光基板的示意图。例如，如图11所示，在一些实施例中，发光基板10还包括沿第二方向延伸的多条第一驱动电压线191和多条第一公共电压线201，以及还包括沿第一方向延伸的多条第二驱动电压线192和多条第二公共电压线202。
例如，第一驱动电压线191与每个发光单元100的驱动电压端Vled电连接，且配置为传输驱动电压。第二驱动电压线192与第一驱动电压线191电连接且形成网格状走线，以减小传输电阻，提高发光基板10内的电压一致性。
例如，第一公共电压线201与每个发光单元100的驱动电路110的公共电压端GND电连接，且配置为传输公共电压(例如接地电压)。第二公共电压线202与第一公共电压线201电连接且形成网格状走线，以减小传输电阻，提高发光基板10内的电压一致性。
例如，第一驱动电压线191和第一公共电压线201位于同一层，且与源地址线150和源电压线160位于同一层。由于第一驱动电压线191、第一公共电压线201、源地址线150和源电压线160均沿第二方向延伸，因此四者可以设置在同一层且彼此不会交叠，从而简化结构，简化制备工艺。
例如，第二驱动电压线192和第二公共电压线202位于同一层，且与地址转接线130和电压转接线140位于同一层。由于第二驱动电压线192、第二公共电压线202、地址转接线130和电压转接线140均沿第一方向延伸，因此四者可以设置在同一层且彼此不会交叠，从而简化结构，简化制备工艺。
需要说明的是，图11中的第一驱动电压线191所在的膜层位于发光元件120之下，因此，第一驱动电压线191可以延伸至发光元件120的正极下方并通过过孔与发光元件120的正极电连接，也即是，第一驱动电压线191将驱动电压传输至发光元件120的正极(也即传输至驱动电压端Vled)。虽然图11中发光元件120的负极与第一驱动电压线191交叠，但是由于两者位于不同的膜层，因此发光元件120的负极不与第一驱动电压线191电连接。例如，第一公共电压线201所在的膜层位于驱动电路110之下，因此，第一公共电压线201位于驱动电路110下方并通过过孔与驱动电路110的公共电压端GND电连接。
需要说明的是，本公开的实施例中，第一驱动电压线191、第二驱动电压线192、第一公共电压线201和第二公共电压线202的长度和宽度可以设置为任意数值，其长度可以相同或不同，其宽度也可以相同或不同，这可以根据实际需求而定，本公开的实施例对此不作限制。
本公开至少一个实施例还提供一种显示装置，该显示装置包括显示面板和本公开任一实施例提供的发光基板。该显示装置可以实现发光亮度的分区域独立控制，功耗小，集成度高，控制方式简单，可与液晶显示器件配合实现高对比度显示。
图12为本公开一些实施例提供的一种显示装置的剖面示意图。例如，如图12所示，在一些实施例中，显示装置20包括显示面板210和发光基板220。 例如，发光基板220可以为本公开任一实施例提供的发光基板，例如前述的发光基板10。
例如，显示面板210具有显示侧P1和与显示侧P1相对的非显示侧P2，发光基板220设置在显示面板210的非显示侧P2以作为背光单元。例如，发光基板220可以作为面光源向显示面板210提供背光。例如，显示面板210可以为LCD面板、电子纸显示面板等，本公开的实施例对此不作限制。
例如，显示装置20可以为LCD装置、电子纸显示装置等，或者也可以为其他具有显示功能的装置等，本公开的实施例对此不作限制。例如，显示装置20可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、电子书等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
需要说明的是，本公开实施例提供的发光基板10既可以作为背光单元应用到上述显示装置20中，也可以单独作为具有显示功能或发光功能的基板使用，本公开的实施例对此不作限制。
关于该显示装置20的详细说明和技术效果可以参考上文中关于发光基板10的描述，此处不再赘述。该显示装置20还可以包括更多的部件和结构，这可以根据实际需求而定，本公开的实施例对此不作限制。
本公开至少一个实施例还提供一种发光基板的驱动方法，利用该驱动方法可以驱动本公开任一实施例提供的发光基板。利用该驱动方法，可以实现发光亮度的分区域独立控制，控制方式简单，可与液晶显示器件配合实现高对比度显示。
例如，在一些实施例中，该驱动方法包括如下操作：
提供第一输入信号和第二输入信号，使输出端OT在第一时段内输出中继信号，并且使输出端OT在第二时段内提供驱动信号至依次串联的多个发光元件120，从而使多个发光元件120在第二时段内在驱动信号的作用下发光。
关于该驱动方法的详细说明和技术效果可以参考上文中关于发光基板10的描述，此处不再赘述。该驱动方法还可以包括更多的步骤和操作，这可以根据实际需求而定，本公开的实施例对此不作限制。
有以下几点需要说明：
(1)本公开实施例附图只涉及到本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种发光基板，包括阵列排布的多个发光单元，其中，每个发光单元包括驱动电路、多个发光元件和驱动电压端，
    所述驱动电路包括第一输入端、第二输入端和输出端，所述多个发光元件依次串联，并且连接在所述驱动电压端和所述输出端之间，
    所述驱动电路配置为根据所述第一输入端接收的第一输入信号和所述第二输入端接收的第二输入信号在第一时段内通过所述输出端输出中继信号，以及在第二时段内通过所述输出端提供驱动信号至依次串联的所述多个发光元件。
  2. 根据权利要求1所述的发光基板，其中，所述驱动电路还包括解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路和中继信号生成电路；
    所述解调电路与所述第二输入端和所述物理层接口电路电连接，配置为对所述第二输入信号进行解调以得到通信数据，并将所述通信数据传输至所述物理层接口电路；
    所述物理层接口电路还与所述数据处理控制电路电连接，配置为对所述通信数据进行处理以得到数据帧，并将所述数据帧传输至所述数据处理控制电路；
    所述数据处理控制电路还与所述第一输入端、所述脉宽调制电路和所述中继信号生成电路电连接，配置为基于所述数据帧产生脉宽控制信号并将所述脉宽控制信号传输至所述脉宽调制电路，以及基于所述第一输入信号产生中继控制信号并将所述中继控制信号传输至所述中继信号生成电路；
    所述脉宽调制电路还与所述驱动信号生成电路电连接，配置为响应于所述脉宽控制信号产生脉宽调制信号，并将所述脉宽调制信号传输至所述驱动信号生成电路；
    所述驱动信号生成电路还与所述输出端电连接，配置为响应于所述脉宽调制信号产生所述驱动信号，并将所述驱动信号从所述输出端输出；
    所述中继信号生成电路还与所述输出端电连接，配置为基于所述中继控制信号生成所述中继信号，并将所述中继信号从所述输出端输出。
  3. 根据权利要求2所述的发光基板，其中，所述第二输入信号为电力线 载波通信信号，所述电力线载波通信信号包含对应于所述通信数据的信息。
  4. 根据权利要求1-3任一所述的发光基板，还包括多条地址转接线，其中，所述多条地址转接线沿第一方向延伸且配置为传输所述第一输入信号，
    所述多个发光单元排列为N行M列且划分为多组，每组发光单元包括X行M列共X*M个发光单元，所述多条地址转接线与多组发光单元一一对应，
    在同一组发光单元中，所述X*M个发光单元根据行列分布位置依次编号，编号为1的发光单元的驱动电路的第一输入端与该组发光单元对应的地址转接线电连接，编号为P的发光单元的驱动电路的输出端与编号为P+1的发光单元的驱动电路的第一输入端电连接，所述编号为P+1的发光单元的驱动电路的第一输入端接收所述编号为P的发光单元的驱动电路的输出端输出的所述中继信号以作为所述第一输入信号，
    N为大于0的整数，M为大于0的整数，0<X≤N且X为整数，0<P<X*M且P为整数。
  5. 根据权利要求4所述的发光基板，其中，在同一组发光单元中，所述X*M个发光单元按照Z形逐行逐列依次编号，或者按照S形逐行逐列依次编号。
  6. 根据权利要求4或5所述的发光基板，还包括多条电压转接线，
    其中，所述多条电压转接线沿所述第一方向延伸且配置为传输所述第二输入信号，所述多条电压转接线与N行发光单元一一对应，
    所述驱动电路的第二输入端与包括该驱动电路的发光单元所在行对应的电压转接线电连接。
  7. 根据权利要求6所述的发光基板，还包括沿第二方向延伸的多条源地址线和多条源电压线，
    其中，所述多条源地址线与所述多条地址转接线一一对应电连接，且配置为传输所述第一输入信号，
    所述多条源电压线与所述多组发光单元一一对应，每条源电压线与对应的一组发光单元对应的多条电压转接线电连接，且配置为传输所述第二输入信号，
    所述第一方向与所述第二方向交叉。
  8. 根据权利要求7所述的发光基板，其中，所述源地址线与所述源电压线位于同一层，所述电压转接线与所述地址转接线位于同一层，所述源地址 线与所述地址转接线位于不同层。
  9. 根据权利要求7或8所述的发光基板，还包括多个第一测试点、多个第二测试点、多个第三测试点和多个第四测试点；
    其中，所述多个第一测试点位于所述源地址线和所述源电压线远离所述发光单元的一端；
    所述多个第二测试点位于所述源地址线与所述地址转接线的连接处，以及位于所述源电压线与和该源电压线相连的电压转接线中距离所述第一测试点最远的电压转接线的连接处；
    所述多个第三测试点位于所述电压转接线的两端，以及位于所述地址转接线远离所述发光单元的一端；
    所述多个第四测试点位于所述源电压线与所述电压转接线的连接处中除所述第二测试点所在位置以外的连接处。
  10. 根据权利要求7-9任一所述的发光基板，其中，所述多条源地址线沿所述第一方向排布，所述多条源地址线沿所述第二方向的长度彼此不同，在沿所述第一方向相距最远的两条源地址线中，与叠置在所述发光基板上的显示面板中栅极驱动电路相距较近的源地址线的长度小于与所述栅极驱动电路相距较远的源地址线的长度；
    所述多条源电压线沿所述第一方向排布，所述多条源电压线沿所述第二方向的长度彼此不同，在沿所述第一方向相距最远的两条源电压线中，与所述栅极驱动电路相距较近的源电压线的长度小于与所述栅极驱动电路相距较远的源电压线的长度。
  11. 根据权利要求10所述的发光基板，其中，所述多条源地址线彼此平行，沿所述第一方向依序排布的所述多条源地址线的长度单调变化；
    所述多条源电压线彼此平行，沿所述第一方向依序排布的所述多条源电压线的长度单调变化。
  12. 根据权利要求10或11所述的发光基板，其中，对应于同一组发光单元的源地址线和源电压线相邻设置。
  13. 根据权利要求10-12任一所述的发光基板，其中，所述源电压线不与所述地址转接线相交叠。
  14. 根据权利要求7-13任一所述的发光基板，其中，所述源地址线与所述源电压线位于多列发光单元的空隙中。
  15. 根据权利要求7-14任一所述的发光基板，还包括沿所述第二方向延伸的多条第一驱动电压线和多条第一公共电压线，
    其中，所述第一驱动电压线与每个发光单元的驱动电压端电连接，且配置为传输驱动电压，
    所述驱动电路还包括公共电压端，所述第一公共电压线与每个发光单元的驱动电路的公共电压端电连接，且配置为传输公共电压。
  16. 根据权利要求15所述的发光基板，其中，所述第一驱动电压线和所述第一公共电压线位于同一层，且与所述源地址线和所述源电压线位于同一层。
  17. 根据权利要求15或16所述的发光基板，还包括沿所述第一方向延伸的多条第二驱动电压线和多条第二公共电压线，
    其中，所述第二驱动电压线与所述第一驱动电压线电连接且形成网格状走线，所述第二公共电压线与所述第一公共电压线电连接且形成网格状走线，
    所述第二驱动电压线和所述第二公共电压线位于同一层，且与所述地址转接线和所述电压转接线位于同一层。
  18. 根据权利要求1-17任一所述的发光基板，其中，在同一个发光单元中，所述多个发光元件阵列排布，所述驱动电路位于所述多个发光元件构成的阵列的空隙中。
  19. 根据权利要求1-18任一所述的发光基板，其中，所述发光元件为微型发光二极管。
  20. 根据权利要求9所述的发光基板，还包括柔性印刷电路板，
    其中，所述柔性印刷电路板与所述源地址线和所述源电压线交叠且电连接，所述第一测试点位于所述柔性印刷电路板远离所述发光单元的一侧。
  21. 一种显示装置，包括显示面板和如权利要求1-20任一所述的发光基板，
    其中，所述显示面板具有显示侧和与所述显示侧相对的非显示侧，所述发光基板设置在所述显示面板的非显示侧以作为背光单元。
  22. 一种如权利要求1-20任一所述的发光基板的驱动方法，包括：
    提供所述第一输入信号和所述第二输入信号，使所述输出端在所述第一时段内输出所述中继信号，并且使所述输出端在所述第二时段内提供所述驱动信号至依次串联的所述多个发光元件，从而使所述多个发光元件在所述第 二时段内在所述驱动信号的作用下发光。
PCT/CN2020/079734 2020-03-17 2020-03-17 发光基板及其驱动方法、显示装置 WO2021184202A1 (zh)

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JP2021568846A JP2023527096A (ja) 2020-03-17 2020-03-17 発光基板及びその駆動方法、表示装置
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