WO2023028794A1 - 发光基板及显示装置 - Google Patents

发光基板及显示装置 Download PDF

Info

Publication number
WO2023028794A1
WO2023028794A1 PCT/CN2021/115479 CN2021115479W WO2023028794A1 WO 2023028794 A1 WO2023028794 A1 WO 2023028794A1 CN 2021115479 W CN2021115479 W CN 2021115479W WO 2023028794 A1 WO2023028794 A1 WO 2023028794A1
Authority
WO
WIPO (PCT)
Prior art keywords
light
line
fan
electrically connected
emitting
Prior art date
Application number
PCT/CN2021/115479
Other languages
English (en)
French (fr)
Inventor
吴信涛
许邹明
田�健
刘纯建
雷杰
王杰
张建英
徐佳伟
谢晓冬
何敏
徐文结
张新秀
赵雪
桑华煜
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21955373.2A priority Critical patent/EP4294156A4/en
Priority to CN202180002351.4A priority patent/CN116075879A/zh
Priority to PCT/CN2021/115479 priority patent/WO2023028794A1/zh
Publication of WO2023028794A1 publication Critical patent/WO2023028794A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G09G3/342—Control of illumination source using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133612—Electrical details
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light-emitting substrate and a display device.
  • the first conductive layer is located on the base substrate; wherein, the first conductive layer includes a plurality of common voltage lines and a plurality of first connecting lines arranged at intervals; the plurality of common voltage lines are arranged along the first direction extended and aligned along the second direction;
  • a first insulating layer located on a side of the first conductive layer away from the base substrate
  • the second conductive layer is located on the side of the first insulating layer away from the base substrate; wherein the second conductive layer includes a plurality of first bridges arranged at intervals from each other;
  • At least one of the plurality of common voltage lines includes a plurality of signal line segments arranged at intervals; in the same common voltage line, two adjacent signal line segments are electrically connected through the first bridge portion and two adjacent At least one first connection line is provided at a line segment gap between the signal line segments;
  • the orthographic projection of the first bridging portion on the base substrate overlaps with the orthographic projection of the first connecting line on the base substrate .
  • the second conductive layer further includes a first connection part and a second connection part arranged at intervals from each other;
  • the first end of the first connection line is electrically connected to the first connection part through a first via hole, and the second end of the first connection line is electrically connected to the second connection part through a second via hole; Wherein, the first via hole and the second via hole penetrate the first insulating layer.
  • the orthographic projection of the first connection line on the base substrate covers the orthographic projection of the first via hole on the base substrate, and the first connection part is on the base substrate
  • the orthographic projection of the first via hole covers the orthographic projection of the first via hole on the base substrate
  • the orthographic projection of the first connecting line on the base substrate covers the orthographic projection of the second via hole on the base substrate, and the orthographic projection of the second connecting portion on the base substrate covers all Orthographic projection of the second via hole on the base substrate.
  • a width in the first direction of a region of the first connecting portion covering the first via hole is greater than a width in the first direction of the first connection line
  • the width of the area of the second connecting part covering the second via hole in the first direction is greater than the width of the first connecting line in the first direction.
  • the width of the first bridging portion in the first direction ranges from 100 microns to 250 microns, and the width of the first connecting line in the first direction ranges from 0.6 microns to 2.5 microns.
  • the length of the first connection line in the second direction is greater than the length of the first bridging portion in the second direction.
  • first gap between the first bridging portion extending to the first connecting portion and the first connecting portion, the first bridging portion extending to the second connecting portion
  • second gap between one side of one side and the second connecting part
  • At least one of the width of the first gap and the width of the second gap ranges from 20 microns to 50 microns.
  • the width of the gap between the first connection line and the signal line segment in the first direction ranges from 20 microns to 50 microns.
  • the thickness of the first bridging portion is greater than or equal to the thickness of the first connecting portion and the second connecting portion in the second conductive layer.
  • the second conductive layer further includes a plurality of pads
  • One end of the first connecting portion is electrically connected to one of the pads, and the other end is electrically connected to the first end of the first connecting line;
  • the other end of the second connection portion is electrically connected to the other pad, and the other end is electrically connected to the second end of the first connection line.
  • the plurality of common voltage lines are located in the display area; the display area further includes a plurality of light emitting units, and the light emitting units include a driving circuit and a plurality of light emitting elements; wherein the driving circuit includes a common voltage terminal and the output terminal; the plurality of light-emitting elements are sequentially connected in series between the driving voltage terminal and the output terminal; the common voltage terminal is electrically connected to the common voltage line; the pad is connected to the light-emitting element and the at least one electrical connection in the drive circuit;
  • the multiple light emitting elements in the light emitting unit are divided into M element groups, each element group includes N light emitting elements arranged along the first direction; the M element groups are arranged along the second direction; N is an integer greater than 0, and M is an integer greater than 0;
  • the first light-emitting element in the element group numbered 1 is electrically connected to the driving voltage terminal;
  • the first light-emitting element in the element group numbered k is electrically connected to the first light-emitting element in the element group numbered k+1 through the first connecting line; wherein, 1 ⁇ k ⁇ M and k is an integer ;
  • the last first light-emitting element in the element group numbered M is electrically connected to the output terminal;
  • a column of light-emitting units corresponds to one common voltage line, and the common voltage line is located between the element group numbered k and the element group numbered k+1 in the corresponding column of light-emitting units.
  • the second conductive layer further includes a plurality of series wirings arranged at intervals; the light-emitting elements in the same element group are electrically connected in series through the series wiring, and the element group numbered k-1 The last light-emitting element is electrically connected to the last light-emitting element in the element group numbered k through the series wiring;
  • the orthographic projection of the common voltage line on the substrate does not overlap with the orthographic projection of the series wiring on the substrate.
  • the light-emitting substrate further includes a fan-out region
  • the first conductive layer also includes a plurality of first fan-out lines and a plurality of second connection lines located in the fan-out area; wherein, one of the common voltage lines is electrically connected to one of the first fan-out lines; the The first fan-out line includes a first sub-fan-out line and a second sub-fan-out line; the first sub-fan-out line extends along the first direction, and the second sub-fan-out line extends along the second direction;
  • the second conductive layer further includes a plurality of second bridging portions located in the fan-out area;
  • the first fan-out sub-line includes a plurality of first fan-out line segments arranged at intervals; in the same first fan-out sub-line, two adjacent first fan-out line segments are electrically connected through the second bridge and adjacent to each other. At least one second connection line is provided in a gap between two first fan-out line segments;
  • the orthographic projection of the second bridging portion on the base substrate and the second connection line on the base substrate Orthographic projection overlay At the gap between two adjacent first fan-out line segments in the first sub-fan-out line, the orthographic projection of the second bridging portion on the base substrate and the second connection line on the base substrate Orthographic projection overlay.
  • the first conductive layer further includes a plurality of third connection lines
  • the second conductive layer further includes a plurality of third bridges located in the fan-out region;
  • the second fan-out sub-line includes a plurality of second fan-out line segments arranged at intervals; in the same second fan-out sub-line, two adjacent second fan-out line segments are electrically connected through the third bridge and are adjacent to each other. At least one third connection line is provided in a gap between two second fan-out line segments;
  • the orthographic projection of the third bridging portion on the base substrate and the third connecting line on the base substrate Orthographic projection overlay At the gap between two adjacent second fan-out line segments in the second sub-fan-out line, the orthographic projection of the third bridging portion on the base substrate and the third connecting line on the base substrate Orthographic projection overlay.
  • the fan-out area includes a plurality of light emitting units, and the light emitting unit includes a driving circuit and a plurality of light emitting elements; wherein, the driving circuit includes a common voltage terminal and an output end; the plurality of light emitting elements are sequentially connected in series between the drive voltage terminal and the output terminal;
  • the common voltage terminal is electrically connected to the first fan-out line
  • At least two of the light-emitting elements are electrically connected through the second connection line; and/or, at least two of the light-emitting elements are electrically connected through the third connection line.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned light-emitting substrate.
  • Figure 1a is a schematic structural view of a light-emitting substrate in the related art
  • FIG. 1b is a schematic diagram of a partial layout of a light-emitting substrate in the related art
  • FIG. 2 is a schematic structural view of a light-emitting substrate in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a partial specific structure of a light-emitting substrate in an embodiment of the present disclosure
  • FIG. 4 is a waveform diagram of a second input signal in a driving circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a signal timing diagram of a driving circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a partial layout of a light-emitting substrate in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of an enlarged layout of the FB area in FIG. 6;
  • Fig. 8 a is a schematic cross-sectional structure diagram along AA' direction in Fig. 7;
  • Fig. 8 b is a schematic cross-sectional structure diagram along the BB' direction in Fig. 7;
  • FIG. 9 is a schematic diagram of a partial layout of a fan-out area in an embodiment of the present disclosure.
  • a first conductive layer 02 , an insulating layer 03 and a second conductive layer 04 are sequentially disposed on the substrate 01 .
  • the first conductive layer 02 has a driving voltage line 220 and a common voltage line 210 .
  • the second conductive layer 04 has metal connection lines. Taking the light emitting unit having 9 light emitting elements as an example, the 9 light emitting elements are electrically connected in series through metal connecting wires. Divide the metal connecting wires between these 9 light-emitting elements into 8 sections: A section, B section, C section, D section, E section, F section, and G section.
  • the voltage transmitted by the driving voltage line 220 is 27V
  • the voltage transmitted by the common voltage line 210 is 0V
  • the voltage transmitted by the metal connection line of section A is 24V
  • the voltage transmitted by the metal connection line of section B is 21V
  • the voltage transmitted by the metal connection line of section C is 24V.
  • the voltage transmitted by the connecting wire is 18V
  • the voltage transmitted by the metal connecting wire of D section is 15V
  • the voltage transmitted by the metal connecting wire of E section is 12V
  • the voltage transmitted by the metal connecting wire of F section is 9V
  • the metal connecting wire of G section The transmitted voltage is 6V
  • the voltage transmitted by the metal connecting wire of the H section is 3V.
  • the metal connection lines of section C overlap between the orthographic projection of the base substrate and the orthographic projection of the driving voltage line 220 on the base substrate, and the metal connection lines of section F overlap with the common voltage line 210 in the orthographic projection of the base substrate. Overlap between orthographic projections of the substrate substrate.
  • the direction of the electric field between the overlaps of the metal connection wires of section F and the common voltage line 210 is directed from the second conductive layer to the first conductive layer. Since the second conductive layer is easily exposed and easily attracts water and oxygen, and the material of the first conductive layer 02 and the second conductive layer 04 is generally low-resistance Cu material. Since the Cu material is relatively active, it is easy to cause metal corrosion under the action of an electric field. There is a potential difference between the metal connection line of section F and the common voltage line 210, forming an electrochemical corrosion anode and a protective cathode.
  • the metal connection line of section F is the positive electrode for oxidation reaction
  • the common voltage line 210 is the cathode for reduction reaction.
  • the continuous progress of electrochemical corrosion eventually leads to a short circuit between the metal connecting wire of section F and the common voltage wire 210.
  • it will affect the light-emitting stability of the light-emitting substrate.
  • At least one embodiment of the present disclosure provides a light-emitting substrate and a display device, which can reduce the influence of electrochemical corrosion on the light-emitting substrate and improve light-emitting stability.
  • the light-emitting substrate provided by at least one embodiment of the present disclosure may include a base substrate 10 .
  • the base substrate 10 may include a display area and a fan-out area FO.
  • the material of the base substrate 10 may be selected from plastics, polyimide, silicon, ceramics, glass, quartz, etc., which is not limited in the embodiments of the present disclosure.
  • the display area may include a plurality of light emitting units PX arranged in an array.
  • a plurality of light emitting units PX are arranged in multiple rows and multiple columns.
  • the number of light-emitting units PX can be determined according to actual needs, for example, according to the size of the light-emitting substrate and the required brightness. Although only 6 rows and 5 columns of light-emitting units PX are shown in FIG. 2, it should be understood that , the number of light emitting units PX is not limited thereto.
  • the light emitting units PX may be arranged in multiple rows and multiple columns along the first direction F1 and the second direction F2 .
  • the light-emitting substrate is rectangular
  • the first direction F1 may be a direction parallel to the long side of the light-emitting substrate
  • the second direction F2 may be a direction parallel to the short side of the light-emitting substrate.
  • the first direction F1 may also be a direction parallel to the short side of the light emitting substrate
  • the second direction F2 may also be a direction parallel to the long side of the light emitting substrate.
  • first direction F1 and the second direction F2 may be any directions, as long as the first direction F1 and the second direction F2 intersect.
  • the plurality of light emitting units PX are not limited to being arranged in a straight line, and may also be arranged in a zigzag line, in a ring, or in any manner, which may be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • each light emitting unit PX may include a driving circuit QD0 and a plurality of light emitting elements QD1.
  • the driving circuit QD0 may include a first input terminal Di, a second input terminal Pwr, an output terminal OT and a common voltage terminal GND.
  • a plurality of light emitting elements QD1 in the light emitting unit PX are serially connected in series, and are electrically connected between the driving voltage terminal Vled and the output terminal OT of the driving circuit QD0 .
  • the plurality of light emitting elements QD1 in the light emitting unit PX can also be connected in parallel to be electrically connected between the driving voltage terminal Vled and the output terminal OT of the driving circuit QD0 .
  • the plurality of light emitting elements QD1 in the light emitting unit PX may also be connected in parallel and then connected in series, so as to be electrically connected between the driving voltage terminal Vled and the output terminal OT of the driving circuit QD0.
  • the design may be determined according to actual requirements, which is not limited here.
  • the driving circuit QD0 may be configured to pass through the output terminal OT within the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr.
  • a relay signal is output, and a current path is formed through the output terminal OT and the light-emitting element QD1 connected in series during the second period.
  • the first input terminal Di receives a first input signal, such as an address signal, for gating the driving circuit QD0 corresponding to the address.
  • the addresses of different driving circuits QD0 may be the same or different.
  • the first input signal may be an 8-bit address signal, and the address to be transmitted can be obtained by analyzing the address signal.
  • the second input terminal Pwr receives a second input signal, such as a power line carrier communication signal.
  • the second input signal not only provides electric energy for the driving circuit QD0, but also transmits communication data to the driving circuit QD0.
  • the communication data can be used to control the light-emitting duration of the corresponding light-emitting unit PX, and then control its visual light-emitting brightness.
  • the output terminal OT can output different signals in different time periods, such as outputting a relay signal and a driving signal respectively.
  • the relay signal is an address signal provided to the other driving circuit QD0, that is, the first input terminal Di of the other driving circuit QD0 receives the relay signal as the first input signal, so as to obtain the address signal.
  • the driving signal can be a driving current for driving the light emitting element QD1 to emit light.
  • the common voltage terminal GND receives a common voltage signal, such as a ground signal.
  • the drive circuit QD0 is configured to output a relay signal through the output terminal OT during the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr, and to output a relay signal during the second period
  • a driving signal is provided to a plurality of light-emitting elements QD1 connected in series through the output terminal OT.
  • the output terminal OT outputs a relay signal
  • the relay signal is provided to other driving circuits QD0 so that other driving circuits QD0 obtain address signals.
  • the output terminal OT outputs a driving signal, which is provided to a plurality of light-emitting elements QD1 connected in series, so that the light-emitting element QD1 emits light during the second period.
  • the first time period and the second time period are different time periods, for example, the first time period may be earlier than the second time period.
  • the first time period can be continuous with the second time period, and the end time of the first time period is the start time of the second time period; or, there can be other time periods between the first time period and the second time period, which can be used to realize For other required functions, the other time period can also be used only to separate the first time period from the second time period, so as to prevent the signals of the output terminal OT from interfering with each other during the first time period and the second time period.
  • the driving signal when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light emitting element QD1, or flow from the light emitting element QD1 to the output terminal OT, and the flow direction of the driving current can be determined according to actual needs.
  • the output terminal OT outputs a driving signal means that the output terminal OT provides a driving signal, and the direction of the driving signal can either flow out of the output terminal OT or flow into the output terminal OT.
  • Mini Light Emitting Diode or Micro Light Emitting Diode (Micro Light Emitting Diode, Micro-LED) are small in size and high in brightness, and can be widely used in display devices or their backlight modules. Perform fine adjustments to realize the display of high dynamic range images (High-Dynamic Range, HDR).
  • the typical size (such as length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (such as length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns.
  • the light emitting element QD1 may be a micro light emitting diode (Micro-LED) or a miniature light emitting diode (Mini-LED).
  • each light-emitting element QD1 includes a positive pole (+) and a negative pole (-) (or, also called an anode and a cathode), and the positive poles and negative poles of a plurality of light-emitting elements QD1 are connected in series end-to-end in sequence, so that the driving voltage terminals Vled and A current flow path is formed between the output terminals OT.
  • the driving voltage terminal Vled can provide a driving voltage, for example, a high voltage during a period (second period) when the light emitting element QD1 needs to emit light, and a low voltage during other periods.
  • the driving signal (such as driving current) flows from the driving voltage terminal Vled through the plurality of light emitting elements QD1 sequentially, and then flows into the output terminal OT of the driving circuit QD0.
  • a plurality of light-emitting elements QD1 emit light when the driving current flows, and by controlling the duration of the driving current, the light-emitting duration of the light-emitting elements QD1 can be controlled, thereby controlling the visual brightness of light.
  • the light emitting unit PX may include nine light emitting elements QD1 arranged in three rows and three columns.
  • the nine light-emitting elements QD1 when the nine light-emitting elements QD1 are connected in series, the light-emitting element QD1 electrically connected to the driving voltage terminal Vled is used as the starting point of the series connection of the nine light-emitting elements QD1, and the light-emitting element electrically connected to the output terminal OT of the drive circuit QD0 QD1 serves as the end point of the series connection of the nine light emitting elements QD1.
  • the driving voltage terminal Vled can be electrically connected to the anode of the light emitting element QD1
  • the output terminal OT of the driving circuit QD0 can be electrically connected to the negative electrode of the light emitting element QD1.
  • the number of light emitting elements QD1 in each light emitting unit PX is not limited, and can be any number such as 6, 8, 12, etc., and is not limited to 9.
  • the plurality of light emitting elements QD1 can be arranged in any arrangement, such as arranged in a required pattern, not limited to a matrix arrangement.
  • the setting position of the driving circuit QD0 is not limited, and can be set in any gap between the light-emitting elements QD1 , which can be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • the relative positions of the driving circuit QD0 in the light emitting unit PX may be different, or the positions of the driving circuit QD0 in the light emitting unit PX may also be the same.
  • the relative positional relationship of the light emitting elements QD1 in each light emitting unit PX can be made the same.
  • the relative positional relationship of the light emitting elements QD1 in one light emitting unit PX may be used as a reference, and the light emitting elements QD1 may be periodically and repeatedly arranged along the first direction F1 and the second direction F2.
  • the light emitting elements QD1 located at the same position in each light emitting unit PX may be arranged substantially on the same straight line along the first direction F1.
  • the light emitting elements QD1 located at the same position in each light emitting unit PX may be arranged substantially on the same straight line along the second direction F2.
  • the driving circuit QD0 may include a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a driving signal generating circuit, a relay signal generating circuit and a power supply circuit.
  • the demodulation circuit is electrically connected to the second input terminal Pwr and the physical layer interface circuit, configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit.
  • the second input signal input to the second input terminal Pwr is a power line carrier communication signal
  • the power line carrier communication signal includes information corresponding to communication data.
  • the communication data is the data reflecting the duration of light emission, and further represents the required light emission brightness.
  • SPI Serial Peripheral Interface
  • the embodiment of the present disclosure adopts the power line carrier communication (Power Line Carrier Communication, PLC) protocol to superimpose the communication data on the power signal, thereby effectively reducing the The number of signal lines.
  • PLC Power Line Carrier Communication
  • the dotted ellipse represents an enlarged view of the corresponding waveform.
  • the second input signal is at a high level, its high level amplitude fluctuates around the threshold amplitude Vth, for example, the first amplitude V1 and The second amplitude V2 varies, V2 ⁇ Vth ⁇ V1.
  • Vth threshold amplitude
  • the communication data can be modulated into the second input signal, so that the second input signal transmits information corresponding to the communication data while transmitting electric energy.
  • the demodulation circuit filters out the DC power component of the second input signal, so that the communication data can be obtained.
  • the second input signal For the detailed description of the second input signal, reference may be made to the conventional power line carrier communication signal, which will not be described in detail here.
  • the detailed description of the demodulation circuit can also refer to the conventional power line carrier communication signal demodulation circuit, which will not be described in detail here.
  • the physical layer interface circuit is also electrically connected to the data processing control circuit, configured to process the communication data to obtain a data frame (for example, frame rate data), and transmit the data frame to the data processing control circuit.
  • the data frame obtained by the physical layer interface circuit contains information that needs to be transmitted to the driving circuit QD0 , such as information related to the lighting time (eg, the specific duration of the lighting time).
  • the physical layer interface circuit may be a common port physical layer (Physical, PHY).
  • PHY Physical, PHY
  • the data processing control circuit is also electrically connected to the first input terminal Di, the pulse width modulation circuit and the relay signal generating circuit.
  • the data processing control circuit is configured to generate a pulse width control signal based on the data frame and transmit the pulse width control signal to the pulse width modulation circuit, and generate a relay control signal based on the first input signal and transmit the relay control signal to the Following the signal generation circuit.
  • the required light-emitting duration of the light-emitting element QD1 connected to the driving circuit QD0 can be known, so a corresponding pulse width control signal is generated based on the light-emitting duration.
  • the relay control signal is a signal generated after the data processing control circuit processes the first input signal.
  • the address signal corresponding to the driving circuit QD0 can be obtained, and a relay control signal corresponding to the subsequent address will be generated.
  • the subsequent address corresponds to Other drive circuit QD0.
  • the data processing control circuit can be implemented as a single chip microcomputer, a central processing unit (Central Processing Unit, CPU), a digital signal processor, and the like.
  • the pulse width modulation circuit is also electrically connected to the driving signal generating circuit, configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the driving signal generating circuit.
  • the pulse width modulation signal generated by the pulse width modulation circuit corresponds to the required light-emitting duration of the light-emitting element QD1 , for example, the effective pulse-width duration is equal to the required light-emitting duration of the light-emitting element QD1 .
  • the detailed description of the pulse width modulation circuit can refer to the conventional pulse width modulation circuit, which will not be described in detail here.
  • the driving signal generating circuit is further electrically connected to the output terminal OT, configured to generate a driving signal in response to the pulse width modulation signal, and output the driving signal from the output terminal OT.
  • outputting the driving signal from the output terminal OT may mean that the driving signal (such as the driving current) flows from the output terminal OT to the light-emitting element QD1, or it may mean that the driving signal (such as the driving current) flows from the light-emitting element QD1 to the output terminal OT.
  • the direction of current flow is not restricted.
  • the driving signal generating circuit may include a current source and a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor (Field Effect Transistor, FET), the Metal-oxide-semiconductor field-effect transistors are called MOS transistors.
  • MOS Metal Oxide Semiconductor
  • FET Field Effect Transistor
  • the control electrode of the MOS transistor receives the pulse width modulation signal transmitted by the pulse width modulation circuit, and thus is turned on or off under the control of the pulse width modulation signal.
  • the first pole of the MOS transistor is connected to the output terminal OT, the second pole of the MOS transistor is connected to the first pole of the current source, and the second pole of the current source is connected to the common voltage terminal GND to receive the common voltage.
  • the current source can be a constant current source.
  • the MOS transistor When the pulse width modulation signal is at an active level, the MOS transistor is turned on, and the current source provides a driving current through the output terminal OT. When the pulse width modulation signal is at an inactive level, the MOS transistor is turned off, and the output terminal OT does not provide a driving current at this time.
  • the duration of the active level of the pulse width modulation signal is equal to the conduction duration of the MOS transistor, and the conduction duration of the MOS transistor is equal to the duration of the drive current provided by the output terminal OT. In this way, the light-emitting duration of the light-emitting element QD1 can be further controlled, and further the visual light-emitting brightness can be controlled.
  • the driving current flows into the driving circuit QD0 from the OT terminal, flows through the MOS transistor and the current source in turn, and then flows into the ground terminal (such as the common voltage terminal GND).
  • the driving signal generating circuit may also adopt other circuit structures, which are not limited in the embodiments of the present disclosure.
  • the relay signal generating circuit is further electrically connected to the output terminal OT, configured to generate a relay signal based on the relay control signal, and output the relay signal from the output terminal OT.
  • the relay control signal corresponds to a subsequent address
  • the relay signal generated based on the relay control signal includes the subsequent address
  • the subsequent address corresponds to the other driving circuit QD0.
  • the relay signal is output from the output terminal OT, it is provided to the first input terminal Di of the driving circuit QD0 provided separately, and the relay signal is input to the driving circuit QD0 provided separately as the first input signal, so that the driving circuit QD0 provided separately
  • the driving circuit QD0 obtains the corresponding address signal.
  • the relay signal generating circuit may be implemented by a latch, a decoder, an encoder, etc., which is not limited in the embodiments of the present disclosure.
  • both the driving signal generating circuit and the relay signal generating circuit are electrically connected to the output terminal OT, the driving signal generating circuit and the relay signal generating circuit respectively output driving The signal and relay signal, drive signal and relay signal are time-divisionally transmitted through the output terminal OT, so they will not affect each other.
  • the power supply circuit is electrically connected to the demodulation circuit and the data processing control circuit respectively, and is configured to receive electric energy and supply power to the data processing control circuit.
  • the second input signal is a power line carrier communication signal.
  • the DC power component that is, electric energy
  • the power supply circuit may also be electrically connected with other circuits in the driving circuit QD0 to provide electric energy.
  • the power supply circuit may be realized by a switch circuit, a voltage conversion circuit, a voltage stabilization circuit, etc., which are not limited in the embodiments of the present disclosure.
  • the drive circuit QD0 may also include more circuits and components, not limited to the above-mentioned demodulation circuit, physical layer interface circuit, data processing control circuit, pulse width modulation circuit, drive signal
  • the generation circuit, the relay signal generation circuit and the power supply circuit may be determined according to the functions to be realized, which are not limited in the embodiments of the present disclosure.
  • the driving circuit QD0 when the driving circuit QD0 is working, it is first powered on (that is, powered on) to complete the initialization, and then the address writing operation is performed in the period S1, that is, in the period S1, the first input signal Di_1 passes through the first input terminal Di is input to the driving circuit QD0, thereby writing an address.
  • the first input signal Di_1 is transmitted through an additionally provided transmitter.
  • the relay signal Di_2 is output through the output terminal OT.
  • the relay signal Di_2 is input as the first input signal to the first input terminal Di of the driving circuit QD0 provided separately.
  • the aforementioned first time period is the time period S2.
  • the driving voltage terminal Vled is energized.
  • the period S3 is entered after about 10 microseconds. At this moment, the driving voltage provided by the driving voltage terminal Vled becomes high level.
  • the driving circuit QD0 is in the normal working mode, and the output terminal OT provides a driving signal (such as a driving current) according to the required duration, so that the light emitting element QD1 connected to the driving circuit QD0 emits light according to the required duration.
  • the aforementioned second time period is the time period S4.
  • the light-emitting substrate using the driving circuit QD0 works in a local backlight adjustment (Local Dimming) mode, which can achieve a high dynamic range effect.
  • the system is shut down, that is, the driving circuit QD0 is powered off, and the driving voltage provided by the driving voltage terminal Vled becomes low level, and the light emitting element QD1 stops emitting light.
  • VREG, POR, Vreg_1.8, OSC, and Re_B are all internal signals of the driving circuit QD0, and will not be input or input through the first input terminal Di, the second input terminal Pwr, the output terminal OT, and the common voltage terminal GND. output.
  • Di_1 is the first input signal received by the driving circuit QD0
  • Di_2 is the relay signal output by the driving circuit QD0 (that is, the first input signal received by the next connected driving circuit QD0)
  • Di_n is a plurality of sequentially connected The first input signal received by the nth driving circuit QD0 in the driving circuits QD0.
  • the drive circuit QD0 can be configured as a chip, the chip size (for example, length) can be tens of microns, and the chip area is about several hundred square microns or even smaller, which is similar to the size of Mini-LED and has
  • the feature of miniaturization makes it easy to integrate into the light-emitting substrate (for example, bonded to the surface of the light-emitting substrate), saves the installation space of the printed circuit board, simplifies the structure, and is conducive to realizing light and thin.
  • Each driving circuit QD0 directly drives a light-emitting unit PX, which avoids problems such as complicated operation and easy flickering of the row scanning control mode.
  • the driving circuit QD0 has a small number of ports, a small number of required signals, a simple control method, a simple wiring method, and low cost.
  • a buffer layer (Buffer) 400 is disposed on the base substrate 10 to improve the adhesion of the first conductive layer.
  • the first conductive layer is located on a side of the buffer layer 400 away from the base substrate 10 .
  • the first conductive layer may include: a plurality of common voltage lines 210 , a plurality of driving voltage lines 220 , a plurality of source voltage lines 230 and a plurality of first connection lines 110 arranged at intervals.
  • one column of light emitting units PX may correspond to one common voltage line 210 , one source voltage line 230 and one driving voltage line 220 .
  • the orthographic projection of the common voltage line 210 on the base substrate 10 is located between the driving voltage line 220 and the source voltage line 230 between.
  • the plurality of driving voltage lines 220 extend along the first direction F1 and are arranged along the second direction F2.
  • a column of light emitting units PX may be corresponding to one driving voltage line 220 , so that the driving voltage terminal Vled of the column of light emitting units PX is electrically connected to the corresponding driving voltage line 220 .
  • the nine light emitting elements QD1 are connected in series
  • the light emitting element QD1 electrically connected to the driving voltage line 220 is used as the starting point for the nine light emitting elements QD1 to be connected in series.
  • the plurality of source voltage lines 230 extend along the first direction F1 and are arranged along the second direction F2.
  • the source voltage line 230 may be electrically connected to the second input terminal Pwr of the driving circuit QD0. In this way, the second input signal can be transmitted to the second input terminal Pwr of the driving circuit QD0 through the source voltage line 230 .
  • the plurality of common voltage lines 210 extend along the first direction F1 and are arranged along the second direction F2.
  • the common voltage terminal can be electrically connected to the common voltage line 210 to provide a voltage to the common voltage terminal of the driving circuit QD0 through the common voltage line 210 .
  • the wiring space can be reasonably designed and signal interference can be reduced.
  • one column of light emitting units PX corresponds to one common voltage line 210 and one driving voltage line 220 . That is, the common voltage terminals GND of the driving circuits QD0 in a column of light emitting units PX are all electrically connected to the same common voltage line 210 , and the driving voltage terminals Vled in a column of light emitting units PX are all electrically connected to the same driving voltage line 220 .
  • the common voltage line 210 is located on the driving voltage line 220 and source voltage line 230.
  • the width of the common voltage line 210 in the second direction F2 is larger than the width of the driving voltage line 220 in the second direction F2.
  • the width of the driving voltage line 220 in the second direction F2 is larger than the width of the source voltage line 230 in the second direction F2.
  • the width of the source voltage line 230 in the second direction F2 is greater than the width of the cascaded wiring 240 in the second direction F2.
  • the first conductive layer may use a metal material to form a single-layer structure.
  • the first conductive layer may also use metal materials to form a laminated structure.
  • two first conductive layers formed of metal materials are used, for example, the first conductive layer has a C-1 layer and a C-2 layer.
  • the metal material may include but not limited to Cu.
  • the first insulating layer 310 is formed on the first conductive layer, that is, the first insulating layer 310 is located on a side of the first conductive layer away from the base substrate 10 . Moreover, the first insulating layer 310 is provided with a first via hole GK1 , a second via hole GK2 , a third via hole GK3 , and a fourth via hole GK4 .
  • the first insulating layer 310 may form a single layer structure using inorganic, organic or organic-inorganic composite materials. Alternatively, the first insulating layer 310 may also be a multi-layer structure formed by using at least one of inorganic, organic or organic-inorganic composite materials.
  • the first insulating layer 310 may be formed using multiple layers of organic materials.
  • the first insulating layer 310 may also be formed using multiple layers of inorganic materials.
  • the first insulating layer 310 may also be formed by stacking organic materials and inorganic materials.
  • the first insulating layer 310 may include an insulating layer 311 and an insulating layer 312 .
  • the material of the insulating layer 312 may be an organic material
  • the material of the insulating layer 311 may be an inorganic material.
  • the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like.
  • the organic material may be polyimide (PI) or the like.
  • a second conductive layer is formed on the first insulating layer 310 , that is, the second conductive layer is located on the side of the first insulating layer 310 away from the base substrate 10 side.
  • the second conductive layer may include: a plurality of pads (such as PD1, PD2, PD3, PD4), and a plurality of cascaded wires 240 arranged at intervals.
  • the multiple cascaded wires 240 extend along the first direction F1.
  • the driving circuits QD0 in the light emitting units PX in a column may be coupled to each other, and in a column, the driving circuits QD0 in adjacent light emitting units PX are coupled through the cascaded wiring 240 .
  • the first row to the sixth row are defined.
  • first to fifth columns are defined. Taking the first column as an example, the output terminal of the driving circuit QD0 in the first row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the second row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the second row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the third row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the third row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the fourth row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the fourth row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the fifth row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the fifth row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the sixth row of light emitting units PX through a cascaded wire 240 .
  • the output end of the driving circuit QD0 in the sixth row of light emitting units PX is coupled to the cascade output terminal through a cascade output wiring. In this way, the cascading wiring 240 and the driving circuit QD0 can be cascaded in the same direction, reducing signal overlapping area and signal interference.
  • the pad may be electrically connected to the driving circuit.
  • the pads are electrically connected with corresponding pins in the driving circuit for signal transmission.
  • the welding pad may also be electrically connected to the light emitting element.
  • each electrode of the light emitting element is electrically connected to a pad correspondingly.
  • the pad PD3 is electrically connected to the positive electrode of the light emitting element QD1
  • the pad PD1 is electrically connected to the negative electrode of the light emitting element QD1.
  • the pad PD2 is electrically connected to the positive electrode of the light emitting element QD1
  • the pad PD4 is electrically connected to the negative electrode of the light emitting element QD1. The rest can be deduced in the same way, and will not be repeated here.
  • the second insulating layer 320 is formed on the second conductive layer, that is, the second insulating layer 320 is located on a side of the second conductive layer away from the substrate 10 .
  • the second insulating layer 320 may form a single layer structure using inorganic, organic or organic-inorganic composite materials.
  • the second insulating layer 320 may also be a multi-layer structure formed by using at least one of inorganic, organic or organic-inorganic composite materials.
  • the second insulating layer 320 may be formed using multiple layers of organic materials.
  • the second insulating layer 320 may also be formed using multiple layers of inorganic materials.
  • the second insulating layer 320 may also be formed by stacking organic materials and inorganic materials.
  • the second insulating layer 320 may include an insulating layer 321 and an insulating layer 322 .
  • the material of the insulating layer 322 may be an organic material
  • the material of the insulating layer 321 may be an inorganic material.
  • the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like.
  • the organic material may be polyimide (PI) or the like.
  • At least one of the plurality of common voltage lines 210 may include a plurality of signal line segments arranged at intervals.
  • each common voltage line 210 may include a plurality of signal line segments arranged at intervals.
  • the common voltage line 210 may include signal line segments 211-1, 211-2.
  • the second conductive layer further includes a plurality of first bridge portions QB1 arranged at intervals from each other.
  • first bridge portions QB1 arranged at intervals from each other.
  • two adjacent signal line segments can be electrically connected through the first bridge portion QB1, so that the signal line segments can be electrically connected through the first bridge portion QB1 to transmit signals.
  • the signal line segments 211-1 and 211-2 may be electrically connected through the first bridge part QB1.
  • the signal line segment 211-2 is electrically connected to the first bridge portion QB1 through the third via hole GK3, and the signal line segment 211-1 is electrically connected to the first bridge portion QB1 through the fourth via hole GK4.
  • two adjacent signal line segments may be electrically connected through one, two, three or more first bridge portions QB1.
  • the number of the first bridge parts QB1 connected between two adjacent signal line segments can be designed and determined according to the actual environment, and is not limited here.
  • At least one first connection line 110 is disposed at a line segment gap between two adjacent signal line segments.
  • a first connection line 110 may be provided at a line segment gap between two adjacent signal line segments.
  • a first connection line 110 may be provided at a line segment gap between the signal line segments 211-1 and 211-2.
  • two, three or more first connection lines 110 may also be provided at the line segment gap between two adjacent signal line segments, which can be designed and determined according to the actual environment. This is not limited.
  • connection line 110 Orthographic projections of a connection line 110 on the base substrate 10 overlap.
  • the first bridging portion QB1 and the first connection line 110 can have an overlapping area in a direction perpendicular to the plane of the base substrate 10 , which can reduce the extra space occupied by the first connection line 110 .
  • the voltage transmitted on the first bridge portion QB1 can be made smaller than the voltage transmitted on the first connection line 110 .
  • the voltage of the common voltage line 210 may be a ground voltage
  • the first bridge portion QB1 may be a ground voltage, such as 0V.
  • the voltage of the first connection line 110 may be a positive value, for example, 9V.
  • the voltage of the common voltage line 210 and the voltage of the first connection line 110 can be designed and determined according to the actual application environment, and no limitation is made here.
  • the overlapping first bridge portion and the second bridge portion in the orthographic projection of the base substrate 10 There is an electric field between the connecting lines, and the direction F02 of the electric field is from the first conductive layer to the second conductive layer. Therefore, it is possible to avoid the reduction reaction of the first connection line 110 as the cathode, and also avoid the oxidation reaction of the first bridge portion QB1 as the anode. Moreover, the first bridge portion QB1 is protected by the second insulating layer 320 , and the intrusion path of water and oxygen is relatively far. Therefore, the situation of electrochemical corrosion can be effectively reduced. Especially for the metal connecting wire of section F shown in FIG. 1 b , the situation of electrochemical corrosion can be effectively reduced.
  • the thickness and number of layers of the first insulating layer 310 can be increased.
  • the voltage applied to the first connecting line 110 is greater than the voltage applied to the first bridge portion QB1
  • the electric field direction of the electric field generated between the first connecting line 110 and the first bridge portion QB1 is determined by the first bridge portion QB1.
  • a connection line 110 points to the direction F02 of the first bridging portion QB1, which can effectively reduce the situation of electrochemical corrosion. Therefore, there is no need to additionally increase the thickness and number of layers of the insulating layer, which can save production capacity.
  • the first connection line 110 may extend along the second direction F2.
  • the second conductive layer may further include a first connection part BL1 and a second connection part BL2 arranged at intervals; wherein, the first end of the first connection line 110 is electrically connected to the first connection part BL1 through the first via hole GK1, and the second A second end of a connection line 110 is electrically connected to the second connection portion BL2 through the second via hole GK2 .
  • the first via hole GK1 and the second via hole GK2 penetrate through the first insulating layer 310 .
  • the orthographic projection of the first connecting portion BL1 on the base substrate 10 is located within the orthographic projection of the line segment gap on the base substrate 10, and the orthographic projection of the first connecting portion BL1 on the base substrate 10 is located within the line segment gap on the substrate
  • the first end of the orthographic projection of the substrate 10 and the orthographic projection of the first connecting portion BL1 on the base substrate 10 do not overlap with the orthographic projection of the first bridging portion QB1 on the base substrate 10 .
  • the orthographic projection of the second connecting portion BL2 on the base substrate 10 is located within the orthographic projection of the line segment gap on the base substrate 10, and the orthographic projection of the second connecting portion BL2 on the base substrate 10 is located within the orthographic projection of the line segment gap on the base substrate 10.
  • the second end of the projection, and the orthographic projection of the second connecting portion BL2 on the base substrate 10 do not overlap with the orthographic projection of the first bridging portion QB1 on the base substrate 10 .
  • the first connecting portion BL1 is also electrically connected to one of the plurality of pads (such as PD1), and the second connecting portion BL2 is also electrically connected to Another pad (for example, PD2 ) among the plurality of pads is electrically connected. That is, one end of the first connection portion BL1 is electrically connected to one pad (for example, PD1 ), and the other end is electrically connected to the first end of the first connection line. The other end of the second connection portion BL2 is electrically connected to another pad (for example, PD2 ), and the other end is electrically connected to the second end of the first connection line.
  • the light emitting element QD1 can be connected in series with another light emitting element QD1 through the bonding pad PD1, the first connecting portion BL1, the first connecting line 110, the second connecting portion BL2 and the bonding pad PD2.
  • the orthographic projection of the first connection line 110 on the base substrate 10 covers the orthographic projection of the first via hole GK1 on the base substrate 10
  • the first The orthographic projection of the connecting portion BL1 on the base substrate 10 covers the orthographic projection of the first via hole GK1 on the base substrate 10 . That is to say, the size of the first via hole GK1 cannot exceed the size of the first connecting line 110 where the overlapping area is located, and the size of the first via hole GK1 cannot exceed the size of the first connecting portion BL1 where the overlapping area is located. In this way, the first connection line 110 can be in contact with the first connection part BL1 through the first via hole GK1 as much as possible, so as to improve the reliability of the electrical connection.
  • the width W11 in the first direction F1 of the area where the first connecting part BL1 covers the first via hole GK1 can be larger than that of the first connecting line 110 in the first direction F1.
  • the area where the first connecting part BL1 covers the first via hole GK1 is not only larger than the area where the first via hole GK1 is located, but also larger than the area where the first connecting line 110 covers the first via hole GK1, so that the first via hole GK1 can be made larger.
  • a connection part BL1 is in contact with the first connection line through the first via hole as much as possible, so as to improve the reliability of the electrical connection.
  • the width W30 of the first bridging portion QB1 in the first direction F1 may range from 100 microns to 250 microns.
  • the width W30 of the first bridging portion QB1 in the first direction F1 may be 100 micrometers.
  • the width W30 of the first bridging portion QB1 in the first direction F1 may also be 150 microns.
  • the width W30 of the first bridging portion QB1 in the first direction F1 may also be 200 microns.
  • the width W30 of the first bridging portion QB1 in the first direction F1 may also be 250 microns.
  • the specific value of the width W30 of the first bridging portion QB1 in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.
  • the width W0 of the first connection line 110 in the first direction F1 may range from 0.6 microns to 2.5 microns.
  • the width W0 of the first connection line 110 in the first direction F1 may be 0.6 microns.
  • the width W0 of the first connection line 110 in the first direction F1 may also be 0.8 microns.
  • the width W0 of the first connection line 110 in the first direction F1 may also be 1.0 ⁇ m.
  • the width W0 of the first connection line 110 in the first direction F1 may also be 1.6 microns.
  • the width W0 of the first connection line 110 in the first direction F1 may also be 2.0 microns.
  • the width W0 of the first connection line 110 in the first direction F1 may also be 2.5 microns.
  • the specific value of the width W0 of the first connection line 110 in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may range from 20 microns to 50 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may be 20 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may also be 25 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may also be 30 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may also be 35 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may also be 40 microns.
  • the width W40 of the gap between the first connection line 110 and the signal line segment in the first direction F1 may also be 50 microns.
  • the specific value of the width of the gap between the first connection line 110 and the signal line segment in the first direction F1 can be designed and determined according to the actual application environment, and is not limited here.
  • the orthographic projection of the connecting portion BL2 on the base substrate 10 covers the orthographic projection of the second via hole GK2 on the base substrate 10 . That is to say, the size of the second via hole GK2 cannot exceed the size of the first connecting line 110 where the overlapping area is located, and the size of the second via hole GK2 cannot exceed the size of the second connecting portion BL2 where the overlapping area is located. In this way, the first connection line 110 can be in contact with the second connection part BL2 through the second via hole GK2 as much as possible, so as to improve the reliability of the electrical connection.
  • the width W21 in the first direction F1 of the area where the second connection portion BL2 covers the second via hole GK2 is larger than that of the first connection line 110 in the first direction. Width in direction F1.
  • the area where the second connecting portion BL2 covers the second via hole GK2 is not only larger than the area where the second via hole GK2 is located, but also larger than the area where the first connecting line 110 covers the second via hole GK2, so that the second via hole GK2 can be covered.
  • the second connection part BL2 is in contact with the first connection line through the second via hole as much as possible, so as to improve the reliability of the electrical connection.
  • the length of the first connection line 110 in the second direction F2 may be greater than the length of the first bridging portion QB1 in the second direction F2.
  • the first via hole GK1 and the second via hole GK2 can be located on both sides of the first bridge portion QB1, and the first via hole GK1 and the second via hole GK2 do not overlap with the first bridge portion QB1, reducing the first The possibility that the bridging portion QB1 is short-circuited with the first connection line 110 through the first via hole GK1 and the second via hole GK2 .
  • the first bridging portion QB1 is a planar structure, and there is a gap between the side of the first bridging portion QB1 extending to the first connecting portion BL1 and the first connecting portion BL1.
  • the width X1 of the first gap may range from 20 microns to 50 microns. Exemplarily, the width X1 of the first gap may be 20 microns. The width X1 of the first gap may also be 30 microns. The width X1 of the first gap may also be 40 microns. The width X1 of the first gap may also be 50 microns.
  • the specific value of the width X1 of the first gap can be designed and determined according to the actual application environment, and is not limited here.
  • the first bridging portion QB1 is a planar structure, and there is a gap between the side of the first bridging portion QB1 extending to the second connecting portion BL2 and the second connecting portion BL2.
  • second gap The width X2 of the second gap may range from 20 microns to 50 microns. Exemplarily, the width X2 of the second gap may be 20 microns. The width X2 of the second gap may also be 30 microns. The width X2 of the second gap may also be 40 microns. The width X2 of the second gap may also be 50 microns. Of course, in practical applications, the specific value of the width X2 of the second gap can be designed and determined according to the actual application environment, and is not limited here.
  • the width X1 of the first gap and the width X2 of the second gap may be approximately equal.
  • the thickness of the first bridging portion QB1 may be equal to the thickness of other structures in the second conductive layer.
  • the thickness of the first bridging part QB1 is equal to the thickness of the first connecting part and the second connecting part.
  • the thickness of the first bridging portion QB1 may be equal to the thickness of the first connecting portion BL1 and the thickness of the second connecting portion BL2 .
  • the entire surface of the base substrate 10 can be coated with a Cu film layer, and then the Cu film layer can be patterned through a patterning process, and the first bridge portion QB1 and the first connection can be formed at the same time.
  • the thickness of the first bridging portion QB1 may also be made greater than the thickness of other structures in the second conductive layer.
  • the resistance of the first bridge portion QB1 can be reduced.
  • the thickness of the first bridging portion QB1 is greater than the thicknesses of the first connecting portion and the second connecting portion.
  • a Cu film layer disposed on the entire surface can be coated on the base substrate 10, and then the Cu film layer can be patterned through a patterning process, and the first bridging portion QB1 can be formed at the same time.
  • a film layer, the first connection part BL1, the second connection part BL2, the cascade wiring 240 and other structures in the second conductive layer are patterned on the first film layer of the first bridge part QB1
  • One or more film layers are further arranged so that these film layers form the first bridging portion QB1.
  • At least two light emitting elements QD1 are electrically connected through the first connection line 110 .
  • one light emitting element QD1 is electrically connected to another light emitting element QD1 through the first connection part BL1.
  • the first connection part BL1 is electrically connected to the cathode of one light emitting element QD1
  • the first connection part BL1 is electrically connected to the first end of the first connection line 110 .
  • the second connection part BL2 is electrically connected to the anode of another light emitting element QD1
  • the second connection part BL2 is electrically connected to the second end of the first connection line 110 .
  • one light emitting element QD1 can be arranged in series with another light emitting element QD1 through the first connecting portion BL1.
  • the plurality of light emitting elements QD1 in the light emitting unit PX can be divided into M element groups, and each element group includes N light emitting elements arranged along the first direction F1 QD1: M element groups are arranged along the second direction F2.
  • N is an integer greater than
  • M is an integer greater than 0.
  • the element groups Z-1, Z-2 and Z-3 are arranged along the second direction F2.
  • the element group Z-1 has three light emitting elements QD1 arranged along the first direction F1
  • the element group Z-2 also has three light emitting elements QD1 arranged along the first direction F1
  • the element group Z-3 also has three light emitting elements QD1 arranged along the first direction F1.
  • At least two element groups are electrically connected through the first connection wire 110 .
  • a plurality of element groups are numbered sequentially in the order that the driving voltage end points to the output end; the first light-emitting element QD1 in the element group numbered 1 is electrically connected to the driving voltage end; the element group numbered k is The first light-emitting element QD1 is electrically connected to the first light-emitting element QD1 in the element group numbered k+1 through the first connection line 110; the last first light-emitting element QD1 in the element group numbered M is connected to the output terminal electrical connection; 1 ⁇ k ⁇ M and k is an integer.
  • the element group numbered 1 is Z-1
  • the element group numbered 2 is Z-2
  • the element group numbered 3 is Z-3
  • the terminals are electrically connected
  • the last light-emitting element QD1 in the element group numbered 1 is electrically connected to the last light-emitting element QD1 in the element group Z-2 numbered 2.
  • the first light-emitting element QD1 in the element group Z- 2 numbered 2 is electrically connected to the first light-emitting element QD1 in the element group Z- 3 numbered 3 through the first connection line 110 .
  • the first and last light-emitting element QD1 in the element group Z-3 numbered 3 is electrically connected to the output terminal.
  • the second conductive layer may further include a plurality of series wiring 250 arranged at intervals; the light emitting elements QD1 in the same element group are connected in series through the series wiring 250 electrical connection.
  • the light-emitting element QD1 is electrically connected to the pad, and the pad is electrically connected to the series wiring 250 , so that the light-emitting elements QD1 in the same element group are electrically connected through the pad and the series wiring 250 .
  • the last light-emitting element QD1 in the element group numbered k-1 and the last light-emitting element QD1 in the element group numbered k They are electrically connected through the first connection line 110 .
  • the first light-emitting element QD1 and the second light-emitting element QD1 are electrically connected in series through a series wiring 250, and the second light-emitting element QD1 and the third light-emitting element QD1 are electrically connected in series through a Traces 250 are electrically connected in series.
  • the first light-emitting element QD1 and the second light-emitting element QD1 are electrically connected in series through a series wiring 250, and the second light-emitting element QD1 and the third light-emitting element QD1 are electrically connected in series through a Traces 250 are electrically connected in series.
  • the first light-emitting element QD1 and the second light-emitting element QD1 are electrically connected in series through a series wiring 250, and the second light-emitting element QD1 and the third light-emitting element QD1 are electrically connected in series through a Traces 250 are electrically connected in series.
  • the last light-emitting element QD1 in the element group Z-1 numbered 1 is electrically connected to the last light-emitting element QD1 in the element group Z-2 numbered 2 through a series wiring 250 .
  • the orthographic projection of the common voltage line 210 on the base substrate 10 does not overlap with the orthographic projection of the series wiring 250 on the base substrate 10 . In this way, a positive electric field can be avoided between the common voltage line 210 and the series wiring 250 .
  • a row of light emitting units PX corresponding to: common voltage line 210, source voltage line 230 and driving voltage line 220, element group Z-1 numbered 1
  • a driving voltage line 220 is set between the element group Z-2 numbered 2
  • a common voltage line 210 is set between the element group Z-2 numbered 2 and the element group Z-3 numbered 3.
  • a source voltage line 230 is provided between the element group Z-3 of the element group Z-3 and the element group Z-1 numbered 1 in the adjacent light-emitting unit PX.
  • the orthographic projection of the pad on the base substrate and the orthographic projection of the common voltage line 210 on the base substrate do not overlap.
  • both sides of the common voltage line 210 respectively have avoidance areas, and pads located on both sides of the common voltage line 210 are located in the avoidance areas.
  • the pads electrically connected to the light-emitting element QD1 in the element group Z-2 numbered 2 are located in the avoidance area on the side of the common voltage line 210 facing the driving voltage line 220, and the pads in the element group Z-3 numbered 3
  • the pad to which the light emitting element QD1 is electrically connected is located in the avoidance area on the side of the common voltage line 210 away from the driving voltage line 220 .
  • the orthographic projection of the common voltage line 210 on the base substrate is electrically connected to the pad that is electrically connected to the light-emitting element QD1 in the element group Z-2 numbered 2 and the light-emitting element QD1 in the element group Z-3 numbered 3
  • the electrically connected pads do not overlap in the orthographic projection of the base substrate.
  • the fan-out area FO may also include a plurality of light emitting units PX to increase the light emitting area.
  • the common voltage terminal in the light-emitting unit PX is electrically connected to the first fan-out line, and the implementation of the light-emitting unit PX in the fan-out area FO can be basically the same as that of the light-emitting unit PX in the display area, that is, the fan-out
  • the specific implementation manner of the light emitting unit PX in the out-of-area FO reference may be made to the above-mentioned implementation manner of the light-emitting unit PX in the display area, and details are not repeated here.
  • the first conductive layer may further include a plurality of first fan-out lines and a plurality of second connection lines 112 arranged at intervals, a plurality of first fan-out lines and a plurality of The second connection line 112 is located in the fan-out area FO.
  • one common voltage line 210 is electrically connected to one first fan-out line.
  • at least one first fan-out line includes a first sub-fan-out line 511 and a second sub-fan-out line 512 .
  • the first sub-fan-out line 511 extends along the first direction F1
  • the second sub-fan-out line 512 extends along the second direction F2.
  • the first sub-fan-out line 511 and the second sub-fan-out line 512 are electrically connected to each other to form a first fan-out line. That is, the first fan-out line has a right-angled portion.
  • the second conductive layer may further include a plurality of second bridge portions QB2 arranged at intervals. Moreover, a plurality of second bridge parts QB2 are located in the fan-out area FO.
  • the first sub-fanout line 511 includes a plurality of first fanout line segments arranged at intervals. In the same first sub-fanout line 511, two adjacent first fanout line segments are electrically connected through the second bridge portion QB2. For example, the first fan-out line segments 511-1 and 511-2 are electrically connected through the second bridge portion QB2. Moreover, in the same first fan-out sub-line 511 , at least one second connection line 112 is disposed in a gap between two adjacent first fan-out line segments.
  • the orthographic projection of the second bridging portion QB2 on the base substrate 10 is perpendicular to the orthographic projection of the second connection line 112 on the base substrate 10 stack.
  • at least one light emitting unit PX at least two light emitting elements QD1 are electrically connected through the second connection line 112 .
  • both the first sub-fan-out line 511 and the common voltage line 210 extend along the first direction F1
  • the implementation principle of the second connection line 112 and the second bridge portion QB2 is the same as that of the first connection line 110 and the first bridge portion
  • the implementation principle of QB1 is basically the same. Therefore, the implementation of the second connection line 112 and the second bridge part QB2 can be basically the same as that of the first connection line 110 and the first bridge part QB1, that is, the specific implementation of the second connection line 112 and the second bridge part QB2
  • the first conductive layer may further include a plurality of third connection lines 113 .
  • at least one light emitting unit PX at least two light emitting elements QD1 are electrically connected through the third connection line 113 .
  • some of the light emitting elements QD1 in the same element group are electrically connected in series through the third connection line 113 .
  • the second light emitting element QD1 in the element group Z-1 numbered 1 is electrically connected in series with the third light emitting element QD1 through a third connection line 113 .
  • the second light-emitting element QD1 in the element group Z-2 numbered 2 is electrically connected in series with the third light-emitting element QD1 through a third connection line 113 .
  • the second conductive layer further includes a plurality of third bridge portions QB3 located in the fan-out area FO.
  • the second sub-fanout line 512 includes a plurality of second fanout line segments arranged at intervals. In the same second fan-out line 512, two adjacent second fan-out line segments are electrically connected through the third bridge part QB3, and, in the same second fan-out line 512, between two adjacent second fan-out line segments At least one third connection line 113 is disposed in the gap.
  • the orthographic projection of the third bridging portion QB3 on the base substrate 10 overlaps with the orthographic projection of the third connecting line 113 on the base substrate 10 .
  • the second sub-fan-out line 512 is arranged vertically to the common voltage line 210, therefore, the implementation principle after rotating the first connecting line 110 and the first bridge part QB1 by 90 degrees can be the same as that of the third connecting line 113 and the third
  • the implementation principle of the bridge part QB3 is basically the same.
  • the implementation of the third connecting line 113 and the third bridging portion QB3 can be implemented after rotating the first connecting line 110 and the first bridging portion QB1 by 90 degrees, that is, the third connecting line 113 and the third bridging portion QB3
  • the third connecting line 113 and the third bridging portion QB3 For specific implementation manners, reference may also be made to the above-mentioned implementation manners of the first connection line 110 and the first bridging portion QB1 , and details are not repeated here.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned light-emitting substrate provided by the embodiment of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the above-mentioned light-emitting substrate, so the implementation of the display device can refer to the implementation of the above-mentioned light-emitting substrate, and repeated descriptions will not be repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本公开实施例公开了发光基板及显示装置，包括：衬底基板；第一导电层，位于衬底基板上；第一导电层包括相互间隔设置的多条公共电压线和多条第一连接线；多条公共电压线沿第一方向延伸且沿第二方向排列；第一绝缘层，位于第一导电层背离衬底基板一侧；第二导电层，位于第一绝缘层背离衬底基板一侧；第二导电层包括相互间隔设置的多个第一桥接部；多条公共电压线中的至少一条包括多个间隔设置的信号线段；同一公共电压线中，相邻两个信号线段通过第一桥接部电连接且相邻两个信号线段之间的线段间隙处设置有至少一条第一连接线；公共电压线中相邻两个信号线段的线段间隙处，第一桥接部在衬底基板的正投影与第一连接线在衬底基板的正投影交叠。

Description

发光基板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及发光基板及显示装置。
背景技术
随着发光二极管技术的发展，采用亚毫米量级甚至微米量级的发光二极管的背光源得到了广泛的应用。由此，不仅可以使利用该背光源的例如透射式显示产品的画面对比度达到有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品的水平，还可以使产品保留液晶显示(Liquid Crystal Display，LCD)的技术优势，进而提升画面的显示效果，为用户提供更优质的视觉体验。
发明内容
本公开实施例提供的发光基板，包括：
衬底基板；
第一导电层，位于所述衬底基板上；其中，所述第一导电层包括相互间隔设置的多条公共电压线和多条第一连接线；所述多条公共电压线沿第一方向延伸且沿第二方向排列；
第一绝缘层，位于所述第一导电层背离所述衬底基板一侧；
第二导电层，位于所述第一绝缘层背离所述衬底基板一侧；其中，所述第二导电层包括相互间隔设置的多个第一桥接部；
其中，所述多条公共电压线中的至少一条包括多个间隔设置的信号线段；同一所述公共电压线中，相邻两个信号线段通过所述第一桥接部电连接且相邻两个所述信号线段之间的线段间隙处设置有至少一条所述第一连接线；
所述公共电压线中相邻两个信号线段的线段间隙处，所述第一桥接部在所述衬底基板的正投影与所述第一连接线在所述衬底基板的正投影交叠。
在一些示例中，在所述衬底基板的正投影交叠的所述第一桥接部与第一连接线之间具有电场，且所述电场的方向为由所述第一导电层指向所述第二导电层。
在一些示例中，所述第二导电层还包括相互间隔设置的第一连接部和第二连接部；
所述第一连接线的第一端通过第一过孔与所述第一连接部电连接，所述第一连接线的第二端通过第二过孔与所述第二连接部电连接；其中，所述第一过孔和所述第二过孔贯穿所述第一绝缘层。
在一些示例中，所述第一连接线在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影，且所述第一连接部在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影；
所述第一连接线在所述衬底基板的正投影覆盖所述第二过孔在所述衬底基板的正投影，且所述第二连接部在所述衬底基板的正投影覆盖所述第二过孔在所述衬底基板的正投影。
在一些示例中，所述第一连接部覆盖所述第一过孔的区域在所述第一方向上的宽度大于所述第一连接线在所述第一方向上的宽度；
所述第二连接部覆盖所述第二过孔的区域在所述第一方向上的宽度大于所述第一连接线在所述第一方向上的宽度。
在一些示例中，所述第一桥接部在所述第一方向上的宽度的范围为100微米～250微米，所述第一连接线在所述第一方向上的宽度的范围为0.6微米～2.5微米。
在一些示例中，所述第一连接线在所述第二方向上的长度大于所述第一桥接部在所述第二方向上的长度。
在一些示例中，所述第一桥接部延伸至所述第一连接部的一侧与所述第一连接部之间具有第一间隙，所述第一桥接部延伸至所述第二连接部的一侧与所述第二连接部之间具有第二间隙；
所述第一间隙的宽度和所述第二间隙的宽度中的至少一个的范围为20微 米～50微米。
在一些示例中，所述第一连接线和所述信号线段之间的间隙在所述第一方向上的宽度的范围为20微米～50微米。
在一些示例中，在垂直于所述衬底基板所在平面的方向上，所述第一桥接部的厚度大于或等于所述第二导电层中第一连接部和第二连接部的厚度。
在一些示例中，所述第二导电层还包括多个焊盘；
所述第一连接部的一端与一个所述焊盘电连接，另一端与所述第一连接线的第一端电连接；
所述第二连接部的另一端与另一个所述焊盘电连接，另一端与所述第一连接线的第二端电连接。
在一些示例中，所述多条公共电压线位于显示区；所述显示区还包括多个发光单元，所述发光单元包括驱动电路与多个发光元件；其中，所述驱动电路包括公共电压端和输出端；所述多个发光元件依次串联于驱动电压端和所述输出端之间；所述公共电压端与所述公共电压线电连接；所述焊盘与所述发光元件和所述驱动电路中的至少一个电连接；
所述发光单元中的多个发光元件分为M个元件组，每个元件组包括沿所述第一方向排列的N个发光元件；所述M个元件组沿所述第二方向排列；N为大于0的整数，M为大于0的整数；
沿所述驱动电压端指向所述输出端的顺序，将所述多个元件组依次编号；
编号为1的元件组中的第1个发光元件与所述驱动电压端电连接；
编号为k的元件组中的第1个发光元件与编号为k+1的元件组中的第1个发光元件通过所述第一连接线电连接；其中，1<k<M且k为整数；
编号为M的元件组中的最后第1个发光元件与所述输出端电连接；
一列发光单元对应一条所述公共电压线，且所述公共电压线位于对应所述列发光单元中编号为k的元件组和编号为k+1的元件组之间。
在一些示例中，所述第二导电层还包括间隔设置的多条串联走线；同一所述元件组中的发光元件通过串联走线串联电连接，且编号为k-1的元件组中 的最后1个发光元件与编号为k的元件组中的最后1个发光元件通过所述串联走线电连接；
所述公共电压线在所述衬底基板的正投影与所述串联走线在所述衬底基板的正投影不交叠。
在一些示例中，所述发光基板还包括扇出区；
所述第一导电层还包括位于所述扇出区的多条第一扇出线和多条第二连接线；其中，一条所述公共电压线与一条所述第一扇出线电连接；所述第一扇出线包括第一子扇出线和第二子扇出线；所述第一子扇出线沿所述第一方向延伸，所述第二子扇出线沿所述第二方向延伸；
所述第二导电层还包括位于所述扇出区的多个第二桥接部；
所述第一子扇出线包括多个间隔设置的第一扇出线段；同一所述第一子扇出线中，相邻两个第一扇出线段通过所述第二桥接部电连接且相邻两个所述第一扇出线段之间的间隙处设置有至少一条所述第二连接线；
所述第一子扇出线中相邻两个第一扇出线段的间隙处，所述第二桥接部在所述衬底基板的正投影与所述第二连接线在所述衬底基板的正投影交叠。
在一些示例中，所述第一导电层还包括多条第三连接线；
所述第二导电层还包括位于所述扇出区的多个第三桥接部；
所述第二子扇出线包括多个间隔设置的第二扇出线段；同一所述第二子扇出线中，相邻两个第二扇出线段通过所述第三桥接部电连接且相邻两个所述第二扇出线段之间的间隙处设置有至少一条所述第三连接线；
所述第二子扇出线中相邻两个第二扇出线段的间隙处，所述第三桥接部在所述衬底基板的正投影与所述第三连接线在所述衬底基板的正投影交叠。
在一些示例中，所述扇出区包括多个发光单元，所述发光单元包括驱动电路与多个发光元件；其中，所述驱动电路包括公共电压端和输出端；所述多个发光元件依次串联于驱动电压端和所述输出端之间；
所述公共电压端与所述第一扇出线电连接；
至少一个所述发光单元中，至少两个所述发光元件通过所述第二连接线 电连接；和/或，至少两个所述发光元件通过所述第三连接线电连接。
本公开实施例提供的显示装置，包括上述发光基板。
附图说明
图1a为相关技术中的发光基板的结构示意图；
图1b为相关技术中的发光基板的局部版图布局示意图；
图2为本公开实施例中的发光基板的结构示意图；
图3为本公开实施例中的发光基板的局部具体结构示意图；
图4为本公开实施例提供的驱动电路中第二输入信号的波形图；
图5为本公开实施例提供的驱动电路的信号时序图；
图6为本公开实施例中的发光基板的局部版图布局示意图；
图7为图6中FB区域的放大版图布局示意图；
图8a为图7中沿AA’方向上的剖视结构示意图；
图8b为图7中沿BB’方向上的剖视结构示意图；
图9为本公开实施例中扇出区的局部版图布局示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元 件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
结合图1a与图1b，基板01上依次设置了第一导电层02、绝缘层03以及第二导电层04。其中，第一导电层02具有驱动电压线220、公共电压线210。第二导电层04具有金属连接线。以发光单元具有9个发光元件为例，这9个发光元件通过金属连接线依次串联电连接。将这9个发光元件之间的金属连接线分成8段：A段、B段、C段、D段、E段、F段、G段。例如，驱动电压线220传输的电压为27V，公共电压线210传输的电压为0V，A段的金属连接线传输的电压为24V，B段的金属连接线传输的电压为21V，C段的金属连接线传输的电压为18V，D段的金属连接线传输的电压为15V，E段的金属连接线传输的电压为12V，F段的金属连接线传输的电压为9V，G段的金属连接线传输的电压为6V，H段的金属连接线传输的电压为3V。并且，C段的金属连接线在衬底基板的正投影与驱动电压线220在衬底基板的正投影之间交叠，F段的金属连接线在衬底基板的正投影与公共电压线210在衬底基板的正投影之间交叠。
由于F段的金属连接线传输的电压大于公共电压线210传输的电压，使得F段的金属连接线和公共电压线210的交叠处之间的电场的方向为由第二导电层指向第一导电层。由于第二导电层易于暴露，容易引人水氧，并且第一导电层02和第二导电层04的材料通常采用低电阻的Cu材质。由于Cu材料比较活泼，因此在电场作用下容易产生金属腐蚀的情形。F段的金属连接线和公共电压线210之间存在电势差，构成电化学腐蚀阳极与保护阴级，F段的金属连接线为正极发生氧化反应，公共电压线210为阴极发生还原反应。电化学腐蚀的不断进行，最终导致F段的金属连接线和公共电压线210接触短 路。然而，在发光基板中若存在电化学腐蚀，则会对发光基板的发光稳定性造成影响。
并且，由于C段的金属连接线传输的电压小于驱动电压线220传输的电压，使得C段的金属连接线和驱动电压线220的交叠处之间的电场的方向为由第一导电层指向第二导电层。而驱动电压线220还有绝缘层03保护，并且水氧的入侵路径也比较远，因此可以降低电化学腐蚀的情形。有鉴于此，本公开至少一个实施例提供了发光基板及显示装置，降低电化学腐蚀对发光基板的影响，提高发光稳定性。
在一些实施例中，如图2所示，本公开至少一个实施例提供的发光基板，可以包括衬底基板10。衬底基板10可以包括显示区和扇出区FO。示例性地，衬底基板10的材质可以选自塑料、聚酰亚胺、硅、陶瓷、玻璃、石英等，本公开的实施例对此不作限制。
在一些实施例中，如图2所示，显示区可以包括阵列排布的多个发光单元PX。例如，多个发光单元PX排列为多行多列。在实际应用中，发光单元PX的数量可以根据实际需求而定，例如根据发光基板的尺寸和所需要的亮度而定，虽然图2中仅示出了6行5列发光单元PX，但是应当理解，发光单元PX的数量不限于此。
在一些实施例中，如图2所示，显示区中，发光单元PX可以沿第一方向F1和第二方向F2排列为多行多列。示例性地，发光基板呈矩形，第一方向F1可以为平行于发光基板的长边的方向，第二方向F2可以为平行于发光基板的短边的方向。或者，第一方向F1也可以为平行于发光基板的短边的方向，第二方向F2也可以为平行于发光基板的长边的方向。当然，本公开的实施例不限于此，第一方向F1和第二方向F2可以为任意的方向，只需使第一方向F1和第二方向F2交叉即可。并且，多个发光单元PX也不限于沿直线排列，也可以沿折线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
在一些实施例中，如图2与图3所示，每个发光单元PX可以包括驱动电 路QD0与多个发光元件QD1。示例性地，驱动电路QD0可以包括第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND。并且，发光单元PX中的多个发光元件QD1依次串联，并电连接于驱动电压端Vled和驱动电路QD0的输出端OT之间。当然，发光单元PX中的多个发光元件QD1也可以采用并联方式，以电连接于驱动电压端Vled和驱动电路QD0的输出端OT之间。或者，发光单元PX中的多个发光元件QD1也可以采用先将部分发光元件QD1并联后再进行串联方式，以电连接于驱动电压端Vled和驱动电路QD0的输出端OT之间。在实际应用中，可以根据实际的需求进行设计确定，在此不作限定。
在一些示例中，在具体实施时，驱动电路QD0可以被配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT与串联的发光元件QD1形成电流通路。示例性地，第一输入端Di接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动电路QD0。例如，不同的驱动电路QD0的地址可以相同或不同。第一输入信号可以为8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入端Pwr接收第二输入信号，第二输入信号例如为电力线载波通信信号。例如，第二输入信号不仅为驱动电路QD0提供电能，还向驱动电路QD0传输通信数据，该通信数据可用于控制相应的发光单元PX的发光时长，进而控制其视觉上的发光亮度。输出端OT可在不同的时段内分别输出不同的信号，例如分别输出中继信号和驱动信号。例如，中继信号为提供给其他驱动电路QD0的地址信号，即其他驱动电路QD0的第一输入端Di接收该中继信号以作为第一输入信号，从而获取地址信号。例如，驱动信号可以为驱动电流，用于驱动发光元件QD1发光。公共电压端GND接收公共电压信号，例如接地信号。
以及，驱动电路QD0配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT提供驱动信号至依次串联的多个发光 元件QD1。其中，在第一时段内，输出端OT输出中继信号，该中继信号被提供给其他驱动电路QD0以使其他驱动电路QD0获得地址信号。在第二时段内，输出端OT输出驱动信号，该驱动信号被提供给依次串联的多个发光元件QD1，使得发光元件QD1在第二时段内发光。例如，第一时段与第二时段为不同的时段，第一时段例如可以早于第二时段。第一时段可以与第二时段连续相接，第一时段的结束时刻即为第二时段的开始时刻；或者，第一时段与第二时段中间还可以有其他时段，该其他时段可以用于实现其他需要的功能，该其他时段也可以仅用于使第一时段和第二时段间隔开，以避免输出端OT在第一时段和第二时段的信号彼此干扰。
需要说明的是，当驱动信号为驱动电流时，驱动电流可以从输出端OT流向发光元件QD1，也可以从发光元件QD1流入输出端OT，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。在本文中，“输出端OT输出驱动信号”表示输出端OT提供驱动信号，而驱动信号的方向既可以从输出端OT流出，也可以流入输出端OT。
迷你发光二极管(Mini Light Emitting Diode，Mini-LED)或微型发光二极管(Micro Light Emitting Diode，Micro-LED)的尺寸小且亮度高，可以大量应用于显示装置或其背光模组中，通过对背光进行精细调节，从而实现高动态范围图像(High-Dynamic Range，HDR)的显示。例如，Micro-LED的典型尺寸(例如长度)小于100微米，例如10微米～80微米；Mini-LED的典型尺寸(例如长度)为80微米～350微米，例如80微米～120微米。示例性地，发光元件QD1可以为微型发光二极管(Micro-LED)或迷你发光二极管(Mini-LED)。
例如，每个发光元件QD1包括正极(+)和负极(-)(或者，也可称为阳极和阴极)，多个发光元件QD1的正极和负极依序首尾串联，从而在驱动电压端Vled和输出端OT之间形成电流流通路径。并且，驱动电压端Vled可以提供驱动电压，例如在需要使发光元件QD1发光的时段(第二时段)内为高电压，而在其他时段内为低电压。由此，在第二时段内，驱动信号(例如驱 动电流)从驱动电压端Vled依次流经多个发光元件QD1，然后流入驱动电路QD0的输出端OT。多个发光元件QD1在驱动电流流过时发光，通过控制驱动电流的持续时间，可以控制发光元件QD1的发光时长，从而控制视觉上的发光亮度。
在一些示例中，如图2与图3所示，发光单元PX可以包括9个发光元件QD1，该9个发光元件QD1排列为3行3列。示例性地，将这9个发光元件QD1串联时，以与驱动电压端Vled电连接的发光元件QD1作为这9个发光元件QD1串联的起点，与驱动电路QD0的输出端OT电连接的发光元件QD1作为这9个发光元件QD1串联的终点。并且，驱动电压端Vled可以与发光元件QD1的正极电连接，驱动电路QD0的输出端OT可以与发光元件QD1的负极电连接。采用这种分布方式和串联方式，可以有效避免走线交叠，便于设计和制备。并且，串联线路上任意的相邻两个发光元件QD1之间的信号连线的长度可以设置大致相同，使得信号连线本身的电阻较为均衡，可以提高负载均衡性，提高电路的稳定性。
需要说明的是，本公开的实施例中，每个发光单元PX中的发光元件QD1的数量不受限制，可以为6个、8个、12个等任意数量，而不限于9个。多个发光元件QD1可以采用任意的排列方式，例如按照所需要的图案排列，而不限于矩阵排列方式。并且，驱动电路QD0的设置位置不受限制，可以设置在发光元件QD1彼此之间的任意空隙中，这可以根据实际需求而定，本公开的实施例对此不作限制。
在一些示例中，在具体实施时，结合图2与图3所示，驱动电路QD0在发光单元PX中的相对位置可以不同，或者，驱动电路QD0在发光单元PX中的位置也可以相同。以及，可以使每个发光单元PX中的发光元件QD1的相对位置关系相同。例如，可以将一个发光单元PX中的发光元件QD1的相对位置关系作为基准，沿第一方向F1和第二方向F2周期性的重复排列。例如，在第一方向F1上排列的多个发光单元PX中，位于每个发光单元PX中相同位置处的发光元件QD1可以沿第一方向F1大致排布于同一条直线上。 在第二方向F2上排列的多个发光单元PX中，位于每个发光单元PX中相同位置处的发光元件QD1可以沿第二方向F2大致排布于同一条直线上。
在一些示例中，在具体实施时，驱动电路QD0可以包括解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路、中继信号生成电路和电源供给电路。
示例性地，解调电路与第二输入端Pwr和物理层接口电路电连接，被配置为对第二输入信号进行解调以得到通信数据，并将该通信数据传输至物理层接口电路。例如，第二输入端Pwr输入的第二输入信号为电力线载波通信信号，该电力线载波通信信号包含对应于通信数据的信息。例如，通信数据为反映发光时长的数据，进而代表了所需要的发光亮度。相比于通常的串行外设接口(Serial Peripheral Interface，SPI)协议，本公开实施例通过采用电力线载波通信(Power Line Carrier Communication，PLC)协议，将通信数据叠加在电源信号上，从而有效减少信号线的数量。
如图4所示，虚线椭圆框表示相应波形的放大图，第二输入信号为高电平时，其高电平的幅值在阈值幅值Vth的附近波动，例如，在第一幅值V1和第二幅值V2之间变化，V2<Vth<V1。通过调制第一幅值V1和第二幅值V2的变化规律，可以将通信数据调制到第二输入信号中，从而使第二输入信号在传输电能的同时传输对应于通信数据的信息。例如，解调电路将第二输入信号的直流电源成分滤掉，从而可以得到通信数据。关于第二输入信号的详细说明可以参考常规的电力线载波通信信号，此处不再详述。相应地，解调电路的详细说明也可以参考常规的电力线载波通信信号的解调电路，此处不再详述。
示例性地，物理层接口电路还与数据处理控制电路电连接，被配置为对通信数据进行处理以得到数据帧(例如帧频数据)，并将数据帧传输至数据处理控制电路。物理层接口电路得到的数据帧包含了需要传输给该驱动电路QD0的信息，例如与发光时间相关的信息(例如发光时间的具体时长)。例如，物理层接口电路可以为通常的端口物理层(Physical，PHY)，详细说明可参考 常规设计，此处不再详述。
示例性地，数据处理控制电路还与第一输入端Di、脉宽调制电路和中继信号生成电路电连接。数据处理控制电路被配置为基于数据帧产生脉宽控制信号并将该脉宽控制信号传输至脉宽调制电路，以及基于第一输入信号产生中继控制信号并将该中继控制信号传输至中继信号生成电路。例如，根据数据帧可以获知与该驱动电路QD0相连的发光元件QD1所需要的发光时长，因此基于该发光时长产生对应的脉宽控制信号。例如，中继控制信号为数据处理控制电路对第一输入信号处理之后产生的信号。通过对第一输入信号进行处理(例如解析、锁存、译码等)，可以获知对应于该驱动电路QD0的地址信号，并且会产生对应于后续地址的中继控制信号，该后续地址对应于其他驱动电路QD0。例如，数据处理控制电路可以实现为单片机、中央处理器(Central Processing Unit，CPU)、数字信号处理器等。
示例性地，脉宽调制电路还与驱动信号生成电路电连接，被配置为响应于脉宽控制信号产生脉宽调制信号，并将脉宽调制信号传输至驱动信号生成电路。例如，脉宽调制电路产生的脉宽调制信号对应于发光元件QD1所需要的发光时长，例如有效脉宽时长等于发光元件QD1所需要的发光时长。例如，脉宽调制电路的详细说明可以参考常规的脉宽调制电路，此处不再详述。
示例性地，驱动信号生成电路还与输出端OT电连接，被配置为响应于脉宽调制信号产生驱动信号，并将该驱动信号从输出端OT输出。这里，将驱动信号从输出端OT输出，可以表示驱动信号(例如驱动电流)从输出端OT流向发光元件QD1，也可以表示驱动信号(例如驱动电流)从发光元件QD1流入输出端OT，具体的电流方向不受限制。
示例性地，在一些示例中，当驱动信号为驱动电流时，驱动信号生成电路可以包括电流源和金属氧化物半导体(Metal Oxide Semiconductor，MOS)场效应晶体管(Field Effect Transistor，FET)，将该金属氧化物半导体场效应晶体管称为MOS管。MOS管的控制极接收脉宽调制电路传输的脉宽调制信号，从而在脉宽调制信号的控制下导通或截止。MOS管的第一极与输出端OT 连接，MOS管的第二极与电流源的第一极连接，电流源的第二极与公共电压端GND连接以接收公共电压。例如，电流源可以为恒流源。
当脉宽调制信号为有效电平时，MOS管导通，电流源通过输出端OT提供驱动电流。当脉宽调制信号为无效电平时，MOS管截止，此时输出端OT不提供驱动电流。脉宽调制信号的有效电平的时长等于MOS管的导通时长，MOS管的导通时长等于输出端OT提供驱动电流的时长。由此，可以进一步控制发光元件QD1的发光时长，进而控制视觉上的发光亮度。例如，在一些示例中，当MOS管导通时，驱动电流从OT端流入驱动电路QD0，并依次流经MOS管和电流源，然后流入接地端(例如公共电压端GND)。需要说明的是，本公开的实施例中，驱动信号生成电路还可以采用其他电路结构形式，本公开的实施例对此不作限制。
示例性地，中继信号生成电路还与输出端OT电连接，被配置为基于中继控制信号生成中继信号，并将中继信号从输出端OT输出。例如，中继控制信号对应于后续地址，基于中继控制信号产生的中继信号包含了后续地址，该后续地址对应于其他驱动电路QD0。中继信号从输出端OT输出后，被提供给另行提供的驱动电路QD0的第一输入端Di，该中继信号作为第一输入信号输入到该另行提供的驱动电路QD0，从而使该另行提供的驱动电路QD0获取对应的地址信号。中继信号生成电路可以通过锁存器、译码器、编码器等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，虽然驱动信号生成电路和中继信号生成电路均与输出端OT电连接，但是，驱动信号生成电路和中继信号生成电路分别在不同的时段输出驱动信号和中继信号，驱动信号和中继信号通过输出端OT分时传输，因此不会彼此影响。
示例性地，电源供给电路分别与解调电路和数据处理控制电路电连接，被配置为接收电能并给数据处理控制电路供电。例如，第二输入信号为电力线载波通信信号，经过解调电路解调后，第二输入信号中的直流电源成分(即电能)传输至电源供给电路，再由电源供给电路提供给数据处理控制电路。 当然，本公开的实施例不限于此，电源供给电路还可以与驱动电路QD0中的其他电路电连接以提供电能。电源供给电路可以通过开关电路、电压转换电路、稳压电路等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，驱动电路QD0还可以包括更多的电路和部件，不限于上述的解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路、中继信号生成电路和电源供给电路，这可以根据需要实现的功能而定，本公开的实施例对此不作限制。
如图5所示，驱动电路QD0工作时，首先上电(也即通电)完成初始化，接着在时段S1进行写地址操作，也即是，在时段S1，第一输入信号Di_1通过第一输入端Di输入驱动电路QD0，从而写入地址。例如，第一输入信号Di_1通过另行提供的发送器发送。
接着，在时段S2，进行驱动配置，并且，通过输出端OT输出中继信号Di_2。例如，中继信号Di_2作为第一输入信号被输入到另行提供的驱动电路QD0的第一输入端Di。例如，前述的第一时段为时段S2。
然后，在时段S3，驱动电压端Vled通电。例如，当多个驱动电路QD0均获取到对应的地址后，大约间隔10微秒之后进入时段S3。此时，驱动电压端Vled提供的驱动电压变为高电平。
接着，在时段S4，驱动电路QD0处于正常工作模式，输出端OT根据所需要的时长提供驱动信号(例如驱动电流)，以使与该驱动电路QD0连接的发光元件QD1根据需要的时长发光。例如，前述的第二时段为时段S4。例如，在作为显示装置的背光单元的情形，采用该驱动电路QD0的发光基板在局部背光调节(Local Dimming)模式下工作，可以实现高动态范围效果。
最后，在时段S5，系统关闭，也即是，该驱动电路QD0断电，且驱动电压端Vled提供的驱动电压变为低电平，发光元件QD1停止发光。
需要说明的是，上述工作流程仅为示意性的，而非限制性的，驱动电路QD0实际的工作流程可以根据实际需求而定，本公开的实施例对此不作限制。在图5中，VREG、POR、Vreg_1.8、OSC、Re_B均为驱动电路QD0的内部 信号，不会经过第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND输入或输出。Di_1为该驱动电路QD0接收的第一输入信号，Di_2为该驱动电路QD0输出的中继信号(也即为相连的下一个驱动电路QD0接收的第一输入信号)，Di_n为依次连接的多个驱动电路QD0中第n个驱动电路QD0接收的第一输入信号。
示例性地，在具体实施时，驱动电路QD0可以设置为芯片，芯片尺寸(例如长度)可以为几十微米，芯片面积约为几百平方微米甚至更小，与Mini-LED的大小相似，具有小型化特点，便于集成到发光基板中(例如绑定连接在发光基板表面)，节省了印刷电路板的设置空间，简化了结构，有利于实现轻薄化。每一个驱动电路QD0直接驱动一个发光单元PX，避免了行扫描控制方式操作复杂且容易闪烁等问题。并且，该驱动电路QD0的端口数量少，所需信号数量少，控制方式简单，走线方式简单，成本低。
在具体实施时，在本公开实施例中，如图6至图8b所示，衬底基板10上设置有缓冲层(Buffer)400，以提高第一导电层的附着力。第一导电层位于缓冲层400背离衬底基板10一侧。示例性地，第一导电层可以包括：相互间隔设置的多条公共电压线210、多条驱动电压线220、多条源电压线230以及多条第一连接线110。示例性地，可以使一列发光单元PX对应一条公共电压线210，一条源电压线230以及一条驱动电压线220。其中，针对一列发光单元PX对应：公共电压线210、源电压线230以及驱动电压线220，该公共电压线210在衬底基板10的正投影位于该驱动电压线220和该源电压线230之间。
示例性地，多条驱动电压线220沿第一方向F1延伸且沿第二方向F2排列。可以使一列发光单元PX对应一条驱动电压线220，以使该列发光单元PX的驱动电压端Vled与对应的驱动电压线220电连接。例如，如图3所示，将这9个发光元件QD1串联时，以与驱动电压线220电连接的发光元件QD1作为这9个发光元件QD1串联的起点。
示例性地，多条源电压线230沿第一方向F1延伸且沿第二方向F2排列。 可以使源电压线230与驱动电路QD0的第二输入端Pwr电连接。这样可以通过源电压线230向驱动电路QD0的第二输入端Pwr传输第二输入信号。
示例性地，多条公共电压线210沿第一方向F1延伸且沿第二方向F2排列。在一些示例中，可以使公共电压端与公共电压线210电连接，以通过公共电压线210向驱动电路QD0的公共电压端提供电压。
需要说明的是，通过使第一导电层中的大部分信号线的延伸方向一致，可以合理设计布线空间，降低信号干扰。
示例性地，一列发光单元PX对应一条公共电压线210和一条驱动电压线220。即，一列发光单元PX中的驱动电路QD0的公共电压端GND均与同一条公共电压线210电连接，一列发光单元PX中的驱动电压端Vled均与同一条驱动电压线220电连接。
在一些示例中，在具体实施时，如图6与图7所示，针对一列发光单元PX对应的公共电压线210、驱动电压线220以及源电压线230，公共电压线210位于驱动电压线220与源电压线230之间。示例性地，公共电压线210在第二方向F2上的宽度大于驱动电压线220在第二方向F2上的宽度。驱动电压线220在第二方向F2上的宽度大于源电压线230在第二方向F2上的宽度。源电压线230在第二方向F2上的宽度大于级联走线240在第二方向F2上的宽度。
在一些示例中，第一导电层可以采用金属材料形成单层结构。或者，第一导电层也可以采用金属材料形成叠层结构。例如，采用两层由金属材料形成的第一导电层，例如第一导电层具有C-1层和C-2层。示例性地，金属材料可以包括但不限于Cu。
在具体实施时，在本公开实施例中，在第一导电层上形成有第一绝缘层310，即第一绝缘层310位于第一导电层背离衬底基板10的一侧。并且，第一绝缘层310设置有第一过孔GK1、第二过孔GK2、第三过孔GK3、第四过孔GK4。示例性地，第一绝缘层310可以形成采用无机、有机或者有机-无机复合材料的单层结构。或者，第一绝缘层310也可以为采用无机、有机或者 有机-无机复合材料中的至少一种形成的多层结构。例如，可以采用多层有机材料形成第一绝缘层310。也可以采用多层无机材料形成第一绝缘层310。也可以采用层叠设置有机材料和无机材料形成第一绝缘层310。示例性地，如图8a与图8b所示，第一绝缘层310可以包括绝缘层311和绝缘层312。其中，可以使绝缘层312的材料为有机材料，绝缘层311的材料为无机材料。
示例性地，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一。有机材料可以聚酰亚胺(PI)等。
在一些示例中，在具体实施时，如图6至图8b所示，在第一绝缘层310上形成有第二导电层，即第二导电层位于第一绝缘层310背离衬底基板10的一侧。示例性地，第二导电层可以包括：多个焊盘(如PD1、PD2、PD3、PD4)、相互间隔设置的多条级联走线240。示例性地，多条级联走线240沿第一方向F1延伸。例如，沿第一方向F1，一列中的发光单元PX中的驱动电路QD0可以相互耦接，并且，一列中，相邻的发光单元PX中的驱动电路QD0通过级联走线240耦接。例如，沿第一方向F1的箭头所指的方向，定义第一行至第六行。沿第二方向F2的箭头所指的方向，定义第一列至第五列。以第一列为例，第一行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第二行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第二行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第三行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第三行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第四行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第四行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第五行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第五行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第六行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第六行发光单元PX中的驱动电路QD0的输出端通过一条级联输出走线与级联输出端子耦接。这样可以使级联走线240与驱动电路QD0级联的方向一致，降低信号交叠面积，降低信号干扰。
在具体实施时，在本公开实施例中，焊盘可以与驱动电路电连接。例如，焊盘与驱动电路中的相应的引脚电连接，以进行信号传输。
在具体实施时，在本公开实施例中，如图6与图7所示，焊盘也可以与发光元件电连接。例如，发光元件的每一个电极与一个焊盘对应电连接。例如，焊盘PD3与发光元件QD1的正极电连接，焊盘PD1与发光元件QD1的负极电连接。焊盘PD2与发光元件QD1的正极电连接，焊盘PD4与发光元件QD1的负极电连接。其余以此类推，在此不作赘述。
在具体实施时，在本公开实施例中，在第二导电层上形成有第二绝缘层320，即第二绝缘层320位于第二导电层背离衬底基板10的一侧。示例性地，第二绝缘层320可以形成采用无机、有机或者有机-无机复合材料的单层结构。或者，第二绝缘层320也可以为采用无机、有机或者有机-无机复合材料中的至少一种形成的多层结构。例如，可以采用多层有机材料形成第二绝缘层320。也可以采用多层无机材料形成第二绝缘层320。也可以采用层叠设置有机材料和无机材料形成第二绝缘层320。示例性地，如图8a与图8b所示，第二绝缘层320可以包括绝缘层321和绝缘层322。其中，可以使绝缘层322的材料为有机材料，绝缘层321的材料为无机材料。
示例性地，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一。有机材料可以聚酰亚胺(PI)等。
在一些示例中，在具体实施时，如图6至图8b所示，多条公共电压线210中的至少一条可以包括多个间隔设置的信号线段。示例性地，每一条公共电压线210可以包括多个间隔设置的信号线段。例如，公共电压线210可以包括信号线段211-1、211-2。例如，同一条公共电压线210中，相邻两个信号线段之间具有线段间隙，一个线段间隙可以位于一个发光单元PX中。
在一些示例中，在具体实施时，如图6至图8b所示，第二导电层还包括相互间隔设置的多个第一桥接部QB1。同一公共电压线210中，相邻两个信号线段可以通过第一桥接部QB1电连接，以使信号线段可以通过第一桥接部QB1进行电连接，传输信号。例如，信号线段211-1、211-2可以通过第一桥 接部QB1电连接。信号线段211-2通过第三过孔GK3与第一桥接部QB1电连接，信号线段211-1通过第四过孔GK4与第一桥接部QB1电连接。示例性地，同一条公共电压线210中，相邻两个信号线段可以通过一个、两个、三个或更多个第一桥接部QB1电连接。当然，相邻两个信号线段之间连接的第一桥接部QB1的数量，可以根据实际环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如图6至图8b所示，同一条公共电压线210中，相邻两个信号线段之间的线段间隙处设置有至少一条第一连接线110。示例性地，同一条公共电压线210中，相邻两个信号线段之间的线段间隙处可以设置有一条第一连接线110。例如，信号线段211-1、211-2之间的线段间隙处可以设置有一条第一连接线110。当然，同一条公共电压线210中，相邻两个信号线段之间的线段间隙处也可以设置有两条、三条或更多条第一连接线110，这可以根据实际环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如图6至图8b所示，公共电压线210中相邻两个信号线段的线段间隙处，第一桥接部QB1在衬底基板10的正投影与第一连接线110在衬底基板10的正投影交叠。这样可以使第一桥接部QB1和第一连接线110在垂直于衬底基板10所在平面的方向上具有交叠区域，可以降低第一连接线110占用过多额外的空间。
在一些示例中，在具体实施时，如图6至图8b所示，可以使第一桥接部QB1上传输的电压小于第一连接线110上传输的电压。例如，公共电压线210的电压可以为接地电压，则第一桥接部QB1可以为接地电压，例如0V。第一连接线110的可以为正值，例如为9V。当然，在实际应用中，公共电压线210的电压和第一连接线110的电压可以根据实际应用环境来设计确定，在此不作限定。
本公开实施例中，如图8a所示，若对第一连接线110加载的电压大于第一桥接部QB1加载的电压时，在衬底基板10的正投影交叠的第一桥接部与第一连接线之间具有电场，且该电场的方向F02为由第一导电层指向第二导电层。从而可以避免使第一连接线110作为阴极发生还原反应，也可以避免使 第一桥接部QB1作为正极发生氧化反应。并且，第一桥接部QB1上有第二绝缘层320的保护，而且水氧的入侵路径也比较远。因此可以有效的降低电化学腐蚀的情形。尤其是针对图1b所示的F段的金属连接线，可以有效的降低电化学腐蚀的情形。
在实际应用中，为了降低电化学腐蚀，可以增加第一绝缘层310的厚度和层数。而本公开实施例中，若对第一连接线110加载的电压大于第一桥接部QB1加载的电压时，第一连接线110和第一桥接部QB1之间产生的电场的电场方向为由第一连接线110指向第一桥接部QB1的方向F02，可以有效的降低电化学腐蚀的情形。因此，可以不用再额外的增加绝缘层的厚度和层数，可以节约产能。
在一些示例中，在具体实施时，如图6与图7所示，第一连接线110可以沿第二方向F2延伸。第二导电层还可以包括相互间隔设置的第一连接部BL1和第二连接部BL2；其中，第一连接线110的第一端通过第一过孔GK1与第一连接部BL1电连接，第一连接线110的第二端通过第二过孔GK2与第二连接部BL2电连接。其中，第一过孔GK1和第二过孔GK2贯穿第一绝缘层310。示例性地，第一连接部BL1在衬底基板10的正投影位于线段间隙在衬底基板10的正投影内，且第一连接部BL1在衬底基板10的正投影位于线段间隙在衬底基板10的正投影的第一端，以及第一连接部BL1在衬底基板10的正投影与第一桥接部QB1在衬底基板10的正投影不交叠。第二连接部BL2在衬底基板10的正投影位于线段间隙在衬底基板10的正投影内，且第二连接部BL2在衬底基板10的正投影位于线段间隙在衬底基板10的正投影的第二端，以及第二连接部BL2在衬底基板10的正投影与第一桥接部QB1在衬底基板10的正投影不交叠。
在一些示例中，在具体实施时，如图6与图7所示，第一连接部BL1还与这些多个焊盘中的一个焊盘(例如PD1)电连接，第二连接部BL2还与这些多个焊盘中的另一个焊盘(例如PD2)电连接。即，第一连接部BL1的一端与一个焊盘(例如PD1)电连接，另一端与第一连接线的第一端电连接。 第二连接部BL2的另一端与另一个焊盘(例如PD2)电连接，另一端与第一连接线的第二端电连接。这样可以使发光元件QD1通过焊盘PD1、第一连接部BL1、第一连接线110、第二连接部BL2以及焊盘PD2与另一个发光元件QD1串联。
在一些示例中，在具体实施时，如图6与图7所示，第一连接线110在衬底基板10的正投影覆盖第一过孔GK1在衬底基板10的正投影，且第一连接部BL1在衬底基板10的正投影覆盖第一过孔GK1在衬底基板10的正投影。也就是说，第一过孔GK1的尺寸不能超过交叠区域所在的第一连接线110的尺寸，以及第一过孔GK1的尺寸也不能超过交叠区域所在的第一连接部BL1的尺寸。这样可以使第一连接线110与第一连接部BL1通过第一过孔GK1尽可能的接触，以提高电连接的可靠性。
在一些示例中，在具体实施时，如图6与图7所示，可以使第一连接部BL1覆盖第一过孔GK1的区域在第一方向F1上的宽度W11大于第一连接线110在第一方向F1上的宽度W12。这样可以使第一连接部BL1覆盖第一过孔GK1的区域不仅比第一过孔GK1所在的区域大，还可以比第一连接线110覆盖第一过孔GK1的区域大，从而可以使第一连接部BL1尽可能通过第一过孔与第一连接线接触，以提高电连接的可靠性。
在一些示例中，在具体实施时，如图7所示，第一桥接部QB1在第一方向F1上的宽度W30的范围可以为100微米～250微米。示例性地，第一桥接部QB1在第一方向F1上的宽度W30可以为100微米。第一桥接部QB1在第一方向F1上的宽度W30也可以为150微米。第一桥接部QB1在第一方向F1上的宽度W30也可以为200微米。第一桥接部QB1在第一方向F1上的宽度W30也可以为250微米。当然，第一桥接部QB1在第一方向F1上的宽度W30的具体数值，可以根据实际应用环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如图7所示，第一连接线110在第一方向F1上的宽度W0的范围可以为0.6微米～2.5微米。示例性地，第一连接线110在第一方向F1上的宽度W0可以为0.6微米。第一连接线110在第一方 向F1上的宽度W0也可以为0.8微米。第一连接线110在第一方向F1上的宽度W0也可以为1.0微米。第一连接线110在第一方向F1上的宽度W0也可以为1.6微米。第一连接线110在第一方向F1上的宽度W0也可以为2.0微米。第一连接线110在第一方向F1上的宽度W0也可以为2.5微米。当然，第一连接线110在第一方向F1上的宽度W0的具体数值，可以根据实际应用环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如图7所示，第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40的范围可以为20微米～50微米。示例性地，第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40可以为20微米。第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40也可以为25微米。第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40也可以为30微米。第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40也可以为35微米。第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40也可以为40微米。第一连接线110和信号线段之间的间隙在第一方向F1上的宽度W40也可以为50微米。当然，第一连接线110和信号线段之间的间隙在第一方向F1上的宽度的具体数值，可以根据实际应用环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如图6至图8a所示，第一连接线110在衬底基板10的正投影覆盖第二过孔GK2在衬底基板10的正投影，且第二连接部BL2在衬底基板10的正投影覆盖第二过孔GK2在衬底基板10的正投影。也就是说，第二过孔GK2的尺寸不能超过交叠区域所在的第一连接线110的尺寸，以及第二过孔GK2的尺寸也不能超过交叠区域所在的第二连接部BL2的尺寸。这样可以使第一连接线110与第二连接部BL2通过第二过孔GK2尽可能的接触，以提高电连接的可靠性。
在一些示例中，在具体实施时，如图6至图8a所示，第二连接部BL2覆盖第二过孔GK2的区域在第一方向F1上的宽度W21大于第一连接线110在第一方向F1上的宽度。这样可以使第二连接部BL2覆盖第二过孔GK2的区 域不仅比第二过孔GK2所在的区域大，还可以比第一连接线110覆盖第二过孔GK2的区域大，从而可以使第二连接部BL2尽可能通过第二过孔与第一连接线接触，以提高电连接的可靠性。
在一些示例中，在具体实施时，如图7与图8b所示，可以使第一连接线110在第二方向F2上的长度大于第一桥接部QB1在第二方向F2上的长度。这样可以使第一过孔GK1和第二过孔GK2可以位于第一桥接部QB1的两侧，并且第一过孔GK1与第二过孔GK2与第一桥接部QB1不交叠，降低第一桥接部QB1通过第一过孔GK1和第二过孔GK2与第一连接线110短接的可能性。
在一些示例中，在具体实施时，如7所示，第一桥接部QB1为面状结构，且第一桥接部QB1延伸至第一连接部BL1的一侧与第一连接部BL1之间具有第一间隙。第一间隙的宽度X1的范围可以为20微米～50微米。示例性地，第一间隙的宽度X1可以为20微米。第一间隙的宽度X1也可以为30微米。第一间隙的宽度X1也可以为40微米。第一间隙的宽度X1也可以为50微米。当然，在实际应用中，第一间隙的宽度X1的具体数值，可以根据实际应用环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，如7所示，第一桥接部QB1为面状结构，且第一桥接部QB1延伸至第二连接部BL2的一侧与第二连接部BL2之间具有第二间隙。第二间隙的宽度X2的范围可以为20微米～50微米。示例性地，第二间隙的宽度X2可以为20微米。第二间隙的宽度X2也可以为30微米。第二间隙的宽度X2也可以为40微米。第二间隙的宽度X2也可以为50微米。当然，在实际应用中，第二间隙的宽度X2的具体数值，可以根据实际应用环境来设计确定，在此不作限定。
在一些示例中，在具体实施时，可以使第一间隙的宽度X1和第二间隙的宽度X2大致相等。
在一些示例中，在具体实施时，在垂直于衬底基板10所在平面的方向上，可以使第一桥接部QB1的厚度等于第二导电层中其他结构的厚度。例如，第 一桥接部QB1的厚度等于第一连接部和第二连接部的厚度。示例性地，可以使第一桥接部QB1的厚度等于第一连接部BL1的厚度和第二连接部BL2的厚度。这样在制备第二导电层时，可以在衬底基板10上涂覆整面设置的Cu膜层，之后通过构图工艺对Cu膜层进行图形化，可以同时形成第一桥接部QB1、第一连接部BL1、第二连接部BL2、级联走线240以及第二导电层中其他结构的图形。
在一些示例中，在具体实施时，在垂直于衬底基板10所在平面的方向上，也可以使第一桥接部QB1的厚度大于第二导电层中其他结构的厚度。通过增加第一桥接部QB1的厚度，可以降低第一桥接部QB1的电阻。例如，第一桥接部QB1的厚度大于第一连接部和第二连接部的厚度。示例性地，在制备第二导电层时可以在衬底基板10上涂覆整面设置的Cu膜层，之后通过构图工艺对Cu膜层进行图形化，可以同时形成第一桥接部QB1的第一个膜层、第一连接部BL1、第二连接部BL2、级联走线240以及第二导电层中其他结构的图形，之后采用构图工艺在第一桥接部QB1的第一个膜层上再设置一个或多个膜层，以使这些膜层形成第一桥接部QB1。或者，也可以在衬底基板10上涂覆整面设置的Cu膜层，之后通过构图工艺对才灰度掩膜版，Cu膜层进行图形化，可以同时形成第一桥接部QB1、第一连接部BL1、第二连接部BL2、级联走线240以及第二导电层中其他结构的图形，并使第一桥接部QB1的厚度大于第二导电层中其余结构的厚度。
在一些示例中，在具体实施时，同一发光单元PX中，至少两个发光元件QD1通过第一连接线110电连接。示例性地，一个发光元件QD1通过第一连接部BL1与另一个发光元件QD1电连接。例如，第一连接部BL1与一个发光元件QD1的负极电连接，并且第一连接部BL1与第一连接线110的第一端电连接。第二连接部BL2与另一个发光元件QD1的正极电连接，并且第二连接部BL2与第一连接线110的第二端电连接。这样可以使一个发光元件QD1通过第一连接部BL1与另一个发光元件QD1串联设置。
在一些示例中，在具体实施时，如图3所示，发光单元PX中的多个发光 元件QD1可以分为M个元件组，每个元件组包括沿第一方向F1排列的N个发光元件QD1；M个元件组沿第二方向F2排列。其中，N为大于0的整数，M为大于0的整数。示例性地，以发光单元PX包括9个发光元件QD1为例，可以使M＝3，N＝3。也就是说，将这9个发光元件QD1分为3个元件组Z-1、Z-2以及Z-3。元件组Z-1、Z-2以及Z-3沿第二方向F2排列。并且，元件组Z-1中具有沿第一方向F1排列的3个发光元件QD1，元件组Z-2中也具有沿第一方向F1排列的3个发光元件QD1，元件组Z-3中也具有沿第一方向F1排列的3个发光元件QD1。
在一些示例中，在具体实施时，如图3与图6、图7所示，同一发光单元PX中，至少两个元件组通过第一连接线110电连接。示例性地，沿驱动电压端指向输出端的顺序，将多个元件组依次编号；编号为1的元件组中的第1个发光元件QD1与驱动电压端电连接；编号为k的元件组中的第1个发光元件QD1与编号为k+1的元件组中的第1个发光元件QD1通过第一连接线110电连接；编号为M的元件组中的最后第1个发光元件QD1与输出端电连接；1<k<M且k为整数。例如，以发光单元PX包括9个发光元件QD1为例，可以使M＝3，N＝3，k＝2。编号为1的元件组为Z-1，编号为2的元件组为Z-2，编号为3的元件组为Z-3，编号为1的元件组中的第1个发光元件QD1与驱动电压端电连接，编号为1的元件组中的最后1个发光元件QD1与编号为2的元件组Z-2中的最后1个发光元件QD1电连接。编号为2的元件组Z-2中的第1个发光元件QD1与编号为3的元件组Z-3中的第1个发光元件QD1通过第一连接线110电连接。编号为3的元件组Z-3中的最后第1个发光元件QD1与输出端电连接。
在一些示例中，在具体实施时，如图3与图6所示，第二导电层还可以包括间隔设置的多条串联走线250；同一元件组中的发光元件QD1通过串联走线250串联电连接。示例性地，发光元件QD1与焊盘电连接，焊盘与串联走线250电连接，以使同一元件组中的发光元件QD1通过焊盘和串联走线250进行电连接。
在一些示例中，在具体实施时，如图3与图6所示，编号为k-1的元件组中的最后1个发光元件QD1与编号为k的元件组中的最后1个发光元件QD1通过第一连接线110电连接。示例性地，以发光单元PX包括9个发光元件QD1为例，可以使M＝3，N＝3，k＝2。编号为1的元件组Z-1中，第1个发光元件QD1与第2个发光元件QD1通过一条串联走线250串联电连接，第2个发光元件QD1与第3个发光元件QD1通过一条串联走线250串联电连接。编号为2的元件组Z-2中，第1个发光元件QD1与第2个发光元件QD1通过一条串联走线250串联电连接，第2个发光元件QD1与第3个发光元件QD1通过一条串联走线250串联电连接。编号为3的元件组Z-3中，第1个发光元件QD1与第2个发光元件QD1通过一条串联走线250串联电连接，第2个发光元件QD1与第3个发光元件QD1通过一条串联走线250串联电连接。编号为1的元件组Z-1中的最后1个发光元件QD1与编号为2的元件组Z-2中的最后1个发光元件QD1通过一条串联走线250电连接。
在一些示例中，在具体实施时，如图6所示，公共电压线210在衬底基板10的正投影与串联走线250在衬底基板10的正投影不交叠。这样可以避免公共电压线210和串联走线250之间形成正对电场。
在一些示例中，在具体实施时，如图3与图6所示，针对一列发光单元PX对应：公共电压线210、源电压线230以及驱动电压线220，编号为1的元件组Z-1和编号为2的元件组Z-2之间设置一条驱动电压线220，编号为2的元件组Z-2和编号为3的元件组Z-3之间设置一条公共电压线210，编号为3的元件组Z-3与相邻的发光单元PX中编号为1的元件组Z-1之间设置一条源电压线230。
在具体实施时，在本公开实施例中，如图6与图7所示，焊盘在衬底基板的正投影与公共电压线210在衬底基板的正投影不交叠。
在一些示例中，在具体实施时，如图3与图6所示，公共电压线210的两侧分别具有避让区域，位于公共电压线210的两侧的焊盘位于该避让区域内。例如，编号为2的元件组Z-2中的发光元件QD1电连接的焊盘位于公共 电压线210面向驱动电压线220的一侧的避让区域中，编号为3的元件组Z-3中的发光元件QD1电连接的焊盘位于公共电压线210背离驱动电压线220的一侧的避让区域中。也就是说，公共电压线210在衬底基板的正投影与编号为2的元件组Z-2中的发光元件QD1电连接的焊盘和编号为3的元件组Z-3中的发光元件QD1电连接的焊盘在衬底基板的正投影不交叠。
在一些示例中，在具体实施时，如图9所示，扇出区FO也可以包括多个发光单元PX，提高发光面积。需要说明的是，发光单元PX中的公共电压端与第一扇出线电连接，并且，扇出区FO中发光单元PX的实施方式可以与显示区中发光单元PX的实施方式基本相同，即扇出区FO中发光单元PX的具体实施方式可以参见上述显示区中发光单元PX的实施方式，具体在此不作赘述。
在一些示例中，在具体实施时，如图9所示，第一导电层还可以包括间隔设置的多条第一扇出线和多条第二连接线112，多条第一扇出线和多条第二连接线112位于扇出区FO。其中，一条公共电压线210与一条第一扇出线电连接。并且，至少一条第一扇出线包括第一子扇出线511和第二子扇出线512。第一子扇出线511沿第一方向F1延伸，第二子扇出线512沿第二方向F2延伸。并且，第一子扇出线511和第二子扇出线512相互电连接形成了一条第一扇出线。也就是说，第一扇出线具有呈直角的部分。
在一些示例中，在具体实施时，如图9所示，第二导电层还可以包括相互间隔设置的多个第二桥接部QB2。并且，多个第二桥接部QB2位于扇出区FO。第一子扇出线511包括多个间隔设置的第一扇出线段。同一第一子扇出线511中，相邻两个第一扇出线段通过第二桥接部QB2电连接。例如，第一扇出线段511-1、511-2通过第二桥接部QB2电连接。并且，同一第一子扇出线511中，相邻两个第一扇出线段之间的间隙处设置有至少一条第二连接线112。以及，第一子扇出线511中相邻两个第一扇出线段的间隙处，第二桥接部QB2在衬底基板10的正投影与第二连接线112在衬底基板10的正投影交叠。示例性地，至少一个发光单元PX中，至少两个发光元件QD1通过第二 连接线112电连接。
需要说明的是，第一子扇出线511与公共电压线210均是沿第一方向F1延伸，第二连接线112和第二桥接部QB2的实施原理与第一连接线110和第一桥接部QB1的实施原理基本相同。因此，第二连接线112和第二桥接部QB2的实施方式可以与第一连接线110和第一桥接部QB1的实施方式基本相同，即第二连接线112和第二桥接部QB2的具体实施方式可以参见上述第一连接线110和第一桥接部QB1的实施方式，具体在此不作赘述。
在一些示例中，在具体实施时，如图9所示，第一导电层还可以包括多条第三连接线113。其中，至少一个发光单元PX中，至少两个发光元件QD1通过第三连接线113电连接。示例性地，同一元件组中的部分发光元件QD1通过第三连接线113串联电连接。例如，编号为1的元件组Z-1中的第2个发光元件QD1通过一条第三连接线113与第3个发光元件QD1串联电连接。编号为2的元件组Z-2中的第2个发光元件QD1通过一条第三连接线113与第3个发光元件QD1串联电连接。
在一些示例中，在具体实施时，如图9所示，第二导电层还包括位于扇出区FO的多个第三桥接部QB3。第二子扇出线512包括多个间隔设置的第二扇出线段。同一第二子扇出线512中，相邻两个第二扇出线段通过第三桥接部QB3电连接，并且，同一第二子扇出线512中，相邻两个第二扇出线段之间的间隙处设置有至少一条第三连接线113。以及第二子扇出线512中相邻两个第二扇出线段的间隙处，第三桥接部QB3在衬底基板10的正投影与第三连接线113在衬底基板10的正投影交叠。
需要说明的是，第二子扇出线512与公共电压线210垂直设置，因此，可以将第一连接线110和第一桥接部QB1旋转90度后的实施原理与第三连接线113和第三桥接部QB3的实施原理基本相同。因此，第三连接线113和第三桥接部QB3的实施方式可以是将第一连接线110和第一桥接部QB1旋转90度后进行实施的，即第三连接线113和第三桥接部QB3的具体实施方式也可以参见上述第一连接线110和第一桥接部QB1的实施方式，具体在此不作 赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述发光基板。该显示装置解决问题的原理与前述发光基板相似，因此该显示装置的实施可以参见前述发光基板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种发光基板，包括：
    衬底基板；
    第一导电层，位于所述衬底基板上；其中，所述第一导电层包括相互间隔设置的多条公共电压线和多条第一连接线；所述多条公共电压线沿第一方向延伸且沿第二方向排列；
    第一绝缘层，位于所述第一导电层背离所述衬底基板一侧；
    第二导电层，位于所述第一绝缘层背离所述衬底基板一侧；其中，所述第二导电层包括相互间隔设置的多个第一桥接部；
    其中，所述多条公共电压线中的至少一条包括多个间隔设置的信号线段；同一所述公共电压线中，相邻两个信号线段通过所述第一桥接部电连接且相邻两个所述信号线段之间的线段间隙处设置有至少一条所述第一连接线；
    所述公共电压线中相邻两个信号线段的线段间隙处，所述第一桥接部在所述衬底基板的正投影与所述第一连接线在所述衬底基板的正投影交叠。
  2. 如权利要求1所述的发光基板，其中，在所述衬底基板的正投影交叠的所述第一桥接部与第一连接线之间具有电场，且所述电场的方向为由所述第一导电层指向所述第二导电层。
  3. 如权利要求1所述的发光基板，其中，所述第二导电层还包括相互间隔设置的第一连接部和第二连接部；
    所述第一连接线的第一端通过第一过孔与所述第一连接部电连接，所述第一连接线的第二端通过第二过孔与所述第二连接部电连接；其中，所述第一过孔和所述第二过孔贯穿所述第一绝缘层。
  4. 如权利要求3所述的发光基板，其中，所述第一连接线在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影，且所述第一连接部在所述衬底基板的正投影覆盖所述第一过孔在所述衬底基板的正投影；
    所述第一连接线在所述衬底基板的正投影覆盖所述第二过孔在所述衬底 基板的正投影，且所述第二连接部在所述衬底基板的正投影覆盖所述第二过孔在所述衬底基板的正投影。
  5. 如权利要求4所述的发光基板，其中，所述第一连接部覆盖所述第一过孔的区域在所述第一方向上的宽度大于所述第一连接线在所述第一方向上的宽度；
    所述第二连接部覆盖所述第二过孔的区域在所述第一方向上的宽度大于所述第一连接线在所述第一方向上的宽度。
  6. 如权利要求5所述的发光基板，其中，所述第一桥接部在所述第一方向上的宽度的范围为100微米～250微米，所述第一连接线在所述第一方向上的宽度的范围为0.6微米～2.5微米。
  7. 如权利要求3所述的发光基板，其中，所述第一连接线在所述第二方向上的长度大于所述第一桥接部在所述第二方向上的长度。
  8. 如权利要求7所述的发光基板，其中，所述第一桥接部延伸至所述第一连接部的一侧与所述第一连接部之间具有第一间隙，所述第一桥接部延伸至所述第二连接部的一侧与所述第二连接部之间具有第二间隙；
    所述第一间隙的宽度和所述第二间隙的宽度中的至少一个的范围为20微米～50微米。
  9. 如权利要求3所述的发光基板，其中，所述第一连接线和所述信号线段之间的间隙在所述第一方向上的宽度的范围为20微米～50微米。
  10. 如权利要求1-9任一项所述的发光基板，其中，在垂直于所述衬底基板所在平面的方向上，所述第一桥接部的厚度大于或等于所述第二导电层中第一连接部和第二连接部的厚度。
  11. 如权利要求1-9任一项所述的发光基板，其中，所述第二导电层还包括多个焊盘；
    所述第一连接部的一端与一个所述焊盘电连接，另一端与所述第一连接线的第一端电连接；
    所述第二连接部的另一端与另一个所述焊盘电连接，另一端与所述第一 连接线的第二端电连接。
  12. 如权利要求1-9任一项所述的发光基板，其中，所述多条公共电压线位于显示区；所述显示区还包括多个发光单元，所述发光单元包括驱动电路与多个发光元件；其中，所述驱动电路包括公共电压端和输出端；所述多个发光元件依次串联于驱动电压端和所述输出端之间；所述公共电压端与所述公共电压线电连接；所述焊盘与所述发光元件和所述驱动电路中的至少一个电连接；
    所述发光单元中的多个发光元件分为M个元件组，每个元件组包括沿所述第一方向排列的N个发光元件；所述M个元件组沿所述第二方向排列；N为大于0的整数，M为大于0的整数；
    沿所述驱动电压端指向所述输出端的顺序，将所述多个元件组依次编号；
    编号为1的元件组中的第1个发光元件与所述驱动电压端电连接；
    编号为k的元件组中的第1个发光元件与编号为k+1的元件组中的第1个发光元件通过所述第一连接线电连接；其中，1<k<M且k为整数；
    编号为M的元件组中的最后第1个发光元件与所述输出端电连接；
    一列发光单元对应一条所述公共电压线，且所述公共电压线位于对应所述列发光单元中编号为k的元件组和编号为k+1的元件组之间。
  13. 如权利要求12所述的发光基板，其中，所述第二导电层还包括间隔设置的多条串联走线；同一所述元件组中的发光元件通过串联走线串联电连接，且编号为k-1的元件组中的最后1个发光元件与编号为k的元件组中的最后1个发光元件通过所述串联走线电连接；
    所述公共电压线在所述衬底基板的正投影与所述串联走线在所述衬底基板的正投影不交叠。
  14. 如权利要求1-9任一项所述的发光基板，其中，所述发光基板还包括扇出区；
    所述第一导电层还包括位于所述扇出区的多条第一扇出线和多条第二连接线；其中，一条所述公共电压线与一条所述第一扇出线电连接；所述第一 扇出线包括第一子扇出线和第二子扇出线；所述第一子扇出线沿所述第一方向延伸，所述第二子扇出线沿所述第二方向延伸；
    所述第二导电层还包括位于所述扇出区的多个第二桥接部；
    所述第一子扇出线包括多个间隔设置的第一扇出线段；同一所述第一子扇出线中，相邻两个第一扇出线段通过所述第二桥接部电连接且相邻两个所述第一扇出线段之间的间隙处设置有至少一条所述第二连接线；
    所述第一子扇出线中相邻两个第一扇出线段的间隙处，所述第二桥接部在所述衬底基板的正投影与所述第二连接线在所述衬底基板的正投影交叠。
  15. 如权利要求14所述的发光基板，其中，所述第一导电层还包括多条第三连接线；
    所述第二导电层还包括位于所述扇出区的多个第三桥接部；
    所述第二子扇出线包括多个间隔设置的第二扇出线段；同一所述第二子扇出线中，相邻两个第二扇出线段通过所述第三桥接部电连接且相邻两个所述第二扇出线段之间的间隙处设置有至少一条所述第三连接线；
    所述第二子扇出线中相邻两个第二扇出线段的间隙处，所述第三桥接部在所述衬底基板的正投影与所述第三连接线在所述衬底基板的正投影交叠。
  16. 如权利要求15所述的发光基板，其中，所述扇出区包括多个发光单元，所述发光单元包括驱动电路与多个发光元件；其中，所述驱动电路包括公共电压端和输出端；所述多个发光元件依次串联于驱动电压端和所述输出端之间；
    所述公共电压端与所述第一扇出线电连接；
    至少一个所述发光单元中，至少两个所述发光元件通过所述第二连接线电连接；和/或，至少两个所述发光元件通过所述第三连接线电连接。
  17. 一种显示装置，包括如权利要求1-16任一项所述的发光基板。
PCT/CN2021/115479 2021-08-30 2021-08-30 发光基板及显示装置 WO2023028794A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21955373.2A EP4294156A4 (en) 2021-08-30 2021-08-30 LIGHT-EMITTING SUBSTRATE AND DISPLAY DEVICE
CN202180002351.4A CN116075879A (zh) 2021-08-30 2021-08-30 发光基板及显示装置
PCT/CN2021/115479 WO2023028794A1 (zh) 2021-08-30 2021-08-30 发光基板及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/115479 WO2023028794A1 (zh) 2021-08-30 2021-08-30 发光基板及显示装置

Publications (1)

Publication Number Publication Date
WO2023028794A1 true WO2023028794A1 (zh) 2023-03-09

Family

ID=85411788

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/115479 WO2023028794A1 (zh) 2021-08-30 2021-08-30 发光基板及显示装置

Country Status (3)

Country Link
EP (1) EP4294156A4 (zh)
CN (1) CN116075879A (zh)
WO (1) WO2023028794A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012003088A (ja) * 2010-06-17 2012-01-05 Hitachi Displays Ltd エレクトロルミネセンス表示装置
CN111965908A (zh) * 2020-08-27 2020-11-20 京东方科技集团股份有限公司 一种阵列基板和显示装置
US20210020725A1 (en) * 2019-07-16 2021-01-21 Samsung Display Co., Ltd. Display device
US20210193952A1 (en) * 2019-12-19 2021-06-24 Lg Display Co., Ltd. Light Emitting Display Panel and Light Emitting Display Apparatus Including the Same
DE102020135114A1 (de) * 2019-12-31 2021-07-01 Lg Display Co., Ltd. Lichtemissionsvorrichtung und damit versehene Mehrbildschirmanzeigevorrichtung
CN113096573A (zh) * 2021-03-19 2021-07-09 上海中航光电子有限公司 显示面板和显示装置
CN113160716A (zh) * 2021-02-26 2021-07-23 上海天马微电子有限公司 发光组件及显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108897454B (zh) * 2018-06-29 2021-07-23 武汉天马微电子有限公司 触控面板及其制作方法、集成触控的显示面板、显示装置
CN109343735B (zh) * 2018-09-18 2022-08-09 京东方科技集团股份有限公司 一种触控显示基板及其制备方法、触控显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012003088A (ja) * 2010-06-17 2012-01-05 Hitachi Displays Ltd エレクトロルミネセンス表示装置
US20210020725A1 (en) * 2019-07-16 2021-01-21 Samsung Display Co., Ltd. Display device
US20210193952A1 (en) * 2019-12-19 2021-06-24 Lg Display Co., Ltd. Light Emitting Display Panel and Light Emitting Display Apparatus Including the Same
DE102020135114A1 (de) * 2019-12-31 2021-07-01 Lg Display Co., Ltd. Lichtemissionsvorrichtung und damit versehene Mehrbildschirmanzeigevorrichtung
CN111965908A (zh) * 2020-08-27 2020-11-20 京东方科技集团股份有限公司 一种阵列基板和显示装置
CN113160716A (zh) * 2021-02-26 2021-07-23 上海天马微电子有限公司 发光组件及显示装置
CN113096573A (zh) * 2021-03-19 2021-07-09 上海中航光电子有限公司 显示面板和显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4294156A4 *

Also Published As

Publication number Publication date
EP4294156A4 (en) 2024-05-01
EP4294156A1 (en) 2023-12-20
CN116075879A (zh) 2023-05-05

Similar Documents

Publication Publication Date Title
CN111261057B (zh) 显示面板以及显示装置
US20230052091A1 (en) Array substrate, display panel and display module
TWI751857B (zh) 發光基板及顯示裝置
WO2021174473A1 (zh) 发光基板及其驱动方法、发光模组、显示装置
US11569334B2 (en) Display substrate including first reference voltage line being electrically coupled to first reference voltage auxiliary line through via holes penetrating through insulation layer therebetween, and display device having the same
US11881184B2 (en) Light emitting substrate, method of driving light emitting substrate, and display device
WO2023028794A1 (zh) 发光基板及显示装置
WO2022104752A1 (zh) 发光基板及显示装置
WO2023028793A1 (zh) 发光基板及显示装置
WO2022110238A1 (zh) 发光基板及显示装置
CN114556205A (zh) 显示基板和显示装置
WO2021003716A1 (zh) 显示基板及其制造方法、显示面板、显示装置
TWM546017U (zh) 一種可撓的發光二極體顯示器
WO2021147000A1 (zh) 发光基板及显示装置
TW201739043A (zh) 一種可撓的發光二極體顯示器
WO2023087155A1 (zh) 驱动器电路及其驱动方法、阵列基板、显示装置
WO2022266795A1 (zh) 驱动背板及其制作方法、显示装置
WO2023004798A1 (zh) 发光基板及其制造方法、背光源、显示装置
CN114333693B (zh) 阵列基板、显示面板及显示装置
CN116246564A (zh) 一种显示面板及显示装置
JPS60229091A (ja) 液晶表示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 18550153

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 21 955 373.2

Country of ref document: EP

Ref document number: 2021955373

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021955373

Country of ref document: EP

Effective date: 20230915

NENP Non-entry into the national phase

Ref country code: DE