WO2023028793A1 - 发光基板及显示装置 - Google Patents

发光基板及显示装置 Download PDF

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Publication number
WO2023028793A1
WO2023028793A1 PCT/CN2021/115478 CN2021115478W WO2023028793A1 WO 2023028793 A1 WO2023028793 A1 WO 2023028793A1 CN 2021115478 W CN2021115478 W CN 2021115478W WO 2023028793 A1 WO2023028793 A1 WO 2023028793A1
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WIPO (PCT)
Prior art keywords
light
emitting
electrically connected
voltage line
conductive layer
Prior art date
Application number
PCT/CN2021/115478
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English (en)
French (fr)
Inventor
李振涛
郭总杰
张志�
王杰
王鹏华
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21955372.4A priority Critical patent/EP4276908A4/en
Priority to PCT/CN2021/115478 priority patent/WO2023028793A1/zh
Priority to CN202180002347.8A priority patent/CN116075947A/zh
Publication of WO2023028793A1 publication Critical patent/WO2023028793A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, in particular to a light-emitting substrate and a display device.
  • the first conductive layer is located on the base substrate; wherein the first conductive layer includes a plurality of driving voltage lines arranged at intervals;
  • a plurality of light-emitting units located on the side of the first conductive layer away from the base substrate; wherein each of the light-emitting units includes a plurality of light-emitting elements; the plurality of light-emitting elements are divided into a plurality of element groups;
  • At least two element groups are electrically connected to different driving voltage lines.
  • one light-emitting unit is connected to two driving voltage lines, and the orthographic projection of one of the two driving voltage lines on the base substrate is the same as that of the light-emitting unit on the base substrate.
  • the orthographic projection of the other driving voltage line overlaps with the orthographic projection of the other driving voltage line on the base substrate and the orthographic projection of the light emitting unit on the base substrate.
  • the light-emitting substrate also includes:
  • a first insulating layer located between the first conductive layer and the plurality of light emitting units
  • a second conductive layer located between the first insulating layer and the plurality of light emitting units
  • a second insulating layer located between the second conductive layer and the plurality of light emitting units
  • the second conductive layer includes: a plurality of element traces arranged at intervals;
  • each element group two adjacent light-emitting elements are electrically connected through element wiring.
  • the first conductive layer further includes a plurality of common voltage lines and a plurality of source voltage lines arranged at intervals;
  • the plurality of driving voltage lines, the plurality of common voltage lines, and the plurality of source voltage lines extend along a first direction, and, according to the driving voltage lines, the common voltage lines, and the source voltage lines The order is repeated along the second direction;
  • the first hollow gap, the second hollow gap and the third hollow gap are respectively provided with an element group in a row of light-emitting units and element wiring connected between adjacent light-emitting elements in the element group.
  • different element groups of the same light emitting unit are arranged on both sides of the common voltage line; and the element groups on both sides of the common voltage line are electrically connected to different driving voltage lines.
  • different element groups are arranged in parallel through the first connection part
  • the parallel connection is the lowest voltage.
  • the voltage on the first connection part is less than or equal to the voltage of the common voltage line.
  • the voltage on the common voltage line is a ground voltage.
  • the voltage on the first connection part is less than or equal to the voltage of the driving voltage line.
  • the number of light emitting units electrically connected to the second driving voltage line to the N-1 driving voltage line is the same; wherein, N is the total number of driving voltage lines in the light emitting substrate.
  • the number of element groups electrically connected to the 2nd driving voltage line to the N ⁇ 1 th driving voltage line is the same.
  • the number of light emitting elements electrically connected to the second driving voltage line to the N ⁇ 1 driving voltage line is the same.
  • one column of the light emitting units corresponds to one of the driving voltage lines, one of the common voltage lines and one of the source voltage lines; and, in the second direction, the last of the source voltage lines deviates from the A driving voltage line is arranged on one side of the common voltage line;
  • the second conductive layer includes: a plurality of jumpers; wherein, the component group located at the second hollow gap is electrically connected to the driving voltage line on the side of the source voltage line away from the common voltage line through the jumper lines .
  • the second conductive layer further includes a plurality of connection pads; one electrode of the light emitting element is electrically connected to one connection pad;
  • the orthographic projection of the jumper on the substrate does not overlap with the orthographic projection of the connection pad on the substrate.
  • the second conductive layer further includes: a plurality of second connecting parts; wherein, in the same light-emitting unit, the element groups located on the side of the common voltage line facing the driving voltage line respectively pass through the first The second connecting part is electrically connected to the same driving voltage line;
  • the portion of the jumper wire close to the electrically connected driving voltage line includes a first avoidance portion and a second avoidance portion; wherein, the first avoidance portion extends along a first direction, and the second avoidance portion extends along a second direction Extend; the length of the second avoiding portion ranges from 3.0 mm to 3.1 mm;
  • first avoidance gap between the side of the second connecting portion that is electrically connected to the driving voltage line facing the second avoiding portion and the side of the second avoiding portion facing away from the second connecting portion;
  • the width of the first avoidance gap ranges from 0.9 mm to 1.0 mm.
  • the orthographic projection of the jumper on the substrate does not overlap with the orthographic projection of the common voltage line on the substrate.
  • each of the light emitting units further includes a driving circuit;
  • the driving circuit includes a common voltage terminal and an output terminal;
  • the common voltage terminal is electrically connected to the common voltage line
  • the last light emitting element in different element groups is electrically connected to the output end.
  • the plurality of light emitting elements in the light emitting unit are divided into M element groups, each element group includes N light emitting elements arranged along a first direction; the M element groups are arranged along a second direction; N is an integer greater than 0, and M is an integer greater than 0;
  • the first light-emitting element is electrically connected to the driving voltage line corresponding to the light-emitting unit numbered a; the first light-emitting element in the element group numbered M in the light-emitting unit numbered a is connected to the light-emitting unit numbered a+1 The corresponding driving voltage line is electrically connected;
  • the last light-emitting element in the element group numbered k is electrically connected to the last light-emitting element in the element group numbered k+1 through the first connection part; the light-emitting element numbered a
  • the last light-emitting element in the element group numbered M in the unit is electrically connected to the output terminal of the drive circuit;
  • a is an integer greater than 0, 1 ⁇ k ⁇ M and k is an integer.
  • the cascade wiring is located on the first conductive layer; the first conductive layer further includes a cascade connection line;
  • the second conductive layer also includes a cascade bridge
  • the first end of the cascaded wiring is electrically connected to the last light-emitting element in the element group numbered M in the light-emitting unit numbered a, and the second end of the cascaded wiring is connected to the light-emitting element numbered a
  • the first input end of the driving circuit in the light emitting unit of +1 is electrically connected;
  • the output end of the drive circuit in the light emitting unit numbered a is electrically connected to the first end of the cascade connection line through the first cascade via hole, and the second end of the cascade connection line is connected through the second cascade connection line.
  • the hole is electrically connected to the first end of the cascade bridge portion, and the second end of the cascade bridge portion is electrically connected to the first end of the cascade wiring through the third cascade via hole.
  • the cascaded wiring is located on the second conductive layer; the first end of the cascaded wiring is electrically connected to the output end of the driving circuit in the light emitting unit numbered a, and the cascaded wiring The second end of the line is electrically connected to the first input end of the drive circuit in the light emitting unit numbered a+1;
  • the first conductive layer also includes a jumper bridging portion; the jumper includes a first jumper and a second jumper; wherein,
  • the first light-emitting element in the element group numbered M in the light-emitting unit numbered a is electrically connected to the first end of the first jumper wire, and the second end of the first jumper wire passes through the first jumper wire
  • the via hole is electrically connected to the first end of the jumper bridge part, and the second end of the jumper bridge part is electrically connected to the first end of the second jumper wire through the second jumper via hole.
  • the second end of the two jumper wires is electrically connected to the driving voltage line corresponding to the light emitting unit numbered a+1.
  • the first connection part is located on the second conductive layer.
  • the first connecting portion for electrically connecting the element groups disposed on both sides of the common voltage line is located on the first conductive layer;
  • the common voltage line is divided into a plurality of second line segments, and the second conductive layer further includes a second line segment bridging portion; wherein, the gap between adjacent second line segments in the same common voltage line is provided with the first connecting portion; and, in the same common voltage line, adjacent second line segments are electrically connected through the second line segment bridging portion.
  • the common voltage line has an avoidance area
  • the orthographic projection of the connection pads on the base substrate to which the light-emitting elements on both sides of the common voltage line are electrically connected is located within the orthographic projection of the avoidance area on the base substrate.
  • a display device provided by an embodiment of the present disclosure includes the above-mentioned light-emitting substrate.
  • Figure 1a is a schematic structural view of a light-emitting substrate in the related art
  • FIG. 1b is a schematic diagram of a partial layout of a light-emitting substrate in the related art
  • FIG. 2 is a schematic structural view of a light-emitting substrate in an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a partial specific structure of a light-emitting substrate in an embodiment of the present disclosure
  • FIG. 4 is a waveform diagram of a second input signal in a driving circuit provided by an embodiment of the present disclosure
  • FIG. 5 is a signal timing diagram of a driving circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic layout diagram of some partial layouts of the light-emitting substrate in an embodiment of the present disclosure
  • Figure 7a is a schematic diagram of the enlarged layout of the FB1 area in Figure 6;
  • Figure 7b is a schematic diagram of the enlarged layout of the FB2 area in Figure 6;
  • FIG. 8 is a schematic diagram of some partial layouts of the light-emitting substrate in an embodiment of the present disclosure.
  • Figure 9a is a schematic diagram of the enlarged layout of the FB3 area in Figure 8.
  • Figure 9b is a schematic diagram of the enlarged layout of the FB4 area in Figure 8.
  • FIG. 10 is a schematic diagram of some other partial layouts of the light-emitting substrate in the embodiment of the present disclosure.
  • a first conductive layer 02 , an insulating layer 03 and a second conductive layer 04 are sequentially disposed on the substrate 01 .
  • the first conductive layer 02 has a driving voltage line 220 and a common voltage line 210 .
  • the second conductive layer 04 has metal connection lines. Taking the light emitting unit having 9 light emitting elements as an example, the 9 light emitting elements are electrically connected in series through metal connecting wires. Divide the metal connecting wires between these 9 light-emitting elements into 8 sections: A section, B section, C section, D section, E section, F section, and G section.
  • the voltage transmitted by the driving voltage line 220 is 27V
  • the voltage transmitted by the common voltage line 210 is 0V
  • the voltage transmitted by the metal connection line of section A is 24V
  • the voltage transmitted by the metal connection line of section B is 21V
  • the voltage transmitted by the metal connection line of section C is 24V.
  • the voltage transmitted by the connecting wire is 18V
  • the voltage transmitted by the metal connecting wire of D section is 15V
  • the voltage transmitted by the metal connecting wire of E section is 12V
  • the voltage transmitted by the metal connecting wire of F section is 9V
  • the metal connecting wire of G section The transmitted voltage is 6V
  • the voltage transmitted by the metal connecting wire of the H section is 3V.
  • the metal connection lines of section C overlap between the orthographic projection of the base substrate and the orthographic projection of the driving voltage line 220 on the base substrate, and the metal connection lines of section F overlap with the common voltage line 210 in the orthographic projection of the base substrate. Overlap between orthographic projections of the substrate substrate.
  • the direction of the electric field between the overlaps of the metal connection wires of section F and the common voltage line 210 is directed from the second conductive layer to the first conductive layer. Since the second conductive layer is easily exposed and easily attracts water and oxygen, and the material of the first conductive layer 02 and the second conductive layer 04 is generally low-resistance Cu material. Since the Cu material is relatively active, it is easy to cause metal corrosion under the action of an electric field. There is a potential difference between the metal connection line of section F and the common voltage line 210, forming an electrochemical corrosion anode and a protective cathode.
  • the metal connection line of section F is the positive electrode for oxidation reaction
  • the common voltage line 210 is the cathode for reduction reaction.
  • the continuous progress of electrochemical corrosion eventually leads to a contact short circuit between the metal connection line of section F and the common voltage line 210 .
  • it will affect the light-emitting stability of the light-emitting substrate.
  • At least one embodiment of the present disclosure provides a light-emitting substrate and a display device, which reduce the influence of electrochemical corrosion on the light-emitting substrate and improve light-emitting stability.
  • the light-emitting substrate provided by at least one embodiment of the present disclosure may include a base substrate.
  • the base substrate may include a display area.
  • the material of the base substrate may be selected from plastics, polyimide, silicon, ceramics, glass, quartz, etc., which is not limited in the embodiments of the present disclosure.
  • the display area may include a plurality of light emitting units PX arranged in an array.
  • a plurality of light emitting units PX are arranged in multiple rows and multiple columns.
  • the number of light-emitting units PX can be determined according to actual needs, for example, according to the size of the light-emitting substrate and the required brightness. Although only 6 rows and 5 columns of light-emitting units PX are shown in FIG. 2, it should be understood that , the number of light emitting units PX is not limited thereto.
  • the light emitting units PX may be arranged in multiple rows and multiple columns along the first direction F1 and the second direction F2 .
  • the light-emitting substrate is rectangular
  • the first direction F1 may be a direction parallel to the long side of the light-emitting substrate
  • the second direction F2 may be a direction parallel to the short side of the light-emitting substrate.
  • the first direction F1 may also be a direction parallel to the short side of the light emitting substrate
  • the second direction F2 may also be a direction parallel to the long side of the light emitting substrate.
  • first direction F1 and the second direction F2 may be any directions, as long as the first direction F1 and the second direction F2 intersect.
  • the plurality of light emitting units PX are not limited to being arranged in a straight line, and may also be arranged in a zigzag line, in a ring, or in any manner, which may be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • each light emitting unit PX may include a driving circuit QD0 and a plurality of light emitting elements QD1 .
  • the driving circuit QD0 may include a first input terminal Di, a second input terminal Pwr, an output terminal OT and a common voltage terminal GND.
  • Mini Light Emitting Diodes or Micro Light Emitting Diodes (Micro Light Emitting Diodes, Micro-LEDs) are small in size and high in brightness, and can be used in a large number of In the display device or its backlight module, the display of high-dynamic range images (High-Dynamic Range, HDR) is realized by finely adjusting the backlight.
  • the typical size (such as length) of Micro-LED is less than 100 microns, such as 10 microns to 80 microns; the typical size (such as length) of Mini-LED is 80 microns to 350 microns, such as 80 microns to 120 microns.
  • the light emitting element QD1 may be at least one of a micro light emitting diode (Micro-LED) or a miniature light emitting diode (Mini-LED).
  • the driving circuit QD0 may be configured to pass through the output terminal OT within the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr.
  • a relay signal is output, and a current path is formed through the output terminal OT and the light-emitting element QD1 connected in series during the second period.
  • the first input terminal Di receives a first input signal, such as an address signal, for gating the driving circuit QD0 corresponding to the address.
  • the addresses of different driving circuits QD0 may be the same or different.
  • the first input signal may be an 8-bit address signal, and the address to be transmitted can be obtained by analyzing the address signal.
  • the second input terminal Pwr receives a second input signal, such as a power line carrier communication signal.
  • the second input signal not only provides electric energy for the driving circuit QD0, but also transmits communication data to the driving circuit QD0.
  • the communication data can be used to control the light-emitting duration of the corresponding light-emitting unit PX, and then control its visual light-emitting brightness.
  • the output terminal OT can output different signals in different time periods, such as outputting a relay signal and a driving signal respectively.
  • the relay signal is an address signal provided to the other driving circuit QD0, that is, the first input terminal Di of the other driving circuit QD0 receives the relay signal as the first input signal, so as to obtain the address signal.
  • the driving signal can be a driving current for driving the light emitting element QD1 to emit light.
  • the common voltage terminal GND receives a common voltage signal, such as a ground signal.
  • the drive circuit QD0 is configured to output a relay signal through the output terminal OT during the first period according to the first input signal received by the first input terminal Di and the second input signal received by the second input terminal Pwr, and to output a relay signal during the second period
  • a driving signal is provided to a plurality of light-emitting elements QD1 connected in series through the output terminal OT.
  • the output terminal OT outputs a relay signal
  • the relay signal is provided to other driving circuits QD0 so that other driving circuits QD0 obtain address signals.
  • the output terminal OT outputs a driving signal, which is provided to a plurality of light-emitting elements QD1 connected in series, so that the light-emitting element QD1 emits light during the second period.
  • the first time period and the second time period are different time periods, for example, the first time period may be earlier than the second time period.
  • the first time period can be continuous with the second time period, and the end time of the first time period is the start time of the second time period; or, there can be other time periods between the first time period and the second time period, which can be used to realize For other required functions, the other time period can also be used only to separate the first time period from the second time period, so as to prevent the signals of the output terminal OT from interfering with each other during the first time period and the second time period.
  • the driving signal when the driving signal is a driving current, the driving current can flow from the output terminal OT to the light emitting element QD1, or flow from the light emitting element QD1 to the output terminal OT, and the flow direction of the driving current can be determined according to actual needs.
  • the output terminal OT outputs a driving signal means that the output terminal OT provides a driving signal, and the direction of the driving signal can either flow out of the output terminal OT or flow into the output terminal OT.
  • the relative positions of the driving circuit QD0 in the light emitting unit PX may be different, or the positions of the driving circuit QD0 in the light emitting unit PX may also be the same.
  • the relative positional relationship of the light emitting elements QD1 in each light emitting unit PX can be made the same.
  • the relative positional relationship of the light emitting elements QD1 in one light emitting unit PX may be used as a reference, and the light emitting elements QD1 may be periodically and repeatedly arranged along the first direction F1 and the second direction F2.
  • the light emitting elements QD1 located at the same position in each light emitting unit PX may be arranged substantially on the same straight line along the first direction F1.
  • the light emitting elements QD1 located at the same position in each light emitting unit PX may be arranged substantially on the same straight line along the second direction F2.
  • the driving circuit QD0 may include a demodulation circuit, a physical layer interface circuit, a data processing control circuit, a pulse width modulation circuit, a driving signal generating circuit, a relay signal generating circuit and a power supply circuit.
  • the demodulation circuit is electrically connected to the second input terminal Pwr and the physical layer interface circuit, configured to demodulate the second input signal to obtain communication data, and transmit the communication data to the physical layer interface circuit.
  • the second input signal input to the second input terminal Pwr is a power line carrier communication signal
  • the power line carrier communication signal includes information corresponding to communication data.
  • the communication data is the data reflecting the duration of light emission, and further represents the required light emission brightness.
  • SPI Serial Peripheral Interface
  • the embodiment of the present disclosure adopts the power line carrier communication (Power Line Carrier Communication, PLC) protocol to superimpose the communication data on the power signal, thereby effectively reducing the The number of signal lines.
  • PLC Power Line Carrier Communication
  • the dotted ellipse represents an enlarged view of the corresponding waveform.
  • the second input signal is at a high level, its high level amplitude fluctuates around the threshold amplitude Vth, for example, the first amplitude V1 and The second amplitude V2 varies, V2 ⁇ Vth ⁇ V1.
  • Vth threshold amplitude
  • the communication data can be modulated into the second input signal, so that the second input signal transmits information corresponding to the communication data while transmitting electric energy.
  • the demodulation circuit filters out the DC power component of the second input signal, so that the communication data can be obtained.
  • the second input signal For the detailed description of the second input signal, reference may be made to the conventional power line carrier communication signal, which will not be described in detail here.
  • the detailed description of the demodulation circuit can also refer to the conventional power line carrier communication signal demodulation circuit, which will not be described in detail here.
  • the physical layer interface circuit is also electrically connected to the data processing control circuit, configured to process the communication data to obtain a data frame (for example, frame rate data), and transmit the data frame to the data processing control circuit.
  • the data frame obtained by the physical layer interface circuit contains information that needs to be transmitted to the driving circuit QD0 , such as information related to the lighting time (eg, the specific duration of the lighting time).
  • the physical layer interface circuit may be a common port physical layer (Physical, PHY). For details, reference may be made to conventional designs, and details will not be described here.
  • the data processing control circuit is also electrically connected to the first input terminal Di, the pulse width modulation circuit and the relay signal generating circuit.
  • the data processing control circuit is configured to generate a pulse width control signal based on the data frame and transmit the pulse width control signal to the pulse width modulation circuit, and generate a relay control signal based on the first input signal and transmit the relay control signal to the Following the signal generation circuit.
  • the required light-emitting duration of the light-emitting element QD1 connected to the driving circuit QD0 can be known, so a corresponding pulse width control signal is generated based on the light-emitting duration.
  • the relay control signal is a signal generated after the data processing control circuit processes the first input signal.
  • the address signal corresponding to the driving circuit QD0 can be obtained, and a relay control signal corresponding to the subsequent address will be generated.
  • the subsequent address corresponds to Other drive circuit QD0.
  • the data processing control circuit can be implemented as a single chip microcomputer, a central processing unit (Central Processing Unit, CPU), a digital signal processor, and the like.
  • the pulse width modulation circuit is also electrically connected to the driving signal generating circuit, configured to generate a pulse width modulation signal in response to the pulse width control signal, and transmit the pulse width modulation signal to the driving signal generating circuit.
  • the pulse width modulation signal generated by the pulse width modulation circuit corresponds to the required light-emitting duration of the light-emitting element QD1 , for example, the effective pulse-width duration is equal to the required light-emitting duration of the light-emitting element QD1 .
  • the detailed description of the pulse width modulation circuit can refer to the conventional pulse width modulation circuit, which will not be described in detail here.
  • the driving signal generating circuit is further electrically connected to the output terminal OT, configured to generate a driving signal in response to the pulse width modulation signal, and output the driving signal from the output terminal OT.
  • outputting the driving signal from the output terminal OT may mean that the driving signal (such as the driving current) flows from the output terminal OT to the light-emitting element QD1, or it may mean that the driving signal (such as the driving current) flows from the light-emitting element QD1 to the output terminal OT.
  • the direction of current flow is not restricted.
  • the driving signal generating circuit may include a current source and a metal oxide semiconductor (Metal Oxide Semiconductor, MOS) field effect transistor (Field Effect Transistor, FET), the Metal-oxide-semiconductor field-effect transistors are called MOS transistors.
  • MOS Metal Oxide Semiconductor
  • FET Field Effect Transistor
  • the control electrode of the MOS transistor receives the pulse width modulation signal transmitted by the pulse width modulation circuit, and thus is turned on or off under the control of the pulse width modulation signal.
  • the first pole of the MOS transistor is connected to the output terminal OT, the second pole of the MOS transistor is connected to the first pole of the current source, and the second pole of the current source is connected to the common voltage terminal GND to receive the common voltage.
  • the current source can be a constant current source.
  • the MOS transistor When the pulse width modulation signal is at an active level, the MOS transistor is turned on, and the current source provides a driving current through the output terminal OT. When the pulse width modulation signal is at an inactive level, the MOS transistor is turned off, and the output terminal OT does not provide a driving current at this time.
  • the duration of the active level of the pulse width modulation signal is equal to the conduction duration of the MOS transistor, and the conduction duration of the MOS transistor is equal to the duration of the drive current provided by the output terminal OT. In this way, the light-emitting duration of the light-emitting element QD1 can be further controlled, and further the visual light-emitting brightness can be controlled.
  • the driving current flows into the driving circuit QD0 from the OT terminal, flows through the MOS transistor and the current source in turn, and then flows into the ground terminal (such as the common voltage terminal GND).
  • the driving signal generating circuit may also adopt other circuit structures, which are not limited in the embodiments of the present disclosure.
  • the relay signal generating circuit is further electrically connected to the output terminal OT, configured to generate a relay signal based on the relay control signal, and output the relay signal from the output terminal OT.
  • the relay control signal corresponds to a subsequent address
  • the relay signal generated based on the relay control signal includes the subsequent address
  • the subsequent address corresponds to the other driving circuit QD0.
  • the relay signal is output from the output terminal OT, it is provided to the first input terminal Di of the driving circuit QD0 provided separately, and the relay signal is input to the driving circuit QD0 provided separately as the first input signal, so that the driving circuit QD0 provided separately
  • the driving circuit QD0 obtains the corresponding address signal.
  • the relay signal generating circuit may be implemented by a latch, a decoder, an encoder, etc., which is not limited in the embodiments of the present disclosure.
  • both the driving signal generating circuit and the relay signal generating circuit are electrically connected to the output terminal OT, the driving signal generating circuit and the relay signal generating circuit respectively output driving The signal and relay signal, drive signal and relay signal are time-divisionally transmitted through the output terminal OT, so they will not affect each other.
  • the power supply circuit is electrically connected to the demodulation circuit and the data processing control circuit respectively, and is configured to receive electric energy and supply power to the data processing control circuit.
  • the second input signal is a power line carrier communication signal.
  • the DC power component that is, electric energy
  • the power supply circuit may also be electrically connected with other circuits in the driving circuit QD0 to provide electric energy.
  • the power supply circuit may be realized by a switch circuit, a voltage conversion circuit, a voltage stabilization circuit, etc., which are not limited in the embodiments of the present disclosure.
  • the drive circuit QD0 may also include more circuits and components, not limited to the above-mentioned demodulation circuit, physical layer interface circuit, data processing control circuit, pulse width modulation circuit, drive signal
  • the generation circuit, the relay signal generation circuit and the power supply circuit may be determined according to the functions to be realized, which are not limited in the embodiments of the present disclosure.
  • the driving circuit QD0 when the driving circuit QD0 is working, it is first powered on (that is, powered on) to complete the initialization, and then the address writing operation is performed in the period S1, that is, in the period S1, the first input signal Di_1 passes through the first input terminal Di is input to the driving circuit QD0, thereby writing an address.
  • the first input signal Di_1 is transmitted through an additionally provided transmitter.
  • the relay signal Di_2 is output through the output terminal OT.
  • the relay signal Di_2 is input as the first input signal to the first input terminal Di of the driving circuit QD0 provided separately.
  • the aforementioned first time period is the time period S2.
  • the driving voltage line 220 is energized.
  • the period S3 is entered after about 10 microseconds. At this time, the driving voltage supplied from the driving voltage line 220 becomes a high level.
  • the driving circuit QD0 is in the normal working mode, and the output terminal OT provides a driving signal (such as a driving current) according to the required duration, so that the light emitting element QD1 connected to the driving circuit QD0 emits light according to the required duration.
  • the aforementioned second time period is the time period S4.
  • the light-emitting substrate using the driving circuit QD0 works in a local backlight adjustment (Local Dimming) mode, which can achieve a high dynamic range effect.
  • the system is shut down, that is, the driving circuit QD0 is powered off, and the driving voltage provided by the driving voltage line 220 becomes low level, and the light emitting element QD1 stops emitting light.
  • VREG, POR, Vreg_1.8, OSC, and Re_B are all internal signals of the driving circuit QD0, and will not be input or input through the first input terminal Di, the second input terminal Pwr, the output terminal OT, and the common voltage terminal GND. output.
  • Di_1 is the first input signal received by the driving circuit QD0
  • Di_2 is the relay signal output by the driving circuit QD0 (that is, the first input signal received by the next connected driving circuit QD0)
  • Di_n is a plurality of sequentially connected The first input signal received by the nth driving circuit QD0 in the driving circuits QD0.
  • the drive circuit QD0 can be configured as a chip, the chip size (for example, length) can be tens of microns, and the chip area is about several hundred square microns or even smaller, which is similar to the size of Mini-LED and has
  • the feature of miniaturization makes it easy to integrate into the light-emitting substrate (for example, bonded to the surface of the light-emitting substrate), saves the installation space of the printed circuit board, simplifies the structure, and is conducive to realizing light and thin.
  • Each driving circuit QD0 directly drives a light-emitting unit PX, which avoids problems such as complicated operation and easy flickering of the row scanning control mode.
  • the drive circuit QD0 has a small number of ports, a small number of required signals, a simple control method, a simple wiring method, and low cost.
  • a buffer layer (Buffer) 400 is disposed on the substrate to improve the adhesion of the first conductive layer.
  • the first conductive layer is located on a side of the buffer layer 400 away from the base substrate.
  • the first conductive layer may include: a plurality of common voltage lines 210 , a plurality of driving voltage lines 220 , and a plurality of source voltage lines 230 arranged at intervals.
  • one column of light emitting units PX may correspond to one common voltage line 210 , one source voltage line 230 and one driving voltage line 220 .
  • the multiple common voltage lines 210 , the multiple driving voltage lines 220 , and the multiple source voltage lines 230 extend along the first direction F1 respectively. Moreover, the plurality of common voltage lines 210 , the plurality of driving voltage lines 220 , and the plurality of source voltage lines 230 are respectively arranged along the second direction F2 . Exemplarily, the order of the driving voltage lines 220 , the common voltage lines 210 and the source voltage lines 230 may be repeatedly arranged along the second direction F2 .
  • the orthographic projection of the common voltage line 210 on the base substrate is located on the driving voltage line 220 and the source voltage line 230 between.
  • the source voltage line 230 is electrically connected to the second input terminal Pwr of the driving circuit QD0.
  • the second input signal can be transmitted to the second input terminal Pwr of the driving circuit QD0 through the source voltage line 230 .
  • the second input terminals Pwr of the driving circuits QD0 in a column of light emitting units PX are all electrically connected to the same source voltage line 230 .
  • the common voltage line 210 is electrically connected to the common voltage terminal GND of the drive circuit QD0, so that the voltage on the common voltage line 210 is the ground voltage, so as to provide the ground voltage to the common voltage terminal of the drive circuit QD0 through the common voltage line 210 Signal.
  • the common voltage terminals GND of the driving circuits QD0 in a column of light emitting units PX are all electrically connected to the same common voltage line 210 .
  • the wiring space can be reasonably designed and signal interference can be reduced.
  • the common voltage line 210 is located on the driving voltage line 220 and source voltage line 230.
  • the width of the driving voltage line 220 in the second direction F2 is larger than the width of the source voltage line 230 in the second direction F2.
  • the width of the source voltage line 230 in the second direction F2 is greater than the width of the cascaded wiring 240 in the second direction F2.
  • the first conductive layer may use a metal material to form a single-layer structure.
  • the first conductive layer may also use metal materials to form a laminated structure.
  • two first conductive layers formed of metal materials are used, and the first conductive layer has a C-1 layer and a C-2 layer.
  • the metal material may include but not limited to Cu.
  • a first insulating layer is formed on the first conductive layer, that is, the first insulating layer is located on a side of the first conductive layer away from the base substrate.
  • the first insulating layer may form a single-layer structure using inorganic, organic or organic-inorganic composite materials.
  • the first insulating layer may also be a multilayer structure formed by using at least one of inorganic, organic or organic-inorganic composite materials. For example, multiple layers of organic materials may be used to form the first insulating layer. It is also possible to use multiple layers of inorganic materials to form the first insulating layer.
  • the first insulating layer may also be formed by stacking organic materials and inorganic materials.
  • the first insulating layer may include a first sub-insulating layer and a second sub-insulating layer.
  • the material of the second sub-insulation layer may be an organic material
  • the material of the first sub-insulation layer may be an inorganic material.
  • the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like.
  • the organic material may be polyimide (PI) or the like.
  • a second conductive layer is formed on the first insulating layer, that is, the second conductive layer is located on a side of the first insulating layer away from the substrate.
  • a second insulating layer is formed on the second conductive layer, that is, the second insulating layer is located on a side of the second conductive layer away from the base substrate.
  • the light emitting element QD1 is formed on the second insulating layer.
  • the second insulating layer may form a single layer structure using inorganic, organic or organic-inorganic composite materials.
  • the second insulating layer may also be a multilayer structure formed by using at least one of inorganic, organic or organic-inorganic composite materials.
  • the second insulating layer may be formed using multiple layers of organic materials. It is also possible to use multiple layers of inorganic materials to form the second insulating layer.
  • the second insulating layer may also be formed by stacking an organic material and an inorganic material.
  • the second insulating layer may include a third sub-insulating layer and a fourth sub-insulating layer. Wherein, the material of the fourth sub-insulation layer may be an organic material, and the material of the third sub-insulation layer may be an inorganic material.
  • the inorganic material may be selected from at least one of silicon nitride (SiNx), silicon oxide (SiOX), silicon oxynitride (SiON), and the like.
  • the organic material may be polyimide (PI) or the like.
  • the second conductive layer may include: a plurality of connection pads (such as PDs), and a plurality of cascade wires 240 arranged at intervals.
  • the multiple cascaded wires 240 extend along the first direction F1.
  • the driving circuits QD0 in the light emitting units PX in a column may be coupled to each other, and in a column, the driving circuits QD0 in adjacent light emitting units PX are coupled through the cascaded wiring 240 .
  • the first row to the sixth row are defined.
  • first to fifth columns are defined.
  • the output terminal of the driving circuit QD0 in the first row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the second row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the second row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the third row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the third row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the fourth row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the fourth row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the fifth row of light emitting units PX through a cascaded wire 240 .
  • the output terminal of the driving circuit QD0 in the fifth row of light emitting units PX is coupled to the first input terminal Di of the driving circuit QD0 in the sixth row of light emitting units PX through a cascaded wire 240 .
  • the output end of the driving circuit QD0 in the sixth row of light emitting units PX is coupled to the cascade output terminal through a cascade output wiring. In this way, the cascading wiring 240 and the driving circuit QD0 can be cascaded in the same direction, reducing signal overlapping area and signal interference.
  • one electrode of the light emitting element is electrically connected to one connection pad PD.
  • the anode of the light emitting element QD1 is electrically connected to one connection pad PD
  • the cathode of the light emitting element QD1 is electrically connected to the other connection pad PD.
  • the connection pads PD corresponding to the light emitting elements QD1 arranged in series can be electrically connected through the series wiring 250 .
  • the connection pads PD corresponding to the light emitting elements QD1 arranged in parallel can be electrically connected through the first connection part 110 . The rest can be deduced in the same way, and will not be repeated here.
  • the plurality of light emitting elements QD1 in the light emitting unit PX can be divided into multiple element groups, wherein, in the same light emitting unit PX, at least two element groups are electrically connected to different driving voltages Line 220.
  • the plurality of light emitting elements QD1 in the light emitting unit PX are divided into M element groups, each element group includes N light emitting elements QD1 arranged along the first direction F1; the M element groups are arranged along the second direction F2; N is an integer greater than 0, and M is an integer greater than 0.
  • these nine light-emitting elements QD1 can be divided into three element groups Z-1, Z-2 and Z-3.
  • the element groups Z-1, Z-2 and Z-3 are arranged along the second direction F2.
  • the element group Z-1 has three light emitting elements QD1 arranged along the first direction F1
  • the element group Z-2 also has three light emitting elements QD1 arranged along the first direction F1
  • the element group Z-3 also has three light emitting elements QD1 arranged along the first direction F1.
  • the element group Z-1 and the element group Z-2 are connected to the driving voltage line 220 on the left side of the light-emitting unit PX where they are located, and the element group Z-3 is connected to the right side of the light-emitting unit PX where they are located.
  • the driving voltage line 220 In this way, the overlapping area of the second conductive layer and the common voltage line 210 can be reduced.
  • one light emitting unit PX can be connected to two driving voltage lines 220, and one of the two driving voltage lines 220 is connected to the base substrate.
  • the orthographic projection overlaps with the orthographic projection of the light emitting unit PX on the base substrate, and the orthographic projection of the other driving voltage line 220 on the base substrate does not overlap with the orthographic projection of the light emitting unit PX on the base substrate.
  • these driving voltage lines 220 are respectively electrically connected to two adjacent columns of light emitting units PX.
  • N is the total number of driving voltage lines in the light emitting substrate. In practical applications, the value of N can be designed and determined according to requirements of practical applications, and is not limited here.
  • N driving voltage lines 220 are set on the light-emitting substrate, and the multiple driving voltage lines 220 set on the light-emitting substrate can be defined in the direction pointed by the arrow F2.
  • the number of light emitting units PX electrically connected to the second to N ⁇ 1th driving voltage lines 220 may be the same.
  • the loads of the second to N ⁇ 1 driving voltage lines 220 can be substantially the same, and the light emission stability can be further improved.
  • the design difficulty of the light emitting unit PX can also be reduced.
  • the number of element groups electrically connected to the second to N ⁇ 1 driving voltage lines 220 may be the same.
  • the loads of the second to N ⁇ 1 driving voltage lines 220 can be substantially the same, and the light emission stability can be further improved. And, it can further reduce the design difficulty of the component group.
  • the number of light emitting elements QD1 electrically connected to the second to N ⁇ 1th driving voltage lines 220 may be the same.
  • the loads of the second to N ⁇ 1 driving voltage lines 220 can be substantially the same, and the light emission stability can be further improved.
  • the design difficulty of the light emitting element QD1 can be further reduced.
  • different element groups may be arranged in parallel in the same light emitting unit PX.
  • the voltages across the element groups Z-1, Z-2 and Z-3 are all the same.
  • different element groups can be arranged in parallel through the first connection part.
  • the lowest voltage points of the element groups Z-1, Z-2 and Z-3 are arranged in parallel through the first connection part. That is to say, in the same light-emitting unit, the parallel connection is the lowest voltage.
  • the last light emitting element QD1 in different element groups may be electrically connected to the output end of the driving circuit QD0 .
  • the last light emitting element QD1 in different element groups can be arranged in parallel through the first connection part 110 . That is to say, in the same light emitting unit PX, the last light emitting element QD1 in different element groups can be electrically connected to the output terminal of the driving circuit QD0 through the first connection part 110 .
  • the last light-emitting element QD1 in element group Z-1 is electrically connected to the last light-emitting element QD1 in element group Z-2 through the first connection part 110, and the last light-emitting element QD1 in element group Z-2 is electrically connected to the last light-emitting element QD1 in element group Z-2 through the first
  • the connection part 110 is electrically connected to the last light-emitting element QD1 in the element group Z-3.
  • the last light-emitting element QD1 in the element group Z-3 is directly electrically connected to the output terminal of the driving circuit QD0.
  • the first connection part 110 may be located on the second conductive layer.
  • the voltage electrically connected to the last light-emitting element QD1 in different element groups is the lowest, so that the current flow path in each element group is connected to the drive circuit QD0.
  • the output end of the LED is electrically connected to the last light-emitting element QD1.
  • the last light-emitting element QD1 in the element group Z-1 is electrically connected to the lowest voltage.
  • the last light-emitting element QD1 in the element group Z-2 is electrically connected to the lowest voltage.
  • the last light-emitting element QD1 in the element group Z-3 is electrically connected to the lowest voltage.
  • the types of electrodes of the light emitting elements QD1 arranged in parallel in different element groups are the same.
  • the anode of the first light-emitting element QD1 in element group Z-1, the anode of the first light-emitting element QD1 in element group Z-2, and the anode of the first light-emitting element QD1 in element group Z-3 are arranged in parallel.
  • the cathode of the last light-emitting element QD1 in element group Z-1, the cathode of the last light-emitting element QD1 in element group Z-2, and the cathode of the last light-emitting element QD1 in element group Z-3 are arranged in parallel.
  • the voltage on the first connecting portion 110 may be made less than or equal to the voltage on the common voltage line 210 .
  • the voltage on the first connecting portion 110 may also be made less than or equal to the voltage on the driving voltage line 220 .
  • the light emitting elements QD1 are arranged in series.
  • the second conductive layer may further include: a plurality of element wires 250 arranged at intervals; wherein, in each element group, two adjacent light emitting elements QD1 are electrically connected through the element wires 250 .
  • each light-emitting element QD1 includes a positive electrode (+) and a negative electrode (-) (or, it can also be called an anode and a cathode). Between the voltage line 220 and the output terminal OT, a current flow path is formed between the driving voltage line 220 and the output terminal OT.
  • the anode and cathode of the light-emitting element QD1 in the element group Z-1 are connected in series end-to-end in sequence, and are connected in series between the driving voltage line 220 and the output terminal OT, that is, the light-emitting element QD1 electrically connected to the driving voltage line 220 is used as an element.
  • the starting point of the series connection of the three light-emitting elements QD1 in the group Z-1 is the light-emitting element QD1 electrically connected to the output terminal OT as the end point of the series connection of the three light-emitting elements QD1 in the group Z-1.
  • the anode and cathode of the light-emitting element QD1 in the element group Z-2 are also connected in series end to end, and connected in series between the driving voltage line 220 and the output terminal OT, that is, the light-emitting element QD1 electrically connected to the driving voltage line 220 is used as an element group
  • the starting point of the series connection of the three light emitting elements QD1 in Z-2 is the light emitting element QD1 electrically connected to the output terminal OT as the end point of the series connection of the three light emitting elements QD1 in the element group Z-2.
  • the anode and cathode of the light-emitting element QD1 in the element group Z-3 are also connected in series end to end, and connected in series between the driving voltage line 220 and the output terminal OT, that is, the light-emitting element QD1 electrically connected to the driving voltage line 220 is used as an element group
  • the starting point of the series connection of the three light emitting elements QD1 in Z-3 is the light emitting element QD1 electrically connected to the output terminal OT as the end point of the series connection of the three light emitting elements QD1 in the element group Z-3.
  • the second connecting portion 130 corresponding to the element group Z-1 and the element group Z-2 is connected to the driving voltage line 220 on the left side
  • the second connecting portion 130 corresponding to the element group Z-3 is connected to the driving voltage line 220 on the right side.
  • the driving voltage line 220 can provide a driving voltage, for example, a high voltage during a period (second period) when the light emitting element QD1 needs to emit light, and a low voltage during other periods. Therefore, in the second period, the driving signal (for example, driving current) flows from the driving voltage line 220 through the light-emitting element QD1 in each element in sequence, and then flows into the output terminal OT of the driving circuit QD0 .
  • the light-emitting element QD1 emits light when the driving current flows, and by controlling the duration of the driving current, the light-emitting time of the light-emitting element QD1 can be controlled, thereby controlling the visual brightness of the light.
  • connection mode of the light emitting elements QD1 in the element group may also be a way of first connecting part of the light emitting elements QD1 in parallel and then connecting them in series.
  • connection manner of the light emitting elements QD1 in the element group may also be a manner of connecting part of the light emitting elements QD1 in series first and then in parallel.
  • the design may be determined according to actual requirements, which is not limited here.
  • the number of light emitting elements QD1 in each light emitting unit PX is not limited, and can be any number such as 6, 8, 12, etc., and is not limited to 9.
  • the plurality of light emitting elements QD1 can be arranged in any arrangement, such as arranged in a required pattern, not limited to a matrix arrangement.
  • the setting position of the driving circuit QD0 is not limited, and can be set in any gap between the light-emitting elements QD1 , which can be determined according to actual needs, which is not limited by the embodiments of the present disclosure.
  • the first hollow gap, the second hollow gap and the third hollow gap are respectively provided with an element group in a row of light-emitting units PX and element traces 250 connected between adjacent light-emitting elements QD1 in the element group.
  • the element group Z-2 is disposed in the first hollow gap
  • the element group Z-3 is disposed in the second hollow gap
  • the element group Z-1 is disposed in the third hollow gap.
  • different element groups are arranged on both sides of the common voltage line 210; and, the element groups on both sides of the common voltage line 210 are electrically connected to different driving voltages line 220.
  • two element groups in the same light emitting unit PX are arranged on both sides of a common voltage line 210, for example, element group Z-2 is arranged on the side of the common voltage line 210 facing the driving voltage line 220, and the common voltage line The side of the 210 facing the source voltage line 230 is provided with an element group Z-3.
  • the element group Z-2 located on the side of the common voltage line 210 facing the driving voltage line 220 is electrically connected to the driving voltage line 220 located on the side of the common voltage line 210 away from the source voltage line 230, and located on the side of the common voltage line 210 facing the source voltage
  • the element group Z- 3 on one side of the line 230 is electrically connected to the driving voltage line 220 on the side of the source voltage line 230 away from the common voltage line 210 .
  • a drive voltage line 220 is provided on the side of the last source voltage line 230 away from the common voltage line 210 .
  • the second conductive layer may further include: a plurality of jumper wires 120 ; wherein, the element group located in the second hollow gap is electrically connected to the driving voltage line 220 located on the side of the source voltage line 230 away from the common voltage line 210 through the jumper wires 120 .
  • the component group located at the second hollow gap is Z-3, and the component group Z-3 is electrically connected to the driving voltage line 220 on the side of the source voltage line 230 away from the common voltage line 210 through the jumper line 120 .
  • the orthographic projection of the jumper 120 on the substrate does not overlap with the orthographic projection of the common voltage line 210 on the substrate.
  • the second conductive layer may further include: a plurality of second connecting parts 130;
  • the element groups on one side of the line 220 are electrically connected to the same driving voltage line 220 through the second connecting portion 130 .
  • the element group Z-1 is electrically connected to the driving voltage line 220 through a second connecting portion 130
  • the element group Z-2 is electrically connected to the same driving voltage line 220 through a second connecting portion 130 .
  • the material of the first conductive layer 01 and the second conductive layer 02 is generally low-resistance Cu material. Since the Cu material is relatively active, it is easy to cause metal corrosion under the action of an electric field. There is a potential difference between the first conductive layer 02 and the second conductive layer 04, forming an electrochemical corrosion anode and a protective cathode, the second conductive layer 04 is the positive electrode for oxidation reaction, and the first conductive layer 02 is the cathode for reduction reaction. The continuous progress of electrochemical corrosion eventually leads to a contact short circuit between the first conductive layer 02 and the second conductive layer 04 . However, if there is electrochemical corrosion in the light-emitting substrate, it will affect the light-emitting stability of the light-emitting substrate.
  • the voltage loaded on the driving voltage line is greater than the voltage loaded on the common voltage line
  • both the second connecting portion 130 and the jumper wire 120 are electrically connected to the driving voltage line, so that the second connecting portion 130 and the jumper wire 120 The voltages on both are greater than the voltage loaded on the common voltage line.
  • by connecting the light-emitting elements on both sides of the common voltage line to the driving voltage lines on both sides of the common voltage line it is possible to avoid the positive projection of the jumper line on the base substrate from the normal projection of the common voltage line on the base substrate.
  • the overlapping projections can prevent the jumper wires from facing the common voltage line, thereby avoiding the reduction reaction of the jumper wires as cathodes and the oxidation reaction of the common voltage wires as positive electrodes. Moreover, the jumper is protected by a second insulating layer, and the path of moisture intrusion is relatively far away. Therefore, the situation of electrochemical corrosion can be effectively reduced.
  • the thickness and number of layers of the first insulating layer can be increased.
  • the orthographic projection of the jumper on the base substrate overlaps with the orthographic projection of the common voltage line on the substrate, thereby avoiding the existence of a direct facing area between the jumper and the common voltage line, and further avoiding that the jumper Reduction reaction occurs as the cathode, and oxidation reaction occurs on the common voltage line as the positive electrode, which can effectively reduce the situation of electrochemical corrosion. Therefore, there is no need to increase the thickness and number of layers of the first insulating layer, which can save production capacity.
  • the orthographic projection of the jumper wire 120 on the base substrate does not overlap with the orthographic projection of the connection pad PD on the base substrate.
  • the portion BG of the jumper line close to the electrically connected driving voltage line may include a first avoidance portion 121 and a second avoidance portion 122; wherein, the first avoidance portion 121 extends along the first direction F1 , the second escape portion 122 extends along the second direction F2; the length H1 of the second avoidance portion 122 ranges from 3.0 mm to 3.1 mm.
  • the length H1 of the second escape portion 122 may be 3.0 mm.
  • the length H1 of the second escape portion 122 may also be 3.05 mm.
  • the length H1 of the second escape portion 122 may also be 3.1 mm.
  • the length H1 of the second escape portion 122 can be designed and determined according to the requirements of practical applications, and is not limited here.
  • the second connecting portion 130 electrically connected to the driving voltage line 220 faces the side of the second escape portion 122 and the second escape portion
  • the width H2 of the first avoidance gap ranges from 0.9 mm to 1.0 mm.
  • the width H2 of the first avoidance gap may be 0.9 mm.
  • the width H2 of the first avoidance gap may also be 0.95 mm.
  • the width H2 of the first avoidance gap may also be 1.0 mm.
  • the width H2 of the first avoidance gap can be designed and determined according to the requirements of practical applications, and is not limited here.
  • the multiple element groups in the light emitting unit PX are sequentially numbered along the second direction F2, and the columns of the light emitting unit PX are sequentially numbered along the second direction F2,
  • the first light-emitting element QD1 in the element group numbered k in the light-emitting unit PX numbered a is electrically connected to the driving voltage line 220 corresponding to the light-emitting unit PX numbered a; the number in the light-emitting unit PX numbered a
  • the first light-emitting element QD1 in the element group M is electrically connected to the driving voltage line 220 corresponding to the light-emitting unit PX numbered a+1.
  • a is an integer greater than 0, 1 ⁇ k ⁇ M and k is an integer.
  • the element group numbered 1 is Z-1
  • the component group numbered 2 is Z-2
  • the component group numbered 3 is Z-3.
  • the negative electrode of the last light-emitting element QD1 in the element group Z-1 numbered 1 passes through the negative electrode of the last light-emitting element QD1 in the element group Z-2 numbered 2.
  • a first connection part 110 is electrically connected.
  • the negative electrode of the last light-emitting element QD1 in the element group Z-2 numbered 2 is connected to the negative electrode of the last light-emitting element QD1 in the element group Z-3 numbered 3.
  • the negative electrode is electrically connected through a first connecting portion 110 .
  • the cathode of the last light-emitting element QD1 in the element group Z-3 numbered 3 in the light-emitting unit PX numbered a is electrically connected to the output terminal of the driving circuit QD0.
  • specific values of a, k, and M may be set according to requirements of practical applications, and are not limited here.
  • the light emitting units PX in a column are sequentially numbered along the first direction F1, and the output terminal of the driving circuit QD0 of the light emitting unit PX numbered b is connected to The first input end of the driving circuit QD0 of the light emitting unit PX of b+1 is coupled through the cascade wiring 240 ; wherein, b is an integer greater than 0.
  • the output end of the driving circuit QD0 of the light emitting unit PX numbered 1 is coupled to the first input end of the driving circuit QD0 of the light emitting unit PX numbered 2 through the cascade wiring 240 .
  • the output end of the driving circuit QD0 of the light emitting unit PX numbered 2 is coupled to the first input end of the driving circuit QD0 of the light emitting unit PX numbered 3 through the cascade wiring 240 .
  • the output end of the driving circuit QD0 of the light emitting unit PX numbered 3 is coupled to the first input end of the driving circuit QD0 of the light emitting unit PX numbered 4 through the cascade wiring 240 .
  • the output end of the driving circuit QD0 of the light emitting unit PX numbered 4 is coupled to the first input end of the driving circuit QD0 of the light emitting unit PX numbered 5 through the cascade wiring 240 .
  • the specific value of b can be designed according to the requirements of practical applications, which is not limited here.
  • the cascaded wiring 240 may be located on the first conductive layer.
  • the first conductive layer further includes a cascade connection line 241
  • the second conductive layer further includes a cascade bridge portion 242 .
  • the first end of the cascaded wiring 240 is electrically connected to the last light-emitting element QD1 in the element group numbered M in the light-emitting unit PX numbered a
  • the second end of the cascaded wiring 240 is electrically connected to the second end of the cascaded wiring 240.
  • the first input end of the driving circuit QD0 in the light emitting unit PX of a+1 is electrically connected.
  • the output end of the drive circuit QD0 in the light emitting unit PX numbered a is electrically connected to the first end of the cascade connection line 241 through the first cascade via hole GL1
  • the second end of the cascade connection line 241 is electrically connected to the second end of the cascade connection line 241 through the second
  • the cascade via GL2 is electrically connected to the first end of the cascade bridge portion 242
  • the second end of the cascade bridge portion 242 is electrically connected to the first end of the cascade wire 240 through the third cascade via GL3 .
  • the second end of the cascade wiring 240 is electrically connected to the first input end of the driving circuit QD0 in the light emitting unit PX numbered a+1 through the fourth cascade via GL4 .
  • the second conductive layer further includes a common bridging portion 211; the first end of the common bridging portion 211 communicates with the driving The common voltage end of the circuit QD0 is electrically connected, and the second end of the common bridge portion 211 is electrically connected to the common voltage line 210 through the second common via hole ND2.
  • the first conductive layer further includes a source connection line 231; the first end of the source connection line 231 connects with the drive circuit QD0 through the source via hole WR.
  • the second input end Pwr of the source connection line 231 is electrically connected to the second end of the source voltage line 230 directly.
  • the orthographic projection of the source connection line 231 on the base substrate overlaps with the orthographic projection of the cascade bridge portion 242 on the base substrate.
  • the two sides of the common voltage line 210 respectively have avoidance areas, and the connection pads PD located on both sides of the common voltage line 210 are located in the avoidance areas.
  • the connection pad electrically connected to the light-emitting element QD1 in the element group Z-2 numbered 2 is located in the avoidance area on the side of the common voltage line 210 facing the driving voltage line 220, and in the element group Z-3 numbered 3
  • the connection pad electrically connected to the light-emitting element QD1 is located in the avoidance area on the side of the common voltage line 210 away from the driving voltage line 220 .
  • the orthographic projection of the common voltage line 210 on the base substrate is electrically connected to the connection pad of the light-emitting element QD1 in the element group Z-2 numbered 2 and the light-emitting element in the element group Z-3 numbered 3.
  • the connection pads to which QD1 is electrically connected do not overlap in the orthographic projection of the base substrate.
  • Embodiments of the present disclosure provide structural schematic diagrams of other light-emitting substrates, as shown in FIG. 8 to FIG. 9 b , which are modified for the implementation manners in the above-mentioned embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • the first end of the cascaded wiring 240 is electrically connected to the output end of the driving circuit QD0 in the light emitting unit PX numbered a
  • the second end of the cascade wiring 240 is electrically connected to the first input end of the driving circuit QD0 in the light emitting unit PX numbered a+1.
  • the cascade wire 240 may be located on the second conductive layer.
  • the first end of the cascaded wiring 240 is electrically connected to the output end of the driving circuit QD0 in the light emitting unit PX numbered a through the fourth cascaded via hole GL4, and the second end of the cascaded wiring 240 is connected through the fourth cascaded via hole GL4.
  • the five cascaded via holes GL5 are electrically connected to the first input terminal of the driving circuit QD0 in the light emitting unit PX numbered a+1.
  • the first conductive layer may further include a jumper bridging portion 241; the jumper 120 includes a first jumper 1201 and a second jumper 1202; Wherein, the second jumper line 1202 has an avoidance graph BG.
  • the first light-emitting element QD1 in the element group numbered M in the light-emitting unit PX numbered a is electrically connected to the first end of the first jumper 1201, and the second end of the first jumper 1201 passes through the first
  • the jumper via hole KJ1 is electrically connected to the first end of the jumper bridge portion 241
  • the second end of the jumper bridge portion 242 is electrically connected to the first end of the second jumper wire 1202 through the second jumper hole KJ2
  • the second The second end of the jumper wire 1202 is electrically connected to the driving voltage line 220 corresponding to the light emitting unit PX numbered a+1.
  • the first jumper via hole KJ1 and the second jumper via hole KJ2 respectively penetrate through the first insulating layer.
  • the orthographic projection of the jumper bridging portion 241 on the base substrate overlaps with the orthographic projection of the cascade wiring 240 on the substrate. Moreover, the orthographic projection of the jumper wire 120 on the base substrate does not overlap with the orthographic projection of the cascade wiring on the base substrate.
  • Embodiments of the present disclosure provide other structural schematic diagrams of light-emitting substrates, as shown in FIG. 10 , which are modified for the implementation manners in the foregoing embodiments. The following only describes the differences between this embodiment and the above-mentioned embodiments, and the similarities will not be repeated here.
  • part of the first connecting portion 110 may be located on the first conductive layer.
  • the first connection portion 110 electrically connected to the component groups disposed on both sides of the common voltage line 210 may be located on the first conductive layer.
  • the transition part connected to the cathode of the last light-emitting element QD1 in element group Z-2 is electrically connected to the transition part connected to the cathode of the last light-emitting element QD1 in element group Z-3 through the first connection part 110 located on the first conductive layer. connect.
  • the transfer portion where the negative electrode of the last light-emitting element QD1 in the element group Z-2 is electrically connected passes through the via hole ZL3 It is electrically connected to the first end of the first connection part 110, and the transition part electrically connected to the cathode of the last light-emitting element QD1 in the element group Z-3 is electrically connected to the second end of the first connection part 110 through the via hole ZL4. .
  • the common voltage line 210 is divided into a plurality of second line segments, and the second conductive layer further includes a second line segment bridging portion 113 .
  • the gap between the adjacent second line segments in the same common voltage line 210 is provided with the first connecting portion 110.
  • adjacent second line segments are electrically connected through the second line segment bridging portion 113 .
  • the first end of the second line segment bridging portion 113 is electrically connected to a second line segment through the via hole QL3, and the first end of the second line segment bridging portion 113 The two ends are electrically connected to another second line segment through the via hole QL4.
  • the orthographic projection of the second line segment bridging portion 113 on the substrate overlaps with the orthographic projection of the first connecting portion 110 on the substrate.
  • the orthographic projection of the first connecting portion 110 on the base substrate does not overlap with the orthographic projection of the common voltage line 210 on the base substrate.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned light-emitting substrate provided by the embodiment of the present disclosure.
  • the problem-solving principle of the display device is similar to that of the above-mentioned light-emitting substrate, so the implementation of the display device can refer to the implementation of the above-mentioned light-emitting substrate, and repeated descriptions will not be repeated here.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as limitations on the present disclosure.

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Abstract

本公开实施例公开了发光基板及显示装置，包括：衬底基板；第一导电层，位于衬底基板上；其中，第一导电层包括相互间隔设置的多条驱动电压线；多个发光单元，位于第一导电层背离衬底基板一侧；其中，每个发光单元包括多个发光元件；多个发光元件分为多个元件组；其中，同一发光单元中，至少两个元件组电连接不同的驱动电压线。

Description

发光基板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及发光基板及显示装置。
背景技术
随着发光二极管技术的发展，采用亚毫米量级甚至微米量级的发光二极管的背光源得到了广泛的应用。由此，不仅可以使利用该背光源的例如透射式显示产品的画面对比度达到有机发光二极管(Organic Light-Emitting Diode，OLED)显示产品的水平，还可以使产品保留液晶显示(Liquid Crystal Display，LCD)的技术优势，进而提升画面的显示效果，为用户提供更优质的视觉体验。
发明内容
本公开实施例提供的发光基板，包括：
衬底基板；
第一导电层，位于所述衬底基板上；其中，所述第一导电层包括相互间隔设置的多条驱动电压线；
多个发光单元，位于所述第一导电层背离所述衬底基板一侧；其中，每个所述发光单元包括多个发光元件；所述多个发光元件分为多个元件组；
其中，同一所述发光单元中，至少两个元件组电连接不同的驱动电压线。
在一些示例中，一个所述发光单元连接两条驱动电压线，所述两条驱动电压线中的一条驱动电压线在所述衬底基板的正投影与所述发光单元在所述衬底基板的正投影交叠，且另一条驱动电压线在所述衬底基板的正投影与所述发光单元在所述衬底基板的正投影不交叠。
在一些示例中，所述发光基板还包括：
第一绝缘层，位于所述第一导电层和所述多个发光单元之间；
第二导电层，位于所述第一绝缘层和所述多个发光单元之间；
第二绝缘层，位于所述第二导电层与所述多个发光单元之间；
所述第二导电层包括：相互间隔设置的多条元件走线；
每一个所述元件组中，相邻两个发光元件之间通过元件走线电连接。
在一些示例中，所述第一导电层还包括相互间隔设置的多条公共电压线与多条源电压线；
所述多条驱动电压线、所述多条公共电压线以及所述多条源电压线沿第一方向延伸，并且，根据所述驱动电压线、所述公共电压线以及所述源电压线的顺序沿第二方向重复排列；
相邻的所述驱动电压线和所述公共电压线之间具有第一镂空间隙，相邻的所述公共电压线和所述源电压线之间具有第二镂空间隙，以及相邻的所述源电压线与所述驱动电压线之间具有第三镂空间隙；
所述第一镂空间隙、所述第二镂空间隙以及所述第三镂空间隙分别设置有一列发光单元中的一个元件组和连接于所述元件组中相邻发光元件之间的元件走线。
在一些示例中，所述公共电压线的两侧设置有同一发光单元的不同元件组；并且，位于所述公共电压线两侧的元件组电连接不同的所述驱动电压线。
在一些示例中，同一所述发光单元中，不同所述元件组通过第一连接部并联设置；
同一所述发光单元中，并联连接处为电压最低处。
在一些示例中，所述第一连接部上的电压小于或等于所述公共电压线的电压。
在一些示例中，所述公共电压线上的电压为接地电压。
在一些示例中，所述第一连接部上的电压小于或等于所述驱动电压线的电压。
在一些示例中，第2条驱动电压线至第N-1条驱动电压线电连接的发光 单元的数量相同；其中，N为所述发光基板中驱动电压线的总数。
在一些示例中，第2条驱动电压线至第N-1条驱动电压线电连接的元件组的数量相同。
在一些示例中，第2条驱动电压线至第N-1条驱动电压线电连接的发光元件的数量相同。
在一些示例中，一列所述发光单元对应一条所述驱动电压线、一条所述公共电压线以及一条所述源电压线；并且，在第二方向上，最后一条所述源电压线背离所述公共电压线一侧设置有一条驱动电压线；
所述第二导电层包括：多个跨接线；其中，位于第二镂空间隙处的元件组通过所述跨接线与位于所述源电压线背离所述公共电压线一侧的驱动电压线电连接。
在一些示例中，所述第二导电层还包括多个连接焊盘；所述发光元件的一个电极电连接一个连接焊盘；
所述跨接线在所述衬底基板的正投影与所述连接焊盘在所述衬底基板的正投影不交叠。
在一些示例中，所述第二导电层还包括：多个第二连接部；其中，同一发光单元中，位于所述公共电压线面向所述驱动电压线一侧的元件组分别通过所述第二连接部与同一驱动电压线电连接；
所述跨接线靠近电连接的所述驱动电压线的部分包括第一避让部和第二避让部；其中，所述第一避让部沿第一方向延伸，所述第二避让部沿第二方向延伸；所述第二避让部的长度的范围为3.0mm～3.1mm；
同一行中，所述驱动电压线电连接的第二连接部面向所述第二避让部一侧和所述第二避让部背离所述第二连接部一侧之间具有第一避让间隙；所述第一避让间隙的宽度的范围为0.9mm～1.0mm。
在一些示例中，所述跨接线在所述衬底基板的正投影与所述公共电压线在所述衬底基板的正投影不交叠。
在一些示例中，每个所述发光单元还包括驱动电路；所述驱动电路包括 公共电压端和输出端；
所述公共电压端与所述公共电压线电连接；
同一所述发光单元中，不同所述元件组中的最后一个发光元件电连接所述输出端。
在一些示例中，所述发光单元中的多个发光元件分为M个元件组，每个元件组包括沿第一方向排列的N个发光元件；所述M个元件组沿第二方向排列；N为大于0的整数，M为大于0的整数；
沿第二方向将所述发光单元中的多个元件组依次编号，以及沿所述第二方向将所述发光单元列依次编号，编号为a的发光单元中的编号为k的元件组中的第1个发光元件与编号为a的发光单元对应的驱动电压线电连接；编号为a的发光单元中的编号为M的元件组中的第1个发光元件与编号为a+1的发光单元对应的驱动电压线电连接；
编号为a的发光单元中，编号为k的元件组中的最后1个发光元件与编号为k+1的元件组中的最后1个发光元件通过第一连接部电连接；编号为a的发光单元中的编号为M的元件组中的最后1个发光元件与驱动电路的输出端电连接；
其中，a为大于0的整数，1≤k<M且k为整数。
在一些示例中，所述级联走线位于第一导电层；所述第一导电层还包括级联连接线；
所述第二导电层还包括级联桥接部；
所述级联走线的第一端与编号为a的发光单元中的编号为M的元件组中的最后1个发光元件电连接，且所述级联走线的第二端与编号为a+1的发光单元中的驱动电路的第一输入端电连接；
编号为a的发光单元中的驱动电路的输出端通过第一级联过孔与所述级联连接线的第一端电连接，所述级联连接线的第二端通过第二级联过孔与所述级联桥接部的第一端电连接，所述级联桥接部的第二端通过第三级联过孔与所述级联走线的第一端电连接。
在一些示例中，所述级联走线位于第二导电层；所述级联走线的第一端与编号为a的发光单元中的驱动电路的输出端电连接，且所述级联走线的第二端与编号为a+1的发光单元中的驱动电路的第一输入端电连接；
所述第一导电层还包括跨接桥接部；所述跨接线包括第一跨接线和第二跨接线；其中，
编号为a的发光单元中的编号为M的元件组中的第1个发光元件与所述第一跨接线的第一端电连接，所述第一跨接线的第二端通过第一跨接过孔与所述跨接桥接部的第一端电连接，所述跨接桥接部的第二端通过第二跨接过孔与所述第二跨接线的第一端电连接，所述第二跨接线的第二端与编号为a+1的发光单元对应的驱动电压线电连接。
在一些示例中，所述第一连接部位于所述第二导电层。
在一些示例中，设置于所述公共电压线两侧的元件组电连接的第一连接部位于所述第一导电层；
所述公共电压线分为多个第二线段，所述第二导电层还包括第二线段桥接部；其中，同一所述公共电压线中相邻的所述第二线段之间的间隙设置有所述第一连接部；并且，同一所述公共电压线中，相邻的所述第二线段通过所述第二线段桥接部电连接。
在一些示例中，所述公共电压线具有避让区域；
位于所述公共电压线两侧的发光元件电连接的连接焊盘在所述衬底基板的正投影位于所述避让区域在所述衬底基板的正投影内。
本公开实施例提供的显示装置，包括上述发光基板。
附图说明
图1a为相关技术中的发光基板的结构示意图；
图1b为相关技术中的发光基板的局部版图布局示意图；
图2为本公开实施例中的发光基板的结构示意图；
图3为本公开实施例中的发光基板的局部具体结构示意图；
图4为本公开实施例提供的驱动电路中第二输入信号的波形图；
图5为本公开实施例提供的驱动电路的信号时序图；
图6为本公开实施例中的发光基板的一些局部版图布局示意图；
图7a为图6中FB1区域的放大版图布局示意图；
图7b为图6中FB2区域的放大版图布局示意图；
图8为本公开实施例中的发光基板的一些局部版图布局示意图；
图9a为图8中FB3区域的放大版图布局示意图；
图9b为图8中FB4区域的放大版图布局示意图；
图10为本公开实施例中的发光基板的又一些局部版图布局示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
结合图1a与图1b，基板01上依次设置了第一导电层02、绝缘层03以及第二导电层04。其中，第一导电层02具有驱动电压线220、公共电压线210。第二导电层04具有金属连接线。以发光单元具有9个发光元件为例，这9个发光元件通过金属连接线依次串联电连接。将这9个发光元件之间的金属连接线分成8段：A段、B段、C段、D段、E段、F段、G段。例如，驱动电压线220传输的电压为27V，公共电压线210传输的电压为0V，A段的金属连接线传输的电压为24V，B段的金属连接线传输的电压为21V，C段的金属连接线传输的电压为18V，D段的金属连接线传输的电压为15V，E段的金属连接线传输的电压为12V，F段的金属连接线传输的电压为9V，G段的金属连接线传输的电压为6V，H段的金属连接线传输的电压为3V。并且，C段的金属连接线在衬底基板的正投影与驱动电压线220在衬底基板的正投影之间交叠，F段的金属连接线在衬底基板的正投影与公共电压线210在衬底基板的正投影之间交叠。
由于F段的金属连接线传输的电压大于公共电压线210传输的电压，使得F段的金属连接线和公共电压线210的交叠处之间的电场的方向为由第二导电层指向第一导电层。由于第二导电层易于暴露，容易引人水氧，并且第一导电层02和第二导电层04的材料通常采用低电阻的Cu材质。由于Cu材料比较活泼，因此在电场作用下容易产生金属腐蚀的情形。F段的金属连接线和公共电压线210之间存在电势差，构成电化学腐蚀阳极与保护阴级，F段的金属连接线为正极发生氧化反应，公共电压线210为阴极发生还原反应。电化学腐蚀的不断进行，最终导致F段的金属连接线和公共电压线210接触短路。然而，在发光基板中若存在电化学腐蚀，则会对发光基板的发光稳定性造成影响。
并且，由于C段的金属连接线传输的电压小于驱动电压线220传输的电压，使得C段的金属连接线和驱动电压线220的交叠处之间的电场的方向为由第一导电层指向第二导电层。而驱动电压线220还有绝缘层03保护，并且水氧的入侵路径也比较远，因此可以降低电化学腐蚀的情形。有鉴于此，本 公开至少一个实施例提供了发光基板及显示装置，降低电化学腐蚀对发光基板的影响，提高发光稳定性。
在一些实施例中，如图2所示，本公开至少一个实施例提供的发光基板，可以包括衬底基板。衬底基板可以包括显示区。示例性地，衬底基板的材质可以选自塑料、聚酰亚胺、硅、陶瓷、玻璃、石英等，本公开的实施例对此不作限制。
在一些实施例中，如图2所示，显示区可以包括阵列排布的多个发光单元PX。例如，多个发光单元PX排列为多行多列。在实际应用中，发光单元PX的数量可以根据实际需求而定，例如根据发光基板的尺寸和所需要的亮度而定，虽然图2中仅示出了6行5列发光单元PX，但是应当理解，发光单元PX的数量不限于此。
在一些实施例中，如图2所示，显示区中，发光单元PX可以沿第一方向F1和第二方向F2排列为多行多列。示例性地，发光基板呈矩形，第一方向F1可以为平行于发光基板的长边的方向，第二方向F2可以为平行于发光基板的短边的方向。或者，第一方向F1也可以为平行于发光基板的短边的方向，第二方向F2也可以为平行于发光基板的长边的方向。当然，本公开的实施例不限于此，第一方向F1和第二方向F2可以为任意的方向，只需使第一方向F1和第二方向F2交叉即可。并且，多个发光单元PX也不限于沿直线排列，也可以沿折线排列、沿环形排列或按照任意的方式排列，这可以根据实际需求而定，本公开的实施例对此不作限制。
在一些实施例中，如图2与图3所示，每个发光单元PX可以包括驱动电路QD0与多个发光元件QD1。示例性地，驱动电路QD0可以包括第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND。在具体实施时，在本公开实施例中，迷你发光二极管(Mini Light Emitting Diode，Mini-LED)或微型发光二极管(Micro Light Emitting Diode，Micro-LED)的尺寸小且亮度高，可以大量应用于显示装置或其背光模组中，通过对背光进行精细调节，从而实现高动态范围图像(High-Dynamic Range，HDR)的显示。例如， Micro-LED的典型尺寸(例如长度)小于100微米，例如10微米～80微米；Mini-LED的典型尺寸(例如长度)为80微米～350微米，例如80微米～120微米。示例性地，发光元件QD1可以为微型发光二极管(Micro-LED)或迷你发光二极管(Mini-LED)中的至少一种。
在一些示例中，在具体实施时，驱动电路QD0可以被配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT与串联的发光元件QD1形成电流通路。示例性地，第一输入端Di接收第一输入信号，该第一输入信号例如为地址信号，以用于选通相应地址的驱动电路QD0。例如，不同的驱动电路QD0的地址可以相同或不同。第一输入信号可以为8bit的地址信号，通过解析该地址信号可以获知待传输的地址。第二输入端Pwr接收第二输入信号，第二输入信号例如为电力线载波通信信号。例如，第二输入信号不仅为驱动电路QD0提供电能，还向驱动电路QD0传输通信数据，该通信数据可用于控制相应的发光单元PX的发光时长，进而控制其视觉上的发光亮度。输出端OT可在不同的时段内分别输出不同的信号，例如分别输出中继信号和驱动信号。例如，中继信号为提供给其他驱动电路QD0的地址信号，即其他驱动电路QD0的第一输入端Di接收该中继信号以作为第一输入信号，从而获取地址信号。例如，驱动信号可以为驱动电流，用于驱动发光元件QD1发光。公共电压端GND接收公共电压信号，例如接地信号。
以及，驱动电路QD0配置为根据第一输入端Di接收的第一输入信号和第二输入端Pwr接收的第二输入信号在第一时段内通过输出端OT输出中继信号，以及在第二时段内通过输出端OT提供驱动信号至依次串联的多个发光元件QD1。其中，在第一时段内，输出端OT输出中继信号，该中继信号被提供给其他驱动电路QD0以使其他驱动电路QD0获得地址信号。在第二时段内，输出端OT输出驱动信号，该驱动信号被提供给依次串联的多个发光元件QD1，使得发光元件QD1在第二时段内发光。例如，第一时段与第二时段为不同的时段，第一时段例如可以早于第二时段。第一时段可以与第二时段连 续相接，第一时段的结束时刻即为第二时段的开始时刻；或者，第一时段与第二时段中间还可以有其他时段，该其他时段可以用于实现其他需要的功能，该其他时段也可以仅用于使第一时段和第二时段间隔开，以避免输出端OT在第一时段和第二时段的信号彼此干扰。
需要说明的是，当驱动信号为驱动电流时，驱动电流可以从输出端OT流向发光元件QD1，也可以从发光元件QD1流入输出端OT，驱动电流的流动方向可以根据实际需求而定，本公开的实施例对此不作限制。在本文中，“输出端OT输出驱动信号”表示输出端OT提供驱动信号，而驱动信号的方向既可以从输出端OT流出，也可以流入输出端OT。
在一些示例中，在具体实施时，结合图2与图3所示，驱动电路QD0在发光单元PX中的相对位置可以不同，或者，驱动电路QD0在发光单元PX中的位置也可以相同。以及，可以使每个发光单元PX中的发光元件QD1的相对位置关系相同。例如，可以将一个发光单元PX中的发光元件QD1的相对位置关系作为基准，沿第一方向F1和第二方向F2周期性的重复排列。例如，在第一方向F1上排列的多个发光单元PX中，位于每个发光单元PX中相同位置处的发光元件QD1可以沿第一方向F1大致排布于同一条直线上。在第二方向F2上排列的多个发光单元PX中，位于每个发光单元PX中相同位置处的发光元件QD1可以沿第二方向F2大致排布于同一条直线上。
在一些示例中，在具体实施时，驱动电路QD0可以包括解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路、中继信号生成电路和电源供给电路。
示例性地，解调电路与第二输入端Pwr和物理层接口电路电连接，被配置为对第二输入信号进行解调以得到通信数据，并将该通信数据传输至物理层接口电路。例如，第二输入端Pwr输入的第二输入信号为电力线载波通信信号，该电力线载波通信信号包含对应于通信数据的信息。例如，通信数据为反映发光时长的数据，进而代表了所需要的发光亮度。相比于通常的串行外设接口(Serial Peripheral Interface，SPI)协议，本公开实施例通过采用电 力线载波通信(Power Line Carrier Communication，PLC)协议，将通信数据叠加在电源信号上，从而有效减少信号线的数量。
如图4所示，虚线椭圆框表示相应波形的放大图，第二输入信号为高电平时，其高电平的幅值在阈值幅值Vth的附近波动，例如，在第一幅值V1和第二幅值V2之间变化，V2<Vth<V1。通过调制第一幅值V1和第二幅值V2的变化规律，可以将通信数据调制到第二输入信号中，从而使第二输入信号在传输电能的同时传输对应于通信数据的信息。例如，解调电路将第二输入信号的直流电源成分滤掉，从而可以得到通信数据。关于第二输入信号的详细说明可以参考常规的电力线载波通信信号，此处不再详述。相应地，解调电路的详细说明也可以参考常规的电力线载波通信信号的解调电路，此处不再详述。
示例性地，物理层接口电路还与数据处理控制电路电连接，被配置为对通信数据进行处理以得到数据帧(例如帧频数据)，并将数据帧传输至数据处理控制电路。物理层接口电路得到的数据帧包含了需要传输给该驱动电路QD0的信息，例如与发光时间相关的信息(例如发光时间的具体时长)。例如，物理层接口电路可以为通常的端口物理层(Physical，PHY)，详细说明可参考常规设计，此处不再详述。
示例性地，数据处理控制电路还与第一输入端Di、脉宽调制电路和中继信号生成电路电连接。数据处理控制电路被配置为基于数据帧产生脉宽控制信号并将该脉宽控制信号传输至脉宽调制电路，以及基于第一输入信号产生中继控制信号并将该中继控制信号传输至中继信号生成电路。例如，根据数据帧可以获知与该驱动电路QD0相连的发光元件QD1所需要的发光时长，因此基于该发光时长产生对应的脉宽控制信号。例如，中继控制信号为数据处理控制电路对第一输入信号处理之后产生的信号。通过对第一输入信号进行处理(例如解析、锁存、译码等)，可以获知对应于该驱动电路QD0的地址信号，并且会产生对应于后续地址的中继控制信号，该后续地址对应于其他驱动电路QD0。例如，数据处理控制电路可以实现为单片机、中央处理器 (Central Processing Unit，CPU)、数字信号处理器等。
示例性地，脉宽调制电路还与驱动信号生成电路电连接，被配置为响应于脉宽控制信号产生脉宽调制信号，并将脉宽调制信号传输至驱动信号生成电路。例如，脉宽调制电路产生的脉宽调制信号对应于发光元件QD1所需要的发光时长，例如有效脉宽时长等于发光元件QD1所需要的发光时长。例如，脉宽调制电路的详细说明可以参考常规的脉宽调制电路，此处不再详述。
示例性地，驱动信号生成电路还与输出端OT电连接，被配置为响应于脉宽调制信号产生驱动信号，并将该驱动信号从输出端OT输出。这里，将驱动信号从输出端OT输出，可以表示驱动信号(例如驱动电流)从输出端OT流向发光元件QD1，也可以表示驱动信号(例如驱动电流)从发光元件QD1流入输出端OT，具体的电流方向不受限制。
示例性地，在一些示例中，当驱动信号为驱动电流时，驱动信号生成电路可以包括电流源和金属氧化物半导体(Metal Oxide Semiconductor，MOS)场效应晶体管(Field Effect Transistor，FET)，将该金属氧化物半导体场效应晶体管称为MOS管。MOS管的控制极接收脉宽调制电路传输的脉宽调制信号，从而在脉宽调制信号的控制下导通或截止。MOS管的第一极与输出端OT连接，MOS管的第二极与电流源的第一极连接，电流源的第二极与公共电压端GND连接以接收公共电压。例如，电流源可以为恒流源。
当脉宽调制信号为有效电平时，MOS管导通，电流源通过输出端OT提供驱动电流。当脉宽调制信号为无效电平时，MOS管截止，此时输出端OT不提供驱动电流。脉宽调制信号的有效电平的时长等于MOS管的导通时长，MOS管的导通时长等于输出端OT提供驱动电流的时长。由此，可以进一步控制发光元件QD1的发光时长，进而控制视觉上的发光亮度。例如，在一些示例中，当MOS管导通时，驱动电流从OT端流入驱动电路QD0，并依次流经MOS管和电流源，然后流入接地端(例如公共电压端GND)。需要说明的是，本公开的实施例中，驱动信号生成电路还可以采用其他电路结构形式，本公开的实施例对此不作限制。
示例性地，中继信号生成电路还与输出端OT电连接，被配置为基于中继控制信号生成中继信号，并将中继信号从输出端OT输出。例如，中继控制信号对应于后续地址，基于中继控制信号产生的中继信号包含了后续地址，该后续地址对应于其他驱动电路QD0。中继信号从输出端OT输出后，被提供给另行提供的驱动电路QD0的第一输入端Di，该中继信号作为第一输入信号输入到该另行提供的驱动电路QD0，从而使该另行提供的驱动电路QD0获取对应的地址信号。中继信号生成电路可以通过锁存器、译码器、编码器等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，虽然驱动信号生成电路和中继信号生成电路均与输出端OT电连接，但是，驱动信号生成电路和中继信号生成电路分别在不同的时段输出驱动信号和中继信号，驱动信号和中继信号通过输出端OT分时传输，因此不会彼此影响。
示例性地，电源供给电路分别与解调电路和数据处理控制电路电连接，被配置为接收电能并给数据处理控制电路供电。例如，第二输入信号为电力线载波通信信号，经过解调电路解调后，第二输入信号中的直流电源成分(即电能)传输至电源供给电路，再由电源供给电路提供给数据处理控制电路。当然，本公开的实施例不限于此，电源供给电路还可以与驱动电路QD0中的其他电路电连接以提供电能。电源供给电路可以通过开关电路、电压转换电路、稳压电路等实现，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中，驱动电路QD0还可以包括更多的电路和部件，不限于上述的解调电路、物理层接口电路、数据处理控制电路、脉宽调制电路、驱动信号生成电路、中继信号生成电路和电源供给电路，这可以根据需要实现的功能而定，本公开的实施例对此不作限制。
如图5所示，驱动电路QD0工作时，首先上电(也即通电)完成初始化，接着在时段S1进行写地址操作，也即是，在时段S1，第一输入信号Di_1通过第一输入端Di输入驱动电路QD0，从而写入地址。例如，第一输入信号Di_1通过另行提供的发送器发送。
接着，在时段S2，进行驱动配置，并且，通过输出端OT输出中继信号Di_2。例如，中继信号Di_2作为第一输入信号被输入到另行提供的驱动电路QD0的第一输入端Di。例如，前述的第一时段为时段S2。
然后，在时段S3，驱动电压线220通电。例如，当多个驱动电路QD0均获取到对应的地址后，大约间隔10微秒之后进入时段S3。此时，驱动电压线220提供的驱动电压变为高电平。
接着，在时段S4，驱动电路QD0处于正常工作模式，输出端OT根据所需要的时长提供驱动信号(例如驱动电流)，以使与该驱动电路QD0连接的发光元件QD1根据需要的时长发光。例如，前述的第二时段为时段S4。例如，在作为显示装置的背光单元的情形，采用该驱动电路QD0的发光基板在局部背光调节(Local Dimming)模式下工作，可以实现高动态范围效果。
最后，在时段S5，系统关闭，也即是，该驱动电路QD0断电，且驱动电压线220提供的驱动电压变为低电平，发光元件QD1停止发光。
需要说明的是，上述工作流程仅为示意性的，而非限制性的，驱动电路QD0实际的工作流程可以根据实际需求而定，本公开的实施例对此不作限制。在图5中，VREG、POR、Vreg_1.8、OSC、Re_B均为驱动电路QD0的内部信号，不会经过第一输入端Di、第二输入端Pwr、输出端OT和公共电压端GND输入或输出。Di_1为该驱动电路QD0接收的第一输入信号，Di_2为该驱动电路QD0输出的中继信号(也即为相连的下一个驱动电路QD0接收的第一输入信号)，Di_n为依次连接的多个驱动电路QD0中第n个驱动电路QD0接收的第一输入信号。
示例性地，在具体实施时，驱动电路QD0可以设置为芯片，芯片尺寸(例如长度)可以为几十微米，芯片面积约为几百平方微米甚至更小，与Mini-LED的大小相似，具有小型化特点，便于集成到发光基板中(例如绑定连接在发光基板表面)，节省了印刷电路板的设置空间，简化了结构，有利于实现轻薄化。每一个驱动电路QD0直接驱动一个发光单元PX，避免了行扫描控制方式操作复杂且容易闪烁等问题。并且，该驱动电路QD0的端口数量少，所需 信号数量少，控制方式简单，走线方式简单，成本低。
在具体实施时，在本公开实施例中，如图6至图7b所示，衬底基板上设置有缓冲层(Buffer)400，以提高第一导电层的附着力。第一导电层位于缓冲层400背离衬底基板一侧。示例性地，第一导电层可以包括：相互间隔设置的多条公共电压线210、多条驱动电压线220、多条源电压线230。示例性地，可以使一列发光单元PX对应一条公共电压线210，一条源电压线230以及一条驱动电压线220。示例性地，多条公共电压线210、多条驱动电压线220、多条源电压线230分别沿第一方向F1延伸。并且，多条公共电压线210、多条驱动电压线220、多条源电压线230分别沿第二方向F2排列。示例性地，可以根据驱动电压线220、公共电压线210以及源电压线230的顺序沿第二方向F2重复排列。例如，针对每一列发光单元PX对应的：公共电压线210、源电压线230以及驱动电压线220，该公共电压线210在衬底基板的正投影位于该驱动电压线220和该源电压线230之间。
示例性地，源电压线230与驱动电路QD0的第二输入端Pwr电连接。这样可以通过源电压线230向驱动电路QD0的第二输入端Pwr传输第二输入信号。在一些示例中，一列发光单元PX中的驱动电路QD0的第二输入端Pwr均与同一条源电压线230电连接。
示例性地，公共电压线210与驱动电路QD0的公共电压端GND电连接，以使公共电压线210上的电压为接地电压，以通过公共电压线210向驱动电路QD0的公共电压端提供接地电压信号。在一些示例中，一列发光单元PX中的驱动电路QD0的公共电压端GND均与同一条公共电压线210电连接。
需要说明的是，通过使第一导电层中的大部分信号线的延伸方向一致，可以合理设计布线空间，降低信号干扰。
在一些示例中，在具体实施时，如图3与图6所示，针对一列发光单元PX对应的公共电压线210、驱动电压线220以及源电压线230，公共电压线210位于驱动电压线220与源电压线230之间。示例性地，驱动电压线220在第二方向F2上的宽度大于源电压线230在第二方向F2上的宽度。源电压线 230在第二方向F2上的宽度大于级联走线240在第二方向F2上的宽度。
在一些示例中，第一导电层可以采用金属材料形成单层结构。或者，第一导电层也可以采用金属材料形成叠层结构。例如，采用两层由金属材料形成的第一导电层，第一导电层具有C-1层和C-2层。示例性地，金属材料可以包括但不限于Cu。
在具体实施时，在本公开实施例中，在第一导电层上形成有第一绝缘层，即第一绝缘层位于第一导电层背离衬底基板的一侧。示例性地，第一绝缘层可以形成采用无机、有机或者有机-无机复合材料的单层结构。或者，第一绝缘层也可以为采用无机、有机或者有机-无机复合材料中的至少一种形成的多层结构。例如，可以采用多层有机材料形成第一绝缘层。也可以采用多层无机材料形成第一绝缘层。也可以采用层叠设置有机材料和无机材料形成第一绝缘层。示例性地，第一绝缘层可以包括第一子绝缘层和第二子绝缘层。其中，可以使第二子绝缘层的材料为有机材料，第一子绝缘层的材料为无机材料。示例性地，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一。有机材料可以聚酰亚胺(PI)等。
在一些示例中，在具体实施时，如图6至图7b所示，在第一绝缘层上形成有第二导电层，即第二导电层位于第一绝缘层背离衬底基板的一侧。以及，在第二导电层上形成有第二绝缘层，即第二绝缘层位于第二导电层背离衬底基板的一侧。以及，在第二绝缘层上形成有发光元件QD1。示例性地，第二绝缘层可以形成采用无机、有机或者有机-无机复合材料的单层结构。或者，第二绝缘层也可以为采用无机、有机或者有机-无机复合材料中的至少一种形成的多层结构。例如，可以采用多层有机材料形成第二绝缘层。也可以采用多层无机材料形成第二绝缘层。也可以采用层叠设置有机材料和无机材料形成第二绝缘层。示例性地，第二绝缘层可以包括第三子绝缘层和第四子绝缘层。其中，可以使第四子绝缘层的材料为有机材料，第三子绝缘层的材料为无机材料。示例性地，无机材料可以选择氮化硅(SiNx)、氧化硅(SiOX)、氮氧化硅(SiON)等至少之一。有机材料可以聚酰亚胺(PI)等。
示例性地，第二导电层可以包括：多个连接焊盘(如PD)、相互间隔设置的多条级联走线240。示例性地，多条级联走线240沿第一方向F1延伸。例如，沿第一方向F1，一列中的发光单元PX中的驱动电路QD0可以相互耦接，并且，一列中，相邻的发光单元PX中的驱动电路QD0通过级联走线240耦接。例如，沿第一方向F1的箭头所指的方向，定义第一行至第六行。沿第二方向F2的箭头所指的方向，定义第一列至第五列。以第一列为例，第一行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第二行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第二行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第三行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第三行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第四行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第四行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第五行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第五行发光单元PX中的驱动电路QD0的输出端通过一条级联走线240与第六行发光单元PX中的驱动电路QD0的第一输入端Di耦接。第六行发光单元PX中的驱动电路QD0的输出端通过一条级联输出走线与级联输出端子耦接。这样可以使级联走线240与驱动电路QD0级联的方向一致，降低信号交叠面积，降低信号干扰。
在具体实施时，在本公开实施例中，如图7a与图7b所示，发光元件的一个电极与一个连接焊盘PD电连接。例如，发光元件QD1的正极与一个连接焊盘PD电连接，发光元件QD1的负极与另一个连接焊盘PD电连接。串联设置的发光元件QD1对应的连接焊盘PD可以通过串联走线250电连接。并联设置的发光元件QD1对应的连接焊盘PD可以通过第一连接部110电连接。其余以此类推，在此不作赘述。
在具体实施时，在本公开实施例中，可以将发光单元PX中的多个发光元件QD1分为多个元件组，其中，同一发光单元PX中，至少两个元件组电连接不同的驱动电压线220。示例性地，发光单元PX中的多个发光元件QD1 分为M个元件组，每个元件组包括沿第一方向F1排列的N个发光元件QD1；M个元件组沿第二方向F2排列；N为大于0的整数，M为大于0的整数。例如，如图3与图6所示，以发光单元PX包括9个发光元件QD1，M＝3，N＝3为例，可以将这9个发光元件QD1分为3个元件组Z-1、Z-2以及Z-3。元件组Z-1、Z-2以及Z-3沿第二方向F2排列。并且，元件组Z-1中具有沿第一方向F1排列的3个发光元件QD1，元件组Z-2中也具有沿第一方向F1排列的3个发光元件QD1，元件组Z-3中也具有沿第一方向F1排列的3个发光元件QD1。其中，同一发光单元PX中，元件组Z-1和元件组Z-2连接其所位于的发光单元PX左侧的驱动电压线220，元件组Z-3连接其所位于的发光单元PX右侧的驱动电压线220。这样可以降低第二导电层与公共电压线210的重叠面积。
在具体实施时，在本公开实施例中，如图6所示，可以使一个发光单元PX连接两条驱动电压线220，两条驱动电压线220中的一条驱动电压线220在衬底基板的正投影与发光单元PX在衬底基板的正投影交叠，且另一条驱动电压线220在衬底基板的正投影与该发光单元PX在衬底基板的正投影不交叠。例如，针对第2条至第N-1条驱动电压线220，这些驱动电压线220分别与相邻两列发光单元PX电连接。这样可以使第2条至第N-1条驱动电压线220的负载大致相同，提高发光稳定性。其中，N为发光基板中驱动电压线的总数。在实际应用中，N的取值可以根据实际应用的需求进行设计确定，在此不作限定。
需要说明的是，发光基板上设置有N条驱动电压线220，可以在沿F2的箭头指向的方向上，将发光基板上设置的多条驱动电压线220进行定义编号：第1条驱动电压线220(例如最左边的驱动电压线220)，第2条驱动电压线220，……，第N-1条驱动电压线220，第N条驱动电压线220(例如最右边的驱动电压线220)。
在具体实施时，在本公开实施例中，如图6所示，可以使第2条至第N-1条驱动电压线220电连接的发光单元PX的数量相同。这样可以进一步使第2 条至第N-1条驱动电压线220的负载大致相同，进一步提高发光稳定性。以及，还可以降低发光单元PX的设计难度。
在具体实施时，在本公开实施例中，如图6所示，可以使第2条至第N-1条驱动电压线220电连接的元件组的数量相同。这样可以进一步使第2条至第N-1条驱动电压线220的负载大致相同，进一步提高发光稳定性。以及，还可以进一步降低元件组的设计难度。
在具体实施时，在本公开实施例中，如图6所示，可以使第2条至第N-1条驱动电压线220电连接的发光元件QD1的数量相同。这样可以进一步使第2条至第N-1条驱动电压线220的负载大致相同，进一步提高发光稳定性。以及，还可以进一步降低发光元件QD1的设计难度。
在具体实施时，在本公开实施例中，如图3与图6所示，可以使同一发光单元PX中，不同元件组并联设置。示例性地，元件组Z-1、Z-2以及Z-3两端的电压均相同。例如，可以使同一发光单元PX中，不同元件组通过第一连接部并联设置。示例性地，元件组Z-1、Z-2以及Z-3的电压最低处通过第一连接部并联设置。也就是说，同一发光单元中，并联连接处为电压最低处。
在具体实施时，在本公开实施例中，如图6所示，同一发光单元PX中，不同元件组中的最后一个发光元件QD1可以电连接驱动电路QD0的输出端。示例性地，同一发光单元PX中，不同元件组中的最后一个发光元件QD1可以通过第一连接部110并联设置。也就是说，同一发光单元PX中，不同元件组中的最后一个发光元件QD1可以通过第一连接部110电连接驱动电路QD0的输出端。例如，元件组Z-1中最后一个发光元件QD1通过第一连接部110与元件组Z-2中最后一个发光元件QD1电连接，以及，元件组Z-2中最后一个发光元件QD1通过第一连接部110与元件组Z-3中最后一个发光元件QD1电连接。元件组Z-3中最后一个发光元件QD1直接与驱动电路QD0的输出端电连接。示例性地，可以使第一连接部110位于第二导电层。
在具体实施时，在本公开实施例中，同一发光单元PX中，不同元件组中的最后一个发光元件QD1电连接的电压最低，以使每一个元件组中的电流流 通路径至与驱动电路QD0的输出端电连接的最后一个发光元件QD1。例如，元件组Z-1中最后一个发光元件QD1电连接的电压最低。元件组Z-2中最后一个发光元件QD1电连接的电压最低。元件组Z-3中最后一个发光元件QD1电连接的电压最低。
在具体实施时，在本公开实施例中，同一发光单元PX中，不同元件组中并联设置的发光元件QD1的电极的种类相同。例如，元件组Z-1中第一个发光元件QD1的正极、元件组Z-2中第一个发光元件QD1的正极、元件组Z-3中第一个发光元件QD1的正极并联设置。元件组Z-1中最后一个发光元件QD1的负极、元件组Z-2中最后一个发光元件QD1的负极、元件组Z-3中最后一个发光元件QD1的负极并联设置。
在具体实施时，在本公开实施例中，可以使第一连接部110上的电压小于或等于公共电压线210上的电压。
在具体实施时，在本公开实施例中，也可以使第一连接部110上的电压小于或等于驱动电压线220上的电压。
在具体实施时，在本公开实施例中，如图6所示，同一元件组中，发光元件QD1串联设置。示例性地，第二导电层还可以包括：相互间隔设置的多条元件走线250；其中，每一个元件组中，相邻两个发光元件QD1之间通过元件走线250电连接。例如，每个发光元件QD1包括正极(+)和负极(-)(或者，也可称为阳极和阴极)，同一元件组中，发光元件QD1的正极和负极依序首尾串联，并串联于驱动电压线220和输出端OT之间，从而在驱动电压线220和输出端OT之间形成电流流通路径。例如，元件组Z-1中的发光元件QD1的正极和负极依序首尾串联，并串联于驱动电压线220和输出端OT之间，即以与驱动电压线220电连接的发光元件QD1作为元件组Z-1中这3个发光元件QD1串联的起点，以与输出端OT电连接的发光元件QD1作为元件组Z-1中这3个发光元件QD1串联的终点。元件组Z-2中的发光元件QD1的正极和负极也依序首尾串联，并串联于驱动电压线220和输出端OT之间，即以与驱动电压线220电连接的发光元件QD1作为元件组Z-2中这3个发光 元件QD1串联的起点，以与输出端OT电连接的发光元件QD1作为元件组Z-2中这3个发光元件QD1串联的终点。元件组Z-3中的发光元件QD1的正极和负极也依序首尾串联，并串联于驱动电压线220和输出端OT之间，即以与驱动电压线220电连接的发光元件QD1作为元件组Z-3中这3个发光元件QD1串联的起点，以与输出端OT电连接的发光元件QD1作为元件组Z-3中这3个发光元件QD1串联的终点。
并且，元件组Z-1和元件组Z-2对应的第二连接部130连接左侧的驱动电压线220，元件组Z-3对应的第二连接部130连接右侧的驱动电压线220。在实际应用中，驱动电压线220可以提供驱动电压，例如在需要使发光元件QD1发光的时段(第二时段)内为高电压，而在其他时段内为低电压。由此，在第二时段内，驱动信号(例如驱动电流)从驱动电压线220依次流经每个元件中的发光元件QD1后流入驱动电路QD0的输出端OT。并且，发光元件QD1在驱动电流流过时发光，通过控制驱动电流的持续时间，可以控制发光元件QD1的发光时长，从而控制视觉上的发光亮度。
当然，元件组中的发光元件QD1的连接方式也可以为先将部分发光元件QD1并联后再进行串联方式。或者，元件组中的发光元件QD1的连接方式也可以为先将部分发光元件QD1串联后再进行并联方式。在实际应用中，可以根据实际的需求进行设计确定，在此不作限定。
需要说明的是，本公开的实施例中，每个发光单元PX中的发光元件QD1的数量不受限制，可以为6个、8个、12个等任意数量，而不限于9个。多个发光元件QD1可以采用任意的排列方式，例如按照所需要的图案排列，而不限于矩阵排列方式。并且，驱动电路QD0的设置位置不受限制，可以设置在发光元件QD1彼此之间的任意空隙中，这可以根据实际需求而定，本公开的实施例对此不作限制。
在具体实施时，在本公开实施例中，如图6所示，相邻的驱动电压线220和公共电压线210之间具有第一镂空间隙，相邻的公共电压线210和源电压线230之间具有第二镂空间隙，以及相邻的源电压线230与驱动电压线220 之间具有第三镂空间隙。其中，第一镂空间隙、第二镂空间隙以及第三镂空间隙分别设置有一列发光单元PX中的一个元件组和连接于元件组中相邻发光元件QD1之间的元件走线250。示例性地，第一镂空间隙中设置有元件组Z-2，第二镂空间隙中设置有元件组Z-3，第三镂空间隙中设置有元件组Z-1。
在具体实施时，在本公开实施例中，如图6所示，公共电压线210的两侧设置有不同的元件组；并且，位于公共电压线210两侧的元件组电连接不同的驱动电压线220。示例性地，一条公共电压线210的两侧设置有同一发光单元PX中的两个元件组，例如，公共电压线210面向驱动电压线220的一侧设置有元件组Z-2，公共电压线210面向源电压线230的一侧设置有元件组Z-3。并且，位于公共电压线210面向驱动电压线220的一侧的元件组Z-2与位于公共电压线210背离源电压线230一侧的驱动电压线220电连接，位于公共电压线210面向源电压线230的一侧的元件组Z-3与位于源电压线230背离公共电压线210一侧的驱动电压线220电连接。
在具体实施时，在本公开实施例中，如图6所示，在第二方向F2上，最后一条源电压线230背离公共电压线210一侧设置有一条驱动电压线220。第二导电层还可以包括：多个跨接线120；其中，位于第二镂空间隙处的元件组通过跨接线120与位于源电压线230背离公共电压线210一侧的驱动电压线220电连接。示例性地，位于第二镂空间隙处的元件组为Z-3，则元件组为Z-3通过跨接线120与位于源电压线230背离公共电压线210一侧的驱动电压线220电连接。
在具体实施时，在本公开实施例中，如图6所示，跨接线120在衬底基板的正投影与公共电压线210在衬底基板的正投影不交叠。
在具体实施时，在本公开实施例中，如图6所示，第二导电层还可以包括：多个第二连接部130；其中，同一发光单元PX中，位于公共电压线210面向驱动电压线220一侧的元件组分别通过第二连接部130与同一驱动电压线220电连接。示例性地，元件组Z-1通过一条第二连接部130与驱动电压线220电连接，并且，元件组Z-2通过一条第二连接部130与同一条驱动电 压线220电连接。
结合图1a与图1b，在实际应用时，第一导电层01和第二导电层02的材料通常采用低电阻的Cu材质。由于Cu材料比较活泼，因此在电场作用下容易产生金属腐蚀的情形。第一导电层02和第二导电层04存在电势差，构成电化学腐蚀阳极与保护阴级，第二导电层04为正极发生氧化反应，第一导电层02为阴极发生还原反应。电化学腐蚀的不断进行，最终导致第一导电层02和第二导电层04接触短路。然而，在发光基板中若存在电化学腐蚀，则会对发光基板的发光稳定性造成影响。
本公开实施例中，由于驱动电压线加载的电压大于公共电压线加载的电压，并且第二连接部130和跨接线120均与驱动电压线电连接，这样使得第二连接部130和跨接线120上的电压均大于公共电压线加载的电压。本公开实施例中，通过将公共电压线两侧的发光元件连接位于公共电压线两侧的驱动电压线，这样可以避免跨接线在衬底基板的正投影与公共电压线在衬底基板的正投影交叠，从而可以避免跨接线与公共电压线存在正对面积，进而可以避免使跨接线作为阴极发生还原反应，也可以避免使公共电压线作为正极发生氧化反应。并且，跨接线上有第二绝缘层的保护，而且水分的入侵的路径也比较远。因此可以有效的降低电化学腐蚀的情形。
在实际应用中，为了降低电化学腐蚀，可以增加第一绝缘层的厚度和层数。而本公开实施例中，跨接线在衬底基板的正投影与公共电压线在衬底基板的正投影交叠，从而可以避免跨接线与公共电压线存在正对面积，进而可以避免使跨接线作为阴极发生还原反应，也可以避免使公共电压线作为正极发生氧化反应，可以有效的降低电化学腐蚀的情形。因此，可以不用再额外的增加第一绝缘层的厚度和层数，可以节约产能。
在具体实施时，在本公开实施例中，如图6与图7a所示，跨接线120在衬底基板的正投影与连接焊盘PD在衬底基板的正投影不交叠。例如，如图6与图7a所示，跨接线靠近电连接的驱动电压线的部分BG可以包括第一避让部121和第二避让部122；其中，第一避让部121沿第一方向F1延伸，第二 避让部122沿第二方向F2延伸；第二避让部122的长度H1的范围为3.0mm～3.1mm。示例性地，第二避让部122的长度H1可以为3.0mm。第二避让部122的长度H1也可以为3.05mm。第二避让部122的长度H1也可以为3.1mm。当然，在实际应用中，第二避让部122的长度H1可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6与图7a所示，同一行中，驱动电压线220电连接的第二连接部130面向第二避让部122一侧和第二避让部122背离第二连接部130一侧之间具有第一避让间隙；第一避让间隙的宽度H2的范围为0.9mm～1.0mm。示例性地，第一避让间隙的宽度H2可以为0.9mm。第一避让间隙的宽度H2也可以为0.95mm。第一避让间隙的宽度H2也可以为1.0mm。当然，在实际应用中，第一避让间隙的宽度H2可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图6所示，沿第二方向F2将发光单元PX中的多个元件组依次编号，以及沿第二方向F2将发光单元PX列依次编号，编号为a的发光单元PX中的编号为k的元件组中的第1个发光元件QD1与编号为a的发光单元PX对应的驱动电压线220电连接；编号为a的发光单元PX中的编号为M的元件组中的第1个发光元件QD1与编号为a+1的发光单元PX对应的驱动电压线220电连接。其中，a为大于0的整数，1≤k<M且k为整数。示例性地，以发光单元PX包括9个发光元件QD1，M＝3，N＝3，k＝1、k＝2为例，如图6所示，编号为1的元件组为Z-1，编号为2的元件组为Z-2，编号为3的元件组为Z-3。在编号为a的发光单元PX中，编号为1的元件组Z-1中的最后1个发光元件QD1的负极与编号为2的元件组Z-2中的最后1个发光元件QD1的负极通过一个第一连接部110电连接。并且，在编号为a的发光单元PX中，编号为2的元件组Z-2中的最后1个发光元件QD1的负极与编号为3的元件组Z-3中的最后1个发光元件QD1的负极通过一个第一连接部110电连接。以及，编号为a的发光单元PX中的编号为3的元件组Z-3中的最后1个发光元件QD1返负极与驱动电路QD0的输出端电连 接。当然，在实际应用中，可以根据实际应用的需求设置a，k，M的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图6所示，沿第一方向F1将一列中的发光单元PX依次编号，编号为b的发光单元PX的驱动电路QD0的输出端与编号为b+1的发光单元PX的驱动电路QD0的第一输入端通过级联走线240耦接；其中，b为大于0的整数。示例性地，b＝1时，编号为1的发光单元PX的驱动电路QD0的输出端与编号为2的发光单元PX的驱动电路QD0的第一输入端通过级联走线240耦接。b＝2时，编号为2的发光单元PX的驱动电路QD0的输出端与编号为3的发光单元PX的驱动电路QD0的第一输入端通过级联走线240耦接。b＝3时，编号为3的发光单元PX的驱动电路QD0的输出端与编号为4的发光单元PX的驱动电路QD0的第一输入端通过级联走线240耦接。b＝4时，编号为4的发光单元PX的驱动电路QD0的输出端与编号为5的发光单元PX的驱动电路QD0的第一输入端通过级联走线240耦接。当然，在实际应用中，可以根据实际应用的需求设计b的具体数值，在此不作限定。
在具体实施时，在本公开实施例中，如图3、图6与图7b所示，可以使级联走线240位于第一导电层。并且，第一导电层还包括级联连接线241，以及，第二导电层还包括级联桥接部242。其中，级联走线240的第一端与编号为a的发光单元PX中的编号为M的元件组中的最后1个发光元件QD1电连接，且级联走线240的第二端与编号为a+1的发光单元PX中的驱动电路QD0的第一输入端电连接。并且，编号为a的发光单元PX中的驱动电路QD0的输出端通过第一级联过孔GL1与级联连接线241的第一端电连接，级联连接线241的第二端通过第二级联过孔GL2与级联桥接部242的第一端电连接，级联桥接部242的第二端通过第三级联过孔GL3与级联走线240的第一端电连接。示例性地，级联走线240的第二端通过第四级联过孔GL4与编号为a+1的发光单元PX中的驱动电路QD0的第一输入端电连接。
在具体实施时，在本公开实施例中，如图6与图7b所示，第二导电层还 包括公共桥接部211；该公共桥接部211的第一端通过第一公共过孔ND1与驱动电路QD0的公共电压端电连接，该公共桥接部211的第二端通过第二公共过孔ND2与公共电压线210电连接。
在具体实施时，在本公开实施例中，如图6与图7b所示，第一导电层还包括源连接线231；该源连接线231的第一端通过源过孔WR与驱动电路QD0的第二输入端Pwr电连接，该源连接线231的第二端直接与源电压线230电连接。示例性地，源连接线231在衬底基板的正投影与级联桥接部242在衬底基板的正投影交叠。
在具体实施时，在本公开实施例中，如图6至图7b所示，公共电压线210的两侧分别具有避让区域，位于公共电压线210的两侧的连接焊盘PD位于该避让区域内。例如，编号为2的元件组Z-2中的发光元件QD1电连接的连接焊盘位于公共电压线210面向驱动电压线220的一侧的避让区域中，编号为3的元件组Z-3中的发光元件QD1电连接的连接焊盘位于公共电压线210背离驱动电压线220的一侧的避让区域中。也就是说，公共电压线210在衬底基板的正投影与编号为2的元件组Z-2中的发光元件QD1电连接的连接焊盘和编号为3的元件组Z-3中的发光元件QD1电连接的连接焊盘在衬底基板的正投影不交叠。
本公开实施例提供了另一些发光基板的结构示意图，如图8至图9b所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图8与图9a所示，级联走线240的第一端与编号为a的发光单元PX中的驱动电路QD0的输出端电连接，且级联走线240的第二端与编号为a+1的发光单元PX中的驱动电路QD0的第一输入端电连接。可以使级联走线240位于第二导电层。并且，级联走线240的第一端通过第四级联过孔GL4与编号为a的发光单元PX中的驱动电路QD0的输出端电连接，且级联走线240的第二端通过第五级联过孔GL5与编号为a+1的发光单元PX中的驱动电路QD0的第一输入端电连接。
在具体实施时，在本公开实施例中，如图8与图9a所示，第一导电层还可以包括跨接桥接部241；跨接线120包括第一跨接线1201和第二跨接线1202；其中，第二跨接线1202具有避让图形BG。并且，编号为a的发光单元PX中的编号为M的元件组中的第1个发光元件QD1与第一跨接线1201的第一端电连接，第一跨接线1201的第二端通过第一跨接过孔KJ1与跨接桥接部241的第一端电连接，跨接桥接部242的第二端通过第二跨接过孔KJ2与第二跨接线1202的第一端电连接，第二跨接线1202的第二端与编号为a+1的发光单元PX对应的驱动电压线220电连接。其中，第一跨接过孔KJ1和第二跨接过孔KJ2分别贯穿第一绝缘层。
在具体实施时，在本公开实施例中，如图8与图9b所示，跨接桥接部241在衬底基板的正投影与级联走线240在衬底基板的正投影交叠。并且，跨接线120在衬底基板的正投影与级联走线在衬底基板的正投影不交叠。
本公开实施例提供了另一些发光基板的结构示意图，如图10所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图10所示，可以使部分第一连接部110位于第一导电层。例如，设置于公共电压线210两侧的元件组电连接的第一连接部110可以位于第一导电层。
元件组Z-2中最后一个发光元件QD1的负极连接的转接部与元件组Z-3中最后一个发光元件QD1的负极连接的转接部通过位于第一导电层的第一连接部110电连接。示例性地，针对连接于元件组Z-2与元件组Z-3之间的第一连接部110，元件组Z-2中最后一个发光元件QD1的负极电连接的转接部通过过孔ZL3与该第一连接部110的第一端电连接，元件组Z-3中最后一个发光元件QD1的负极电连接的转接部通过过孔ZL4与该第一连接部110的第二端电连接。
在具体实施时，在本公开实施例中，如图10所示，公共电压线210分为多个第二线段，并且，第二导电层还包括第二线段桥接部113。其中，同一公 共电压线210中相邻的第二线段之间的间隙设置有第一连接部110。并且，同一公共电压线210中，相邻的第二线段通过第二线段桥接部113电连接。示例性地，针对同一公共电压线210中相邻的两个第二线段，第二线段桥接部113的第一端通过过孔QL3与一个第二线段电连接，第二线段桥接部113的第二端通过过孔QL4与另一个第二线段电连接。
在具体实施时，在本公开实施例中，如图10所示，第二线段桥接部113在衬底基板的正投影与第一连接部110在衬底基板的正投影交叠。并且，第一连接部110在衬底基板的正投影与公共电压线210在衬底基板的正投影不交叠。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述发光基板。该显示装置解决问题的原理与前述发光基板相似，因此该显示装置的实施可以参见前述发光基板的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (24)

  1. 一种发光基板，包括：
    衬底基板；
    第一导电层，位于所述衬底基板上；其中，所述第一导电层包括相互间隔设置的多条驱动电压线；
    多个发光单元，位于所述第一导电层背离所述衬底基板一侧；其中，每个所述发光单元包括多个发光元件；所述多个发光元件分为多个元件组；
    其中，同一所述发光单元中，至少两个元件组电连接不同的驱动电压线。
  2. 如权利要求1所述的发光基板，其中，一个所述发光单元连接两条驱动电压线，所述两条驱动电压线中的一条驱动电压线在所述衬底基板的正投影与所述发光单元在所述衬底基板的正投影交叠，且另一条驱动电压线在所述衬底基板的正投影与所述发光单元在所述衬底基板的正投影不交叠。
  3. 如权利要求2所述的发光基板，其中，所述发光基板还包括：
    第一绝缘层，位于所述第一导电层和所述多个发光单元之间；
    第二导电层，位于所述第一绝缘层和所述多个发光单元之间；
    第二绝缘层，位于所述第二导电层与所述多个发光单元之间；
    所述第二导电层包括：相互间隔设置的多条元件走线；
    每一个所述元件组中，相邻两个发光元件之间通过元件走线电连接。
  4. 如权利要求3所述的发光基板，其中，所述第一导电层还包括相互间隔设置的多条公共电压线与多条源电压线；
    所述多条驱动电压线、所述多条公共电压线以及所述多条源电压线沿第一方向延伸，并且，根据所述驱动电压线、所述公共电压线以及所述源电压线的顺序沿第二方向重复排列；
    相邻的所述驱动电压线和所述公共电压线之间具有第一镂空间隙，相邻的所述公共电压线和所述源电压线之间具有第二镂空间隙，以及相邻的所述源电压线与所述驱动电压线之间具有第三镂空间隙；
    所述第一镂空间隙、所述第二镂空间隙以及所述第三镂空间隙分别设置有一列发光单元中的一个元件组和连接于所述元件组中相邻发光元件之间的元件走线。
  5. 如权利要求4所述的发光基板，其中，所述公共电压线的两侧设置有同一发光单元的不同元件组；并且，位于所述公共电压线两侧的元件组电连接不同的所述驱动电压线。
  6. 如权利要求1-5任一项所述的发光基板，其中，同一所述发光单元中，不同所述元件组通过第一连接部并联设置；
    同一所述发光单元中，并联连接处为电压最低处。
  7. 如权利要求6所述的发光基板，其中，所述第一连接部上的电压小于或等于所述公共电压线的电压。
  8. 如权利要求7所述的发光基板，其中，所述公共电压线上的电压为接地电压。
  9. 如权利要求6所述的发光基板，其中，所述第一连接部上的电压小于或等于所述驱动电压线的电压。
  10. 如权利要求1-5任一项所述的发光基板，其中，第2条驱动电压线至第N-1条驱动电压线电连接的发光单元的数量相同；其中，N为所述发光基板中驱动电压线的总数。
  11. 如权利要求10所述的发光基板，其中，第2条驱动电压线至第N-1条驱动电压线电连接的元件组的数量相同。
  12. 如权利要求11所述的发光基板，其中，第2条驱动电压线至第N-1条驱动电压线电连接的发光元件的数量相同。
  13. 如权利要求3-12任一项所述的发光基板，其中，一列所述发光单元对应一条所述驱动电压线、一条所述公共电压线以及一条所述源电压线；并且，在第二方向上，最后一条所述源电压线背离所述公共电压线一侧设置有一条驱动电压线；
    所述第二导电层包括：多个跨接线；其中，位于第二镂空间隙处的元件 组通过所述跨接线与位于所述源电压线背离所述公共电压线一侧的驱动电压线电连接。
  14. 如权利要求13所述的发光基板，其中，所述第二导电层还包括多个连接焊盘；所述发光元件的一个电极电连接一个连接焊盘；
    所述跨接线在所述衬底基板的正投影与所述连接焊盘在所述衬底基板的正投影不交叠。
  15. 如权利要求14所述的发光基板，其中，所述第二导电层还包括：多个第二连接部；其中，同一发光单元中，位于所述公共电压线面向所述驱动电压线一侧的元件组分别通过所述第二连接部与同一驱动电压线电连接；
    所述跨接线靠近电连接的所述驱动电压线的部分包括第一避让部和第二避让部；其中，所述第一避让部沿第一方向延伸，所述第二避让部沿第二方向延伸；所述第二避让部的长度的范围为3.0mm～3.1mm；
    同一行中，所述驱动电压线电连接的第二连接部面向所述第二避让部一侧和所述第二避让部背离所述第二连接部一侧之间具有第一避让间隙；所述第一避让间隙的宽度的范围为0.9mm～1.0mm。
  16. 如权利要求15所述的发光基板，其中，所述跨接线在所述衬底基板的正投影与所述公共电压线在所述衬底基板的正投影不交叠。
  17. 如权利要求3-16任一项所述的发光基板，其中，每个所述发光单元还包括驱动电路；所述驱动电路包括公共电压端和输出端；
    所述公共电压端与所述公共电压线电连接；
    同一所述发光单元中，不同所述元件组中的最后一个发光元件电连接所述输出端。
  18. 如权利要求1-17任一项所述的发光基板，其中，所述发光单元中的多个发光元件分为M个元件组，每个元件组包括沿第一方向排列的N个发光元件；所述M个元件组沿第二方向排列；N为大于0的整数，M为大于0的整数；
    沿第二方向将所述发光单元中的多个元件组依次编号，以及沿所述第二 方向将所述发光单元列依次编号，编号为a的发光单元中的编号为k的元件组中的第1个发光元件与编号为a的发光单元对应的驱动电压线电连接；编号为a的发光单元中的编号为M的元件组中的第1个发光元件与编号为a+1的发光单元对应的驱动电压线电连接；
    编号为a的发光单元中，编号为k的元件组中的最后1个发光元件与编号为k+1的元件组中的最后1个发光元件通过第一连接部电连接；编号为a的发光单元中的编号为M的元件组中的最后1个发光元件与驱动电路的输出端电连接；
    其中，a为大于0的整数，1≤k<M且k为整数。
  19. 如权利要求18所述的发光基板，其中，所述级联走线位于第一导电层；所述第一导电层还包括级联连接线；
    所述第二导电层还包括级联桥接部；
    所述级联走线的第一端与编号为a的发光单元中的编号为M的元件组中的最后1个发光元件电连接，且所述级联走线的第二端与编号为a+1的发光单元中的驱动电路的第一输入端电连接；
    编号为a的发光单元中的驱动电路的输出端通过第一级联过孔与所述级联连接线的第一端电连接，所述级联连接线的第二端通过第二级联过孔与所述级联桥接部的第一端电连接，所述级联桥接部的第二端通过第三级联过孔与所述级联走线的第一端电连接。
  20. 如权利要求19所述的发光基板，其中，所述级联走线位于第二导电层；所述级联走线的第一端与编号为a的发光单元中的驱动电路的输出端电连接，且所述级联走线的第二端与编号为a+1的发光单元中的驱动电路的第一输入端电连接；
    所述第一导电层还包括跨接桥接部；所述跨接线包括第一跨接线和第二跨接线；其中，
    编号为a的发光单元中的编号为M的元件组中的第1个发光元件与所述第一跨接线的第一端电连接，所述第一跨接线的第二端通过第一跨接过孔与 所述跨接桥接部的第一端电连接，所述跨接桥接部的第二端通过第二跨接过孔与所述第二跨接线的第一端电连接，所述第二跨接线的第二端与编号为a+1的发光单元对应的驱动电压线电连接。
  21. 如权利要求18所述的发光基板，其中，所述第一连接部位于所述第二导电层。
  22. 如权利要求18所述的发光基板，其中，设置于所述公共电压线两侧的元件组电连接的第一连接部位于所述第一导电层；
    所述公共电压线分为多个第二线段，所述第二导电层还包括第二线段桥接部；其中，同一所述公共电压线中相邻的所述第二线段之间的间隙设置有所述第一连接部；并且，同一所述公共电压线中，相邻的所述第二线段通过所述第二线段桥接部电连接。
  23. 如权利要求14-22任一项所述的发光基板，其中，所述公共电压线具有避让区域；
    位于所述公共电压线两侧的发光元件电连接的连接焊盘在所述衬底基板的正投影位于所述避让区域在所述衬底基板的正投影内。
  24. 一种显示装置，包括如权利要求1-23任一项所述的发光基板。
PCT/CN2021/115478 2021-08-30 2021-08-30 发光基板及显示装置 WO2023028793A1 (zh)

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