WO2021179116A1 - 一种微发光二极管外延结构及其制备方法 - Google Patents

一种微发光二极管外延结构及其制备方法 Download PDF

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WO2021179116A1
WO2021179116A1 PCT/CN2020/078410 CN2020078410W WO2021179116A1 WO 2021179116 A1 WO2021179116 A1 WO 2021179116A1 CN 2020078410 W CN2020078410 W CN 2020078410W WO 2021179116 A1 WO2021179116 A1 WO 2021179116A1
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barrier layer
light
layer
emitting
emitting area
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PCT/CN2020/078410
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English (en)
French (fr)
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李水清
杜伟华
赖昭序
邓和清
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厦门市三安光电科技有限公司
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Priority to CN202080002983.6A priority Critical patent/CN112204758B/zh
Priority to DE112020006856.0T priority patent/DE112020006856T5/de
Priority to CN202210562398.2A priority patent/CN115036400A/zh
Priority to JP2022535096A priority patent/JP7480300B2/ja
Priority to PCT/CN2020/078410 priority patent/WO2021179116A1/zh
Priority to KR1020227030355A priority patent/KR20220136405A/ko
Priority to TW109137089A priority patent/TWI766403B/zh
Publication of WO2021179116A1 publication Critical patent/WO2021179116A1/zh
Priority to US17/930,186 priority patent/US20230006092A1/en

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    • H—ELECTRICITY
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • C—CHEMISTRY; METALLURGY
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    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
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    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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    • H01L2933/0008—Processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a micro LED light-emitting element, which belongs to the technical field of semiconductor optoelectronics.
  • the peak photoelectric conversion efficiency of the traditional epitaxial structure LED is distributed in the current density range greater than 5 A/cm 2. As shown in FIG. 9, most of the existing applications work in the high current density (greater than 10 A/cm 2 ) region. However, the current used by the Micro LED used in mobile phones (or watches, bracelets) is very small, often at the level of nA, which is converted into a current density, which is between 0.1 and 1A/cm 2 . The photoelectric conversion efficiency of the traditional epitaxial structure is in a very unstable range when the current density is lower than 1A/cm 2. With the small change of the current, the photoelectric conversion efficiency will also drop rapidly, making the traditional structure epitaxial wafer unable to be applied Products requiring low current density work.
  • Patent CN107833953A proposes a method for growing a Micro LED multi-quantum well layer.
  • the MQW structure is a well layer (InGaN)/barrier layer (GaN)/barrier layer (GaN through H2).
  • the present invention aims to provide a micro LED epitaxial structure and a preparation method thereof.
  • the present invention proposes a micro LED epitaxial structure.
  • the micro LED epitaxial structure includes at least an N-type layer, a light-emitting layer, and a P-type layer.
  • the light-emitting layer includes a quantum well structure of n periods, each
  • the periodic quantum well structure includes a well layer and a barrier layer.
  • the quantum well structure of n1 periods is defined as the first light-emitting area
  • the quantum well structure of n2 periods is defined as the second light-emitting area.
  • n1 and n2 are greater than or equal to 1, and n1+n2 is less than or equal to n, and the first light-emitting area is closer to the N-type layer than the second light-emitting area.
  • the average band gap of the barrier layer materials of the two groups of light-emitting regions meets the following conditions: the first light-emitting region is smaller than the second light-emitting region; the average band gaps of the two groups of light-emitting region well layer materials meet the following conditions: the first light-emitting region is greater than or equal to the second light-emitting region Area.
  • the quantum well structure of each period of the first light-emitting region includes at least a first barrier layer, a second barrier layer, a third barrier layer, and a well layer, wherein the second barrier layer is located at the first barrier layer.
  • the band gap of the second barrier layer material of each quantum well structure is larger than the band gaps of the first barrier layer and the third barrier layer material.
  • the quantum well structure of each period of the second light-emitting region includes at least a first barrier layer, a second barrier layer, a third barrier layer, a well layer, and a fourth barrier layer, wherein the second barrier layer The layer is located between the first barrier layer and the third barrier layer.
  • the fourth barrier layer is located behind the well layer.
  • the band gap of the second barrier layer material of each quantum well structure is larger than that of the first barrier layer.
  • the band gaps of the materials of the first barrier layer and the third barrier layer, and the band gaps of the fourth barrier layer are larger than the band gaps of the materials of the first barrier layer, the second barrier layer and the third barrier layer.
  • the thickness of the first barrier layer, the second barrier layer, the third barrier layer, and the fourth barrier layer are in the range of 10 angstroms to 1000 angstroms; the thickness of the well layer is in the range of 1 angstroms to 100 angstroms. Angstrom. More preferably, in each period of the quantum well structure, the ratio of the total thickness of the first barrier layer, the second barrier layer, and the third barrier layer to the thickness of the well layer is between 5:1 and 20:1; The ratio of the thickness of the fourth barrier layer to the thickness of the well layer is between 5:1 and 20:1.
  • the thickness of the second barrier layer is greater than the thickness of the first barrier layer and the third barrier layer.
  • the thickness of the fourth barrier layer is greater than the thicknesses of the first barrier layer and the third barrier layer.
  • the first barrier layer, the second barrier layer, and the third barrier layer are all or partly doped n-type, and the fourth barrier layer is an unintentional doped layer. More preferably, the concentration of the n-type doping is 1E17/cm 2 to 1E19/cm 2 .
  • the number of periods of the first light-emitting area is 1-5, and the number of periods of the second light-emitting area is 1-5.
  • the material composition of the quantum well structure in each period of the first and second light-emitting regions is the same.
  • the well layer is composed of Al x In y Ga 1-xy N material; the first barrier layer, the second barrier layer, the third barrier layer, and the fourth barrier layer are composed of Al p In q Ga 1-pq N material composition, in each period of the quantum well structure, 0 ⁇ x ⁇ p ⁇ 1;0 ⁇ q ⁇ y ⁇ 1.
  • the average Al composition percentages of the barrier layer materials of the two groups of light-emitting regions meet the following conditions: the first light-emitting region is smaller than the second light-emitting region; the average In composition percentages of the well layer materials of the two groups of light-emitting regions meet the following conditions Condition: The first light-emitting area is less than or equal to the second light-emitting area.
  • the average Al composition percentage content of the second barrier layer material is greater than the average Al composition percentage content of the first barrier layer and the third barrier layer material.
  • the average Al composition percentage of the fourth barrier layer material is greater than the average Al composition of the first barrier layer, the second barrier layer, and the third barrier layer material. Percentage content.
  • the light-emitting area further includes a third light-emitting area, the third light-emitting area includes a quantum well structure of n3 periods, and the third light-emitting area is located between the first light-emitting area and the second light-emitting area ,
  • the band gap of the barrier layer of the third light-emitting area is between the first light-emitting area and the second light-emitting area;
  • the band gap of the well layer of the third light-emitting area is between the first light-emitting area and the second light-emitting area between.
  • the average Al composition percentage of the barrier layer of the third light-emitting region is between the first light-emitting region and the second light-emitting region; the average In composition percentage of the well layer of the third light-emitting region is between Between the first light-emitting area and the second light-emitting area.
  • the third light-emitting area includes a first barrier layer, a second barrier layer, a third barrier layer, and a well layer; the band gap of the second barrier layer material in the third light-emitting area is larger than that of the first barrier layer.
  • the thickness of the second barrier layer in the third light-emitting region is greater than the thickness of the first barrier layer and the third barrier layer.
  • the thickness of the first barrier layer, the second barrier layer, and the third barrier layer in the third light-emitting region is in the range of 10 angstroms to 1000 angstroms; the thickness of the well layer is in the range of 1 angstroms to 100 angstroms .
  • the ratio of the total thickness of the first barrier layer, the second barrier layer, and the third barrier layer to the thickness of the well layer in the third light-emitting region is between 5:1 and 20:1.
  • the first barrier layer, the second barrier layer, and the third barrier layer in the third light-emitting region are all or part of n-type doping. More preferably, the concentration of the n-type doping is 1E17/cm 2 to 1E19/cm 2 .
  • the number of periods of the third light-emitting area is 0-5.
  • the material composition of the quantum well structure in each period of the third light-emitting region is the same.
  • the third light-emitting region well layer is composed of Al x In y Ga 1-xy N material; the first barrier layer, the second barrier layer, and the third barrier layer are composed of AL p In q Ga 1 -pq N material composition, 0 ⁇ x ⁇ p ⁇ 1; 0 ⁇ q ⁇ y ⁇ 1.
  • the average Al composition percentage of the material of the second barrier layer is greater than the average Al composition of the materials of the first barrier layer and the third barrier layer Percentage content.
  • the present invention proposes a method for preparing the aforementioned micro LED epitaxial structure, and the preparation method includes the following process steps:
  • the average growth rate of the first light-emitting region barrier layer is greater than the average growth rate of the second light-emitting region barrier layer; the average growth rate of the first light-emitting region well layer is greater than the average growth rate of the second light-emitting region well layer Growth rate.
  • the average growth rate of the first barrier layer and the third barrier layer is less than or equal to the average growth rate of the second barrier layer.
  • the growth rate of the barrier layer ranges from 0.1 to 10 angstroms/sec; the growth rate of the well layer ranges from 0 to 1 angstroms/sec.
  • the growth temperature of the barrier layer is 700-950°C; the growth temperature of the well layer is 700-900°C.
  • the growth mode of the barrier layer and the well layer of the composite light-emitting region is continuous growth or interrupted growth.
  • the present invention provides a micro light emitting diode, which includes the aforementioned epitaxial structure.
  • the horizontal size of the micro light-emitting diode is between 1 ⁇ m*1 ⁇ m and ⁇ 300 ⁇ m*300 ⁇ m.
  • the present invention also provides a light emitting device, which comprises the aforementioned micro light emitting diode.
  • the light-emitting layer is designed as a composite light-emitting area structure, which effectively suppresses carrier overflow in the light-emitting area, increases the overlap of electron-hole wave functions, and at the same time ensures that the stress of the light-emitting area material can be effectively released, thereby improving small current injection Under the carrier transport and recombination behavior, improve the carrier radiation recombination efficiency and photoelectric conversion efficiency;
  • the defect density of MQW growth can be reduced, the growth quality of MQW can be significantly improved, and non-radiation can be reduced.
  • the recombination center significantly reduces the peak photoelectric conversion efficiency corresponding to the current density and significantly improves the peak photoelectric conversion efficiency;
  • the lattice mismatch stress between the barrier layer and the well layer in the MQW region can be further improved, and the quality of the MQW crystal can be improved.
  • the main light-emitting layer of the LED is mainly the light-emitting layer close to the P-type side
  • the MQW (first light-emitting region) near the N-type side grows at a relatively high speed
  • the MQW (second light-emitting region) near the P-type layer side grows at a low speed.
  • FIG. 1 is a schematic diagram of the epitaxial structure of the first embodiment.
  • FIG. 2 is a schematic diagram of the structure of the first light-emitting area in the first embodiment.
  • FIG. 3 is a schematic diagram of the structure of the third light-emitting area in the first embodiment.
  • FIG. 4 is a schematic diagram of the structure of the second light-emitting area in the first embodiment.
  • FIG. 5 is a schematic diagram of the energy band structure of the composite light-emitting region in the first embodiment.
  • FIG. 6 is a schematic diagram of the structure of the first light-emitting area in the second embodiment.
  • FIG. 7 is a schematic diagram of the structure of the third light-emitting area in the second embodiment.
  • FIG. 8 is a schematic diagram of the structure of the second light-emitting area in the second embodiment.
  • Figure 9 is a WPE (photoelectric conversion efficiency)-J (current density) trend graph of a conventional epitaxial structure LED.
  • Fig. 10 is a comparison of the brightness (LOP)-wavelength (WLD) of the micro LED with the epitaxial structure at a current density of 0.5 A/cm 2 and the conventional structure in the first embodiment.
  • FIG. 11 is a comparison of the test data of WPE (photoelectric conversion efficiency)-J (current density) of the micro LED with an epitaxial structure in the first embodiment and the traditional structure.
  • first light-emitting region 5 including first barrier layer 5A, second barrier layer 5B, The third barrier layer 5C, the well layer 5D
  • the third light emitting area 6 including the first barrier layer 6A, the second barrier layer 6B, the third barrier layer 6C, the well layer 6D
  • the second light emitting area 7 Including first barrier layer 7A, second barrier layer 7B, third barrier layer 7C, well layer 7D, fourth barrier layer 7G
  • PGaN layer 8 first well layer 52D/62D/72D, second The well layer 52E/62E/72E, and the third well layer 52F/62F/72F.
  • this embodiment provides a micro LED epitaxial structure and a manufacturing method thereof, including the following process steps:
  • a substrate 1 which can be selected from sapphire (Al 2 O 3 ), AlN-plated or SiNx sapphire (Al 2 O 3 ), Ga 2 O 3 , AlN-plated or SiNxGa 2 O 3 , SiC, GaN, At least one of ZnO, Si or Ge.
  • the AlN sapphire substrate is preferably plated.
  • AlGaN material is preferred, and the epitaxial growth method can be MOCVD (metal organic chemical vapor deposition) method, MBE (molecular beam epitaxy) method, CVD ( Chemical vapor deposition) method, HVPE (hydride vapor phase epitaxy) method, PECVD (plasma enhanced chemical vapor deposition) method, MOCVD is preferred, but the embodiment is not limited thereto.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • CVD Chemical vapor deposition
  • HVPE hydrogen vapor phase epitaxy
  • PECVD plasma enhanced chemical vapor deposition
  • MOCVD metal organic chemical vapor deposition
  • U-GaN layer 2 and N-GaN layer 3 are epitaxially grown sequentially on the nucleation layer.
  • the U-GaN layer 2 The crystallization performance of the semiconductor layer formed on the layer is enhanced, and this embodiment is not limited to this.
  • the growth mode of the U-GaN layer 2 is three-dimensional mode + two-dimensional mode.
  • island-like growth is first formed to maximize the reversal and merging of dislocations, and then it is converted to a two-dimensional mode to form a flat
  • the growth thickness is about 1 ⁇ 3um.
  • the N-GaN layer 3 is grown.
  • the thickness of the N-GaN layer 3 is 1 to 3 um, and the doping level is between 1E19 to 2.5E19/cm 2 .
  • Stress release layer 4 cool to 750-950°C, grow stress release layer
  • the material is preferably InGaN and GaN, which is an alternately grown superlattice structure or a combination of materials in it, the purpose is to further reduce the subsequent light-emitting layer
  • the misfit dislocations between the high In composition material and the underlying GaN material relieve stress and improve crystal quality.
  • the temperature of the first light-emitting area 5 is changed to the temperature of the barrier layer, and the first barrier layer 5A is grown at 800-900°C.
  • the first barrier layer is preferably made of Si-doped GaN material with a thickness of about 5°C. ⁇ 50 Angstroms, the growth rate is about 0.9 Angstroms/s, and the Si doping level is about 1E17/cm 2 ⁇ 1E19/cm 2 .
  • the second barrier layer 5B is grown at a temperature of 10-50°C.
  • the second barrier layer is made of Si-doped AlGaN material with a thickness of about 30-100 angstroms and a growth rate of about 1.5 angstroms/s , TMAL 2sccm is introduced, the Al composition is about 1-10%, and the preferred embodiment is 1.5%, and the Si doping level is about 1E17/cm 2 -1E19/cm 2 .
  • TMAL 2sccm is introduced
  • the Al composition is about 1-10%
  • the preferred embodiment is 1.5%
  • the Si doping level is about 1E17/cm 2 -1E19/cm 2 .
  • the growth rate It is about 0.9 Angstroms/s, and the Si doping level is about 1E17/cm 2 to 1E19/cm 2 .
  • the material is InGaN, and enter TMIN 800sccm, the thickness is about 5-50 angstroms, and the growth rate is about 0.3 angstroms /s, the preferred embodiment is 20 angstroms, and the average In composition of the well layer is about 18%.
  • the number of periods of the first light-emitting region is 1 to 5, and the material composition of the quantum well structure in each period is the same.
  • the number of alternate stacking of the first light-emitting regions is preferably 2 times.
  • the band gap of the second barrier layer material is greater than or equal to the band gaps of the first barrier layer and the third barrier layer material, in order to effectively suppress carrier overflow and adjust the energy band structure of the light-emitting region.
  • the temperature change and growth rate change of the first barrier layer, the first barrier layer, and the third barrier layer are designed to improve the MQW by adjusting the growth rate of the barrier layer in different growth temperature ranges while improving production efficiency.
  • the crystal quality of the zone material is designed to improve the MQW by adjusting the growth rate of the barrier layer in different growth temperature ranges while improving production efficiency.
  • GaN material is preferred, which is an unintentionally doped layer, and the growth rate is about 0.6 angstroms/s, thickness is about 5-50 angstroms.
  • the second barrier layer 6B is grown at a temperature of 10-50°C, the material of the second barrier layer is Si-doped AlGaN material, the growth rate is about 0.9 angstroms/s, and the thickness is about 30-100 Angstroms, pass TMAL 2.5 sccm, the Al composition is about 1-10%, and the preferred embodiment is 2%, and the Si doping level is about 1E17/cm 2 -1E19/cm 2 .
  • the third barrier layer 6C is made of Si-doped GaN material, and the growth rate is about 0.6 angstroms/s.
  • the thickness is about 5-50 angstroms, and the Si doping level is about 1E17/cm 2 to 1E19/cm 2 .
  • the material is InGaN
  • the introduction of TMIN 900sccm the growth rate is about 0.2 angstroms/s
  • the thickness is about 5 ⁇ 50 angstroms, preferably 20 angstroms in this embodiment
  • the average In composition of the well layer is about 19%.
  • the number of periods of the third light-emitting region is 0-5, and the material composition of the quantum well structure in each period is the same. In this embodiment, the number of alternate stacking of the third light-emitting regions is preferably 2 times.
  • the average band gap of the barrier layer of the third light-emitting area is greater than that of the first light-emitting area, and the average band gap of the well layer of the third light-emitting area is smaller than the average band gap of the first light-emitting area.
  • the carrier overflow in the light-emitting area of the type side is effectively suppressed, while ensuring that the stress of the material in the light-emitting area is effectively released, thereby improving the carrier transport and recombination behavior under small current injection; the barrier layer of the third light-emitting area
  • the growth rate is less than or equal to the growth rate of the barrier layer in the first light-emitting region, and the growth rate of the well layer in the third light-emitting region is less than or equal to the growth rate of the well layer in the first light-emitting region.
  • the growth rate can get better crystal quality.
  • the temperature is raised to 800-900°C to grow the second light-emitting region 7.
  • the first barrier layer 7A is grown.
  • GaN material is preferred, which is an unintentionally doped layer, and the growth rate is The thickness is about 0.3 angstroms/s and the thickness is about 5-50 angstroms.
  • the second barrier layer 7B is grown at a temperature of 10-50°C.
  • the material of the second barrier layer is Si-doped AlGaN material.
  • the growth rate is about 0.5 angstroms/s, the thickness is about 30-100 angstroms, and TMAL 3sccm is introduced.
  • the Al composition is about 1-10%. In this embodiment, 2.5% is preferred.
  • the Si doping level is about 1E17/cm 2 ⁇ 1E19/cm 2 .
  • the temperature is lowered to 700-800°C, and the well layer 7D is grown, the material is InGaN, the TMIN is 1000sccm, the growth rate is about 0.1 angstroms/s, and the thickness is about 5-50 angstroms. For example, 20 angstroms is preferred, and the average In composition of the well layer is about 20%.
  • the temperature is raised to 800-900°C to grow the fourth barrier layer 7G.
  • the material of the fourth barrier layer is GaN/AlGaN, the rate is 0.5 angstroms/s, and the thickness is about 50-100 angstroms.
  • the average composition of the barrier layer Al is about 5-50%, and 15% is preferred in this embodiment.
  • the number of periods of the second light-emitting region is 1 to 5, and the material composition of the quantum well structure in each period is the same.
  • the number of alternate stacking of the second light-emitting regions is preferably one.
  • the average band gap of the barrier layer of the second light-emitting region is larger than the average band gap of the third light-emitting region and the first light-emitting region, and the average band gap of the well layer of the second light-emitting region is smaller than that of the third light-emitting region and the first light-emitting region.
  • the average band gap of a light-emitting region; the band gap of the fourth barrier layer material is greater than or equal to the band gap of the first barrier layer, the second barrier layer, and the third barrier layer.
  • the material band gap of the fourth barrier layer is designed The highest is to effectively block the overflow of electrons and improve the carrier transport and recombination behavior under small current injection.
  • the growth rate of the well layer in the second light-emitting area is less than or equal to the growth rate of the third light-emitting area and the well layer of the first light-emitting area. The purpose is to pass the light-emitting area close to the P-type side with a lower growth rate to obtain better crystals. Quality, thereby improving the carrier recombination behavior under low current injection, and then improving the luminous efficiency under low current injection.
  • this embodiment improves the carrier injection efficiency and recombination efficiency by designing the composite structure design of the MQW light-emitting region, can effectively suppress carrier overflow, increase electron-hole wave function overlap, and improve the low current injection Carrier transport and recombination behavior; control the thickness and growth rate of different regions of MQW growth, reduce the lattice mismatch between MQW and the bottom layer, and the trap barrier in the MQW, reduce stress, improve the growth quality of MQW, and achieve peak efficiency Move to low current density to improve luminous efficiency at low current.
  • a low-temperature P-type layer is grown.
  • the purpose is to protect the MQW from being damaged by the subsequent high temperature, and on the other hand, to provide higher hole injection.
  • the epitaxial wafer with the epitaxial structure is used to prepare an LED chip.
  • the horizontal size of the chip is 19 ⁇ m*31 ⁇ m. It is tested in the chip state. As shown in Figure 10, the data can be seen. At a current density of 0.5A/cm 2, The brightness is increased by about 30% compared to the traditional structure.
  • the photoelectric conversion efficiency (WPE) and the current density (J) change test as shown in Figure 11, the data can be seen, the current density (J) corresponding to the peak photoelectric conversion efficiency (peak-WPE) is 4.0A/cm 2 Decrease to 0.7A/cm 2 .
  • this embodiment is a multi-well layer design, as follows:
  • the first light-emitting area refer to Figure 6.
  • the first well layer 52D starts to grow when the temperature is lowered to the temperature of the well layer (700 ⁇ 800°C), and TMIN 1000sccm is introduced.
  • the material is InGaN, and the rate is about 0.6 angstroms/s.
  • the thickness is about 3 to 8 angstroms.
  • the second well layer 52E is grown, the material is InGaN, the rate is about 0.3 angstroms/s, and the thickness is about 5 to 15 angstroms.
  • the third well layer 52F starts to grow during the process of heating up to the barrier layer temperature (800-900°C), the material is InGaN, the rate is about 0.6 angstroms/s, and the thickness is about 3-8 angstroms.
  • the average In composition is about 20%.
  • the third light-emitting area refer to Figure 7.
  • the first well layer 62D begins to grow when the temperature is lowered to the temperature of the well layer (700 ⁇ 800°C).
  • the material is InGaN, and TMIN 1000sccm is inserted, the rate is about 0.4 angstroms/s, and the thickness
  • the second well layer 62E is grown, the material is InGaN, the rate is about 0.2 angstroms/s, and the thickness is about 5 to 15 angstroms.
  • the third well layer 62F starts to grow when the temperature is raised to the barrier layer temperature (800-900° C.), the material is InGaN, the rate is about 0.4 angstroms/s, and the thickness is about 3 to 8 angstroms.
  • the average In composition is about 20%.
  • the second light-emitting area refer to Figure 8.
  • the temperature is lowered to the temperature of the well layer (700-800°C), and the first well layer 72D begins to grow.
  • the material is InGaN, and TMIN 1000 sccm is inserted at a rate of about 0.2 Angstroms/s.
  • the thickness is about 3 to 8 angstroms.
  • the second well layer 72E is grown, the material is InGaN, the rate is about 0.1 angstroms/s, and the thickness is about 5 to 15 angstroms.
  • the second well layer 72E is grown After the end, the third well layer 72F starts to grow during the process of raising the temperature to the barrier layer temperature (800-900° C.), the material is InGaN, the rate is about 0.1 angstroms/s, and the thickness is about 3-8 angstroms.
  • the average In composition is about 20%.
  • This embodiment is a multi-well layer design, in order to further reduce the lattice mismatch stress between the high In composition well layer and the barrier layer.
  • This design can further improve the single growth by adjusting the growth rate of the well layer in different growth temperature ranges.
  • the mismatch stress of the barrier well layer in the period improves the quality of the MQW crystal, thereby improving the low current characteristics of the device.
  • the composite light-emitting area is a combination of the first light-emitting area and the second light-emitting area.
  • Epitaxial structure substrate, nucleation layer, UGaN, NGaN layer, stress relief layer, P-type layer.
  • the description of the light-emitting area is as follows: The difference from the first embodiment is that the material of the fourth barrier layer of the second light-emitting area is a combination of GaN/AlGaN/AlN or its overlapping combination structure, such as (GaN/AlGaN/AlN) overlapping N times, (GaN/AlGaN) overlap N times/AlN, GaN/(AlGaN/AlN) overlap N times, 1 ⁇ N ⁇ 20.
  • the average Al composition ranges from 5% to 50%.
  • the fourth barrier layer of this embodiment is designed as a combination of GaN/AlGaN/AlN or its overlapping combination structure, and the purpose is to further reduce electron overflow, increase electron-hole wave function overlap, and improve loading under small current injection.
  • the current recombination behavior improves the brightness at low current density.

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Abstract

本发明提出一种微LED外延结构，该外延结构至少包括N型层、发光层、P型层。其中发光层包括n个周期的量子阱结构，每一个周期的量子阱结构包括阱层和势垒层，其中n1个周期的量子阱结构定义为第一发光区，n2个周期的量子阱结构定义为第二发光区，n1和n2大于等于1，且n1+n2小于等于n，第一发光区比第二发光区更接近N型层，两组发光区势垒层材料的平均带隙满足以下条件：第一发光区小于第二发光区；两组发光区阱层材料的平均带隙满足以下条件：第一发光区大于等于第二发光区。利用该外延结构制备的微LED，可实现峰值光电转换效率对应电流密度低于1A/cm 2，且光电转换效率提升约30%。

Description

一种微发光二极管外延结构及其制备方法 技术领域
本发明涉及一种微LED发光元件，属于半导体光电技术领域。
背景技术
传统外延结构LED的峰值光电转换效率分布在大于5A/cm 2的电流密度区间，如图9所示，现有应用多数工作在高电流密度(大于10A/cm 2)区域。然而，手机(或手表、手环)上用的Micro LED使用的电流非常小，往往在nA级的水平，换算成电流密度，在0.1～1A/cm 2之间。传统外延结构在低于1A/cm 2电流密度下，其光电转换效率处在非常不稳定的区间，随着电流的微小变化，光电转换效率亦会出现急速下降，导致传统结构外延片无法应用于低电流密度工作需求的产品。
因此，针对手机(或手表、手环)用途的Micro LED芯片，需要开发出峰值光电转换效率在低电流密度区间内、光电转换效率稳定的LED外延片。
专利CN107833953A提出的一种Micro LED多量子阱层的生长方法。MQW结构为阱层(InGaN)/阻挡层(GaN)/势垒层(GaN通H2)，通过在势垒层中通入H2、在垒阱层之间插入阻挡层，对于MQW的晶格质量与垒阱应力的改善有限，有必要提出进一步提升微发光二极管低电流特性的技术方案。
发明概述
技术问题
问题的解决方案
技术解决方案
为了解决现有技术中存在的问题，本发明旨在提供一种微LED外延结构及其制备方法。
作为本发明的一个方面，本发明提出一种微LED外延结构，所述微LED外延结构至少包括N型层、发光层、P型层，其中发光层包括n个周期的量子阱结构，每一个周期的量子阱结构包括阱层和势垒层，其中n1个周期的量子阱结构定义为 第一发光区，n2个周期的量子阱结构定义为第二发光区，n1和n2大于等于1，且n1+n2小于等于n，第一发光区比第二发光区更接近N型层。两组发光区势垒层材料的平均带隙满足以下条件：第一发光区小于第二发光区；两组发光区阱层材料的平均带隙满足以下条件：第一发光区大于等于第二发光区。
优选的，所述第一发光区每一周期的量子阱结构至少包含第一势垒层、第二势垒层、第三势垒层、阱层，其中第二势垒层位于第一势垒层和第三势垒层之间，在第一发光区内，每一量子阱结构的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙。
优选的，所述第二发光区每一周期的量子阱结构至少包含第一势垒层、第二势垒层、第三势垒层、阱层、第四势垒层，其中第二势垒层位于第一势垒层和第三势垒层之间，第四势垒层位于阱层之后，在第二发光区内，每一量子阱结构的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙，第四势垒层的带隙大于第一势垒层、第二势垒层、第三势垒层材料的带隙。
优选的，所述第一势垒层、第二势垒层、第三势垒层、第四势垒层的厚度范围为10埃～1000埃；所述阱层的厚度范围为1埃～100埃。更优选地，每一周期的量子阱结构中，第一势垒层、第二势垒层、第三势垒层的总厚度与阱层的厚度比在5∶1～20∶1之间；第四势垒层厚度与阱层的厚度比在5∶1～20∶1之间。
优选的，在每一个周期量子阱结构中，第二势垒层的厚度大于第一势垒层、第三势垒层的厚度。
优选的，在所述第二发光区的量子阱结构中，第四势垒层的厚度大于第一势垒层、第三势垒层的厚度。
优选的，所述的两组发光区内，第一势垒层、第二势垒层、第三势垒层为全部或部分n型掺杂，第四势垒层为非故意掺杂层。更优选地，所述n型掺杂的浓度为1E17/cm 2～1E19/cm 2。
优选的，所述第一发光区的周期数为1～5，第二发光区的周期数为1～5。所述第一和第二发光区的每个周期内的量子阱结构的材料组分是相同的。
优选的，所述阱层由Al xIn yGa 1-x-yN材料组成；所述第一势垒层、第二势垒层、第三势垒层、第四势垒层由AL pIn qGa 1-p-qN材料组成，在每一个周期的量子阱 结构中，0≤x＜p＜1；0≤q＜y＜1。
优选的，两组发光区势垒层材料的平均Al组分百分含量满足以下条件：第一发光区小于第二发光区；两组发光区阱层材料的平均In组分百分含量满足以下条件：第一发光区小于等于第二发光区。在每一量子阱结构内，第二势垒层材料的平均Al组分百分含量大于第一势垒层、第三势垒层材料的平均Al组分百分含量。在所述第二发光区的量子阱结构内，第四势垒层材料的平均Al组分百分含量大于第一势垒层、第二势垒层、第三势垒层材料的平均Al组分百分含量。
作为本发明的另一种实施方式，所述发光区还包含第三发光区，第三发光区包括n3个周期的量子阱结构，第三发光区位于第一发光区和第二发光区之间，所述第三发光区的势垒层的带隙介于第一发光区和第二发光区之间；所述第三发光区阱层的带隙介于第一发光区和第二发光区之间。
优选的，所述第三发光区势垒层平均Al组分百分含量介于第一发光区和第二发光区之间；所述第三发光区阱层平均In组分百分含量介于第一发光区和第二发光区之间。
优选的，所述第三发光区包含第一势垒层、第二势垒层、第三势垒层、阱层；所述第三发光区中的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙。
优选的，所述第三发光区中的第二势垒层的厚度大于第一势垒层、第三势垒层的厚度。
优选的，所述第三发光区中第一势垒层、第二势垒层、第三势垒层的厚度范围为10埃～1000埃；所述阱层的厚度范围为1埃～100埃。所述第三发光区中第一势垒层、第二势垒层、第三势垒层的总厚度与阱层的厚度比在5∶1～20∶1之间。
优选的，所述第三发光区中第一势垒层、第二势垒层、第三势垒层为全部或部分n型掺杂。更优选地，所述n型掺杂的浓度为1E17/cm 2～1E19/cm 2。
优选的，所述第三发光区的周期数为0～5。所述第三发光区的每个周期内的量子阱结构的材料组分是相同的。
优选的，所述第三发光区阱层由Al xIn yGa 1-x-yN材料组成；所述第一势垒层、第二势垒层、第三势垒层由AL pIn qGa 1-p-qN材料组成，0≤x＜p＜1；0≤q＜y＜1。
优选的，在所述第三发光区的每一量子阱结构内，第二势垒层材料的平均Al组分百分含量大于第一势垒层、第三势垒层材料的平均Al组分百分含量。
作为本发明的第二方面，本发明提出一种制备前述微LED外延结构的方法，所述制备方法包括以下工艺步骤：
(1)提供一衬底；
(2)在所述衬底上生长成核层、N型层、发光层；
(3)生长P型层。
优选的，所述第一发光区势垒层的平均生长速率大于第二发光区势垒层的平均生长速率；所述第一发光区阱层的平均生长速率大于第二发光区阱层的平均生长速率。
优选的，每一量子阱结构内，第一势垒层和第三势垒层的平均生长速率小于等于第二势垒层的平均生长速率。
优选的，势垒层的生长速率范围0.1～10埃/秒；阱层的生长速率范围0～1埃/秒。优选的，势垒层的生长温度为700～950℃；阱层的生长温度为700～900℃。
优选的，复合发光区势垒层、阱层的生长方式为连续生长或者中断生长。
作为本发明的第三个方面，本发明提供微发光二极管，所述微发光二极管包括前述的外延结构。
优选的，所述微发光二极管，其水平尺寸在1μm*1μm～～300μm*300μm之间。
本发明还提供一种发光装置，所述发光装置包括前述的微发光二极管。
发明的有益效果
有益效果
本发明提出的微LED外延结构及其微发光二极管，具有以下有益效果：
(1)发光层设计为复合发光区结构，使得发光区载流子溢流得到有效抑制，增加电子空穴波函数交叠，同时又保证发光区材料的应力得以有效释放，从而改善小电流注入下的载流子输运和复合行为，提高载流子辐射复合效率和光电转换效率；
(2)每个发光区通过生长较薄的阱层，较厚的势垒层，较大的垒阱层厚度比，可以减小MQW生长的缺陷密度，显著改善MQW的生长质量，减少非辐射复 合中心，使得峰值光电转换效率对应电流密度明显减小，峰值光电转换效率明显提升；
(3)通过不同发光区的不同生长速率的设定，可以进一步改善MQW区域势垒层与阱层的晶格失配应力，改善MQW晶体质量。因为LED主发光层主要为靠近P型侧的发光层，通过在靠近N型侧的MQW(第一发光区)相对高速生长，在靠近P型层侧的MQW(第二发光区)低速生长，可以进一步降低发光层高In区域与底层GaN的晶格失配应力，可以有效提升MQW主发光区的晶格质量，同时保持较短的生长时间，提高生产效率；
(4)在每个量子阱周期内，通过调整不同生长温度区间的势垒层和阱层长速，可以进一步改善单个发光区生长周期内势垒层和阱层的晶格失配应力，改善MQW晶体质量。
对附图的简要说明
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1是实施例一的外延结构示意图。
图2是实施例一的第一发光区的结构示意图。
图3是实施例一的第三发光区的结构示意图。
图4是实施例一的第二发光区的结构示意图。
图5是实施例一复合发光区的能带结构示意图。
图6是实施例二的第一发光区的结构示意图。
图7是实施例二的第三发光区的结构示意图。
图8是实施例二的第二发光区的结构示意图。
图9是传统外延结构LED的WPE(光电转换效率)-J(电流密度)趋势图。
图10是实施例一外延结构的微LED在电流密度0.5A/cm 2下亮度(LOP)-波长(WLD)与传统结构的对比。
图11是实施例一外延结构的微LED WPE(光电转换效率)-J(电流密度)测试数据与传统结构的对比。
补充图中元件标号说明：衬底1，U-GaN层2，N-GaN层3，应力释放层4，第一发光区5(包括第一势垒层5A，第二势垒层5B，第三势垒层5C，阱层5D)，第三发光区6(包括第一势垒层6A，第二势垒层6B，第三势垒层6C，阱层6D)，第二发光区7(包括第一势垒层7A，第二势垒层7B，第三势垒层7C，阱层7D，第四势垒层7G)，PGaN层8，第一阱层52D/62D/72D，第二阱层52E/62E/72E，第三阱层52F/62F/72F。
发明实施例
本发明的实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一
请参照图1～图5，基于本发明的目的，本实施例提供一种微LED外延结构及其制作方法，包括以下工艺步骤：
(1)提供一衬底1，可以选用蓝宝石(Al 2O 3)、镀AlN或镀SiNx蓝宝石(Al 2O 3)、Ga 2O 3、镀AlN或镀SiNxGa 2O 3、SiC、GaN、ZnO、Si或Ge中的至少一种，本实施例优选镀AlN蓝宝石衬底。
(2)在衬底1上外延生长成核层(图中未示出)：优选AlGaN材料，外延生长方法可以选用MOCVD(金属有机化学气相沉积)方法、MBE(分子束外延)方法、CVD(化学气相沉积)方法、HVPE(氢化物气相外延)方法、PECVD(等离子体增强化学气相沉积)方法，优选MOCVD，但实施例不限于此。将镀AlN蓝宝石衬底放入金属有机化学气相沉积(MOCVD)室，先进行氢化处理以去除衬底表面的杂质，然后将温度降到500～600℃左右，生长厚度约为20nm的成核层。
(3)在成核层上依次外延生长U-GaN层2和N-GaN层3，U-GaN层2为了减少衬 底和N-GaN层之间晶格常数差导致的晶格失配，增强形成在该层上的半导体层结晶性能，本实施例不以此为限。U-GaN层2的生长模式为三维模式+二维模式，在成核层基础上，首先形成岛状生长，以最大程度地使得位错发生转向与合并，之后转为二维模式，形成平整的表面，生长厚度约为1～3um。之后生长N-GaN层3，N-GaN层3厚度为1～3um，掺杂水平在1E19～2.5E19/cm 2之间。
(4)应力释放层4，降温至750～950℃，生长应力释放层，材料优选InGaN与GaN，为交替生长的超晶格结构或其中材料的组合形式，目的是进一步减小后续发光层的高In组分材料与底层GaN材料的失配位错，释放应力，改善晶体质量。
(5)第一发光区5，温度变化至势垒层温度，在800～900℃，生长第一势垒层5A，本实施例优选第一势垒层为掺Si GaN材料，厚度约为5～50埃，生长速率约为0.9埃/s，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第一势垒层5A生长结束后，升温10～50℃生长第二势垒层5B，第二势垒层为掺Si AlGaN材料，厚度约为30～100埃，生长速率约为1.5埃/s，通入TMAL 2sccm，Al的组分约为1～10％，本实施例优选1.5％，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第二势垒层5B生长结束后，停止通入TMAL，降温10～50℃生长第三势垒层5C，第三势垒层5C为掺Si GaN材料，厚度约为5～50埃，生长速率约为0.9埃/s，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第三势垒层5C生长结束后，停止通入SiH4，降温至700～800℃，生长阱层5D，材料为InGaN，通入TMIN 800sccm，厚度约为5～50埃，生长速率约为0.3埃/s，本实施例优选20埃，阱层的平均In组分约为18％。第一发光区的周期数为1～5，每个周期内的量子阱结构的材料组分是相同的。本实施例中，第一发光区交替堆叠次数优选2次。其中，第二势垒层材料的带隙大于等于第一势垒层和第三势垒层材料的带隙，目的是为了有效抑制载流子溢流，调节发光区的能带结构。第一势垒层、第一势垒层、第三势垒层的温度变化和生长速率变化，目的是为了在提高生产效率的同时，通过调整不同生长温度区间的势垒层长速，改善MQW区材料的晶体质量。
(6)第三发光区6，升温至800～900℃，生长第三发光区6，首先生长第一势垒层6A，本实施例优选GaN材料，为非故意掺杂层，生长速率约为0.6埃/s，厚度约为5～50埃。第一势垒层6A生长结束后，升温10～50℃生长第二势垒层6B，第二 势垒层材料为掺Si AlGaN材料，生长速率约为0.9埃/s，厚度约为30～100埃，通入TMAL 2.5sccm，Al的组分约为1～10％，本实施例优选2％，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第二势垒层6B生长结束后，停止通入TMAL，降温升温10～50℃生长第三势垒层6C，第三势垒层6C为掺Si GaN材料，生长速率约为0.6埃/s，厚度约为5～50埃，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第三势垒层6C生长结束后，停止通入SiH4，降温至700～800℃，生长阱层6D，材料为InGaN，通入TMIN 900sccm，生长速率约为0.2埃/s，厚度约为5～50埃，本实施例优选20埃，阱层的平均In组分约为19％。第三发光区的周期数为0～5，每个周期内的量子阱结构的材料组分是相同的。本实施例中，第三发光区交替堆叠次数优选2次。其中，第三发光区势垒层的平均带隙大于第一发光区的平均带隙，第三发光区的阱层的平均带隙小于第一发光区的平均带隙，目的是有效保证靠近P型侧发光区的载流子溢流得到有效抑制，同时又保证发光区材料的应力得以有效释放，进而改善小电流注入下的载流子输运和复合行为；第三发光区势垒层的生长速率小于等于第一发光区势垒层的生长速率，第三发光区阱层的生长速率小于等于第一发光区阱层的生长速率，目的是为了通过靠近P型侧的发光区，较低的生长速率，可以得到更好的晶体质量。
(7)第三发光区生长结束后，升温至800～900℃，生长第二发光区7，首先生长第一势垒层7A，本实施例优选GaN材料，为非故意掺杂层，生长速率约为0.3埃/s，厚度约为5～50埃，第一势垒层7A生长结束后，升温10～50℃生长第二势垒层7B，第二势垒层材料为掺Si AlGaN材料，生长速率约为0.5埃/s，厚度约为30～100埃，通入TMAL 3sccm，Al的组分约为1～10％，本实施例优选2.5％，Si掺杂水平约为1E17/cm 2～1E19/cm 2。第二势垒层7B生长结束后，停止通入TMAL，降温10～50℃生长第三势垒层7C，第三势垒层7C为掺Si GaN材料，生长速率约为0.3埃/s，厚度约为5～50埃。第三势垒层7C生长结束后，降温至700～800℃，生长阱层7D，材料为InGaN，通入TMIN 1000sccm，生长速率约为0.1埃/s，厚度约为5～50埃，本实施例优选20埃，阱层的平均In组分约为20％。阱层生长结束后，升温至800～900℃，生长第四势垒层7G，第四势垒层的材料为GaN/AlGaN，速率为0.5埃/s，厚度约为50～100埃，第四势垒层Al的平均组分约为5～50％，本实施例优 选15％。第二发光区的周期数为1～5，每个周期内的量子阱结构的材料组分是相同的。本实施例中，第二发光区交替堆叠次数优选1次。如图5所示，第二发光区势垒层的平均带隙大于第三发光区和第一发光区的平均带隙，第二发光区的阱层的平均带隙小于第三发光区和第一发光区的平均带隙；第四势垒层材料的带隙大于等于第一势垒层、第二势垒层、第三势垒层材料的带隙，设计第四垒层的材料带隙最高，是为了有效阻挡电子溢流，改善小电流注入下的载流子输运和复合行为。第二发光区阱层的生长速率小于等于第三发光区和第一发光区阱层的生长速率，目的是为了通过靠近P型侧的发光区，较低的生长速率，可以得到更好的晶体质量，从而改善小电流注入下的载流子复合行为，进而提升小电流注入下的发光效率。
综上，该实施例通过设计MQW发光区域的复合结构设计，提高载流子注入效率和复合效率，可有效抑制载流子溢流，增加电子空穴波函数交叠，从而改善小电流注入下的载流子输运和复合行为；控制MQW生长不同区域的厚度与长速，减小MQW与底层、MQW中阱垒的晶格失配，减小应力，改善MQW的生长质量，使得峰值效率向小电流密度移动，提升低电流下发光效率。
(8)发光层长完后，生长低温P型层，一方面目的是保护MQW不被后续的高温破坏，一方面提供较高的空穴注入。
(9)之后，升温生长高温PAlGaN和高温PGaN层，填平表面。
(10)利用该外延结构的外延片，制备为LED芯片，芯片水平尺寸为19μm*31μm，在芯片状态下测试，如图10所示，数据可见，在0.5A/cm 2的电流密度下，亮度相比传统结构提升约30％。封装之后，进行光电转换效率(WPE)随电流密度(J)变化测试，如图11所示，数据可见，峰值光电转换效率(peak-WPE)对应的电流密度(J)由4.0A/cm 2下降至0.7A/cm 2。
实施例二
在本实施例中，提供替代性的实施方案，具体的提供如下。
发光区说明如下：与实施例一不同之处在于如下，本实施例为多阱层设计，如下：
第一发光区：可参考图6。第三势垒层5C生长结束后，降温至阱层温度(700～8 00℃)过程中即开始生长第一阱层52D，通入TMIN 1000sccm，材料为InGaN，速率约为0.6埃/s，厚度约为3～8埃，第一阱层生长结束后，生长第二阱层52E，材料为InGaN，速率约为0.3埃/s，厚度约为5～15埃，第二阱层生长结束后，升温至势垒层温度(800～900℃)过程中即开始生长第三阱层52F，材料为InGaN，速率约为0.6埃/s，厚度约为3～8埃。平均In组分约为20％。
第三发光区：可参考图7。第三势垒层6C生长结束后，降温至阱层温度(700～800℃)过程中即开始生长第一阱层62D，材料为InGaN，通入TMIN 1000sccm，速率约为0.4埃/s，厚度约为3～8埃，第一阱层生长结束后，生长第二阱层62E，材料为InGaN，速率约为0.2埃/s，厚度约为5～15埃，第二阱层生长结束后，升温至势垒层温度(800～900℃)过程中即开始生长第三阱层62F，材料为InGaN，速率约为0.4埃/s，厚度约为3～8埃。平均In组分约为20％。
第二发光区：可参考图8。第三势垒层7C生长结束后，降温至阱层温度(700～800℃)过程中，即开始生长第一阱层72D，材料为InGaN，通入TMIN 1000sccm，速率约为0.2埃/s，厚度约为3～8埃，第一阱层72D生长结束后，生长第二阱层72E，材料为InGaN，速率约为0.1埃/s，厚度约为5～15埃，第二阱层72E生长结束后，升温至势垒层温度(800～900℃)过程中即开始生长第三阱层72F，材料为InGaN，速率约为0.1埃/s，厚度约为3～8埃。平均In组分约为20％。
本实施例为多阱层设计，是为了进一步减小高In组分阱层与势垒层的晶格失配应力，此设计通过调整不同生长温度区间的阱层长速，可以进一步改善单个生长周期内的垒阱层的失配应力，改善MQW晶体质量，从而改善器件的低电流特性。
实施例三
在本实施例中，提供替代性的实施方案，具体的提供如下。与实施例一不同之处在于，复合发光区为第一发光区和第二发光区的组合形式。
实施例四
在本实施例中，提供替代性的实施方案，具体的提供如下。外延结构：衬底、成核层、UGaN、NGaN层、应力释放层、P型层。发光区说明如下：与实施例一不同之处在于，第二发光区的第四势垒层材料为GaN/AlGaN/AlN的组合或者其 交叠组合结构，如(GaN/AlGaN/AlN)交叠N次、(GaN/AlGaN)交叠N次/AlN、GaN/(AlGaN/AlN)交叠N次，1≤N≤20。Al平均组分范围5％～50％。本实施例的第四势垒层设计为GaN/AlGaN/AlN的组合或者其交叠组合结构，目的是为了进一步降低电子溢流，增加电子空穴波函数交叠，改善小电流注入下的载流子复合行为，提升低电流密度下亮度。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (35)

  1. 一种微LED外延结构：该外延结构至少包括N型层、发光层、P型层，其中发光层包括n个周期的量子阱结构，每一个周期的量子阱结构包括阱层和势垒层，其中n1个周期的量子阱结构定义为第一发光区，n2个周期的量子阱结构定义为第二发光区，n1和n2大于等于1，且n1+n2小于等于n，第一发光区比第二发光区更接近N型层，两组发光区势垒层材料的平均带隙满足以下条件：第一发光区小于第二发光区；两组发光区阱层材料的平均带隙满足以下条件：第一发光区大于等于第二发光区。
  2. 根据权利要求1所述的一种微LED外延结构，其特征在于：所述第一发光区每一周期的量子阱结构至少包含第一势垒层、第二势垒层、第三势垒层、阱层，其中第二势垒层位于第一势垒层和第三势垒层之间，在第一发光区内，每一量子阱结构的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙。
  3. 根据权利要求1所述的一种微LED外延结构，其特征在于：所述第二发光区每一周期的量子阱结构至少包含第一势垒层、第二势垒层、第三势垒层、阱层、第四势垒层，其中第二势垒层位于第一势垒层和第三势垒层之间，第四势垒层位于阱层之后，在第二发光区内，每一量子阱结构的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙，第四势垒层的带隙大于第一势垒层、第二势垒层、第三势垒层材料的带隙。
  4. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：所述第一势垒层、第二势垒层、第三势垒层、第四势垒层的厚度范围为10埃～1000埃；所述阱层的厚度范围为1埃～100埃。
  5. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：每一周期的量子阱结构中，所述第一势垒层、第二势垒层、第三势垒层的总厚度与阱层的厚度比在5∶1～20∶1之间。
  6. 根据权利要求3所述的一种微LED外延结构，其特征在于：所述第 四势垒层厚度与阱层的厚度比在5∶1～20∶1之间。
  7. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：每一个周期量子阱结构中，第二势垒层的厚度大于第一势垒层、第三势垒层的厚度。
  8. 根据权利要求3所述的一种微LED外延结构，其特征在于：在所述第二发光区的每一周期的量子阱结构中，第四势垒层的厚度大于第一势垒层、第三势垒层的厚度。
  9. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：所述的两组发光区内，第一势垒层、第二势垒层、第三势垒层为全部或部分n型掺杂，第四势垒层为非故意掺杂层。
  10. 根据权利要求9所述的一种微LED外延结构，其特征在于：所述的两组发光区内，第一势垒层、第二势垒层、第三势垒层为全部或部分n型掺杂，n型掺杂的浓度为1E17/cm 2～1E19/cm 2。
  11. 根据权利要求1所述的一种微LED外延结构，其特征在于：所述第一发光区的周期数为1～5，第二发光区的周期数为1～5。
  12. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：所述阱层由Al xIn yGa 1-x-yN材料组成；所述第一势垒层、第二势垒层、第三势垒层、第四势垒层由AL pIn qGa 1-p-qN材料组成，每一周期的量子阱结构中，0≤x＜p＜1；0≤q＜y＜1。
  13. 根据权利要求1所述的一种微LED外延结构，其特征在于：两组发光区势垒层材料的平均Al组分百分含量满足以下条件：第一发光区小于第二发光区；两组发光区阱层材料的平均In组分百分含量满足以下条件：第一发光区小于等于第二发光区。
  14. 根据权利要求2或3所述的一种微LED外延结构，其特征在于：在每一量子阱结构内，第二势垒层材料的平均Al组分百分含量大于第一势垒层、第三势垒层材料的平均Al组分百分含量。
  15. 根据权利要求3所述的一种微LED外延结构，其特征在于：在所述第二发光区每一周期量子阱结构内，第四势垒层材料的平均Al组 分百分含量大于第一势垒层、第二势垒层、第三势垒层材料的平均Al组分百分含量。
  16. 根据权利要求1所述的一种微LED外延结构，其特征在于：所述发光区还包含第三发光区，第三发光区包括n3个周期的量子阱结构，第三发光区位于第一发光区和第二发光区之间，所述第三发光区的势垒层的带隙介于第一发光区和第二发光区之间；所述第三发光区阱层的带隙介于第一发光区和第二发光区之间。
  17. 根据权利要求16所述的一种微LED外延结构，其特征在于：所述第三发光区势垒层平均Al组分百分含量介于第一发光区和第二发光区之间；所述第三发光区阱层平均In组分百分含量介于第一发光区和第二发光区之间。
  18. 根据权利要求16所述的一种微LED外延结构，其特征在于：所述第三发光区包含第一势垒层、第二势垒层、第三势垒层、阱层；所述第三发光区中的第二势垒层材料的带隙大于第一势垒层、第三势垒层材料的带隙。
  19. 根据权利要求18所述的一种微LED外延结构，其特征在于：所述第三发光区中的第二势垒层的厚度大于第一势垒层、第三势垒层的厚度。
  20. 根据权利要求18所述的一种微LED外延结构，其特征在于：所述第三发光区中第一势垒层、第二势垒层、第三势垒层的厚度范围为10埃～1000埃；所述阱层的厚度范围为1埃～100埃。
  21. 根据权利要求18所述的一种微LED外延结构，其特征在于：所述第三发光区中第一势垒层、第二势垒层、第三势垒层的总厚度与阱层的厚度比在5∶1～20∶1之间。
  22. 根据权利要求18所述的一种微LED外延结构，其特征在于：所述第三发光区中第一势垒层、第二势垒层、第三势垒层为全部或部分n型掺杂，n型掺杂的浓度为1E17/cm 2～1E19/cm 2。
  23. 根据权利要求16所述的一种微LED外延结构，其特征在于：所述 第三发光区的周期数为0～5。
  24. 根据权利要求18所述的一种微LED外延结构，其特征在于：所述第三发光区阱层由Al xIn yGa 1-x-yN材料组成；所述第一势垒层、第二势垒层、第三势垒层由AL pIn qGa 1-p-qN材料组成，0≤x＜p＜1；0≤q＜y＜1。
  25. 根据权利要求18所述的一种微LED外延结构，其特征在于：在所述第三发光区的每一量子阱结构内，第二势垒层材料的平均Al组分百分含量大于第一势垒层、第三势垒层材料的平均Al组分百分含量。
  26. 一种如权利要求1～25任一项所述的微LED外延结构的制备方法，包括以下工艺步骤：
    (1)提供一衬底；
    (2)在所述衬底上生长成核层、N型层、发光层；
    (3)生长P型层。
  27. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：所述第一发光区势垒层的平均生长速率大于第二发光区势垒层的平均生长速率。
  28. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：所述第一发光区阱层的平均生长速率大于第二发光区阱层的平均生长速率。
  29. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：每一量子阱结构内，第一势垒层和第三势垒层的平均生长速率小于等于第二势垒层的平均生长速率。
  30. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：势垒层的生长速率范围0.1～10埃/秒；阱层的生长速率范围0～1埃/秒。
  31. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：势垒层的生长温度为700～950℃；阱层的生长温度为700～90 0℃。
  32. 根据权利要求26所述的一种微LED外延结构的制备方法，其特征在于：复合发光区势垒层、阱层的生长方式为连续生长或者中断生长。
  33. 一种微发光二极管，其特征在于，其包括前述权利要求1至25中任一项所述的外延结构。
  34. 根据权利要求33所述的一种微发光二极管，其特征在于：所述微发光二极管的水平尺寸在1μm*1μm～300μm*300μm之间。
  35. 一种发光装置，其特征在于，包括权利要求33所述的一种微发光二极管。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN112864289A (zh) * 2021-02-08 2021-05-28 厦门大学 一种低电流Micro LED芯片外延结构及其制备方法
CN116190522B (zh) * 2023-04-26 2023-07-11 江西兆驰半导体有限公司 一种高光效发光二极管外延片及其制备方法
CN116504894B (zh) * 2023-06-27 2024-05-14 江西兆驰半导体有限公司 GaN基LED外延片及其生长工艺、LED
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110204394A1 (en) * 2010-02-25 2011-08-25 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method of manufacturing the same
CN103682001A (zh) * 2012-09-26 2014-03-26 丰田合成株式会社 第iii族氮化物半导体发光器件
CN106410005A (zh) * 2016-10-18 2017-02-15 华灿光电（浙江）有限公司 一种氮化镓基led外延片及其生长方法
CN108365064A (zh) * 2018-03-26 2018-08-03 郭秀丽 一种多量子阱发光二极管及其制备方法
CN109904288A (zh) * 2019-01-18 2019-06-18 华灿光电（浙江）有限公司 氮化镓基发光二极管外延片及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002084041A (ja) 2000-09-08 2002-03-22 Sharp Corp 窒化物半導体発光素子とそれを含む光学装置
JP4571372B2 (ja) 2002-11-27 2010-10-27 ローム株式会社 半導体発光素子
JP2009059784A (ja) 2007-08-30 2009-03-19 Sharp Corp 窒化物系半導体発光素子
KR100993085B1 (ko) 2009-12-07 2010-11-08 엘지이노텍 주식회사 발광 소자, 발광 소자 패키지 및 라이트 유닛
CN102368519B (zh) * 2011-10-27 2016-04-20 华灿光电股份有限公司 一种提高半导体二极管多量子阱发光效率的方法
KR101596386B1 (ko) * 2011-11-18 2016-02-22 애플 인크. 전기 절연 층을 갖는 마이크로 led 구조체 및 마이크로 led 구조체들의 어레이를 형성하는 방법
KR20220058643A (ko) 2015-06-05 2022-05-09 오스텐도 테크놀로지스 인코포레이티드 다수의 활성층들로 선택적으로 캐리어를 주입한 발광 구조체
US10133426B2 (en) * 2015-06-18 2018-11-20 X-Celeprint Limited Display with micro-LED front light
CN107316925B (zh) * 2017-08-17 2019-03-12 合肥彩虹蓝光科技有限公司 紫光led外延结构及其生长方法
CN107833953A (zh) 2017-09-12 2018-03-23 合肥惠科金扬科技有限公司 microLED多量子阱层生长方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110204394A1 (en) * 2010-02-25 2011-08-25 Kabushiki Kaisha Toshiba Semiconductor light emitting device and method of manufacturing the same
CN103682001A (zh) * 2012-09-26 2014-03-26 丰田合成株式会社 第iii族氮化物半导体发光器件
CN106410005A (zh) * 2016-10-18 2017-02-15 华灿光电（浙江）有限公司 一种氮化镓基led外延片及其生长方法
CN108365064A (zh) * 2018-03-26 2018-08-03 郭秀丽 一种多量子阱发光二极管及其制备方法
CN109904288A (zh) * 2019-01-18 2019-06-18 华灿光电（浙江）有限公司 氮化镓基发光二极管外延片及其制造方法

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