WO2021169562A1 - 移位寄存器、栅极驱动电路及显示面板 - Google Patents

移位寄存器、栅极驱动电路及显示面板 Download PDF

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Publication number
WO2021169562A1
WO2021169562A1 PCT/CN2020/140528 CN2020140528W WO2021169562A1 WO 2021169562 A1 WO2021169562 A1 WO 2021169562A1 CN 2020140528 W CN2020140528 W CN 2020140528W WO 2021169562 A1 WO2021169562 A1 WO 2021169562A1
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Prior art keywords
transistor
pull
sub
circuit
signal
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PCT/CN2020/140528
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English (en)
French (fr)
Inventor
古宏刚
陈俊生
宋洁
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US17/417,470 priority Critical patent/US11875715B2/en
Publication of WO2021169562A1 publication Critical patent/WO2021169562A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the invention belongs to the field of display technology, and specifically relates to a shift register, a gate drive circuit and a display panel.
  • GOA Gate Driver on Array, integrated gate driver circuit
  • GOA Gate Driver on Array, integrated gate driver circuit
  • Pole drive integrated circuit Pole drive integrated circuit part and fan-out (Fan-out) wiring space to simplify the structure of display products.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display panel.
  • an embodiment of the present invention provides a shift register, which includes: an input sub-circuit and a first output sub-circuit;
  • the input sub-circuit is configured to respond to an input signal and pre-charge a pull-up node through a first power supply voltage;
  • the pull-up node is the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit Connection node between;
  • the output sub-circuit is configured to output a clock signal through the first signal output terminal in response to the potential of the pull-up node;
  • the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit;
  • the first noise reduction sub-circuit is configured to respond to the first noise reduction control signal and use a non-operating level signal during the blanking phase to reduce noise on the pull-up node;
  • the second noise reduction sub-circuit is configured to respond to the second noise reduction control signal and use a non-operating level signal during the blanking phase to reduce noise on the first signal output terminal.
  • the first noise reduction sub-circuit includes a first transistor
  • the first electrode of the first transistor is connected to the pull-up node, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the first noise reduction control signal terminal.
  • the second noise reduction sub-circuit includes a second transistor
  • the first electrode of the second transistor is connected to the first signal output terminal, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the second noise reduction control signal terminal.
  • the shift register further includes a plurality of second output sub-circuits
  • Each of the plurality of second output sub-circuits is configured to respond to the corresponding switch control signal, and output the signal output from the first signal output terminal through the corresponding second signal output terminal.
  • each of the plurality of second output sub-circuits includes a third transistor
  • the first pole of the third transistor is connected to the first signal output terminal, the second pole is connected to the second signal output terminal, and the control pole is connected to the switch control signal terminal.
  • the shift register further includes a plurality of second output sub-circuits
  • Each of the plurality of second output sub-circuits is configured to respond to the signal output by the first signal output terminal and output a driving signal through the second signal output terminal corresponding thereto.
  • each of the plurality of second output sub-circuits includes a third transistor
  • the first electrode of the third transistor is connected to the corresponding driving signal terminal, the second electrode is connected to the second signal output terminal, and the control electrode is connected to the first signal output terminal.
  • the shift register further includes a pull-down control sub-circuit, a pull-down sub-circuit, a third noise reduction sub-circuit, and a fourth noise reduction sub-circuit;
  • the pull-down control sub-circuit is configured to respond to a working level signal and transmit the working level signal to a pull-down node;
  • the pull-down node is a connection between the pull-down control sub-circuit and the pull-down sub-circuit node;
  • the pull-down sub-circuit is configured to pull down the potential of the pull-down node through a non-operating level signal in response to the potential of the pull-up node;
  • the third noise reduction sub-circuit is configured to reduce noise on the pull-up node through the non-operating level signal in response to the potential of the pull-down node;
  • the fourth noise reduction sub-circuit is configured to reduce noise on the first signal output terminal through the non-operating level signal in response to the potential of the pull-down node.
  • the pull-down control sub-circuit includes a fourth transistor and a fifth transistor;
  • the first electrode of the fourth transistor is connected to its control electrode, the first electrode of the fifth transistor and the working level terminal, and the second electrode is connected to the pull-down sub-circuit and the control electrode of the fifth transistor;
  • the second pole of the five transistor is connected to the pull-down node.
  • the pull-down sub-circuit includes a sixth transistor and a seventh transistor;
  • a first pole of the sixth transistor is connected to the pull-down node, a second pole is connected to a non-operating level terminal, and a control pole is connected to the pull-up node;
  • the first pole of the seventh transistor is connected to the pull-up control sub-circuit, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-up node.
  • the third noise reduction sub-circuit includes an eighth transistor
  • the first pole of the eighth transistor is connected to the pull-up node, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-down node.
  • the fourth noise reduction sub-circuit includes a ninth transistor
  • the first electrode of the ninth transistor is connected to the first signal output terminal, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the pull-down node.
  • the shift register further includes a plurality of fifth noise reduction sub-circuits arranged in a one-to-one correspondence with the multiple second signal output terminals;
  • Each of the plurality of fifth noise reduction sub-circuits is configured to respond to the potential of the pull-down node to reduce the noise of the second output terminal corresponding thereto through the non-operating level signal.
  • each of the plurality of fifth noise reduction sub-circuits includes a tenth transistor
  • the first pole of the tenth transistor is connected to the corresponding second signal output terminal, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-down node.
  • the shift register further includes a reset sub-circuit
  • the reset sub-circuit is configured to reset the pull-up node through a second power supply voltage in response to a reset signal.
  • the reset sub-circuit includes an eleventh transistor
  • the first electrode of the eleventh transistor is connected to the pull-up node, the second electrode is connected to the second power supply voltage terminal, and the control electrode is connected to the reset signal terminal.
  • the input sub-circuit includes a twelfth transistor
  • the first electrode of the twelfth transistor is connected to the first power supply voltage terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the signal input terminal.
  • the output sub-circuit includes a thirteenth transistor and a storage capacitor
  • the first electrode of the thirteenth transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the pull-up node and the first terminal of the storage capacitor.
  • an embodiment of the present invention provides a gate driving circuit, which includes the above-mentioned shift register; wherein,
  • the signal input terminal of the shift register of this stage is connected to the signal output terminal of the shift register of the previous stage; the reset signal terminal of the shift register of this stage is connected to the signal output terminal of the shift register of the next stage.
  • an embodiment of the present invention provides a display panel including the above-mentioned gate driving circuit.
  • FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
  • FIG. 7 is a circuit of a shift register according to an embodiment of the present invention.
  • FIG. 8 is a working timing diagram of the shift register of FIG. 7.
  • FIG. 9 is a circuit diagram of another shift register according to an embodiment of the present invention.
  • FIG. 10 is a working timing diagram of the shift register of FIG. 9.
  • FIG. 11 is a circuit of a shift register according to an embodiment of the present invention.
  • Fig. 12 is a working timing diagram of the shift register of Fig. 11.
  • FIG. 13 is a schematic diagram of a cascade connection of a gate driving circuit according to an embodiment of the present invention.
  • the existing display panel usually has a display area and a peripheral area surrounding the display area; a plurality of pixel units arranged in an array are arranged in the display area, and each pixel unit is provided with a pixel circuit; among them, pixels located in the same row
  • the cells are connected to the same gate line, and the pixel cells located in the same column are connected to the same data line.
  • a gate drive circuit is provided in the peripheral area, and the gate drive circuit includes a plurality of cascaded shift registers GOA.
  • the shift registers and the gate lines are arranged in one-to-one correspondence, that is, each shift register is connected to a gate line .
  • the gate scan signal is output to the corresponding gate line through the step-by-step shift register to complete the row-by-row scan of the pixel circuit. While each row of the gate line is scanned, each data line The data voltage signal is written into the pixel circuit of the row to light up the pixel unit of the row. There is a blanking stage between the display of two frames. At this time, the pixel units of each row are not displayed. At this time, the shift register is required to output a stable non-operating level signal to ensure the display of this frame. When finished, the next frame can be displayed stably.
  • the inventor provides the following embodiments.
  • the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, the source There is no difference between the drain and the drain. In the embodiment of the present invention, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for description. When N-type transistors are used, the first pole is the source of the N-type transistor, and the second pole is the source of the N-type transistor.
  • the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; correspondingly, The working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.
  • the first power supply voltage written at the first power supply voltage terminal is higher than the second power supply voltage written at the second power supply voltage terminal.
  • the first power supply voltage is the high power supply voltage
  • the second power supply voltage is Take low power supply voltage as an example.
  • an embodiment of the present invention provides a shift register, which includes an input sub-circuit 1 and a first output sub-circuit 2; in particular, the embodiment of the present invention also includes a first noise reduction Sub-circuit 3 and/or second noise reduction sub-circuit 4.
  • the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4 are added to the shift register of the embodiment of the present invention, and in the blanking stage, the first noise reduction sub-circuit 3 can be used in the first noise reduction control signal. Under control, the pull-up node PU is noise-reduced.
  • the second noise reduction sub-circuit 4 can reduce the noise of the first signal output terminal Output under the control of the second noise reduction control signal.
  • the output of the shift register is stable in the stage, so as to avoid the influence of noise on the display of the next frame.
  • the shift register in the embodiment of the present invention may only include one of the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4, but it should be understood that the maximum guarantee The shift register can output stably.
  • the preferred shift register includes the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4 at the same time.
  • the shift register is described as an example where the shift register includes both the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4. Of course, this does not constitute an implementation of the present invention. Limitations of examples.
  • the first noise reduction sub-circuit 3 includes a first transistor M1; the second noise reduction sub-circuit 4 includes a second transistor M2.
  • the source of the first transistor M1 is connected to the pull-up node PU, the drain is connected to the low-level signal terminal VGL, and the gate is connected to the first noise reduction control signal terminal TRST1.
  • the source of the second transistor M2 is connected to the first signal output terminal Output, the drain is connected to the low-level signal terminal VGL, and the gate is connected to the second noise reduction control signal terminal TRST2.
  • the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 may be the same signal terminal.
  • a high level signal is input to the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2.
  • the first transistor M1 and the second transistor M2 are turned on, and the low level signal
  • the low-level signal written to the terminal VGL pulls the pull-up node PU low through the first transistor M1 to reduce the noise of the pull-up node PU; in the same way, the low-level signal written to the low-level signal terminal VGL passes
  • the second transistor M2 pulls the output of the first signal output terminal Output low to reduce noise on the first signal output terminal Output.
  • the shift register not only includes the above structure, but also includes a plurality of second output sub-circuits 5.
  • each of the plurality of second output sub-circuits 5 is configured to output the signal output by the first signal output terminal Output through the second signal output terminal in response to the switch control signal .
  • one shift register can be used to output scan signals for multiple gate lines, which helps to achieve narrower edges of the display panel.
  • Each second output sub-circuit 5 may include a third transistor; the three second output sub-circuits 5 are respectively connected to three second signal output terminals and three switch control signal terminals; in the three second output sub-circuits 5
  • the third transistor is used for M31, M32, M33 respectively; the three second signal output terminals are respectively Gateout1, Gateout2, Gateout3; the three switch control signal terminals are respectively used SW1, SW2, SW3; among them, M31, M32, M33
  • the sources of the three are all connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the gate of M31 is connected to SW1; the drain of M32 is connected to Gateout2, the gate of M32 is connected to SW2; the drain of M33 is connected to Gateout3, M33 The gate is connected to SW3.
  • each of the plurality of second output sub-circuits 5 is configured to respond to the signal output by the first output signal terminal Output and pass the signal output by the driving signal terminal through the second signal Output terminal (for example: Gateout1, Gateout2, Gateout3) for output.
  • the second signal Output terminal for example: Gateout1, Gateout2, Gateout3
  • one shift register can be used to output scan signals for multiple gate lines, which helps to achieve narrower edges of the display panel.
  • Each second output sub-circuit 5 may include a third transistor; the three second output sub-circuits 5 are respectively connected to three second signal output terminals and three switch control signal terminals; in the three second output sub-circuits 5
  • the third transistor is used for M31, M32, and M33 respectively; the three second signal output terminals are respectively Gateout1, Gateout2, Gateout3; the three drive signal terminals are respectively used TQ1, TQ2, TQ3; among them, the three of M31, M32, and M33
  • the gates of both are connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the source of M31 is connected to SW1; the drain of M32 is connected to Gateout2, the source of M32 is connected to SW2; the drain of M33 is connected to Gateout3, and the source of M33 is connected to SW2.
  • the source is connected to SW3.
  • the shift register not only includes the above structure, the shift register also includes a pull-down control sub-circuit 6, a pull-down sub-circuit 7, a third noise reduction sub-circuit 8, and a fourth noise reduction sub-circuit.
  • the pull-down sub-circuit 7 is configured to pull down the potential of the pull-down node PD through a low-level signal in response to the potential of the pull-up node PU;
  • the third noise reduction sub-circuit 8 is configured to respond to the potential of the pull-down node PD , Noise reduction is performed on the pull-up node PU through a low-level potential;
  • the fourth noise reduction sub-circuit 9 is configured to respond to the potential of the pull-down node PD and perform noise reduction on the first signal output terminal Output through a low-level signal .
  • the pull-down control sub-circuit 6 may include a fourth transistor M4 and a fifth transistor M5; the pull-down sub-circuit 7 may include a sixth transistor M6 and a seventh transistor M7; and the third noise reduction The sub-circuit 8 may include an eighth transistor M8; the fourth noise reduction sub-circuit 9 may include a ninth transistor M9.
  • the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain of the fourth transistor M4 is connected to the source of the seventh transistor M7 and the fifth transistor.
  • the gate of M5; the drain of the fifth transistor M5 is connected to the pull-down node PD; the source of the sixth transistor M6 is connected to the pull-down node PD, the drain of the sixth transistor M6 is connected to the low-level signal terminal VGL, and the gate of the sixth transistor M6
  • the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate is connected to the pull-up node PU;
  • the source of the eighth transistor M8 is connected to the pull-up node PU, and the drain of the eighth transistor M8
  • the electrode is connected to the low-level signal terminal VGL, the gate of the eighth transistor M8 is connected to the pull-down node PD; the source of the ninth transistor M9 is connected to the first signal output terminal Output, and the drain of the ninth transistor M9 is connected to the low-level signal terminal VGL ,
  • the gate of the ninth transistor M9 is connected to the pull-down node PD.
  • the pull-up node PU When a shift register of a certain stage outputs a high-level signal, at this time, the pull-up node PU is at a high-level potential. At this time, the sixth transistor M6 and the seventh transistor M7 are turned on, and the input signal will be input through the low-level signal terminal VGL. The low-level signal pulls down the potential of the pull-down node PD to prevent the eighth transistor M8 and the ninth transistor M9 from being turned on and affect the stability of the pull-up node PU and the output of the first signal output terminal Output.
  • the pull-up node PU When a shift register of a certain stage outputs a low-level signal, the pull-up node PU is at a low-level potential at this time, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on, and The potential of the pull-down node PD is pulled up by a high-level signal, so that the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL will be pulled up through the eighth transistor M8.
  • the node PU performs noise reduction
  • the ninth transistor M9 performs noise reduction on the first signal output terminal Output.
  • the shift register may not only include the above structure, but may also include a plurality of fifth noise reduction sub-circuits 10 arranged in a one-to-one correspondence with the plurality of second signal output terminals;
  • Each of the fifth noise reduction sub-circuits 10 responds to the potential of the pull-down node PD, and performs noise reduction on the second signal output terminal corresponding thereto through a low-level signal.
  • each fifth noise reduction sub-circuit 10 may include a tenth transistor; the tenth transistors in the three fifth noise reduction sub-circuits 10 are denoted by M101, M102, and M103, respectively.
  • the gates of M101, M102, and M103 are all connected to the pull-down node PD, the source of M101 is connected to Gateout1, the source of M102 is connected to Gateout2, the source of M103 is connected to Gateout3, and the drain of M101, M102, M103 is connected to the low-level signal terminal VGL .
  • Gateout1, Gateout2, and Gateout3 When the shift register outputs a low-level signal, Gateout1, Gateout2, and Gateout3 output a low-level signal, the pull-up node PU is at a low level, and the pull-down node PD is at a high level input by the high-level signal terminal VGH. The signal is pulled high. At this time, M101, M102, and M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is used to reduce the noise of Gateout1, Gateout2, and Gateout3 through M101, M102, and M103, respectively.
  • the shift register not only includes the aforementioned structure, but also includes a reset sub-circuit 11 configured to reset the potential of the pull-up node PU through a low-level signal in response to a reset signal. .
  • the reset sub-circuit 11 may include an eleventh transistor M11; wherein, the source of the eleventh transistor M11 is connected to the pull-up node PU, and the source of the eleventh transistor M11 is connected to the pull-up node PU.
  • the drain of the eleventh transistor M11 is connected to the second power supply voltage terminal VSS, and the gate of the eleventh transistor M11 is connected to the reset signal terminal Reset.
  • the reset signal terminal Reset is written with a high-level signal
  • the eleventh transistor M11 is turned on
  • the potential of the pull-up node PU is reset by the low power supply voltage written by the second power supply voltage terminal VSS.
  • the input sub-circuit 1 of the shift register may include a twelfth transistor M12.
  • the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD
  • the drain of the twelfth transistor M12 is connected to the pull-up node PU
  • the gate of the twelfth transistor M12 is connected to the signal input terminal Input.
  • a high-level signal is input to the signal input terminal Input, the twelfth transistor M12 is turned on, and the high power supply voltage written into the first power supply voltage terminal VDD is sent to the pull-up node PU through the twelfth transistor M12. Perform pre-charging.
  • the first output sub-circuit 2 of the shift register may include a thirteenth transistor M13 and a storage capacitor C1.
  • the source of the thirteenth transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to Pull the node PU and the first end of the storage capacitor C1.
  • the pull-up node PU is precharged and pulled high during the input stage and stored in the storage capacitor C1.
  • the twelfth transistor M12 is turned off, and the clock signal terminal CLK inputs a high-level signal.
  • the thirteenth transistor M13 is turned on, and the first signal output terminal Output writes the clock signal terminal CLK high Level signal output.
  • the shift register includes an input sub-circuit 1, a first output sub-circuit 2, a reset sub-circuit 11, a pull-down control sub-circuit 6, a pull-down sub-circuit 7, and a first noise reduction sub-circuit Circuit 3, second noise reduction sub-circuit 4, third noise reduction sub-circuit 8 and fourth noise reduction sub-circuit 9.
  • the input sub-circuit 1 includes a twelfth transistor M12; the first output sub-circuit 2 includes a thirteenth transistor M13 and a storage capacitor C1; the reset sub-circuit 11 includes an eleventh transistor M11; the pull-down control sub-circuit 6 includes a fourth transistor M4 and the fifth transistor M5; the pull-down sub-circuit 7 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 3 includes a first transistor M1; the second noise reduction sub-circuit 4 includes a second transistor M2; The noise reduction sub-circuit 8 includes an eighth transistor M8; the fourth noise reduction sub-circuit 9 includes a ninth transistor M9.
  • the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD, the drain of the twelfth transistor M12 is connected to the pull-up node PU, and the gate of the twelfth transistor M12 is connected to the signal input terminal Input;
  • the source of the transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to the pull-up node PU and the storage
  • the first terminal of the capacitor C1; the source of the eleventh transistor M11 is connected to the pull-up node PU, the drain of the eleventh transistor M11 is connected to the second power supply voltage terminal VSS, and the gate of the eleventh transistor M11 is connected to the reset signal terminal Reset ;
  • the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain
  • the driving method of the shift register specifically includes the following stages:
  • the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
  • the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8 and the ninth transistor M9 are kept off, and the first signal output terminal Output outputs a stable low-level signal .
  • the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
  • the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8 and the ninth transistor M9 continue to be turned off, so that the first signal output terminal Output outputs a stable high-level signal.
  • the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL pulls the pull-up node PU low through the eighth transistor M8.
  • the nine transistor M9 pulls the first signal output terminal Output low.
  • the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
  • the node PD is always at a high level potential
  • the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL is used to reduce the noise of the pull-up node PU through the eighth transistor M8.
  • the transistor M9 reduces the noise of the first signal output terminal Output.
  • the coupling noise voltage generated by the clock signal terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output and ensuring the signal output The stability.
  • the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
  • the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
  • the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
  • the shift register includes an input sub-circuit 1, a first output sub-circuit 2, a plurality of second output sub-circuits 5, a reset sub-circuit 11, a pull-down control sub-circuit 6, a pull-down
  • the sub-circuit 7, the first noise reduction sub-circuit 3, the second noise reduction sub-circuit 4, the third noise reduction sub-circuit 8, the fourth noise reduction sub-circuit 9, and the three second output sub-circuits 5 are arranged in one-to-one correspondence
  • the input sub-circuit 1 includes a twelfth transistor M12; the first output sub-circuit 2 includes a thirteenth transistor M13 and a storage capacitor C1; each second output sub-circuit 5 includes a third transistor; the reset sub-circuit 11 includes a Eleven transistors M11; the pull-down control sub-circuit 6 includes a fourth transistor M4 and a fifth transistor M5; the pull-down sub-circuit 7 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 3 includes a first transistor M1; The second noise reduction sub-circuit 4 includes a second transistor M2; the third noise reduction sub-circuit 8 includes an eighth transistor M8; the fourth noise reduction sub-circuit 9 includes a ninth transistor M9, and each fifth noise reduction sub-circuit 10 includes a first Ten transistors.
  • the three third transistors are represented by M31, M32, and M33, and the three tenth transistors are represented by M101, M102, and M103; the three second signal output terminals corresponding to the three third transistors are represented by Gateout1, Gateout2, respectively. , Gateout3, the three switch control signal terminals use SW1, SW2, and SW3 respectively.
  • the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD, the drain of the twelfth transistor M12 is connected to the pull-up node PU, and the gate of the twelfth transistor M12 is connected to the signal input terminal Input;
  • the source of the transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to the pull-up node PU and the storage
  • the first terminal of the capacitor C1; the sources of M31, M32, and M33 are all connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the gate of M31 is connected to SW1; the drain of M32 is connected to Gateout2, and that of M32 The gate is connected to SW2; the drain of M33 is connected to Gateout3, and the gate of M33 is connected to SW3; the source of the eleventh transistor
  • the gate of the eleven transistor M11 is connected to the reset signal terminal Reset; the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain of the fourth transistor M4 is connected to the seventh
  • the driving method of the shift register specifically includes the following stages:
  • the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
  • the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 are kept off, thereby making the first signal output The terminal Output outputs a stable low-level signal.
  • the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
  • the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 continue to be turned off, so that the first signal output terminal
  • the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 are turned on, and the low-level signal input from the low-level signal terminal VGL passes through the eighth transistor M8.
  • the pull-up node PU is pulled low, the first signal output terminal Output is pulled low through the ninth transistor M9, and the second signal output terminals Gateout1, Gateout2, and Gateout3 are pulled low through M101, M102, and M103, respectively.
  • the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
  • the node PD is always at a high-level potential
  • the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is passed through the eighth transistor M8.
  • the node PU is pulled to reduce noise
  • the first signal output terminal Output is reduced through the ninth transistor M9
  • the second signal output terminals Gateout1, Gateout2, Gateout3 are respectively reduced by M101, M102, and M103.
  • the clock signal can be reduced.
  • the coupling noise voltage generated by the terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output, and ensuring the stability of the signal output.
  • the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
  • the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
  • the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
  • the shift register is roughly the same as the shift register in the second specific example, except that the three second output sub-circuits 5 and the three driving signal terminal signals are different from each other.
  • the gates of M31, M32, and M33 are all connected to the first signal output terminal Output
  • the drain of M31 is connected to Gateout1
  • the source of M31 is connected to TQ1
  • the drain of M32 is connected to Gateout2.
  • the source of M32 is connected to TQ2
  • the drain of M33 is connected to Gateout3
  • the source of M33 is connected to TQ3.
  • the other structure of the shift register is the same as the structure of the shift register in the second specific example, so it will not be repeated here.
  • the driving method of the shift register specifically includes the following stages:
  • the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
  • the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 are kept off, thereby making the first signal output The terminal Output outputs a stable low-level signal.
  • the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
  • the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 continue to be turned off, so that the first signal output
  • the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 are turned on, and the low-level signal input from the low-level signal terminal VGL passes through the eighth transistor M8.
  • the pull-up node PU is pulled low, the first signal output terminal Output is pulled low through the ninth transistor M9, and the second signal output terminals Gateout1, Gateout2, and Gateout3 are pulled low through M101, M102, and M103, respectively.
  • the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
  • the node PD is always at a high-level potential
  • the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is passed through the eighth transistor M8.
  • the node PU is pulled to reduce noise
  • the first signal output terminal Output is reduced through the ninth transistor M9
  • the second signal output terminals Gateout1, Gateout2, Gateout3 are respectively reduced by M101, M102, and M103.
  • the clock signal can be reduced.
  • the coupling noise voltage generated by the terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output, and ensuring the stability of the signal output.
  • the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
  • the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
  • the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
  • a shift register has multiple second output sub-circuits 5, that is, multiple The row gate lines provide scanning signals, so that multiple rows of pixel units can be multiplexed with a shift register, thereby reducing the number of shift register units, thereby reducing the size of the gate driving circuit, and reducing the frame size of the display panel , which can facilitate the realization of the narrow frame of the display panel.
  • an embodiment of the present invention provides a gate drive circuit, the gate drive circuit includes a plurality of cascaded any of the above, wherein, in addition to the first stage of shift register, the present The signal input terminal Input of the first stage shift register is connected to the first signal output terminal Output of the previous stage shift register; the signal input terminal Input of the first stage shift register is connected to the frame strobe signal; except for the last stage shift register, The first signal output terminal Output of the shift register of the current stage is connected to the reset signal terminal Reset of the shift register of the next stage.
  • Figure 13 only shows four shift registers GOA1, GOA2, GOA3, GOA4, and the four shift registers are controlled by two clock signal lines.
  • GOA1, GOA2 are controlled by clk1
  • GOA3, GOA4 are controlled by clk2.
  • the number does not constitute a limitation to the embodiment of the present invention.
  • first-stage shift register and the last-stage shift register are opposite, and are determined according to the forward scan and the reverse scan of the gate drive circuit.
  • the shift register unit that provides the scanning signal to the first gate line is the first-stage shift register;
  • the shift register unit that provides scanning signals is the last stage shift register.
  • the shift register unit that provides the scanning signal to the last gate line Is the first stage shift register; the shift register unit that provides the scan signal to the first gate line is the last stage shift register.
  • forward scanning and reverse scanning only need to exchange the input signals of the first power supply voltage terminal VDD and the second power supply voltage terminal VSS, and exchange the signals input from the signal input terminal Input and the reset signal terminal Reset.
  • the gate driving circuit in the embodiment of the present invention includes any of the above-mentioned shift registers, the noise of the pull-up node PU and the first signal output terminal Output can be reduced in the blanking stage, thereby effectively ensuring the next picture frame Show stability.
  • each shift register in the embodiment of the present invention has multiple second output sub-circuits 5, so one shift register can provide scanning signals for multiple rows of gate lines, so that multiple rows of pixel units can be replicated.
  • the number of shift register units is reduced, and the size of the gate driving circuit is reduced, so that the frame size of the display panel is reduced, which can facilitate the realization of the narrow frame of the display panel.
  • an embodiment of the present invention provides a display panel including the above-mentioned gate driving circuit, including the above-mentioned gate driving circuit. Since the above-mentioned gate driving circuit is included, the display effect is better, and a narrow-edge design can be realized.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, and so on.

Abstract

一种移位寄存器、栅极驱动电路及显示面板，属于显示技术领域。移位寄存器包括：输入子电路（1）和第一输出子电路（2）；输入子电路（1）被配置为响应于输入信号，并通过第一电源电压对上拉节点（PU）进行预充电；上拉节点（PU）为输入子电路（1）、第一输出子电路（2）及下拉子电路（7）之间的连接节点；第一输出子电路（2）被配置为响应于上拉节点（PU）的电位，而将时钟信号通过第一信号输出端（Output）进行输出；移位寄存器还包括：第一降噪子电路（3）和/或第二降噪子电路（4）；第一降噪子电路（3）被配置为响应于第一降噪控制信号，并在消隐阶段通过非工作电平信号，对上拉节点（PU）进行降噪；第二降噪子电路（4）被配置为响应于第二降噪控制信号，并在消隐阶段通过非工作电平信号，对第一信号输出端（Output）进行降噪。

Description

[根据细则37.2由ISA制定的发明名称]　移位寄存器、栅极驱动电路及显示面板 技术领域
本发明属于显示技术领域，具体涉及一种移位寄存器、栅极驱动电路及显示面板。
背景技术
GOA(Gate Driver on Array，集成栅极驱动电路)技术可以将栅极驱动电路集成在显示面板的阵列基板上，替代由外接硅片制作的驱动芯片，可以省掉Gate IC(Gate Integrated Circuit，栅极驱动集成电路)部分以及扇出型(Fan-out)布线空间，以简化显示产品的结构。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种移位寄存器、栅极驱动电路及显示面板。
第一方面，本发明实施例提供一种移位寄存器，其包括：输入子电路和第一输出子电路；
所述输入子电路被配置为响应于输入信号，并通过第一电源电压对上拉节点进行预充电；所述上拉节点为所述输入子电路、所述输出子电路及所述下拉子电路之间的连接节点；
所述输出子电路被配置为响应于所述上拉节点的电位，而将时钟信号通过第一信号输出端进行输出；其中，
所述移位寄存器还包括：第一降噪子电路和/或第二降噪子电路；
所述第一降噪子电路被配置为响应于第一降噪控制信号，并在消隐阶段通过非工作电平信号，对所述上拉节点进行降噪；
所述第二降噪子电路被配置为响应于第二降噪控制信号，并在消隐阶段通过非工作电平信号，对所述第一信号输出端进行降噪。
可选地，所述第一降噪子电路包括第一晶体管；
所述第一晶体管的第一极连接所述上拉节点，第二极连接非工作电平端，控制极连接第一降噪控制信号端。
可选地，所述第二降噪子电路包括第二晶体管；
所述第二晶体管的第一极连接所述第一信号输出端，第二极连接非工作电平端，控制极连接第二降噪控制信号端。
可选地，所述移位寄存器还包括多个第二输出子电路；
所述多个第二输出子电路中的每个被配置为响应于与之对应的开关控制信号，而将所述第一信号输出端输出的信号通过与之对应的第二信号输出端输出。
可选地，所述多个第二输出子电路中的每个均包括第三晶体管；
所述第三晶体管的第一极连接所述第一信号输出端，第二极连接所述第二信号输出端，控制极连接开关控制信号端。
可选地，所述移位寄存器还包括多个第二输出子电路；
所述多个第二输出子电路中的每个被配置为响应于所述第一信号输出端输出的信号，而将驱动信号通过与之对应的第二信号输出端输出。
可选地，所述多个第二输出子电路中的每个均包括第三晶体管；
所述第三晶体管的第一极连接与之对应的驱动信号端，第二极连接所述第二信号输出端，控制极连接所述第一信号输出端。
可选地，所述移位寄存器还包括下拉控制子电路、下拉子电路、第三降噪子电路、第四降噪子电路；
所述下拉控制子电路被配置为响应于工作电平信号，并将所述工作电平信号传输至下拉节点；所述下拉节点为所述下拉控制子电路和所述下拉子电路之间的连接节点；
所述下拉子电路被配置为响应于所述上拉节点的电位，通过非工作电平 信号下拉所述下拉节点的电位；
所述第三降噪子电路被配置为响应于所述下拉节点的电位，通过所述非工作电平信号对所述上拉节点进行降噪；
所述第四降噪子电路被配置为响应于所述下拉节点的电位，通过所述非工作电平信号对所述第一信号输出端进行降噪。
可选地，所述下拉控制子电路包括第四晶体管和第五晶体管；
所述第四晶体管的第一极连接其控制极、所述第五晶体管的第一极和工作电平端，第二极连接所述下拉子电路和所述第五晶体管的控制极；所述第五晶体管的第二极连接所述下拉节点。
可选地，所述下拉子电路包括第六晶体管和第七晶体管；
所述第六晶体管的第一极连接所述下拉节点，第二极连接非工作电平端，控制极连接所述上拉节点；
所述第七晶体管的第一极连接所述上拉控制子电路，第二极连接非工作电平端，控制极连接所述上拉节点。
可选地，所述第三降噪子电路包括第八晶体管；
所述第八晶体管的第一极所述上拉节点，第二极连接非工作电平端，控制极连接所述下拉节点。
可选地，所述第四降噪子电路包括第九晶体管；
所述第九晶体管的第一极连接所述第一信号输出端，第二极连接非工作电平端，控制极连接所述下拉节点。
可选地，所述移位寄存器还包括与所述多第二信号输出端一一对应设置的多个第五降噪子电路；
所述多个第五降噪子电路中的每个被配置响应于所述下拉节点的电位，而通过所述非工作电平信号对与之对应的所述第二输出端进行降噪。
可选地，所述多个第五降噪子电路中的每个均包括第十晶体管；
所述第十晶体管的第一极连接与之对应的第二信号输出端，第二极连接非工作电平端，控制极连接所述下拉节点。
可选地，所述移位寄存器还包括复位子电路；
所述复位子电路被配置为响应于复位信号，通过第二电源电压对所述上拉节点进行复位。
可选地，所述复位子电路包括第十一晶体管；
所述第十一晶体管的第一极连接上拉节点，第二极连接第二电源电压端，控制极连接复位信号端。
可选地，所述输入子电路包括第十二晶体管；
所述第十二晶体管的第一极连接第一电源电压端，第二极连接上拉节点，控制极连接信号输入端。
可选地，所述输出子电路包括第十三晶体管和存储电容；
所述第十三晶体管的第一极连接时钟信号端，第二极连接信号输出端和所述存储电容的第二端，控制极连接所述上拉节点和所述存储电容的第一端。
第二方面，本发明实施例提供一种栅极驱动电路，其包括上述移位寄存器；其中，
本级所述移位寄存器的信号输入端连接上一级所述移位寄存器的信号输出端；本级所述移位寄存器的复位信号端连接下一级所述移位寄存器的信号输出端。
第三方面，本发明实施例提供一种显示面板，其包括上述的栅极驱动电路。
附图说明
图1为本发明实施例的一种移位寄存器的结构示意图。
图2为本发明实施例的另一种移位寄存器的结构示意图。
图3为本发明实施例的另一种移位寄存器的结构示意图。
图4为本发明实施例的另一种移位寄存器的结构示意图。
图5为本发明实施例的另一种移位寄存器的结构示意图。
图6为本发明实施例的另一种移位寄存器的结构示意图。
图7为本发明实施例的一种移位寄存器的电路。
图8为图7的移位寄存器的工作时序图。
图9为本发明实施例的另一种移位寄存器的电路图。
图10为图9的移位寄存器的工作时序图。
图11为本发明实施例的一种移位寄存器的电路。
图12为图11的移位寄存器的工作时序图。
图13为本发明实施例的栅极驱动电路的级联示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
现有的显示面板通常具有显示区和环绕显示区的周边区；在显示区中设 置有呈阵列排布的多个像素单元，每个像素单元中设置有像素电路；其中，位于同一行的像素单元连接同一条栅线，位于同一列的像素单元连接同一条数据线。在周边区设置有栅极驱动电路，而栅极驱动电路则包括多个级联的移位寄存器GOA，移位寄存器与栅线一一对应设置，也即每一个移位寄存器则连接一条栅线。在显示每一帧画面时，通过逐级移位寄存器输出栅极扫描信号至与各自对应的栅线，以完成像素电路的逐行扫描，在每一行栅线被扫描的同时，各条数据线将数据电压信号写入该行的像素电路，以点亮该行像素单元。在两帧画面显示之间则为消隐(Blank)阶段，此时，各行像素单元不进行显示，此时则要求移位寄存器能够输出稳定的非工作电平信号，才能够保证本帧画面显示完成，下一帧画面能够稳定显示。对此，在发明中发明人提供如下实施方式。
在此需要说明的是，本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
其中，由于在本发明实施例中以所采用晶体管为N型晶体管，故在本发明实施例中的工作电平信号则是指高电平信号，非工作电平信号为低电平信号；相应的工作电平端为高电平信号端，非工作电平端为低电平信号端。第一电源压端被写入的第一电源电压高于第二电源电压端被写入的第二电源电压，在本发明实施例中以第一电源电压为高电源电压，第二电源电压为低电源电压为例。
第一方面，如图1所示，本发明实施例提供一种移位寄存器，其包括输入子电路1、第一输出子电路2；特别的是，本发明实施例中还包括第一降噪子电路3和/或第二降噪子电路4。其中，输入子电路1被配置为响应于输入信号，并通过第一电源电压对上拉节点PU进行预充电；上拉节点PU为输入子电路1、输出子电路之间的连接节点；第一输出子电路2被配置为响应于所述上拉节点PU的电位，而将时钟信号通过第一信号输出端Output进行输出；第一降噪子电路3被配置为响应于第一降噪控制信号，并在消隐阶段通过非工作电平信号，对上拉节点PU进行降噪；所述第二降噪子电路4被配置为响应于第二降噪控制信号，并在消隐阶段通过低电平信号，对第一信号输出端Output进行降噪。
由于在本发明实施例的移位寄存器中增加了第一降噪子电路3和第二降噪子电路4，且在消隐阶段第一降噪子电路3可以在第一降噪控制信号的控制下，对上拉节点PU进行降噪，第二降噪子电路4可以在第二降噪控制信号的控制下，对第一信号输出端Output降噪，这样一来，可以保证在消隐阶段的移位寄存器的输出稳定性，从而避免噪声对下一帧画面显示造成影响。
在此需要说明的是，在本发明实施例的移位寄存器可以仅包括第一降噪子电路3和第二降噪子电路4中的一者，但应当理解的是，在最大程度的保证移位寄存器可以稳定输出，优选的移位寄存器同时包括第一降噪子电路3和第二降噪子电路4。在本发明实施例中为了便于描述，以移位寄存器同时包括第一降噪子电路3和第二降噪子电路4为例，对移位寄存器进行描述，当然，这并不构成对本发明实施例的限定。
在一些实施例中，如图2所示，第一降噪子电路3包括第一晶体管M1；第二降噪子电路4包括第二晶体管M2。其中，第一晶体管M1的源极连接上拉节点PU，漏极连接低电平信号端VGL，栅极连接第一降噪控制信号端TRST1。第二晶体管M2的源极连接第一信号输出端Output，漏极连接低电平信号端VGL，栅极连接第二降噪控制信号端TRST2。
在此需要说明的是，由于第一降噪子电路3和第二降噪子电路4均工作 在消隐阶段，故第一降噪控制信号和第二降噪控制信号为相同的信号，因此，第一降噪控制信号端TRST1和第二降噪控制信号端TRST2可以同一信号端。
具体的，在消隐阶段，给第一降噪控制信号端TRST1和第二降噪控制信号端TRST2输入高电平信号，此时第一晶体管M1和第二晶体管M2被打开，低电平信号端VGL被写入的低电平信号通过第一晶体管M1将上拉节点PU拉低，对上拉节点PU进行降噪；同理，低电平信号端VGL被写入的低电平信号通过第二晶体管M2将第一信号输出端Output的输出拉低，对第一信号输出端Output进行降噪。
在一些实施例中，如图3所示，该移位寄存器不仅包括上述结构，还包括多个第二输出子电路5。
在一个示例中，如图4所示，多个第二输出子电路5中的每个被配置为响应于开关控制信号，将第一信号输出端Output输出的信号通过第二信号输出端进行输出。这样一来，则可以通过一个移位寄存器为多条栅线输出扫描信号，故有助于实现显示面板的窄边化。
具体的，以移位寄存器包括三个第二输出子电路5为例。每个第二输出子电路5均可以包括第三晶体管；三个第二输出子电路5分别连接三个第二信号输出端和三个开关控制信号端；三个第二输出子电路5中的第三晶体管分别用于M31、M32、M33表示；三个第二信号输出端分别用Gateout1、Gateout2、Gateout3；三个开关控制信号端分别用SW1、SW2、SW3；其中，M31、M32、M33的三者的源极均连接第一信号输出端Output，M31的漏极连接Gateout1，M31的栅极连接SW1；M32的漏极连接Gateout2，M32的栅极连接SW2；M33的漏极连接Gateout3，M33的栅极连接SW3。
当第一输出子电路2在上拉节点PU的控制下，将时钟信号(高电平信号)通过第一信号输出端Output输出时，首先，SW1控制M31打开，Gateout1输出高电平信号；接下来，SW2控制M32打开，Gateout2输出高电平信号；最后，SW3控制M33打开，Gateout3输出高电平信号。应当理解的是，Gateout1、Gateout2、Gateout3分别对应连接显示面板中的三条栅线。
在另一个示例中，如图5所示，多个第二输出子电路5中的每个被配置为响应于第一输出信号端Output输出的信号，将驱动信号端输出的信号通过第二信号输出端(例如：Gateout1、Gateout2、Gateout3)进行输出。这样一来，则可以通过一个移位寄存器为多条栅线输出扫描信号，故有助于实现显示面板的窄边化。
具体的，以移位寄存器包括三个第二输出子电路5为例。每个第二输出子电路5均可以包括第三晶体管；三个第二输出子电路5分别连接三个第二信号输出端和三个开关控制信号端；三个第二输出子电路5中的第三晶体管分别用于M31、M32、M33表示；三个第二信号输出端分别用Gateout1、Gateout2、Gateout3；三个驱动信号端分别用TQ1、TQ2、TQ3；其中，M31、M32、M33的三者的栅极均连接第一信号输出端Output，M31的漏极连接Gateout1，M31的源极连接SW1；M32的漏极连接Gateout2，M32的源极连接SW2；M33的漏极连接Gateout3，M33的源极连接SW3。
当第一输出子电路2在上拉节点PU的控制下，将时钟信号(高电平信号)通过第一信号输出端Output输出时，M31、M32、M33均打开，首次，TQ1写入高电平信号，以使Gateout1输出高电平信号；接下来，TQ2写入高电平信号，Gateout2输出高电平信号；最后，TQ3写入高电平信号，Gateout3输出高电平信号。应当理解的是，Gateout1、Gateout2、Gateout3分别对应连接显示面板中的三条栅线。
在一些实施例中，如图6所示，移位寄存器不仅包括上述结构，该移位寄存器还包括下拉控制子电路6、下拉子电路7、第三降噪子电路8、第四降噪子电路9；其中，下拉控制子电路6被配置为响应于高电平信号，并将该高电平信号传输至下拉节点PD，该下拉节点PD为下拉控制子电路6和下拉子电路7之间的连接节点；下拉子电路7被配置为响应于上拉节点PU的电位，通过低电平信号下拉下拉下拉节点PD的电位；第三降噪子电路8被配置为响应于下拉节点PD的电位，通过低电平电位对上拉节点PU进行降噪；第四降噪子电路9被配置为响应于下拉节点PD的电位，通过低电平信号对 所述第一信号输出端Output进行降噪。
具体的，如图7、9、11所示，下拉控制子电路6可以包括第四晶体管M4和第五晶体管M5；下拉子电路7可以包括第六晶体管M6和第七晶体管M7；第三降噪子电路8可以包括第八晶体管M8；第四降噪子电路9可以包括第九晶体管M9。其中，第四晶体管M4的源极连接其栅极、第五晶体管M5的源极和高电平信号端VGH，第四晶体管M4的漏极连接第七晶体管M7的源极和所述第五晶体管M5的栅极；第五晶体管M5的漏极连接下拉节点PD；第六晶体管M6的源极连接下拉节点PD，第六晶体管M6的漏极连接低电平信号端VGL，第六晶体管M6的栅极连接上拉节点PU；第七晶体管M7的漏极极连接低电平信号端VGL，栅极连接上拉节点PU；第八晶体管M8的源极连接上拉节点PU，第八晶体管M8的漏极连接低电平信号端VGL，第八晶体管M8的栅极连接下拉节点PD；第九晶体管M9的源极连接第一信号输出端Output，第九晶体管M9的漏极连接低电平信号端VGL，第九晶体管M9的栅极连接下拉节点PD。
当某一级移位寄存器输出高电平信号，此时，上拉节点PU的处于高电平电位，此时第六晶体管M6和第七晶体管M7打开，将通过低电平信号端VGL输入的低电平信号将下拉节点PD的电位拉低，以避免第八晶体管M8和第九晶体管M9被打开而影响上拉节点PU和第一信号输出端Output输出的稳定性。
当某一级移位寄存器输出低电平信号，此时上拉节点PU处于低电平电位，高电平信号端VGH输入的高电平信号控制第四晶体管M4和第五晶体管M5打开，并通过高电平信号拉高下拉节点PD的电位，这样一来，第八晶体管M8和第九晶体管M9被打开，低电平信号端VGL输入的低电平信号将通过第八晶体管M8对上拉节点PU进行降噪，通过第九晶体管M9对第一信号输出端Output进行降噪。
在一些实施例中，如图6所示，该移位寄存器不仅可以包括上述结构，还可以包括与多个第二信号输出端一一对应设置的多个第五降噪子电路10； 多个第五降噪子电路10中的每个均响应于下拉节点PD的电位，并通过低电平信号对与之对应的第二信号输出端进行降噪。
具体的，如图9和11所示，同样以该移位寄存器包括三个第二输出子电路5为例，三个第二输出子电路5对应连接的三个第二信号输出端分别为Gateout1、Gateout2、Gateout3。其中，每个第五降噪子电路10均可以包括第十晶体管；三个第五降噪子电路10中的第十晶体管分别用M101、M102、M103表示。M101、M102、M103的栅极均连接下拉节点PD，M101的源极连接Gateout1，M102的源极连接Gateout2，M103的源极连接Gateout3，M101、M102、M103的漏极连接低电平信号端VGL。
在移位寄存器的输出低电平信号时，Gateout1、Gateout2、Gateout3输出低电平信号，上拉节点PU处于低电平电平，下拉节点PD电位被高电平信号端VGH输入的高电平信号拉高，此时，M101、M102、M103均被打开，低电平信号端VGL输入的低电平信号分别通过M101、M102、M103对Gateout1、Gateout2、Gateout3进行降噪。
在一些实施例中，该移位寄存器不仅包括上述的结构，还包括复位子电路11，该复位子电路11被配置为响应于复位信号，通过低电平信号对上拉节点PU的电位进行复位。
在一些实施例，如图7、9、11所示，在本发明实施例中复位子电路11可以包括第十一晶体管M11；其中，第十一晶体管M11的源极连接上拉节点PU，第十一晶体管M11的漏极连接第二电源电压端VSS，第十一晶体管M11的栅极连接复位信号端Reset。
具体的，在复位阶段，复位信号端Reset被写入高电平信号，第十一晶体管M11打开，通过第二电源电压端VSS写入的低电源电压对上拉节点PU的电位进行复位。
在一些实施例中，如图7、9、11所示，该移位寄存器的输入子电路1可以包括第十二晶体管M12。其中，第十二晶体管M12的源极连接第一电 源电压端VDD，第十二晶体管M12的漏极连接上拉节点PU，第十二晶体管M12的栅极连接信号输入端Input。
具体的，在输入阶段，给信号输入端Input输入高电平信号，第十二晶体管M12被打开，第一电源电压端VDD被写入的高电源电压通过第十二晶体管M12给上拉节点PU进行预充电。
在一些实施例中，如图7、9、11所示，该移位寄存器的第一输出子电路2可以包括第十三晶体管M13和存储电容C1。其中，第十三晶体管M13的源极连接时钟信号端CLK，第十三晶体管M13的漏极连接第一信号输出端Output和存储电容C1的第二端；第十三晶体管M13的栅极连接上拉节点PU和存储电容C1的第一端。
具体的，在输出阶段，由于在输入阶段上拉节点PU被预充电而拉高，且存储在存储电容C1中，在该阶段第十二晶体管M12截止，时钟信号端CLK输入高电平信号，写入存储电容C1的第二端，通过存储电容C1自举进一步将上拉节点PU的电位拉高，第十三晶体管M13打开，第一信号输出端Output则将时钟信号端CLK写入的高电平信号输出。
为了清楚本发明实施例中的移位寄存器的结构，通过以下具体示例对本发明实施例的结构及工作过程进行说明。
第一种具体示例，如图7所示，该移位寄存器包括输入子电路1，第一输出子电路2、复位子电路11、下拉控制子电路6、下拉子电路7、第一降噪子电路3、第二降噪子电路4、第三降噪子电路8和第四降噪子电路9。其中，输入子电路1包括第十二晶体管M12；第一输出子电路2包括第十三晶体管M13和存储电容C1；复位子电路11包括第十一晶体管M11；下拉控制子电路6包括第四晶体管M4和第五晶体管M5；下拉子电路7包括第六晶体管M6和第七晶体管M7；第一降噪子电路3包括第一晶体管M1；第二降噪子电路4包括第二晶体管M2；第三降噪子电路8包括第八晶体管M8；第四降噪子电路9包括第九晶体管M9。
具体的，第十二晶体管M12的源极连接第一电源电压端VDD，第十二晶体管M12的漏极连接上拉节点PU，第十二晶体管M12的栅极连接信号输入端Input；第十三晶体管M13的源极连接时钟信号端CLK，第十三晶体管M13的漏极连接第一信号输出端Output和存储电容C1的第二端；第十三晶体管M13的栅极连接上拉节点PU和存储电容C1的第一端；第十一晶体管M11的源极连接上拉节点PU，第十一晶体管M11的漏极连接第二电源电压端VSS，第十一晶体管M11的栅极连接复位信号端Reset；第四晶体管M4的源极连接其栅极、第五晶体管M5的源极和高电平信号端VGH，第四晶体管M4的漏极连接第七晶体管M7的源极和所述第五晶体管M5的栅极；第五晶体管M5的源极连接下拉节点PD；第六晶体管M6的源极连接下拉节点PD，第六晶体管M6的漏极连接低电平信号端VGL，第六晶体管M6的栅极连接上拉节点PU；第七晶体管M7的漏极极连接低电平信号端VGL，栅极连接上拉节点PU；第八晶体管M8的源极连接上拉节点PU，第八晶体管M8的漏极连接低电平信号端VGL，第八晶体管M8的栅极连接下拉节点PD；第九晶体管M9的源极连接第一信号输出端Output，第九晶体管M9的漏极连接低电平信号端VGL，第九晶体管M9的栅极连接下拉节点PD；第一晶体管M1的源极连接上拉节点PU，漏极连接低电平信号端VGL，栅极连接第一降噪控制信号端TRST1；第二晶体管M2的源极连接第一信号输出端Output，漏极连接低电平信号端VGL，栅极连接第二降噪控制信号端TRST2。
以下结合8所示的时序图，通过介绍一个移位寄存器单元在图像帧的显示阶段和两相邻帧画面显示的之间消隐阶段分别如何工作，以更清楚的了解本发明实施例移位寄存器。
图像帧的显示阶段，该移位寄存器的驱动方法具体包括如下阶段：
第一阶段(T1)，即输入阶段：输入信号端被写入高电平信号，第十二晶体管M12打开，时钟信号端CLK写入的时钟信号为低电平信号时，第一电源电压端VDD的高电源电压通过第十二晶体管M12给存储电容C1充电，使得上拉节点PU电压被拉高；在该阶段由于上拉节点PU为高电平，第六 晶体管M6和第七晶体管M7被打开，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8和第九晶体管M9保持关断，进而使得第一信号输出端Output输出稳定的低电平信号。
第二阶段(T2)，即输出阶段：输入信号端被写入低电平信号，第十二晶体管M12关断，上拉节点PU继续保持第一阶段的高电平电位，第十三晶体管M13保持开启；此时，时钟信号端CLK写入高电平信号，上拉节点PU由于存储电容C1自举效应(bootstrapping)电压被放大，以保证第十三晶体管M13持续开启，以使第一信号输出端Output输出高电平信号；此时，由于上拉节点PU为高电平信号，第六晶体管M6和第七晶体管M7持续开启，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8和第九晶体管M9继续保持关断，进而使得第一信号输出端Output输出稳定的高电平信号。
第三阶段(T3)，即复位阶段：复位信号端Reset被写入高电平信号，第十一晶体管M11打开，第二电源电压端VSS写入低电源电压信号将上拉节点PU的电位拉低，此时第十三晶体管M13、第六晶体管M6、第七晶体管M7关断；高电平信号端VGH输入的高电平信号将第四晶体管M4和第五晶体管M5打开，并将下拉节点PD的电位拉高，这样一来，第八晶体管M8和第九晶体管M9被打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU拉低，通过第九晶体管M9将第一信号输出端Output拉低。
第四阶段(T4)，即降噪阶段：第十二晶体管M12一直处于关断状态，高电平信号端VGH输入的高电平信号控制第四晶体管M4和第五晶体管M5打开，以使下拉节点PD一直处于高电平电位，第八晶体管M8、第九晶体管M9打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU进行降噪，通过第九晶体管M9将第一信号输出端Output进行降噪，此时可以使得时钟信号端CLK产生的Coupling噪声电压得以消除，从而实现第一信号输出端Output的低电平信号的输出，且保证了信号输出的稳 定性。
在下一图像帧到来之前，该移位寄存器一直重复第四阶段，不断对移位寄存器进行降噪。在该图像帧结束到下一图像帧来之前为消隐阶段。
其中，消隐阶段：第一降噪控制信号端TRST1和第二降噪控制信号端TRST2被写入高电平信号，第一晶体管M1和第二晶体管M2打开，低电平信号端VGL输入的低电平信号通过第一晶体管M1对上拉节点PU进行降噪，通过第二晶体管M2对第一信号输出端Output进行降噪，保证下一图像帧显示时，该移位寄存器可以稳定的工作，有效避免噪声对显示画面的影响。
第二种具体示例：如图9所示，该移位寄存器包括输入子电路1，第一输出子电路2、多个第二输出子电路5、复位子电路11、下拉控制子电路6、下拉子电路7、第一降噪子电路3、第二降噪子电路4、第三降噪子电路8、第四降噪子电路9，以及与三个第二输出子电路5一一对应设置的三个第五降噪子电路10。其中，输入子电路1包括第十二晶体管M12；第一输出子电路2包括第十三晶体管M13和存储电容C1；每个第二输出子电路5均包括第三晶体管；复位子电路11包括第十一晶体管M11；下拉控制子电路6包括第四晶体管M4和第五晶体管M5；下拉子电路7包括第六晶体管M6和第七晶体管M7；第一降噪子电路3包括第一晶体管M1；第二降噪子电路4包括第二晶体管M2；第三降噪子电路8包括第八晶体管M8；第四降噪子电路9包括第九晶体管M9，每个第五降噪子电路10均包括第十晶体管。其中，三个第三晶体管分别用M31、M32、M33表示，三个第十晶体管分别用M101、M102、M103表示；与三个第三晶体管对应的三个第二信号输出端分别用Gateout1、Gateout2、Gateout3，三个开关控制信号端分别用SW1、SW2、SW3。
具体的，第十二晶体管M12的源极连接第一电源电压端VDD，第十二晶体管M12的漏极连接上拉节点PU，第十二晶体管M12的栅极连接信号输入端Input；第十三晶体管M13的源极连接时钟信号端CLK，第十三晶体管M13的漏极连接第一信号输出端Output和存储电容C1的第二端；第十三晶体管M13的栅极连接上拉节点PU和存储电容C1的第一端；M31、M32、 M33的三者的源极均连接第一信号输出端Output，M31的漏极连接Gateout1，M31的栅极连接SW1；M32的漏极连接Gateout2，M32的栅极连接SW2；M33的漏极连接Gateout3，M33的栅极连接SW3；第十一晶体管M11的源极连接上拉节点PU，第十一晶体管M11的漏极连接第二电源电压端VSS，第十一晶体管M11的栅极连接复位信号端Reset；第四晶体管M4的源极连接其栅极、第五晶体管M5的源极和高电平信号端VGH，第四晶体管M4的漏极连接第七晶体管M7的源极和所述第五晶体管M5的栅极；第五晶体管M5的源极连接下拉节点PD；第六晶体管M6的源极连接下拉节点PD，第六晶体管M6的漏极连接低电平信号端VGL，第六晶体管M6的栅极连接上拉节点PU；第七晶体管M7的漏极极连接低电平信号端VGL，栅极连接上拉节点PU；第八晶体管M8的源极连接上拉节点PU，第八晶体管M8的漏极连接低电平信号端VGL，第八晶体管M8的栅极连接下拉节点PD；第九晶体管M9的源极连接第一信号输出端Output，第九晶体管M9的漏极连接低电平信号端VGL，第九晶体管M9的栅极连接下拉节点PD；第一晶体管M1的源极连接上拉节点PU，漏极连接低电平信号端VGL，栅极连接第一降噪控制信号端TRST1；第二晶体管M2的源极连接第一信号输出端Output，漏极连接低电平信号端VGL，栅极连接第二降噪控制信号端TRST2；M101、M102、M103的栅极均连接下拉节点PD，M101的源极连接Gateout1，M102的源极连接Gateout2，M103的源极连接Gateout3，M101、M102、M103的漏极连接低电平信号端VGL。
在此需要说明的是，本发明实施例中的第二输出子电路5个数局限于3个，可以根据具体情况具体设定。
以下结合10所示的时序图，通过介绍一个移位寄存器单元在图像帧的显示阶段和两相邻帧画面显示的之间消隐阶段分别如何工作，以更清楚的了解本发明实施例移位寄存器。
图像帧的显示阶段，该移位寄存器的驱动方法具体包括如下阶段：
第一阶段(T1)，即输入阶段：输入信号端被写入高电平信号，第十二 晶体管M12打开，时钟信号端CLK写入的时钟信号为低电平信号时，第一电源电压端VDD的高电源电压通过第十二晶体管M12给存储电容C1充电，使得上拉节点PU电压被拉高；在该阶段由于上拉节点PU为高电平，第六晶体管M6和第七晶体管M7被打开，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103保持关断，进而使得第一信号输出端Output输出稳定的低电平信号。
第二阶段(T2)，即输出阶段：输入信号端被写入低电平信号，第十二晶体管M12关断，上拉节点PU继续保持第一阶段的高电平电位，第十三晶体管M13保持开启；此时，时钟信号端CLK写入高电平信号，上拉节点PU由于存储电容C1自举效应(bootstrapping)电压被放大，以保证第十三晶体管M13持续开启，以使第一信号输出端Output输出高电平信号；此时，由于上拉节点PU为高电平信号，第六晶体管M6和第七晶体管M7持续开启，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8和第九晶体管M9、第十晶体管M101、M102、M103继续保持关断，进而使得第一信号输出端Output输出稳定的高电平信号；与此同时，首先SW1写入高电平信号，M31打开，SW2和SW3写入低电平信号，M32、M33保持关断，仅Gateout1将第一信号输出端Output输出的高电平信号输出；接下来，SW2写入高电平信号，M32打开，SW1和SW2写入低电平信号，M31、M33保持关断，仅Gateout2将第一信号输出端Output输出的高电平信号输出；SW3写入高电平信号，M33打开，SW1和SW2写入低电平信号，M31、M32保持关断，仅Gateout3将第一信号输出端Output输出的高电平信号输出。也即，通过一个移位寄存器完成三行栅线扫描信号的输出。
第三阶段(T3)，即复位阶段：复位信号端Reset被写入高电平信号，第十一晶体管M11打开，第二电源电压端VSS写入低电源电压信号将上拉节点PU的电位拉低，此时第十三晶体管M13、第六晶体管M6、第七晶体管M7关断；高电平信号端VGH输入的高电平信号将第四晶体管M4和第五晶 体管M5打开，并将下拉节点PD的电位拉高，这样一来，第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103被打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU拉低，通过第九晶体管M9将第一信号输出端Output拉低，通过M101、M102、M103分别将第二信号输出端Gateout1、Gateout2、Gateout3拉低。
第四阶段(T4)，即降噪阶段：第十二晶体管M12一直处于关断状态，高电平信号端VGH输入的高电平信号控制第四晶体管M4和第五晶体管M5打开，以使下拉节点PD一直处于高电平电位，第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103均打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU进行降噪，通过第九晶体管M9将第一信号输出端Output进行降噪，通过M101、M102、M103分别将第二信号输出端Gateout1、Gateout2、Gateout3降噪，此时可以使得时钟信号端CLK产生的Coupling噪声电压得以消除，从而实现第一信号输出端Output的低电平信号的输出，且保证了信号输出的稳定性。
在下一图像帧到来之前，该移位寄存器一直重复第四阶段，不断对移位寄存器进行降噪。在该图像帧结束到下一图像帧来之前为消隐阶段。
其中，消隐阶段：第一降噪控制信号端TRST1和第二降噪控制信号端TRST2被写入高电平信号，第一晶体管M1和第二晶体管M2打开，低电平信号端VGL输入的低电平信号通过第一晶体管M1对上拉节点PU进行降噪，通过第二晶体管M2对第一信号输出端Output进行降噪，保证下一图像帧显示时，该移位寄存器可以稳定的工作，有效避免噪声对显示画面的影响。
第三种具体示例：如图11所示，该移位寄存器与第二种具体示例中的移位寄存器大致相同，区别仅在于三个第二输出子电路5与分别与三个驱动信号端信号端TQ1、TQ2、TQ3和第一信号输出端Output的连接关系。具体的，在该移位寄存器中，M31、M32、M33的三者的栅极均连接第一信号输出端Output，M31的漏极连接Gateout1，M31的源极连接TQ1；M32的漏极连接Gateout2，M32的源极连接TQ2；M33的漏极连接Gateout3，M33的源 极连接TQ3。该移位寄存器的其它结构与第二种具体示例中的移位寄存器结构一样，故在此不再赘述。
以下结合12所示的时序图，通过介绍一个移位寄存器单元在图像帧的显示阶段和两相邻帧画面显示的之间消隐阶段分别如何工作，以更清楚的了解本发明实施例移位寄存器。
图像帧的显示阶段，该移位寄存器的驱动方法具体包括如下阶段：
第一阶段(T1)，即输入阶段：输入信号端被写入高电平信号，第十二晶体管M12打开，时钟信号端CLK写入的时钟信号为低电平信号时，第一电源电压端VDD的高电源电压通过第十二晶体管M12给存储电容C1充电，使得上拉节点PU电压被拉高；在该阶段由于上拉节点PU为高电平，第六晶体管M6和第七晶体管M7被打开，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103保持关断，进而使得第一信号输出端Output输出稳定的低电平信号。
第二阶段(T2)，即输出阶段：输入信号端被写入低电平信号，第十二晶体管M12关断，上拉节点PU继续保持第一阶段的高电平电位，第十三晶体管M13保持开启；此时，时钟信号端CLK写入高电平信号，上拉节点PU由于存储电容C1自举效应(bootstrapping)电压被放大，以保证第十三晶体管M13持续开启，以使第一信号输出端Output输出高电平信号；此时，由于上拉节点PU为高电平信号，第六晶体管M6和第七晶体管M7持续开启，下拉节点PD被低电源电压端写入的低电平信号拉低，从而使得第八晶体管M8和第九晶体管M9、第十晶体管M101、M102、M103继续保持关断，进而使得第一信号输出端Output输出稳定的高电平信号，M31、M32、M33均打开；与此同时，首先TQ1写入高电平信号，TQ2和TQ3写入低电平信号，此时仅Gateout1将第一信号输出端Output输出的高电平信号输出；接下来，TQ2写入高电平信号，TQ1和TQ2写入低电平信号，仅Gateout2将第一信号输出端Output输出的高电平信号输出；TQ3写入高电平信号，TQ1和TQ2 写入低电平信号，仅Gateout3将第一信号输出端Output输出的高电平信号输出。也即，通过一个移位寄存器完成三行栅线扫描信号的输出。
第三阶段(T3)，即复位阶段：复位信号端Reset被写入高电平信号，第十一晶体管M11打开，第二电源电压端VSS写入低电源电压信号将上拉节点PU的电位拉低，此时第十三晶体管M13、第六晶体管M6、第七晶体管M7关断；高电平信号端VGH输入的高电平信号将第四晶体管M4和第五晶体管M5打开，并将下拉节点PD的电位拉高，这样一来，第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103被打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU拉低，通过第九晶体管M9将第一信号输出端Output拉低，通过M101、M102、M103分别将第二信号输出端Gateout1、Gateout2、Gateout3拉低。
第四阶段(T4)，即降噪阶段：第十二晶体管M12一直处于关断状态，高电平信号端VGH输入的高电平信号控制第四晶体管M4和第五晶体管M5打开，以使下拉节点PD一直处于高电平电位，第八晶体管M8、第九晶体管M9、第十晶体管M101、M102、M103均打开，低电平信号端VGL输入的低电平信号则通过第八晶体管M8将上拉节点PU进行降噪，通过第九晶体管M9将第一信号输出端Output进行降噪，通过M101、M102、M103分别将第二信号输出端Gateout1、Gateout2、Gateout3降噪，此时可以使得时钟信号端CLK产生的Coupling噪声电压得以消除，从而实现第一信号输出端Output的低电平信号的输出，且保证了信号输出的稳定性。
在下一图像帧到来之前，该移位寄存器一直重复第四阶段，不断对移位寄存器进行降噪。在该图像帧结束到下一图像帧来之前为消隐阶段。
其中，消隐阶段：第一降噪控制信号端TRST1和第二降噪控制信号端TRST2被写入高电平信号，第一晶体管M1和第二晶体管M2打开，低电平信号端VGL输入的低电平信号通过第一晶体管M1对上拉节点PU进行降噪，通过第二晶体管M2对第一信号输出端Output进行降噪，保证下一图像帧显示时，该移位寄存器可以稳定的工作，有效避免噪声对显示画面的影响。
综上，本发明实施例提供的移位寄存器，由于增加了第一降噪子电路3和第二降噪子电路4，可以在消隐阶段对上拉节点PU和第一信号输出端Output进行降噪，从而有效的保证的下一画面帧显示的稳定性；同时，在本发明实施例中，一个移位寄存器具有多个第二输出子电路5，也即可以通过一个移位寄存器为多行栅线提供扫描信号，实现多行像素单元可以复用一个移位寄存器，从而减小了移位寄存器单元的数量，进而减小了栅极驱动电路的尺寸，使得显示面板的边框尺寸减小，能够便于实现显示面板的窄边框。
第二方面，如图13所示，本发明实施例提供一种栅极驱动电路，该栅极驱动电路包括多个级联的上述任意一种，其中，除第一级移位寄存器外，本级移位寄存器的信号输入端Input连接上一级移位寄存器的第一信号输出端Output；第一级移位寄存器的信号输入端Input连接帧选通信号；除最后一级移位寄存器外，本级移位寄存器的第一信号输出端Output连接下一级移位寄存器的复位信号端Reset。
其中，图13中仅示意出四个移位寄存器GOA1、GOA2、GOA3、GOA4，且四个移位寄存器由两个时钟信号线控制，其中GOA1、GOA2由clk1控制，GOA3、GOA4由clk2控制，但数量并不构成对本发明实施例的限制。
需要说明的是，上述第一级移位寄存器和最后一级移位寄存器是相对的，根据栅极驱动电路正向扫描和反向扫描而定。该栅极驱动电路用于对栅线进行正向扫描时，根据栅线的扫描顺序，向第一条栅线提供扫描信号的移位寄存器单元，为第一级移位寄存器；向最后一条栅线提供扫描信号的移位寄存器单元，为最后一级移位寄存器。该栅极驱动电路用于对栅线进行反向扫描时，根据栅线的扫描顺序，最后一根栅线先被输入扫描信号，因而，向最后一根栅线提供扫描信号的移位寄存器单元，为第一级移位寄存器；向第一根栅线提供扫描信号的移位寄存器单元，为最后一级移位寄存器。同时，正向扫描和反向扫描也仅需将第一电源电压端VDD和第二电源电压端VSS输入信号互换，将信号输入端Input和复位信号端Reset所输入的信号换即可。
由于在本发明实施例的栅极驱动电路包括上述的任一移位寄存器，可以 在消隐阶段对上拉节点PU和第一信号输出端Output进行降噪，从而有效的保证的下一画面帧显示的稳定性。
在一些实施例中，本发明实施例中的每个移位寄存器具有多个第二输出子电路5，故可以通过一个移位寄存器为多行栅线提供扫描信号，实现多行像素单元可以复用一个移位寄存器，从而减小了移位寄存器单元的数量，进而减小了栅极驱动电路的尺寸，使得显示面板的边框尺寸减小，能够便于实现显示面板的窄边框。
第三方面，本发明实施例提供一种显示面板，其包括上述的栅极驱动电路，包括上述的栅极驱动电路。由于包括上述的栅极驱动电路，故其显示效果较好，且可以实现窄边化设计。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (20)

  1. 一种移位寄存器，其包括：输入子电路和第一输出子电路；
    所述输入子电路被配置为响应于输入信号，并通过第一电源电压对上拉节点进行预充电；所述上拉节点为所述输入子电路、所述输出子电路及所述下拉子电路之间的连接节点；
    所述输出子电路被配置为响应于所述上拉节点的电位，而将时钟信号通过第一信号输出端进行输出；其中，
    所述移位寄存器还包括：第一降噪子电路和/或第二降噪子电路；
    所述第一降噪子电路被配置为响应于第一降噪控制信号，并在消隐阶段通过非工作电平信号，对所述上拉节点进行降噪；
    所述第二降噪子电路被配置为响应于第二降噪控制信号，并在消隐阶段通过非工作电平信号，对所述第一信号输出端进行降噪。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一降噪子电路包括第一晶体管；
    所述第一晶体管的第一极连接所述上拉节点，第二极连接非工作电平端，控制极连接第一降噪控制信号端。
  3. 根据权利要求1所述的移位寄存器，其中，所述第二降噪子电路包括第二晶体管；
    所述第二晶体管的第一极连接所述第一信号输出端，第二极连接非工作电平端，控制极连接第二降噪控制信号端。
  4. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括多个第二输出子电路；
    所述多个第二输出子电路中的每个被配置为响应于与之对应的开关控制信号，而将所述第一信号输出端输出的信号通过与之对应的第二信号输出端输出。
  5. 根据权利要求4所述的移位寄存器，其中，所述N个第二输出子电路中的每个均包括第三晶体管；
    所述第三晶体管的第一极连接所述第一信号输出端，第二极连接所述第二信号输出端，控制极连接开关控制信号端。
  6. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括多个第二输出子电路；
    所述多个第二输出子电路中的每个被配置为响应于所述第一信号输出端输出的信号，而将驱动信号通过与之对应的第二信号输出端输出。
  7. 根据权利要求6所述的移位寄存器，其中，所述多个第二输出子电路中的每个均包括第三晶体管；
    所述第三晶体管的第一极连接与之对应的驱动信号端，第二极连接所述第二信号输出端，控制极连接所述第一信号输出端。
  8. 根据权利要求4-7中任一项所述的移位寄存器，其中，所述移位寄存器还包括下拉控制子电路、下拉子电路、第三降噪子电路、第四降噪子电路；
    所述下拉控制子电路被配置为响应于工作电平信号，并将所述工作电平信号传输至下拉节点；所述下拉节点为所述下拉控制子电路和所述下拉子电路之间的连接节点；
    所述下拉子电路被配置为响应于所述上拉节点的电位，通过非工作电平信号下拉所述下拉节点的电位；
    所述第三降噪子电路被配置为响应于所述下拉节点的电位，通过所述非工作电平信号对所述上拉节点进行降噪；
    所述第四降噪子电路被配置为响应于所述下拉节点的电位，通过所述非工作电平信号对所述第一信号输出端进行降噪。
  9. 根据权利要求8所述的移位寄存器，其中，所述下拉控制子电路包括第四晶体管和第五晶体管；
    所述第四晶体管的第一极连接其控制极、所述第五晶体管的第一极和工 作电平端，第二极连接所述下拉子电路和所述第五晶体管的控制极；所述第五晶体管的第二极连接所述下拉节点。
  10. 根据权利要求8所述移位寄存器，其中，所述下拉子电路包括第六晶体管和第七晶体管；
    所述第六晶体管的第一极连接所述下拉节点，第二极连接非工作电平端，控制极连接所述上拉节点；
    所述第七晶体管的第一极连接所述上拉控制子电路，第二极连接非工作电平端，控制极连接所述上拉节点。
  11. 根据权利要求8所述的移位寄存器，其中，所述第三降噪子电路包括第八晶体管；
    所述第八晶体管的第一极所述上拉节点，第二极连接非工作电平端，控制极连接所述下拉节点。
  12. 根据权利要求8所述的移位寄存器，其中，所述第四降噪子电路包括第九晶体管；
    所述第九晶体管的第一极连接所述第一信号输出端，第二极连接非工作电平端，控制极连接所述下拉节点。
  13. 根据权利要求8-12中任一项所述的移位寄存器，其中，所述移位寄存器还包括与所述多第二信号输出端一一对应设置的多个第五降噪子电路；
    所述多个第五降噪子电路中的每个被配置响应于所述下拉节点的电位，而通过所述非工作电平信号对与之对应的所述第二输出端进行降噪。
  14. 根据权利要求13所述的移位寄存器，其中，所述多个第五降噪子电路中的每个均包括第十晶体管；
    所述第十晶体管的第一极连接与之对应的第二信号输出端，第二极连接非工作电平端，控制极连接所述下拉节点。
  15. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器还包括复位子电路；
    所述复位子电路被配置为响应于复位信号，通过第二电源电压对所述上拉节点进行复位。
  16. 根据权利要求15所述的移位寄存器，其中，所述复位子电路包括第十一晶体管；
    所述第十一晶体管的第一极连接上拉节点，第二极连接第二电源电压端，控制极连接复位信号端。
  17. 根据权利要求1所述的移位寄存器，其中，所述输入子电路包括第十二晶体管；
    所述第十二晶体管的第一极连接第一电源电压端，第二极连接上拉节点，控制极连接信号输入端。
  18. 根据权利要求1所述的移位寄存器，其中，所述输出子电路包括第十三晶体管和存储电容；
    所述第十三晶体管的第一极连接时钟信号端，第二极连接信号输出端和所述存储电容的第二端，控制极连接所述上拉节点和所述存储电容的第一端。
  19. 一种栅极驱动电路，其包括：权利要求1-18中任一项所述移位寄存器；其中，
    本级所述移位寄存器的信号输入端连接上一级所述移位寄存器的信号输出端；本级所述移位寄存器的复位信号端连接下一级所述移位寄存器的信号输出端。
  20. 一种显示面板，其包括权利要求19所述的栅极驱动电路。
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