WO2021169562A1 - 移位寄存器、栅极驱动电路及显示面板 - Google Patents
移位寄存器、栅极驱动电路及显示面板 Download PDFInfo
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- WO2021169562A1 WO2021169562A1 PCT/CN2020/140528 CN2020140528W WO2021169562A1 WO 2021169562 A1 WO2021169562 A1 WO 2021169562A1 CN 2020140528 W CN2020140528 W CN 2020140528W WO 2021169562 A1 WO2021169562 A1 WO 2021169562A1
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- 230000009467 reduction Effects 0.000 claims abstract description 126
- 230000004044 response Effects 0.000 claims abstract description 16
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- 101100069049 Caenorhabditis elegans goa-1 gene Proteins 0.000 description 2
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- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 1
- 101100003180 Colletotrichum lindemuthianum ATG1 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0404—Matrix technologies
- G09G2300/0408—Integration of the drivers onto the display substrate
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
Definitions
- the invention belongs to the field of display technology, and specifically relates to a shift register, a gate drive circuit and a display panel.
- GOA Gate Driver on Array, integrated gate driver circuit
- GOA Gate Driver on Array, integrated gate driver circuit
- Pole drive integrated circuit Pole drive integrated circuit part and fan-out (Fan-out) wiring space to simplify the structure of display products.
- the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display panel.
- an embodiment of the present invention provides a shift register, which includes: an input sub-circuit and a first output sub-circuit;
- the input sub-circuit is configured to respond to an input signal and pre-charge a pull-up node through a first power supply voltage;
- the pull-up node is the input sub-circuit, the output sub-circuit, and the pull-down sub-circuit Connection node between;
- the output sub-circuit is configured to output a clock signal through the first signal output terminal in response to the potential of the pull-up node;
- the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit;
- the first noise reduction sub-circuit is configured to respond to the first noise reduction control signal and use a non-operating level signal during the blanking phase to reduce noise on the pull-up node;
- the second noise reduction sub-circuit is configured to respond to the second noise reduction control signal and use a non-operating level signal during the blanking phase to reduce noise on the first signal output terminal.
- the first noise reduction sub-circuit includes a first transistor
- the first electrode of the first transistor is connected to the pull-up node, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the first noise reduction control signal terminal.
- the second noise reduction sub-circuit includes a second transistor
- the first electrode of the second transistor is connected to the first signal output terminal, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the second noise reduction control signal terminal.
- the shift register further includes a plurality of second output sub-circuits
- Each of the plurality of second output sub-circuits is configured to respond to the corresponding switch control signal, and output the signal output from the first signal output terminal through the corresponding second signal output terminal.
- each of the plurality of second output sub-circuits includes a third transistor
- the first pole of the third transistor is connected to the first signal output terminal, the second pole is connected to the second signal output terminal, and the control pole is connected to the switch control signal terminal.
- the shift register further includes a plurality of second output sub-circuits
- Each of the plurality of second output sub-circuits is configured to respond to the signal output by the first signal output terminal and output a driving signal through the second signal output terminal corresponding thereto.
- each of the plurality of second output sub-circuits includes a third transistor
- the first electrode of the third transistor is connected to the corresponding driving signal terminal, the second electrode is connected to the second signal output terminal, and the control electrode is connected to the first signal output terminal.
- the shift register further includes a pull-down control sub-circuit, a pull-down sub-circuit, a third noise reduction sub-circuit, and a fourth noise reduction sub-circuit;
- the pull-down control sub-circuit is configured to respond to a working level signal and transmit the working level signal to a pull-down node;
- the pull-down node is a connection between the pull-down control sub-circuit and the pull-down sub-circuit node;
- the pull-down sub-circuit is configured to pull down the potential of the pull-down node through a non-operating level signal in response to the potential of the pull-up node;
- the third noise reduction sub-circuit is configured to reduce noise on the pull-up node through the non-operating level signal in response to the potential of the pull-down node;
- the fourth noise reduction sub-circuit is configured to reduce noise on the first signal output terminal through the non-operating level signal in response to the potential of the pull-down node.
- the pull-down control sub-circuit includes a fourth transistor and a fifth transistor;
- the first electrode of the fourth transistor is connected to its control electrode, the first electrode of the fifth transistor and the working level terminal, and the second electrode is connected to the pull-down sub-circuit and the control electrode of the fifth transistor;
- the second pole of the five transistor is connected to the pull-down node.
- the pull-down sub-circuit includes a sixth transistor and a seventh transistor;
- a first pole of the sixth transistor is connected to the pull-down node, a second pole is connected to a non-operating level terminal, and a control pole is connected to the pull-up node;
- the first pole of the seventh transistor is connected to the pull-up control sub-circuit, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-up node.
- the third noise reduction sub-circuit includes an eighth transistor
- the first pole of the eighth transistor is connected to the pull-up node, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-down node.
- the fourth noise reduction sub-circuit includes a ninth transistor
- the first electrode of the ninth transistor is connected to the first signal output terminal, the second electrode is connected to the non-operating level terminal, and the control electrode is connected to the pull-down node.
- the shift register further includes a plurality of fifth noise reduction sub-circuits arranged in a one-to-one correspondence with the multiple second signal output terminals;
- Each of the plurality of fifth noise reduction sub-circuits is configured to respond to the potential of the pull-down node to reduce the noise of the second output terminal corresponding thereto through the non-operating level signal.
- each of the plurality of fifth noise reduction sub-circuits includes a tenth transistor
- the first pole of the tenth transistor is connected to the corresponding second signal output terminal, the second pole is connected to the non-operating level terminal, and the control pole is connected to the pull-down node.
- the shift register further includes a reset sub-circuit
- the reset sub-circuit is configured to reset the pull-up node through a second power supply voltage in response to a reset signal.
- the reset sub-circuit includes an eleventh transistor
- the first electrode of the eleventh transistor is connected to the pull-up node, the second electrode is connected to the second power supply voltage terminal, and the control electrode is connected to the reset signal terminal.
- the input sub-circuit includes a twelfth transistor
- the first electrode of the twelfth transistor is connected to the first power supply voltage terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the signal input terminal.
- the output sub-circuit includes a thirteenth transistor and a storage capacitor
- the first electrode of the thirteenth transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal and the second terminal of the storage capacitor, and the control electrode is connected to the pull-up node and the first terminal of the storage capacitor.
- an embodiment of the present invention provides a gate driving circuit, which includes the above-mentioned shift register; wherein,
- the signal input terminal of the shift register of this stage is connected to the signal output terminal of the shift register of the previous stage; the reset signal terminal of the shift register of this stage is connected to the signal output terminal of the shift register of the next stage.
- an embodiment of the present invention provides a display panel including the above-mentioned gate driving circuit.
- FIG. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention.
- FIG. 2 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
- FIG. 3 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
- FIG. 4 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
- FIG. 5 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
- FIG. 6 is a schematic structural diagram of another shift register according to an embodiment of the present invention.
- FIG. 7 is a circuit of a shift register according to an embodiment of the present invention.
- FIG. 8 is a working timing diagram of the shift register of FIG. 7.
- FIG. 9 is a circuit diagram of another shift register according to an embodiment of the present invention.
- FIG. 10 is a working timing diagram of the shift register of FIG. 9.
- FIG. 11 is a circuit of a shift register according to an embodiment of the present invention.
- Fig. 12 is a working timing diagram of the shift register of Fig. 11.
- FIG. 13 is a schematic diagram of a cascade connection of a gate driving circuit according to an embodiment of the present invention.
- the existing display panel usually has a display area and a peripheral area surrounding the display area; a plurality of pixel units arranged in an array are arranged in the display area, and each pixel unit is provided with a pixel circuit; among them, pixels located in the same row
- the cells are connected to the same gate line, and the pixel cells located in the same column are connected to the same data line.
- a gate drive circuit is provided in the peripheral area, and the gate drive circuit includes a plurality of cascaded shift registers GOA.
- the shift registers and the gate lines are arranged in one-to-one correspondence, that is, each shift register is connected to a gate line .
- the gate scan signal is output to the corresponding gate line through the step-by-step shift register to complete the row-by-row scan of the pixel circuit. While each row of the gate line is scanned, each data line The data voltage signal is written into the pixel circuit of the row to light up the pixel unit of the row. There is a blanking stage between the display of two frames. At this time, the pixel units of each row are not displayed. At this time, the shift register is required to output a stable non-operating level signal to ensure the display of this frame. When finished, the next frame can be displayed stably.
- the inventor provides the following embodiments.
- the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, the source There is no difference between the drain and the drain. In the embodiment of the present invention, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for description. When N-type transistors are used, the first pole is the source of the N-type transistor, and the second pole is the source of the N-type transistor.
- the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; correspondingly, The working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.
- the first power supply voltage written at the first power supply voltage terminal is higher than the second power supply voltage written at the second power supply voltage terminal.
- the first power supply voltage is the high power supply voltage
- the second power supply voltage is Take low power supply voltage as an example.
- an embodiment of the present invention provides a shift register, which includes an input sub-circuit 1 and a first output sub-circuit 2; in particular, the embodiment of the present invention also includes a first noise reduction Sub-circuit 3 and/or second noise reduction sub-circuit 4.
- the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4 are added to the shift register of the embodiment of the present invention, and in the blanking stage, the first noise reduction sub-circuit 3 can be used in the first noise reduction control signal. Under control, the pull-up node PU is noise-reduced.
- the second noise reduction sub-circuit 4 can reduce the noise of the first signal output terminal Output under the control of the second noise reduction control signal.
- the output of the shift register is stable in the stage, so as to avoid the influence of noise on the display of the next frame.
- the shift register in the embodiment of the present invention may only include one of the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4, but it should be understood that the maximum guarantee The shift register can output stably.
- the preferred shift register includes the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4 at the same time.
- the shift register is described as an example where the shift register includes both the first noise reduction sub-circuit 3 and the second noise reduction sub-circuit 4. Of course, this does not constitute an implementation of the present invention. Limitations of examples.
- the first noise reduction sub-circuit 3 includes a first transistor M1; the second noise reduction sub-circuit 4 includes a second transistor M2.
- the source of the first transistor M1 is connected to the pull-up node PU, the drain is connected to the low-level signal terminal VGL, and the gate is connected to the first noise reduction control signal terminal TRST1.
- the source of the second transistor M2 is connected to the first signal output terminal Output, the drain is connected to the low-level signal terminal VGL, and the gate is connected to the second noise reduction control signal terminal TRST2.
- the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 may be the same signal terminal.
- a high level signal is input to the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2.
- the first transistor M1 and the second transistor M2 are turned on, and the low level signal
- the low-level signal written to the terminal VGL pulls the pull-up node PU low through the first transistor M1 to reduce the noise of the pull-up node PU; in the same way, the low-level signal written to the low-level signal terminal VGL passes
- the second transistor M2 pulls the output of the first signal output terminal Output low to reduce noise on the first signal output terminal Output.
- the shift register not only includes the above structure, but also includes a plurality of second output sub-circuits 5.
- each of the plurality of second output sub-circuits 5 is configured to output the signal output by the first signal output terminal Output through the second signal output terminal in response to the switch control signal .
- one shift register can be used to output scan signals for multiple gate lines, which helps to achieve narrower edges of the display panel.
- Each second output sub-circuit 5 may include a third transistor; the three second output sub-circuits 5 are respectively connected to three second signal output terminals and three switch control signal terminals; in the three second output sub-circuits 5
- the third transistor is used for M31, M32, M33 respectively; the three second signal output terminals are respectively Gateout1, Gateout2, Gateout3; the three switch control signal terminals are respectively used SW1, SW2, SW3; among them, M31, M32, M33
- the sources of the three are all connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the gate of M31 is connected to SW1; the drain of M32 is connected to Gateout2, the gate of M32 is connected to SW2; the drain of M33 is connected to Gateout3, M33 The gate is connected to SW3.
- each of the plurality of second output sub-circuits 5 is configured to respond to the signal output by the first output signal terminal Output and pass the signal output by the driving signal terminal through the second signal Output terminal (for example: Gateout1, Gateout2, Gateout3) for output.
- the second signal Output terminal for example: Gateout1, Gateout2, Gateout3
- one shift register can be used to output scan signals for multiple gate lines, which helps to achieve narrower edges of the display panel.
- Each second output sub-circuit 5 may include a third transistor; the three second output sub-circuits 5 are respectively connected to three second signal output terminals and three switch control signal terminals; in the three second output sub-circuits 5
- the third transistor is used for M31, M32, and M33 respectively; the three second signal output terminals are respectively Gateout1, Gateout2, Gateout3; the three drive signal terminals are respectively used TQ1, TQ2, TQ3; among them, the three of M31, M32, and M33
- the gates of both are connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the source of M31 is connected to SW1; the drain of M32 is connected to Gateout2, the source of M32 is connected to SW2; the drain of M33 is connected to Gateout3, and the source of M33 is connected to SW2.
- the source is connected to SW3.
- the shift register not only includes the above structure, the shift register also includes a pull-down control sub-circuit 6, a pull-down sub-circuit 7, a third noise reduction sub-circuit 8, and a fourth noise reduction sub-circuit.
- the pull-down sub-circuit 7 is configured to pull down the potential of the pull-down node PD through a low-level signal in response to the potential of the pull-up node PU;
- the third noise reduction sub-circuit 8 is configured to respond to the potential of the pull-down node PD , Noise reduction is performed on the pull-up node PU through a low-level potential;
- the fourth noise reduction sub-circuit 9 is configured to respond to the potential of the pull-down node PD and perform noise reduction on the first signal output terminal Output through a low-level signal .
- the pull-down control sub-circuit 6 may include a fourth transistor M4 and a fifth transistor M5; the pull-down sub-circuit 7 may include a sixth transistor M6 and a seventh transistor M7; and the third noise reduction The sub-circuit 8 may include an eighth transistor M8; the fourth noise reduction sub-circuit 9 may include a ninth transistor M9.
- the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain of the fourth transistor M4 is connected to the source of the seventh transistor M7 and the fifth transistor.
- the gate of M5; the drain of the fifth transistor M5 is connected to the pull-down node PD; the source of the sixth transistor M6 is connected to the pull-down node PD, the drain of the sixth transistor M6 is connected to the low-level signal terminal VGL, and the gate of the sixth transistor M6
- the drain of the seventh transistor M7 is connected to the low-level signal terminal VGL, and the gate is connected to the pull-up node PU;
- the source of the eighth transistor M8 is connected to the pull-up node PU, and the drain of the eighth transistor M8
- the electrode is connected to the low-level signal terminal VGL, the gate of the eighth transistor M8 is connected to the pull-down node PD; the source of the ninth transistor M9 is connected to the first signal output terminal Output, and the drain of the ninth transistor M9 is connected to the low-level signal terminal VGL ,
- the gate of the ninth transistor M9 is connected to the pull-down node PD.
- the pull-up node PU When a shift register of a certain stage outputs a high-level signal, at this time, the pull-up node PU is at a high-level potential. At this time, the sixth transistor M6 and the seventh transistor M7 are turned on, and the input signal will be input through the low-level signal terminal VGL. The low-level signal pulls down the potential of the pull-down node PD to prevent the eighth transistor M8 and the ninth transistor M9 from being turned on and affect the stability of the pull-up node PU and the output of the first signal output terminal Output.
- the pull-up node PU When a shift register of a certain stage outputs a low-level signal, the pull-up node PU is at a low-level potential at this time, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on, and The potential of the pull-down node PD is pulled up by a high-level signal, so that the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL will be pulled up through the eighth transistor M8.
- the node PU performs noise reduction
- the ninth transistor M9 performs noise reduction on the first signal output terminal Output.
- the shift register may not only include the above structure, but may also include a plurality of fifth noise reduction sub-circuits 10 arranged in a one-to-one correspondence with the plurality of second signal output terminals;
- Each of the fifth noise reduction sub-circuits 10 responds to the potential of the pull-down node PD, and performs noise reduction on the second signal output terminal corresponding thereto through a low-level signal.
- each fifth noise reduction sub-circuit 10 may include a tenth transistor; the tenth transistors in the three fifth noise reduction sub-circuits 10 are denoted by M101, M102, and M103, respectively.
- the gates of M101, M102, and M103 are all connected to the pull-down node PD, the source of M101 is connected to Gateout1, the source of M102 is connected to Gateout2, the source of M103 is connected to Gateout3, and the drain of M101, M102, M103 is connected to the low-level signal terminal VGL .
- Gateout1, Gateout2, and Gateout3 When the shift register outputs a low-level signal, Gateout1, Gateout2, and Gateout3 output a low-level signal, the pull-up node PU is at a low level, and the pull-down node PD is at a high level input by the high-level signal terminal VGH. The signal is pulled high. At this time, M101, M102, and M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is used to reduce the noise of Gateout1, Gateout2, and Gateout3 through M101, M102, and M103, respectively.
- the shift register not only includes the aforementioned structure, but also includes a reset sub-circuit 11 configured to reset the potential of the pull-up node PU through a low-level signal in response to a reset signal. .
- the reset sub-circuit 11 may include an eleventh transistor M11; wherein, the source of the eleventh transistor M11 is connected to the pull-up node PU, and the source of the eleventh transistor M11 is connected to the pull-up node PU.
- the drain of the eleventh transistor M11 is connected to the second power supply voltage terminal VSS, and the gate of the eleventh transistor M11 is connected to the reset signal terminal Reset.
- the reset signal terminal Reset is written with a high-level signal
- the eleventh transistor M11 is turned on
- the potential of the pull-up node PU is reset by the low power supply voltage written by the second power supply voltage terminal VSS.
- the input sub-circuit 1 of the shift register may include a twelfth transistor M12.
- the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD
- the drain of the twelfth transistor M12 is connected to the pull-up node PU
- the gate of the twelfth transistor M12 is connected to the signal input terminal Input.
- a high-level signal is input to the signal input terminal Input, the twelfth transistor M12 is turned on, and the high power supply voltage written into the first power supply voltage terminal VDD is sent to the pull-up node PU through the twelfth transistor M12. Perform pre-charging.
- the first output sub-circuit 2 of the shift register may include a thirteenth transistor M13 and a storage capacitor C1.
- the source of the thirteenth transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to Pull the node PU and the first end of the storage capacitor C1.
- the pull-up node PU is precharged and pulled high during the input stage and stored in the storage capacitor C1.
- the twelfth transistor M12 is turned off, and the clock signal terminal CLK inputs a high-level signal.
- the thirteenth transistor M13 is turned on, and the first signal output terminal Output writes the clock signal terminal CLK high Level signal output.
- the shift register includes an input sub-circuit 1, a first output sub-circuit 2, a reset sub-circuit 11, a pull-down control sub-circuit 6, a pull-down sub-circuit 7, and a first noise reduction sub-circuit Circuit 3, second noise reduction sub-circuit 4, third noise reduction sub-circuit 8 and fourth noise reduction sub-circuit 9.
- the input sub-circuit 1 includes a twelfth transistor M12; the first output sub-circuit 2 includes a thirteenth transistor M13 and a storage capacitor C1; the reset sub-circuit 11 includes an eleventh transistor M11; the pull-down control sub-circuit 6 includes a fourth transistor M4 and the fifth transistor M5; the pull-down sub-circuit 7 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 3 includes a first transistor M1; the second noise reduction sub-circuit 4 includes a second transistor M2; The noise reduction sub-circuit 8 includes an eighth transistor M8; the fourth noise reduction sub-circuit 9 includes a ninth transistor M9.
- the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD, the drain of the twelfth transistor M12 is connected to the pull-up node PU, and the gate of the twelfth transistor M12 is connected to the signal input terminal Input;
- the source of the transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to the pull-up node PU and the storage
- the first terminal of the capacitor C1; the source of the eleventh transistor M11 is connected to the pull-up node PU, the drain of the eleventh transistor M11 is connected to the second power supply voltage terminal VSS, and the gate of the eleventh transistor M11 is connected to the reset signal terminal Reset ;
- the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain
- the driving method of the shift register specifically includes the following stages:
- the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
- the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8 and the ninth transistor M9 are kept off, and the first signal output terminal Output outputs a stable low-level signal .
- the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
- the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8 and the ninth transistor M9 continue to be turned off, so that the first signal output terminal Output outputs a stable high-level signal.
- the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL pulls the pull-up node PU low through the eighth transistor M8.
- the nine transistor M9 pulls the first signal output terminal Output low.
- the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
- the node PD is always at a high level potential
- the eighth transistor M8 and the ninth transistor M9 are turned on, and the low-level signal input from the low-level signal terminal VGL is used to reduce the noise of the pull-up node PU through the eighth transistor M8.
- the transistor M9 reduces the noise of the first signal output terminal Output.
- the coupling noise voltage generated by the clock signal terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output and ensuring the signal output The stability.
- the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
- the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
- the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
- the shift register includes an input sub-circuit 1, a first output sub-circuit 2, a plurality of second output sub-circuits 5, a reset sub-circuit 11, a pull-down control sub-circuit 6, a pull-down
- the sub-circuit 7, the first noise reduction sub-circuit 3, the second noise reduction sub-circuit 4, the third noise reduction sub-circuit 8, the fourth noise reduction sub-circuit 9, and the three second output sub-circuits 5 are arranged in one-to-one correspondence
- the input sub-circuit 1 includes a twelfth transistor M12; the first output sub-circuit 2 includes a thirteenth transistor M13 and a storage capacitor C1; each second output sub-circuit 5 includes a third transistor; the reset sub-circuit 11 includes a Eleven transistors M11; the pull-down control sub-circuit 6 includes a fourth transistor M4 and a fifth transistor M5; the pull-down sub-circuit 7 includes a sixth transistor M6 and a seventh transistor M7; the first noise reduction sub-circuit 3 includes a first transistor M1; The second noise reduction sub-circuit 4 includes a second transistor M2; the third noise reduction sub-circuit 8 includes an eighth transistor M8; the fourth noise reduction sub-circuit 9 includes a ninth transistor M9, and each fifth noise reduction sub-circuit 10 includes a first Ten transistors.
- the three third transistors are represented by M31, M32, and M33, and the three tenth transistors are represented by M101, M102, and M103; the three second signal output terminals corresponding to the three third transistors are represented by Gateout1, Gateout2, respectively. , Gateout3, the three switch control signal terminals use SW1, SW2, and SW3 respectively.
- the source of the twelfth transistor M12 is connected to the first power supply voltage terminal VDD, the drain of the twelfth transistor M12 is connected to the pull-up node PU, and the gate of the twelfth transistor M12 is connected to the signal input terminal Input;
- the source of the transistor M13 is connected to the clock signal terminal CLK, the drain of the thirteenth transistor M13 is connected to the first signal output terminal Output and the second end of the storage capacitor C1; the gate of the thirteenth transistor M13 is connected to the pull-up node PU and the storage
- the first terminal of the capacitor C1; the sources of M31, M32, and M33 are all connected to the first signal output terminal Output, the drain of M31 is connected to Gateout1, the gate of M31 is connected to SW1; the drain of M32 is connected to Gateout2, and that of M32 The gate is connected to SW2; the drain of M33 is connected to Gateout3, and the gate of M33 is connected to SW3; the source of the eleventh transistor
- the gate of the eleven transistor M11 is connected to the reset signal terminal Reset; the source of the fourth transistor M4 is connected to its gate, the source of the fifth transistor M5 and the high-level signal terminal VGH, and the drain of the fourth transistor M4 is connected to the seventh
- the driving method of the shift register specifically includes the following stages:
- the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
- the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 are kept off, thereby making the first signal output The terminal Output outputs a stable low-level signal.
- the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
- the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 continue to be turned off, so that the first signal output terminal
- the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 are turned on, and the low-level signal input from the low-level signal terminal VGL passes through the eighth transistor M8.
- the pull-up node PU is pulled low, the first signal output terminal Output is pulled low through the ninth transistor M9, and the second signal output terminals Gateout1, Gateout2, and Gateout3 are pulled low through M101, M102, and M103, respectively.
- the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
- the node PD is always at a high-level potential
- the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is passed through the eighth transistor M8.
- the node PU is pulled to reduce noise
- the first signal output terminal Output is reduced through the ninth transistor M9
- the second signal output terminals Gateout1, Gateout2, Gateout3 are respectively reduced by M101, M102, and M103.
- the clock signal can be reduced.
- the coupling noise voltage generated by the terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output, and ensuring the stability of the signal output.
- the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
- the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
- the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
- the shift register is roughly the same as the shift register in the second specific example, except that the three second output sub-circuits 5 and the three driving signal terminal signals are different from each other.
- the gates of M31, M32, and M33 are all connected to the first signal output terminal Output
- the drain of M31 is connected to Gateout1
- the source of M31 is connected to TQ1
- the drain of M32 is connected to Gateout2.
- the source of M32 is connected to TQ2
- the drain of M33 is connected to Gateout3
- the source of M33 is connected to TQ3.
- the other structure of the shift register is the same as the structure of the shift register in the second specific example, so it will not be repeated here.
- the driving method of the shift register specifically includes the following stages:
- the first stage (T1) the input stage: when the input signal terminal is written with a high-level signal, the twelfth transistor M12 is turned on, and the clock signal written by the clock signal terminal CLK is a low-level signal, the first power supply voltage terminal
- the high power supply voltage of VDD charges the storage capacitor C1 through the twelfth transistor M12, so that the voltage of the pull-up node PU is pulled up; at this stage, because the pull-up node PU is high, the sixth transistor M6 and the seventh transistor M7 are Turn on, the pull-down node PD is pulled low by the low-level signal written in the low power supply voltage terminal, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 are kept off, thereby making the first signal output The terminal Output outputs a stable low-level signal.
- the second stage (T2) that is, the output stage: the input signal terminal is written with a low-level signal, the twelfth transistor M12 is turned off, and the pull-up node PU continues to maintain the high-level potential of the first stage, and the thirteenth transistor M13 Keep on; at this time, the clock signal terminal CLK writes a high-level signal, and the pull-up node PU is amplified due to the bootstrapping voltage of the storage capacitor C1 to ensure that the thirteenth transistor M13 is continuously turned on to make the first signal
- the output terminal Output outputs a high-level signal; at this time, because the pull-up node PU is a high-level signal, the sixth transistor M6 and the seventh transistor M7 are continuously turned on, and the pull-down node PD is a low-level signal written by the low power supply voltage terminal Pull down, so that the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, and M103 continue to be turned off, so that the first signal output
- the eighth transistor M8, the ninth transistor M9, the tenth transistor M101, M102, and M103 are turned on, and the low-level signal input from the low-level signal terminal VGL passes through the eighth transistor M8.
- the pull-up node PU is pulled low, the first signal output terminal Output is pulled low through the ninth transistor M9, and the second signal output terminals Gateout1, Gateout2, and Gateout3 are pulled low through M101, M102, and M103, respectively.
- the fourth stage (T4), the noise reduction stage: the twelfth transistor M12 is always in the off state, and the high-level signal input from the high-level signal terminal VGH controls the fourth transistor M4 and the fifth transistor M5 to turn on to pull down
- the node PD is always at a high-level potential
- the eighth transistor M8, the ninth transistor M9, and the tenth transistor M101, M102, M103 are all turned on, and the low-level signal input from the low-level signal terminal VGL is passed through the eighth transistor M8.
- the node PU is pulled to reduce noise
- the first signal output terminal Output is reduced through the ninth transistor M9
- the second signal output terminals Gateout1, Gateout2, Gateout3 are respectively reduced by M101, M102, and M103.
- the clock signal can be reduced.
- the coupling noise voltage generated by the terminal CLK can be eliminated, thereby realizing the output of the low-level signal of the first signal output terminal Output, and ensuring the stability of the signal output.
- the shift register keeps repeating the fourth stage to continuously reduce the noise of the shift register. It is the blanking stage before the end of the image frame to the next image frame.
- the blanking stage the first noise reduction control signal terminal TRST1 and the second noise reduction control signal terminal TRST2 are written with high-level signals, the first transistor M1 and the second transistor M2 are turned on, and the low-level signal terminal VGL is input.
- the low-level signal reduces the noise of the pull-up node PU through the first transistor M1, and reduces the noise of the first signal output terminal Output through the second transistor M2 to ensure that the shift register can work stably when the next image frame is displayed. , Effectively avoid the influence of noise on the display screen.
- a shift register has multiple second output sub-circuits 5, that is, multiple The row gate lines provide scanning signals, so that multiple rows of pixel units can be multiplexed with a shift register, thereby reducing the number of shift register units, thereby reducing the size of the gate driving circuit, and reducing the frame size of the display panel , which can facilitate the realization of the narrow frame of the display panel.
- an embodiment of the present invention provides a gate drive circuit, the gate drive circuit includes a plurality of cascaded any of the above, wherein, in addition to the first stage of shift register, the present The signal input terminal Input of the first stage shift register is connected to the first signal output terminal Output of the previous stage shift register; the signal input terminal Input of the first stage shift register is connected to the frame strobe signal; except for the last stage shift register, The first signal output terminal Output of the shift register of the current stage is connected to the reset signal terminal Reset of the shift register of the next stage.
- Figure 13 only shows four shift registers GOA1, GOA2, GOA3, GOA4, and the four shift registers are controlled by two clock signal lines.
- GOA1, GOA2 are controlled by clk1
- GOA3, GOA4 are controlled by clk2.
- the number does not constitute a limitation to the embodiment of the present invention.
- first-stage shift register and the last-stage shift register are opposite, and are determined according to the forward scan and the reverse scan of the gate drive circuit.
- the shift register unit that provides the scanning signal to the first gate line is the first-stage shift register;
- the shift register unit that provides scanning signals is the last stage shift register.
- the shift register unit that provides the scanning signal to the last gate line Is the first stage shift register; the shift register unit that provides the scan signal to the first gate line is the last stage shift register.
- forward scanning and reverse scanning only need to exchange the input signals of the first power supply voltage terminal VDD and the second power supply voltage terminal VSS, and exchange the signals input from the signal input terminal Input and the reset signal terminal Reset.
- the gate driving circuit in the embodiment of the present invention includes any of the above-mentioned shift registers, the noise of the pull-up node PU and the first signal output terminal Output can be reduced in the blanking stage, thereby effectively ensuring the next picture frame Show stability.
- each shift register in the embodiment of the present invention has multiple second output sub-circuits 5, so one shift register can provide scanning signals for multiple rows of gate lines, so that multiple rows of pixel units can be replicated.
- the number of shift register units is reduced, and the size of the gate driving circuit is reduced, so that the frame size of the display panel is reduced, which can facilitate the realization of the narrow frame of the display panel.
- an embodiment of the present invention provides a display panel including the above-mentioned gate driving circuit, including the above-mentioned gate driving circuit. Since the above-mentioned gate driving circuit is included, the display effect is better, and a narrow-edge design can be realized.
- the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
- the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, and so on.
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Abstract
Description
Claims (20)
- 一种移位寄存器,其包括:输入子电路和第一输出子电路;所述输入子电路被配置为响应于输入信号,并通过第一电源电压对上拉节点进行预充电;所述上拉节点为所述输入子电路、所述输出子电路及所述下拉子电路之间的连接节点;所述输出子电路被配置为响应于所述上拉节点的电位,而将时钟信号通过第一信号输出端进行输出;其中,所述移位寄存器还包括:第一降噪子电路和/或第二降噪子电路;所述第一降噪子电路被配置为响应于第一降噪控制信号,并在消隐阶段通过非工作电平信号,对所述上拉节点进行降噪;所述第二降噪子电路被配置为响应于第二降噪控制信号,并在消隐阶段通过非工作电平信号,对所述第一信号输出端进行降噪。
- 根据权利要求1所述的移位寄存器,其中,所述第一降噪子电路包括第一晶体管;所述第一晶体管的第一极连接所述上拉节点,第二极连接非工作电平端,控制极连接第一降噪控制信号端。
- 根据权利要求1所述的移位寄存器,其中,所述第二降噪子电路包括第二晶体管;所述第二晶体管的第一极连接所述第一信号输出端,第二极连接非工作电平端,控制极连接第二降噪控制信号端。
- 根据权利要求1所述的移位寄存器,其中,所述移位寄存器还包括多个第二输出子电路;所述多个第二输出子电路中的每个被配置为响应于与之对应的开关控制信号,而将所述第一信号输出端输出的信号通过与之对应的第二信号输出端输出。
- 根据权利要求4所述的移位寄存器,其中,所述N个第二输出子电路中的每个均包括第三晶体管;所述第三晶体管的第一极连接所述第一信号输出端,第二极连接所述第二信号输出端,控制极连接开关控制信号端。
- 根据权利要求1所述的移位寄存器,其中,所述移位寄存器还包括多个第二输出子电路;所述多个第二输出子电路中的每个被配置为响应于所述第一信号输出端输出的信号,而将驱动信号通过与之对应的第二信号输出端输出。
- 根据权利要求6所述的移位寄存器,其中,所述多个第二输出子电路中的每个均包括第三晶体管;所述第三晶体管的第一极连接与之对应的驱动信号端,第二极连接所述第二信号输出端,控制极连接所述第一信号输出端。
- 根据权利要求4-7中任一项所述的移位寄存器,其中,所述移位寄存器还包括下拉控制子电路、下拉子电路、第三降噪子电路、第四降噪子电路;所述下拉控制子电路被配置为响应于工作电平信号,并将所述工作电平信号传输至下拉节点;所述下拉节点为所述下拉控制子电路和所述下拉子电路之间的连接节点;所述下拉子电路被配置为响应于所述上拉节点的电位,通过非工作电平信号下拉所述下拉节点的电位;所述第三降噪子电路被配置为响应于所述下拉节点的电位,通过所述非工作电平信号对所述上拉节点进行降噪;所述第四降噪子电路被配置为响应于所述下拉节点的电位,通过所述非工作电平信号对所述第一信号输出端进行降噪。
- 根据权利要求8所述的移位寄存器,其中,所述下拉控制子电路包括第四晶体管和第五晶体管;所述第四晶体管的第一极连接其控制极、所述第五晶体管的第一极和工 作电平端,第二极连接所述下拉子电路和所述第五晶体管的控制极;所述第五晶体管的第二极连接所述下拉节点。
- 根据权利要求8所述移位寄存器,其中,所述下拉子电路包括第六晶体管和第七晶体管;所述第六晶体管的第一极连接所述下拉节点,第二极连接非工作电平端,控制极连接所述上拉节点;所述第七晶体管的第一极连接所述上拉控制子电路,第二极连接非工作电平端,控制极连接所述上拉节点。
- 根据权利要求8所述的移位寄存器,其中,所述第三降噪子电路包括第八晶体管;所述第八晶体管的第一极所述上拉节点,第二极连接非工作电平端,控制极连接所述下拉节点。
- 根据权利要求8所述的移位寄存器,其中,所述第四降噪子电路包括第九晶体管;所述第九晶体管的第一极连接所述第一信号输出端,第二极连接非工作电平端,控制极连接所述下拉节点。
- 根据权利要求8-12中任一项所述的移位寄存器,其中,所述移位寄存器还包括与所述多第二信号输出端一一对应设置的多个第五降噪子电路;所述多个第五降噪子电路中的每个被配置响应于所述下拉节点的电位,而通过所述非工作电平信号对与之对应的所述第二输出端进行降噪。
- 根据权利要求13所述的移位寄存器,其中,所述多个第五降噪子电路中的每个均包括第十晶体管;所述第十晶体管的第一极连接与之对应的第二信号输出端,第二极连接非工作电平端,控制极连接所述下拉节点。
- 根据权利要求1所述的移位寄存器,其中,所述移位寄存器还包括复位子电路;所述复位子电路被配置为响应于复位信号,通过第二电源电压对所述上拉节点进行复位。
- 根据权利要求15所述的移位寄存器,其中,所述复位子电路包括第十一晶体管;所述第十一晶体管的第一极连接上拉节点,第二极连接第二电源电压端,控制极连接复位信号端。
- 根据权利要求1所述的移位寄存器,其中,所述输入子电路包括第十二晶体管;所述第十二晶体管的第一极连接第一电源电压端,第二极连接上拉节点,控制极连接信号输入端。
- 根据权利要求1所述的移位寄存器,其中,所述输出子电路包括第十三晶体管和存储电容;所述第十三晶体管的第一极连接时钟信号端,第二极连接信号输出端和所述存储电容的第二端,控制极连接所述上拉节点和所述存储电容的第一端。
- 一种栅极驱动电路,其包括:权利要求1-18中任一项所述移位寄存器;其中,本级所述移位寄存器的信号输入端连接上一级所述移位寄存器的信号输出端;本级所述移位寄存器的复位信号端连接下一级所述移位寄存器的信号输出端。
- 一种显示面板,其包括权利要求19所述的栅极驱动电路。
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