WO2017118057A1 - 一种栅极驱动电路、阵列基板、显示面板以及驱动方法 - Google Patents

一种栅极驱动电路、阵列基板、显示面板以及驱动方法 Download PDF

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WO2017118057A1
WO2017118057A1 PCT/CN2016/097310 CN2016097310W WO2017118057A1 WO 2017118057 A1 WO2017118057 A1 WO 2017118057A1 CN 2016097310 W CN2016097310 W CN 2016097310W WO 2017118057 A1 WO2017118057 A1 WO 2017118057A1
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Prior art keywords
goa
type tft
leakage compensation
turned
level
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PCT/CN2016/097310
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English (en)
French (fr)
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苏秋杰
栗峰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/519,836 priority Critical patent/US10170068B2/en
Publication of WO2017118057A1 publication Critical patent/WO2017118057A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/033—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor
    • G06F3/0354—Pointing devices displaced or positioned by the user, e.g. mice, trackballs, pens or joysticks; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
    • G06F3/03547—Touch pads, in which fingers can move on a surface
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present application relates to the field of liquid crystal display technologies, and in particular, to a gate driving circuit, an array substrate, a display panel, and a driving method.
  • Embodiments of the present invention provide a gate driving circuit, an array substrate, a display panel, and a driving method to avoid display abnormality caused by PU leakage.
  • a gate driving circuit comprising: at least a first unit GOA GOA n n-th stage and the stage n + m n + m GOA GOA unit, wherein the output terminal is connected to the GOA n n + input terminal of the GOA m, and n + m GOA The output is connected to the reset end of the GOA n , the n and m are natural numbers; the signal line provides the leakage compensation signal V LHB ; the leakage compensation module, and the two inputs of the leakage compensation module are respectively connected to the GOA n and the GOA An output end of the n+m , a control end of the leakage compensation module is connected to the signal line, an output end of the leakage compensation module is connected to a PU point of GOA n+m , and the leakage compensation module is configured to respond to the received The leakage compensation signal compensates for the voltage of the PU point of the GOA n+
  • an array substrate is also provided.
  • the array substrate includes: the gate driving circuit and the N gate lines described above.
  • the gate driving circuit includes N GOA units corresponding to the N gate lines one by one, and one end of each gate line is connected to an output end of the corresponding GOA unit, N is a natural number, and n+m ⁇ N.
  • a display panel is also provided.
  • the display panel includes the above array substrate and a pixel matrix.
  • the output end of each GOA unit of the gate driving circuit in the array substrate is connected to the gate line of the corresponding pixel row in the pixel matrix.
  • a driving method for a gate driving circuit including:
  • the leakage compensation signal is at a first level
  • the leakage compensation signal is at a second level, and the leakage compensation module compensates for the voltage of the PU point of the GOA unit GOA n+m ;
  • the leakage compensation module is reset in response to the leakage compensation signal being switched from the second level to the first level.
  • a leakage compensation module is added between the cascaded two GOA units of the gate driving circuit, and the voltage of the PU point of the GOA unit of the next stage is compensated to compensate for the voltage drop caused by the leakage. Therefore, at least the problem of display abnormality due to PU leakage is solved.
  • the PU leakage compensation module can be implemented to include four TFTs and one capacitor, and only one signal line needs to be added, and the whole circuit has a simple structure and is easy to implement.
  • a PU leakage compensation module can be disposed between the two cascaded GOA units in the gate driving circuit, so that when the relative position of the LHB needs to be changed, only the leakage compensation signal V LHB needs to be adjusted accordingly, thereby Increased flexibility in gate drive circuit design.
  • 1A is a schematic diagram of a conventional gate driving circuit
  • FIG. 1B is a timing diagram of the gate driving circuit shown in FIG. 1A;
  • FIG. 2A is a schematic structural view of a gate driving circuit according to a first embodiment of the present invention.
  • FIG. 2B is a timing diagram of the gate driving circuit shown in FIG. 2A;
  • 3A is a schematic structural diagram of an example of a gate driving circuit according to a second embodiment of the present invention.
  • 3B is a timing diagram of the gate driving circuit shown in FIG. 3A;
  • FIG. 4 is a flow chart showing a driving method according to an embodiment of the present invention.
  • the GOA (Gate Driver on Array) technology is a technology that integrates gate driving on an array substrate to facilitate miniaturization of the array substrate.
  • Figure 1A shows a conventional GOA gate drive circuit.
  • the gate driving circuit generally includes a plurality of GOA units: an n-1th GOA unit GOA n-1 , an nth GOA unit GOA n , an n+1th GOA unit GOA n+1 , a nth +2 level GOA unit GOA n+2 , the output end (OUT n-1 , OUT n , OUT n+1 , OUT n+2 ) of each GOA unit is respectively connected to the gate line of the corresponding pixel row on the touch screen, n Is a natural number greater than 1.
  • GOA n output terminal OUT n connected to the next stage unit GOA GOA n + input terminal IN 1 for opening GOA n + 1.
  • the output terminal OUT n+1 of the next stage GOA n+1 is also connected to the reset terminal (RESET) of the GOA n-1 of the previous stage.
  • the STV is used as a start signal to be connected to the input (IN) of the first stage GOA unit in the gate drive circuit.
  • CLK1 and CLK2 are the clock signals of the gate drive circuit.
  • the clock signal input terminals of GOA n and GOA n+2 are connected to the first clock signal CLK1, and the clock signal input terminals of GOA n-1 and GOA n+1 are connected to the second clock signal CLK2.
  • the corresponding GOA unit in the gate driving circuit When the first clock signal CLK1 and the second clock signal CLK2 are at a high level, the corresponding GOA unit in the gate driving circuit outputs a high level, so that the gate line connected to the GOA unit is turned on; when the first clock signal CLK1 and the When the two clock signals CLK2 are at a low level, the corresponding GOA unit in the gate driving circuit outputs a low level, so that the gate line connected thereto is turned off.
  • the high levels of the first clock signal CLK1 and the second clock signal CLK2 are shifted from each other.
  • FIG. 1B is a timing diagram of the gate driving circuit shown in FIG. 1A. Referring to FIG. 1B, it is assumed that the pixel display of the nth row is completed and the LHB period is entered after the end of the pixel data display. When OUT n is high, the PU point PU n+1 level in the n+1th GOA unit GOA n+1 is also pulled high. However, during of LHB (typically milliseconds), GOA n + PU will pass through a point in the TFT source and drain electrodes connected thereto a drain, voltage drop, 1B at B as shown in FIG.
  • LHB typically milliseconds
  • the output voltage of the GOA unit GOA n+1 will be low, and even the pixel TFT of the corresponding row cannot be turned on, resulting in display abnormality, as shown at C in FIG. 1B; and the output of the GOA n+1 is connected.
  • the lower voltage causes the PU point PU n of the GOA n and the output terminal to be unable to be discharged normally, so that it cannot be completely turned off, the noise is large, and an abnormal display is easily caused, such as This is shown at A in Figure 1B.
  • a PU leakage compensation module is added between the two-stage gate driving circuits, and the next-level GOA is added.
  • the PU point of the unit is charged to avoid display abnormality caused by leakage of the PU point.
  • a gate driving circuit is provided.
  • the gate driving circuit of this embodiment may include:
  • N GOA units including a cascaded nth GOA unit GOA n and an n+1th GOA unit GOA n+1 , wherein the output of GOA n is connected to the input of GOA n+1 , and GOA n The output of +1 is also connected to the reset end of GOA n , where n is a natural number, and n+1 ⁇ N;
  • Leakage compensation module two input terminals of the leakage compensation module are respectively connected to the output ends of GOA n and GOA n+1 , the control end of the leakage compensation module is connected to the signal line, and the output end of the leakage compensation module is connected to the GOA n+1
  • the PU point is used to compensate the voltage of the PU point of GOA n+1 in response to the received leakage compensation signal.
  • GOA n and GOA n+1 are two GOA units having a cascading relationship for the N GOA units.
  • the manner in which adjacent GOA units are cascaded is adopted, that is, the output end of the nth stage GOA unit GOA n is connected to the input end of the n+1th GOA unit GOA n+1 , and the n+th The output of level 1 GOA n+1 is connected to the reset side of GOA n .
  • the leakage compensation module can be provided between the two GOA units - GOA n and GOA n+m having a cascade relationship.
  • this embodiment is described as an example of entering the LHB time after the n-th row of pixels is displayed, that is, charging the PU point of the next-level GOA unit-GOA n+1 after each LHB, avoiding the GOA
  • the display of the PM point leakage of n+1 is abnormal.
  • the leakage compensation module is added between other GOA units, there is no limitation.
  • the relative position of the LHB needs to be adjusted according to the actual scene.
  • the tester may change the relative position of the LHB multiple times to optimize the display and touch functions.
  • the leakage compensation module is set so that when the tester changes the position of the LHB, only the timing of the V LHB signal needs to be adjusted accordingly, thereby enhancing the flexibility of the gate drive circuit design.
  • the TFT (thin film transistor) in the GOA cell is a high-level-triggered N-type TFT, and correspondingly, the TFT in the leakage compensation module also uses an N-type TFT.
  • the leakage compensation module specifically includes:
  • a first N-type TFT-NTFT1 having a gate and a drain connected to an output of the nth stage GOA unit GOA n and a source connected to the first node Node1;
  • a fourth N-type TFT-NTFT4 having a gate connected to an output of the n+1th stage GOA unit GOA n+1 , a drain connected to the first node Node1, and a source connected to the voltage VSS;
  • a second N-type TFT-NTFT 2 having a gate connected to the first node Node1, a drain connected to the signal line, a source connected to the second node Node2, and a second node Node2 and the first node Node1 having an upper portion Pull capacitor C1;
  • a third N-type TFT-NTFT having a gate connected to the second node Node2, a drain connected to the signal line, a source connected to the output of the leakage compensation module, and further connected to the PU point of the GOA n+1 , ie PU n+1 in the figure.
  • the voltage VSS continues to be low, the level of the leakage compensation signal V LHB is low during display scanning, and is high level for most of the time in LHB, and the end of LHB is fast (a few microseconds before the end of LHB) It can be turned low. That is to say, the leakage compensation signal is at a high level in the LHB time other than the preset time period before the end of the LHB, and is a low level in the preset time period, and the preset time period can be 0.1 ⁇ s ⁇ The time required between the 20 ⁇ s and the second node Node2 in the leakage compensation module is appropriately selected, which is related to the size of the four NTFTs.
  • the capacitance of the pull-up capacitor C1 is between 1 pF and 10 pF.
  • the function of the leakage compensation module is only to charge the PU point PU n+1 of the GOA n+1 unit, to ensure the functionality can be realized, and the TFT size requirement is not high, and the whole of the gate driving circuit is required. The size will not have a big impact.
  • V LHB is low
  • the first N-type TFT-NTFT1, the second N-type TFT-NTFT2, the third N-type TFT-NTFT, and the fourth N-type TFT-NTFT4 are all turned off, and the leakage compensation module does not work;
  • the first N-type TFT-NTFT1 When OUT n becomes a high level, the first N-type TFT-NTFT1 is turned on, the voltage of the first node Node1 is pulled high, the second N-type TFT-NTFT2 is turned on, and the voltage of the second node Node2 is pulled by the leakage compensation signal V LHB Low, so that the third N-type TFT-NTFT remains off.
  • the leakage compensation module will not affect any GOA unit.
  • the leakage compensation signal V LHB is at a high level for most of the time.
  • OUT n goes low, the first N-type TFT-NTFT1 turns off, but Node1 has been charged to near high level by OUT n , and the second N-type TFT-NTFT 2 remains turned on;
  • the leakage compensation signal V LHB is set to a high level, and the second node Node2 is pulled high by the leakage compensation signal V LHB , so that the third N-type TFT-NTFT is turned on, thereby making PU n+1 high .
  • the voltage of the first node Node1 will jump to nearly twice the voltage of the second node Node2, thus keeping the second N-type TFT-NTFT2 in a conducting state, and the Node2 continues to be V LHB is charged so that the third N-type TFT-NTFT continues to be turned on, and PU n+1 thus receives V LHB charging, thereby compensating the voltage of PU n+1 as shown at A in FIG. 2B.
  • the period in which the leakage compensation signal V LHB is at a high level is referred to as a "compensation phase", that is, the voltage of PU n+1 is compensated.
  • the leakage compensation signal V LHB is set to a low level a few microseconds before the end of the LHB , and the voltage of the second node Node2 is pulled low, so that the third N-type TFT-NTFT is turned off, and the PU n+1 is no longer affected. influences.
  • the fourth N-type TFT-NTFT 4 is turned on, and the voltage of the first node Node1 is pulled low by VSS, so that the second N-type TFT-NTFT 2 is turned off.
  • the reset phase includes a preset period of time, that is, a period from when the leakage compensation signal VLHB is set low to when OUT n+1 becomes high.
  • the preset time period may be between 0.1 ⁇ s and 20 ⁇ s, and is related to the size of the four NTFTs.
  • a gate driving circuit is also provided.
  • the difference between this embodiment and the first embodiment is that the TFT in the GOA cell is a P-type TFT that is turned on at a low level, and the TFT in the corresponding leakage compensation module also adopts a P-type. TFT.
  • the leakage compensation module of this embodiment includes:
  • a first P-type TFT-PTFT1 having a gate and a source connected to an output of the n-th stage GOA unit GOA n and a drain connected to the first node Node1;
  • a fourth P-type TFT-PTFT4 having a gate connected to an output of the n+1th stage GOA unit GOA n+1 , a source connected to the first node Node1, and a drain connected to the voltage VGH;
  • a second P-type TFT-PTFT 2 having a gate connected to the first node Node1, a source connected to the signal line, a drain connected to the second node Node2, and a pull-down between the second node Node2 and the first node Node1 Capacitor C2;
  • a third P-type TFT-PTFT3 having a gate connected to the second node Node2, a source connected to the signal line, a drain connected to the output of the leakage compensation module, and further connected to the PU point of the GOA n+1 , ie PU n+1 shown in the figure.
  • the voltage VGH continues to be at a high level, and the level of the leakage compensation signal V LHB is a high level during display scanning, a low level for most of the time in LHB, and an end of LHB (before the end of LHB) It can be turned high in a few microseconds.
  • the leakage compensation signal V LHB is at a low level in the LHB time other than the preset time period before the end of the LHB, and is a high level in the preset time period, and the preset time period can be 0.1 ⁇ s ⁇
  • the time required for setting the second node Node2 in the leakage compensation module to a high level between 20 ⁇ s is reasonably selected, which is related to the size of the four PTFTs.
  • the capacitance of the pull-down capacitor C2 is between 1pF and 10pF.
  • V LHB is high:
  • the first P-type TFT-PTFT1, the second P-type TFT-PTFT2, the third P-type TFT-PTFT3, and the fourth P-type TFT-PTFT4 are all turned off, and the leakage compensation module does not operate;
  • the leakage compensation module does not affect any GOA unit during the display scan phase.
  • LHB leakage compensation signal V is low most of the time, at the beginning LHB, OUT n becomes high level, the first N-type TFT-NTFT1 off, but has been Node1 OUT n is charged to a low level, and the second P-type TFT-PTFT2 remains turned on; at this time, the leakage compensation signal V LHB is set to a low level, and the Node 2 point is pulled low by V LHB due to the pull-down capacitor C2
  • the Node1 point voltage will jump to nearly twice the Node2 point voltage, thus keeping the second P-type TFT-PTFT2 in the on state, and the Node2 continues to be charged by the leakage compensation signal V LHB , so that the third P-type The TFT-PTFT 3 continues to be turned on, and PU n+1 is thus charged with V LHB as shown at A in FIG. 3B.
  • the period in which the leakage compensation signal V LHB is at a low level is referred to as a "com
  • the leakage compensation signal V LHB is set to a high level a few microseconds before the end of LHB , the Node2 voltage is pulled high, the third P-type TFT-PTFT3 is turned off, and PU n+1 is no longer affected. As shown at B in FIG. 3B, after OUT n+1 becomes a low level, the fourth N-type TFT-NTFT 4 is turned on, and the voltage of the first node Node1 is pulled high by VGH, so that the second N-type TFT-NTFT 2 is turned off.
  • the reset phase includes a preset period of time, that is, a period from when the leakage compensation signal VLHB is set to a high level to when OUT n+1 becomes a low level.
  • the preset time period may be between 0.1 ⁇ s and 20 ⁇ s, and is related to the size of the four NTFTs.
  • an exemplary embodiment of the present invention further provides an array substrate.
  • the array substrate of this embodiment includes the above-described gate driving circuit and a plurality of gate lines.
  • the gate driving circuit includes N GOA units, and a leakage compensation module is disposed between each adjacent two GOA units.
  • the number of gate lines is also N, and the back end of each gate line is connected to the output of the corresponding GOA unit.
  • the exemplary embodiment of the present invention further provides a display surface based on the array substrate of the above embodiment. board.
  • the display panel of this embodiment includes the above array substrate and a pixel matrix.
  • the output end of each GOA unit of the gate driving circuit in the array substrate is connected to the gate line of the corresponding pixel row in the pixel matrix.
  • FIG. 4 shows a flow chart of a driving method of a gate driving circuit according to an embodiment of the present invention.
  • the driving method 40 of the gate driving circuit according to the embodiment of the present invention may include:
  • Step 401 in the display scanning phase, the leakage compensation signal is at a first level
  • Step 403 in the compensation phase, the leakage compensation signal is a second level, and the leakage compensation module compensates the voltage of the PU point of the GOA unit GOA n+m ;
  • Step 405 in the reset phase, the leakage compensation module is reset in response to the leakage compensation signal being switched from the second level to the first level.
  • the leakage compensation module does not compensate for the voltage of PU n+1 .
  • the first N-type TFT is turned off, the second N-type TFT remains turned on, and the third N-type TFT is turned on, thereby pulling the voltage of PU n+1 high.
  • the first N-type TFT, the second N-type TFT, and the third N-type TFT are turned off, and the fourth N-type TFT is turned off.
  • the first N-type TFT, the second N-type TFT, the third N-type TFT, and the fourth N-type The TFTs are all turned off.
  • the drain voltage compensation module PU n + 1 does not compensate.
  • the first P-type TFT is turned off, the second P-type TFT remains turned on, and the third P-type TFT is turned on, thereby pulling the voltage of PU n+1 low.
  • the first P-type TFT, the second P-type TFT, and the third P-type TFT are turned off, and the fourth P-type TFT is turned off.
  • the first P-type TFT, the second P-type TFT, the third P-type TFT, and the fourth P-type The TFTs are all turned off.
  • an embodiment of the present invention provides a gate driving circuit, an array substrate including the gate driving circuit, and a display panel.
  • the gate driving circuit has a PU leakage compensation module, and only one signal line needs to be added. That is, the PU point in the next row of GOA units after the end of the LHB can be charged in the LHB time, the display abnormality caused by the leakage of the PU point is avoided, and the stability of the display is improved; and the compensation structure allows the LHB to be changed. Relative position, only need to adjust the V LHB signal accordingly, with great flexibility.

Abstract

一种栅极驱动电路、一种阵列基板、一种显示面板以及一种驱动方法。该栅极驱动电路包括：至少GOA单元GOA n和GOA单元GOA n+m，其中，GOA n的输出端连接至GOA n+m的输入端（IN），且GOA n+m的输出端连接至GOA n的复位端（Reset）；漏电补偿模块，漏电补偿模块的两个输入端分别连接至GOA n和GOA n+m的输出端（OUT），漏电补偿模块的控制端连接至信号线，漏电补偿模块的输出端连接至GOA n+m的PU点，用于响应于接收到的漏电补偿信号对GOA n+m的PU点的电压进行补偿。上述栅极驱动电路通过在级联的两个GOA单元之间增加了漏电补偿模块，对下一级的GOA单元进行充电，弥补由于漏电而导致的电压降低，从而解决了由于PU点漏电导致的显示异常的问题。

Description

一种栅极驱动电路、阵列基板、显示面板以及驱动方法
本申请要求于2016年1月5日递交的中国专利申请201610006849.9的优先权，该申请合并在此作为引用。
技术领域
本申请涉及液晶显示技术领域，尤其涉及一种的栅极驱动电路、一种阵列基板、一种显示面板以及一种驱动方法。
背景技术
在传统的内嵌式In-CeH触摸屏技术中，对AA(Active Area)区的若干行像素进行显示(display)扫描后，停止显示扫描，开始对AA区部分触摸(touch)电极进行扫描，将每次对触摸电极进行扫描的时间段称为LHB(Long Horizontal Blanking)，之后再进行显示扫描与LHB的交替，反复多次进行此过程(次数依具体产品而定)，从而完成一帧画面的显示和全屏幕触摸电极扫描。
发明内容
本发明实施例提供了一种栅极驱动电路、一种阵列基板、一种显示面板以及一种驱动方法，以避免PU漏电导致的显示异常。
根据本发明实施例的一个方面，提供了一种栅极驱动电路。该栅极驱动电路包括：至少第n级GOA单元GOAn和第n+m级GOA单元GOAn+m，其中，GOAn的输出端连接至GOAn+m的输入端，且GOAn+m的输出端连接至GOAn的复位端，所述n和m为自然数；信号线，提供漏电补偿信号VLHB；漏电补偿模块，所述漏电补偿模块的两个输入端分别连接至GOAn和GOAn+m的输出端，所述漏电补偿模块的控制端连接至信号线，所述漏电补偿模块的输出端连接至GOAn+m的PU点，所述漏电补偿模块用于响应于接收到的漏电补偿信号对GOAn+m单元的PU点的电压进行补偿。
根据本发明实施例的另一个方面，还提供了一种阵列基板。该阵列基板包括：上述的栅极驱动电路以及N条栅线。其中，所述栅极驱动电路中包括与所述N条栅线一一对应的N个GOA单元，每一条栅线的一端连接至对应GOA单元的输出端，N是自然数，且n+m≤N。
根据本发明实施例的再一个方面，还提供了一种显示面板。该显示面板包括：上述的阵列基板以及像素矩阵。其中，所述阵列基板中栅极驱动电路的每一GOA单元的输出端连接至所述像素矩阵中对应的像素行的栅线。
根据本发明实施例的再一个方面，还提供了一种用于根据本发明实施例的栅极驱动电路的驱动方法，包括：
在显示扫描阶段，所述漏电补偿信号为第一电平；
在补偿阶段，所述漏电补偿信号为第二电平，所述漏电补偿模块对GOA单元GOAn+m的PU点的电压进行补偿；以及
在复位阶段，响应于所述漏电补偿信号从第二电平切换为第一电平，使得所述漏电补偿模块复位。
根据本发明实施例，在栅极驱动电路的级联的两个GOA单元之间增加了漏电补偿模块，对下一级的GOA单元的PU点的电压进行补偿，弥补由于漏电而导致的电压降低，从而至少解决了由于PU漏电导致的显示异常的问题。
此外，PU漏电补偿模块可以实现为包括4个TFT及一个电容，此外仅需要增设一根信号线，整个电路结构简单，易于实现。
此外，可以在栅极驱动电路中两个级联的GOA单元之间均设置PU漏电补偿模块，从而在需要改变LHB的相对位置时，只需要对漏电补偿信号VLHB进行相应调整即可，从而增强了栅极驱动电路设计的灵活性。
附图说明
图1A为传统栅极驱动电路的示意图；
图1B为图1A所示栅极驱动电路的时序图；
图2A为根据本发明第一实施例的栅极驱动电路的结构示意图；
图2B为图2A所示栅极驱动电路的时序图；
图3A为根据本发明第二实施例的栅极驱动电路的示例结构示意图；
图3B为图3A所示栅极驱动电路的时序图；以及
图4为示出了根据本发明实施例的驱动方法的流程图。
具体实施方式
GOA(位于阵列基板上的栅极驱动，即Gate driver on Array)技术是将栅极驱动集成在阵列基板上，从而有利于阵列基板小型化的技术。图1A示出了一种传统GOA栅极驱动电路。请参照图1A，栅极驱动电路通常包括若干个GOA单元：第n-1级GOA单元GOAn-1、第n级GOA单元GOAn、第n+1级GOA单元GOAn+1、第n+2级GOA单元GOAn+2，每一个GOA单元的输出端(OUTn-1、OUTn、OUTn+1、OUTn+2)分别连接至触摸屏上对应的像素行的栅线，n是大于1的自然数。如图1A所示，GOAn的输出端OUTn连接至下一级GOA单元GOAn+1的输入端IN，用于开启GOAn+1。同时下一级GOAn+1的输出端OUTn+1还连接至上一级GOA单元GOAn-1的复位端(RESET)。STV作为起始信号，连接至栅极驱动电路中第一级GOA单元的输入端(IN)。其中，CLK1和CLK2为栅极驱动电路的时钟信号。GOAn和GOAn+2的时钟信号输入端连接至第一时钟信号CLK1，GOAn-1和GOAn+1的时钟信号输入端连接至第二时钟信号CLK2。当第一时钟信号CLK1、第二时钟信号CLK2为高电平时，栅极驱动电路中相应的GOA单元输出高电平，使得与该GOA单元相连的栅线开启；当第一时钟信号CLK1和第二时钟信号CLK2为低电平时，栅极驱动电路中相应的GOA单元输出低电平，使得与其相连的栅线关断。为了实现栅线的逐一扫描，第一时钟信号CLK1和第二时钟信号CLK2的高电平相互错开。
图1B为图1A所示栅极驱动电路的时序图。请参照图1B，假设第n行像素数据显示结束之后进入LHB时间段，开始触摸电极扫描。当OUTn为高电平时，第n+1级GOA单元GOAn+1内的PU点PUn+1电平也被拉高。然而，在LHB期间(一般为毫秒量级)，GOAn+1内的PU点会经过与其相连的TFT源漏极漏电，电压降低，如图1B中B处所示。待LHB结束后，该GOA单元GOAn+1的输出电压会较低，甚至无法开启对应行的像素TFT，导致显示异常，如图1B中C处所示；同时GOAn+1的输出端连接至第n级GOA单元GOAn的复位端，其电压较低会导致GOAn的PU点PUn以及输出端无法正常放电，进而其无法彻底关断，噪声较大，也容易造成异常显示，如图1B中A处所示。
本发明实施例在两级栅极驱动电路之间增加了PU漏电补偿模块，对下一级GOA 单元的PU点进行充电，避免了由于PU点漏电导致的显示异常。
为使本发明实施例的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明实施例进一步详细说明。
第一实施例
在本发明实施例的第一示例性实施例中，提供了一种栅极驱动电路。请参照图2A，本实施例栅极驱动电路可以包括：
N个GOA单元，其中包括级联的第n级GOA单元GOAn和第n+1级GOA单元GOAn+1，其中，GOAn的输出端连接至GOAn+1的输入端，且GOAn+1的输出端还连接至GOAn的复位端，其中n自然数，且n+1≤N；
信号线，其提供漏电补偿信号VLHB；
漏电补偿模块，漏电补偿模块的两个输入端分别连接至GOAn和GOAn+1的输出端，漏电补偿模块的控制端连接至信号线，漏电补偿模块的输出端连接至GOAn+1的PU点，用于响应于接收到的漏电补偿信号对GOAn+1的PU点的电压进行补偿。
以下分别对本实施例具有栅极驱动电路的各个组成部分进行详细描述。
可以理解的是，虽然图1A中的栅极驱动电路仅给出了四个GOA单元，但本领域技术人员可以理解，对于包含N个GOA单元的栅极驱动电路整体而言，其连接关系与此类此。GOAn和GOAn+1为该N个GOA单元具有级联关系的两个GOA单元。
进一步地，本实施例中，采用相邻GOA单元级联的方式，即第n级GOA单元GOAn的输出端连接至第n+1级GOA单元GOAn+1的输入端，且第n+1级GOAn+1的输出端连接至GOAn的复位端。除此之外，还存在其他级联方式，例如存在预充电的情况，即GOAn的输出端连接至第n+m级GOA单元-GOAn+m的输入端，且GOAn+m的输出端连接至GOAn的复位端，其中，m可以取2、3、4、5、6中的一值。在这种情况下，可以在具有级联关系的两GOA单元-GOAn和GOAn+m之间来设置漏电补偿模块。
此外，本实施例是针对第n行像素显示完之后进入LHB时间为例进行说明的，即对每个LHB之后的下一级GOA单元-GOAn+1的PU点进行充电，避免了由于GOAn+1的PU点漏电导致的显示异常。而关于其他GOA单元之间是否增加漏电补偿模块，并没有进行限定。
本领域技术人员进行理解，需要根据实际场景调整LHB的相对位置，尤其是在测试阶段，测试人员可能会多次更改LHB的相对位置来使显示和touch功能达到最佳。在变更LHB的位置的情况下，为了保证相应位置处GOA单元的PU点电压得到补偿，在本发明优选的实施例中，在栅极驱动电路中有级联关系的两个GOA单元之间均设置漏电补偿模块，从而在测试人员改变LHB的位置时，只需要对VLHB信号的时序进行相应调整即可，从而增强了栅极驱动电路设计的灵活性。
本实施例中，在GOA单元中的TFT(薄膜晶体管)为高电平触发的N型TFT，与此相对应，漏电补偿模块中的TFT也采用N型TFT。
请参照图2A，漏电补偿模块具体包括：
第一N型TFT-NTFT1，其栅极和漏极连接至第n级GOA单元GOAn的输出端，其源极连接至第一节点Node1；
第四N型TFT-NTFT4，其栅极连接至第n+1级GOA单元GOAn+1的输出端，其漏极连接至第一节点Node1，其源极连接至电压VSS；
第二N型TFT-NTFT2，其栅极连接至第一节点Node1，其漏极连接至信号线，其源极连接至第二节点Node2，该第二节点Node2和第一节点Node1之间具有上拉电容C1；
第三N型TFT-NTFT，其栅极连接至第二节点Node2，其漏极连接至信号线，其源极连接至漏电补偿模块的输出端，进而连接至GOAn+1的PU点，即图中的PUn+1。
其中，电压VSS持续为低电平，漏电补偿信号VLHB的电平在显示扫描时为低电平，在LHB内大部分时间为高电平，LHB快结束时(距LHB结束前几微秒即可)变为低电平。也就是说，漏电补偿信号在除LHB结束前的预设时间段之外的LHB时间内为高电平，在该预设时间段内为低电平，该预设时间段可以在0.1μs～20μs之间依据将漏电补偿模块中第二节点Node2置为低电平所需要的时间合理选择，其与4个NTFT的尺寸有关。
此外，综合考虑性能以及所占用的面积，上拉电容C1的电容值介于1pF～10pF之间。
需要说明的是，该漏电补偿模块的作用只是为GOAn+1单元的PU点PUn+1充电，保证功能性能够实现即可，对TFT尺寸要求并不高，对栅极驱动电路的整体尺寸不会有较大影响。
以下结合图2B的时序关系具体说明本实施例的栅极驱动电路电路的工作原理：
(1)在显示扫描阶段期间，VLHB为低电平：
当OUTn为低电平时，第一N型TFT-NTFT1，第二N型TFT-NTFT2，第三N型TFT-NTFT，第四N型TFT-NTFT4均关断，漏电补偿模块不工作；
当OUTn变为高电平时，第一N型TFT-NTFT1导通，第一节点Node1电压被拉高，第二N型TFT-NTFT2导通，第二节点Node2电压被漏电补偿信号VLHB拉低，使得第三N型TFT-NTFT保持关断。
综上，在显示扫描阶段，漏电补偿模块不会对任何的GOA单元造成影响。
(2)在LHB时间段期间，漏电补偿信号VLHB在大部分时间为高电平。在LHB开始时，OUTn变为低电平，第一N型TFT-NTFT1关断，但Node1已被OUTn充电至接近高电平，第二N型TFT-NTFT2保持导通；此时，漏电补偿信号VLHB被置为高电平，第二节点Node2被漏电补偿信号VLHB拉为高电平，使得第三N型TFT-NTFT导通，从而使PUn+1变为高电平。此时，由于上拉电容C1的自举作用，第一节点Node1电压会跳变为接近2倍的第二节点Node2电压，因此使第二N型TFT-NTFT2继续保持导通状态，Node2持续由VLHB充电，使得第三N型TFT-NTFT继续导通，PUn+1因此得到VLHB充电，从而使PUn+1的电压得到补偿，如图2B中A处所示。可以将该漏电补偿信号VLHB为高电平的时间段称为“补偿阶段”，即，对PUn+1的电压进行补偿。
在LHB快结束前几微秒将漏电补偿信号VLHB置为低电平，第二节点Node2电压被拉成低电平，使得第三N型TFT-NTFT关断，PUn+1不再受影响。如图2B中B处所示，之后OUTn+1变为高电平，第四N型TFT-NTFT4导通，第一节点Node1电压被VSS拉低，使得第二N型TFT-NTFT2关断，之后，OUTn+1变为低电平，使得第四N型TFT-NTFT4关断，由此漏电补偿模块的所有TFT均处于关断状态，漏电补偿模块复位。可以将该时间段称为“复位阶段”。如上文所述，该复位阶段包括预设时间段，即，从漏电补偿信号VLHB置为低电平到OUTn+1变为高电平的时间段。依据将漏电补偿模块中第二节点Node2置为低电平所需要的时间，该预设时间段可以在0.1μs～20μs之间，并且与4个NTFT的尺寸有关。
第二实施例
在本发明实施例的第二示例性实施例中，还提供了一种栅极驱动电路。如图3A所示，本实施例与第一实施例相比，其区别在于，GOA单元中的TFT为低电平导通的P型TFT，与此对应漏电补偿模块中的TFT也采用P型TFT。
请参照图3A，本实施例漏电补偿模块包括：
第一P型TFT-PTFT1，其栅极和源极连接至第n级GOA单元GOAn的输出端，其漏极连接至第一节点Node1；
第四P型TFT-PTFT4，其栅极连接至第n+1级GOA单元GOAn+1的输出端，其源极连接至第一节点Node1，其漏极连接至电压VGH；
第二P型TFT-PTFT2，其栅极连接至第一节点Node1，其源极连接至信号线，其漏极连接至第二节点Node2，该第二节点Node2和第一节点Node1之间具有下拉电容C2；
第三P型TFT-PTFT3，其栅极连接至第二节点Node2，其源极连接至信号线，其漏极连接至漏电补偿模块的输出端，进而连接至GOAn+1的PU点，即图中所示的PUn+1。
本实施例中，电压VGH持续为高电平，漏电补偿信号VLHB的电平在显示扫描时为高电平，在LHB内大部分时间为低电平，LHB快结束时(距LHB结束前几微秒即可)变为高电平。同样，漏电补偿信号VLHB在除LHB结束前的预设时间段之外的LHB时间内为低电平，在该预设时间段内为高电平，该预设时间段可以在0.1μs～20μs之间依据将漏电补偿模块中第二节点Node2置为高电平所需要的时间合理选择，其与4个PTFT的尺寸有关。
同样，综合考虑性能以及所占用的面积，下拉电容C2的电容值介于1pF～10pF之间。
以下结合图3B的时序关系具体说明本实施例栅极驱动电路的工作原理：
(1)在显示扫描阶段期间，VLHB为高电平：
当OUTn为高电平时，第一P型TFT-PTFT1，第二P型TFT-PTFT2，第三P型TFT-PTFT3，第四P型TFT-PTFT4均关断，漏电补偿模块不工作；
当OUTn为低电平时，第一P型TFT-PTFT1导通，Node1点电压被拉低，第二P型TFT-PTFT2导通，Node2点电压被漏电补偿信号VLHB拉高，使得第三P型TFT-PTFT3关断。
综上，在显示扫描阶段期间，漏电补偿模块不会对任何GOA单元造成影响。
(2)在LHB时间段内，漏电补偿信号VLHB在大部分时间为低电平，在LHB开始时，OUTn变为高电平，第一N型TFT-NTFT1关断，但Node1已被OUTn充电至接近低电平，第二P型TFT-PTFT2保持导通；此时，漏电补偿信号VLHB被置为低电平，Node2点被VLHB拉为低电平，由于下拉电容C2的自举作用，Node1点电压会跳变为接近2倍的Node2点电压，因此使第二P型TFT-PTFT2继续保持导通状态，Node2持续由漏电补偿信号VLHB充电，使得第三P型TFT-PTFT3继续导通，PUn+1因此得到VLHB充电，如图3B中A处所示。可以将该漏电补偿信号VLHB为低电平的时间段称为“补偿阶段”，即，对PUn+1的电压进行补偿。
在LHB快结束前几微秒将漏电补偿信号VLHB置为高电平，Node2电压被拉成高电平，第三P型TFT-PTFT3关断，PUn+1不再受影响。如图3B中B处所示，之后OUTn+1变为低电平，第四N型TFT-NTFT4导通，第一节点Node1电压被VGH拉高，使得第二N型TFT-NTFT2关断，之后，OUTn+1变为高电平，第四N型TFT-NTFT4关断，由此漏电补偿模块所有TFT处于关断状态，漏电补偿模块复位。可以将该时间段称为“复位阶段”。如上文所述，该复位阶段包括预设时间段，即，从漏电补偿信号VLHB置为高电平到OUTn+1变为低电平的时间段。依据将漏电补偿模块中第二节点Node2置为高电平所需要的时间，该预设时间段可以在0.1μs～20μs之间，并且与4个NTFT的尺寸有关。
为了达到简要说明的目的，上述第一实施例中任何可作相同应用的技术特征叙述皆并于此，无需再重复相同叙述。
基于上述两实施例的栅极驱动电路，本发明实施例的示例性实施例还提供了一种阵列基板。本实施例阵列基板包括上述的栅极驱动电路以及若干条栅线。
其中，栅极驱动电路中包括N个GOA单元，每相邻的两GOA单元之间设置漏电补偿模块。栅线的条数同样为N，每一条栅线的后端连接至对应GOA单元的输出端。
基于上述实施例的阵列基板，本发明实施例的示例性实施例还提供了一种显示面 板。本实施例显示面板包括上述的阵列基板以及像素矩阵。其中，阵列基板中栅极驱动电路的每一GOA单元的输出端连接至上述像素矩阵中对应的像素行的栅线。
图4示出了根据本发明实施例的栅极驱动电路的驱动方法的流程图。如图4所示，根据本发明实施例的栅极驱动电路的驱动方法40可以包括：
步骤401，在显示扫描阶段，所述漏电补偿信号为第一电平；
步骤403，在补偿阶段，所述漏电补偿信号为第二电平，所述漏电补偿模块对GOA单元GOAn+m的PU点的电压进行补偿；以及
步骤405，在复位阶段，响应于所述漏电补偿信号从第二电平切换为第一电平，所述漏电补偿模块复位。
接下来将结合图2A、图2B和图4来详细描述当将根据本实施例的驱动方法应用于图2A所示的栅极驱动电路时的驱动方法。
首先，在显示扫描阶段，当所述第n级GOA单元GOAn的输出端是低电平时，所述第一N型TFT、第二N型TFT、第三N型TFT和第四N型TFT均关断；当所述第n级GOA单元GOAn的输出端变为高电平时，第一N型TFT和第二N型TFT导通，第三N型TFT和第四N型TFT关断。因此漏电补偿模块不对PUn+1的电压进行补偿。
在补偿阶段，所述第一N型TFT关断，第二N型TFT保持导通，第三N型TFT导通，从而将PUn+1的电压拉高。
然后，在复位阶段，当所述GOA单元GOAn+m的输出端是高电平时，所述第一N型TFT、第二N型TFT、第三N型TFT关断，第四N型TFT导通；响应于所述GOA单元GOAn+m的输出端从高电平切换为低电平，所述第一N型TFT、第二N型TFT、第三N型TFT和第四N型TFT均关断。
接下来将结合图3A、图3B和图4来详细描述当将根据本实施例的驱动方法应用于图3A所示的栅极驱动电路时的驱动方法。
首先，在显示扫描阶段，当所述第n级GOA单元GOAn的输出端是高电平时，所述第一P型TFT、第二P型TFT、第三P型TFT和第四P型TFT均关断；当所述 第n级GOA单元的输出端变为低电平时，第一P型TFT和第二P型TFT导通，第三P型TFT和第四P型TFT关断。因此漏电补偿模块不对PUn+1的电压进行补偿。
在补偿阶段，所述第一P型TFT关断，第二P型TFT保持导通，第三P型TFT导通，从而将PUn+1的电压拉低。
然后，在复位阶段，当所述GOA单元GOAn+m的输出端是低电平时，所述第一P型TFT、第二P型TFT、第三P型TFT关断，第四P型TFT导通；响应于所述GOA单元GOAn+m的输出端从低电平切换为高电平，所述第一P型TFT、第二P型TFT、第三P型TFT和第四P型TFT均关断。
需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换。
综上所述，本发明实施例提供一种栅极驱动电路、包括所述栅极驱动电路的阵列基板及显示面板，其在栅极驱动电路具有PU漏电补偿模块，仅需增加一条信号线，即可以在LHB时间内对LHB结束后的下一行GOA单元内的PU点进行充电，避免了由于该PU点漏电导致的显示异常，提高了显示的稳定性；另外此种补偿结构允许改变LHB的相对位置，只需要对VLHB信号进行相应调整即可，具有极强的灵活性。
以上所述的具体实施例，对本发明实施例的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明实施例，凡在本发明实施例的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明实施例的保护范围之内。

Claims (14)

  1. 一种栅极驱动电路，包括：
    至少第n级GOA单元GOAn和第n+m级GOA单元GOAn+m，其中，GOAn的输出端连接至GOAn+m的输入端，且GOAn+m的输出端连接至GOAn的复位端，所述n和m为自然数；
    信号线，提供漏电补偿信号VLHB；
    漏电补偿模块，所述漏电补偿模块的两个输入端分别连接至GOAn和GOAn+m的输出端，所述漏电补偿模块的控制端连接至信号线，所述漏电补偿模块的输出端连接至GOAn+m的PU点，所述漏电补偿模块用于响应于接收到的漏电补偿信号VLHB对GOAn+m的PU点的电压进行补偿。
  2. 根据权利要求1所述的栅极驱动电路，其特征在于，包括：N个GOA单元；
    所述GOAn和GOAn+m为该N个GOA单元中具有级联关系的两个GOA单元，其中，N为自然数且N≥n+m。
  3. 根据权利要求2所述的栅极驱动电路，其特征在于，所述m＝1、2、3、4、5或6。
  4. 根据权利要求2所述的栅极驱动电路，其特征在于，多个所述漏电补偿模块中的每一个分别设置在所述N个GOA单元中任意两个具有级联关系的GOA单元之间；其中所述多个漏电补偿模块的控制端均连接至所述信号线。
  5. 根据权利要求1所述的栅极驱动电路，其特征在于，所述GOAn和GOAn+m中的薄膜晶体管为高电平导通的N型TFT；
    所述漏电补偿模块包括：
    第一N型TFT(NTFT1)，其栅极和漏极连接至GOAn的输出端，其源极连接至第一节点(Node1)；
    第四N型TFT(NTFT4)，其栅极连接至GOAn+1的输出端，其漏极连接至第一节点(Node1)，其源极连接至电压VSS；
    第二N型TFT(NTFT2)，其栅极连接至第一节点(Node1)，其漏极连接至所述信号线，其源极连接至第二节点(Node2)，该第二节点(Node2)和第一节点(Node1)之间具有上拉电容(C1)；
    第三N型TFT(NTFT)，其栅极连接至第二节点(Node2)，其漏极连接至所述信号线，其源极连接至漏电补偿模块的输出端；
    其中，所述电压VSS为低电平。
  6. 根据权利要求5所述的栅极驱动电路，其特征在于，所述上拉电容(C1)的电容值介于1pF～10pF之间。
  7. 根据权利要求1所述的栅极驱动电路，其特征在于，所述GOAn和GOAn+m中的薄膜晶体管为低电平导通的P型TFT；
    所述漏电补偿模块包括：
    第一P型TFT(PTFT1)，其栅极和源极连接至GOAn的输出端，其漏极连接至第一节点(Node1)；
    第四P型TFT(PTFT4)，其栅极连接至GOAn+1单元的输出端，其源极连接至第一节点(Node1)，其漏极连接至电压VGH；
    第二P型TFT(PTFT2)，其栅极连接至第一节点(Node1)，其源极连接至信号线，其漏极连接至第二节点(Node2)，该第二节点(Node2)和第一节点(Node1)之间具有下拉电容(C2)；
    第三P型TFT(PTFT3)，其栅极连接至第二节点(Node2)，其源极连接至信号线，其漏极连接至漏电补偿模块的输出端；
    其中，所述电压VGH为高电平。
  8. 根据权利要求7所述的栅极驱动电路，其特征在于，所述下拉电容(C2)的电容值介于1pF～10pF之间。
  9. 根据权利要求5至8中任一项所述的栅极驱动电路，其特征在于，所述预设时间段介于0.1μs～20μs之间。
  10. 一种阵列基板，包括：权利要求1至9中任一项所述的栅极驱动电路以及若干条栅线；
    其中，所述栅极驱动电路中包括N个GOA单元，所述栅线的条数同样为N，每一条栅线的后端连接至对应GOA单元的输出端。
  11. 一种显示面板，包括：权利要求10所述的阵列基板以及像素矩阵；
    其中，所述阵列基板中栅极驱动电路的每一GOA单元的输出端分别连接至所述像素矩阵中对应的像素行的栅线。
  12. 一种用于如权利要求1所述的栅极驱动电路的驱动方法，包括：
    在显示扫描阶段，所述漏电补偿信号为第一电平；
    在补偿阶段，所述漏电补偿信号为第二电平，使得所述漏电补偿模块对GOA单元GOAn+m的PU点的电压进行补偿；以及
    在复位阶段，响应于所述漏电补偿信号从第二电平切换为第一电平，所述漏电补偿模块复位。
  13. 根据权利要求12所述的驱动方法，其特征在于，所述漏电补偿模块包括第一N型TFT、第二N型TFT、第三N型TFT和第四N型TFT，所述第一电平为低电平，所述第二电平为高电平；
    在显示扫描阶段，当所述第n级GOA单元GOAn的输出端是低电平时，所述第一N型TFT、第二N型TFT、第三N型TFT和第四N型TFT均关断；当所述第n级GOA单元GOAn的输出端变为高电平时，第一N型TFT和第二N型TFT导通，第三N型TFT和第四N型TFT关断，
    在补偿阶段，所述第一N型TFT关断，第二N型TFT保持导通，第三N型TFT导通，从而将PUn+1的电压拉高；以及
    在复位阶段，当所述GOA单元GOAn+m的输出端是高电平时，所述第一N型TFT、第二N型TFT、第三N型TFT关断，第四N型TFT导通；响应于所述GOA单元GOAn+m的输出端从高电平切换为低电平，所述第一N型TFT、第二N型TFT、第三N型TFT和第四N型TFT均关断。
  14. 根据权利要求12所述的驱动方法，其特征在于，所述漏电补偿模块包括第一P型TFT、第二P型TFT、第三P型TFT和第四P型TFT，所述第一电平为高电平，所述第二电平为低电平；
    在显示扫描阶段，当所述第n级GOA单元GOAn的输出端是高电平时，所述第一P型TFT、第二P型TFT、第三P型TFT和第四P型TFT均关断；当所述第n级GOA单元的输出端变为低电平时，第一P型TFT和第二P型TFT导通，第三P型TFT和第四P型TFT关断，
    在补偿阶段，所述第一P型TFT关断，第二P型TFT保持导通，第三P型TFT导通，从而将PUn+1的电压拉低；以及
    在复位阶段，当所述GOA单元GOAn+m的输出端是低电平时，所述第一P型TFT、 第二P型TFT、第三P型TFT关断，第四P型TFT导通；响应于所述GOA单元GOAn+m的输出端从低电平切换为高电平，所述第一P型TFT、第二P型TFT、第三P型TFT和第四P型TFT均关断。
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