WO2021164075A1 - Oled 显示装置及 tft 阵列基板的制备方法 - Google Patents

Oled 显示装置及 tft 阵列基板的制备方法 Download PDF

Info

Publication number
WO2021164075A1
WO2021164075A1 PCT/CN2020/079107 CN2020079107W WO2021164075A1 WO 2021164075 A1 WO2021164075 A1 WO 2021164075A1 CN 2020079107 W CN2020079107 W CN 2020079107W WO 2021164075 A1 WO2021164075 A1 WO 2021164075A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
thin film
metal layer
film transistor
insulating layer
Prior art date
Application number
PCT/CN2020/079107
Other languages
English (en)
French (fr)
Inventor
张乐陶
张晓星
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/757,510 priority Critical patent/US11335756B2/en
Publication of WO2021164075A1 publication Critical patent/WO2021164075A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • This application relates to the field of display technology, and in particular to a method for manufacturing an OLED display device and a TFT array substrate.
  • OLED display devices have self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, close to 180° viewing angle, wide operating temperature range, and can realize flexible display and Large-area full-color display and many other advantages are recognized by the industry as the display device with the most potential for development.
  • the 3T1C that is, the structure of three thin film transistors and one capacitor
  • the 3T1C that is, the structure of three thin film transistors and one capacitor
  • TFT top-gate self-aligned amorphous oxide
  • the use of a top-gate self-aligned amorphous oxide TFT structure will introduce a light-shielding layer, adding an additional yellow light manufacturing process, but can not increase the device ⁇ On-state current.
  • an embodiment of the present application provides an OLED display device, including an OLED pixel driving circuit, the OLED pixel driving circuit includes a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3) ), a storage capacitor (Cst) and an organic light emitting diode;
  • the drain of the first thin film transistor (T1) is connected to the power supply voltage (Vdd), and the source is electrically connected to the anode of the organic light emitting diode;
  • the cathode of the second thin film transistor (T2) is connected to the common ground voltage;
  • the gate of the second thin film transistor (T2) is connected to the first scan signal (Scan 1), the drain is connected to the data signal line (Data), and the source is connected to the first thin film
  • the gate of the transistor (T1) and one end of the storage capacitor (Cst) are electrically connected; the other end of the storage capacitor (Cst) is electrically connected to the source of
  • the first thin film transistor (T1), the second thin film transistor (T2), and the third thin film transistor (T3) are all disposed on a substrate in the same layer;
  • the first thin film transistor (T1) is For double-gate oxide thin film transistors
  • the second thin film transistor (T2) and the third thin film transistor (T3) are both top-gate self-aligned oxide thin film transistors.
  • the measuring probe includes a plurality of photodiodes and a measuring subunit; wherein, the plurality of photodiodes are used to obtain the brightness signal of the display panel, so The measurement subunit is used to average the at least one brightness signal to obtain an analog brightness waveform signal of the display panel.
  • the double-gate oxide thin film transistor includes: the substrate; a first bottom gate electrode formed above the substrate; A buffer layer; a first semiconductor layer formed above the buffer layer; a first gate insulating layer formed above the first semiconductor layer; a first top gate electrode formed above the first gate insulating layer An interlayer insulating layer formed on the buffer layer and completely covering the first semiconductor layer, the first gate insulating layer and the first top gate electrode; formed on the interlayer insulating layer A first source metal layer and a first drain metal layer; a passivation layer formed on the interlayer insulating layer and completely covering the first source metal layer and the first drain metal layer; The double-gate thin film transistor further includes a first pixel electrode and a second pixel electrode, and the first pixel electrode and the second pixel electrode are formed on the passivation layer.
  • the first pixel electrode is electrically connected to the first bottom gate electrode through a first via hole, and the first pixel electrode is also electrically connected to the first bottom gate electrode via a second via hole.
  • the first top gate electrode is electrically connected; the second pixel electrode is electrically connected to the first drain metal layer through a third via hole; the first source metal layer and the first drain metal layer It is electrically connected to the first semiconductor layer through the fourth via hole.
  • the top gate self-aligned oxide thin film transistor includes: the substrate, a light shielding layer formed above the substrate, and the buffer layer; and the buffer layer is formed on the buffer layer
  • the second source metal layer and the second drain metal layer are electrically connected to the second semiconductor layer through a fifth via hole, and the second drain The polar metal layer is also electrically connected to the light shielding layer through the sixth via hole.
  • the materials of the buffer layer, the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the passivation layer are all It is at least one of silicon dioxide, silicon nitride, and aluminum oxide.
  • the materials of the second top gate electrode, the second source metal layer, and the second drain metal layer are all at least one of Mo, Al, Ti, and Cu.
  • an embodiment of the present application also provides an OLED display device, including an OLED pixel driving circuit, the OLED pixel driving circuit includes a first thin film transistor (T1), a second thin film transistor (T2), and a third thin film transistor ( T3), a storage capacitor (Cst), and an organic light emitting diode;
  • the drain of the first thin film transistor (T1) is connected to the power supply voltage (Vdd), and the source is electrically connected to the anode of the organic light emitting diode;
  • the organic light emitting diode The cathode of the diode is connected to the common ground voltage;
  • the gate of the second thin film transistor (T2) is connected to the first scan signal (Scan 1), the drain is connected to the data signal line (Data), and the source is connected to the first
  • the gate of the thin film transistor (T1) and one end of the storage capacitor (Cst) are electrically connected; the other end of the storage capacitor (Cst) is electrically connected to the source of the first thin film
  • the first thin film transistor (T1) is a double-gate oxide thin film transistor
  • the second thin film transistor (T2) and the third thin film transistor (T3) are both top-gate self-aligned oxide thin film transistors.
  • the double-gate oxide thin film transistor includes: the substrate; a first bottom gate electrode formed above the substrate; A buffer layer; a first semiconductor layer formed above the buffer layer; a first gate insulating layer formed above the first semiconductor layer; a first top gate electrode formed above the first gate insulating layer An interlayer insulating layer formed on the buffer layer and completely covering the first semiconductor layer, the first gate insulating layer and the first top gate electrode; formed on the interlayer insulating layer A first source metal layer and a first drain metal layer; a passivation layer formed on the interlayer insulating layer and completely covering the first source metal layer and the first drain metal layer; The double-gate thin film transistor further includes a first pixel electrode and a second pixel electrode, and the first pixel electrode and the second pixel electrode are formed on the passivation layer.
  • the first pixel electrode is electrically connected to the first bottom gate electrode through a first via hole, and the first pixel electrode is also electrically connected to the first bottom gate electrode via a second via hole.
  • the first top gate electrode is electrically connected; the second pixel electrode is electrically connected to the first drain metal layer through a third via hole; the first source metal layer and the first drain metal layer It is electrically connected to the first semiconductor layer through the fourth via hole.
  • the top gate self-aligned oxide thin film transistor includes: the substrate, a light shielding layer formed above the substrate, and the buffer layer; and the buffer layer is formed on the buffer layer
  • the second source metal layer and the second drain metal layer are electrically connected to the second semiconductor layer through a fifth via hole, and the second drain The polar metal layer is also electrically connected to the light shielding layer through the sixth via hole.
  • the materials of the buffer layer, the first gate insulating layer, the second gate insulating layer, the interlayer insulating layer, and the passivation layer are all It is at least one of silicon dioxide, silicon nitride, and aluminum oxide.
  • the materials of the second top gate electrode, the second source metal layer, and the second drain metal layer are all at least one of Mo, Al, Ti, and Cu.
  • the embodiments of the present application provide a method for preparing a TFT array substrate.
  • the TFT array substrate is used for preparing the OLED display device, and the method includes:
  • S20 Prepare a buffer layer, a semiconductor layer, a gate insulating layer, and the first metal layer in sequence on the substrate, and use a halftone mask as a second mask to form a first semiconductor layer on the buffer layer, A second semiconductor layer, a first gate insulating layer, a second gate insulating layer, a first top gate electrode, and a second top gate electrode;
  • a metal oxide layer is formed on the passivation layer, and the metal oxide layer is patterned into a first pixel electrode and a second pixel electrode with a sixth photomask, and the first pixel electrode passes through the
  • the first through hole is electrically connected to the first bottom gate electrode, the first pixel electrode is also electrically connected to the first top gate electrode through the third through hole, and the second pixel electrode is also electrically connected through
  • the sixth through hole is electrically connected to the first drain metal layer.
  • both ends of the edge of the first semiconductor layer and both ends of the edge of the second semiconductor layer are conducted through a plasma treatment process.
  • Treatment; the plasma treatment gas in the plasma treatment process is at least one of Ar, He and N 2.
  • the materials of the buffer layer, the first gate insulating layer, and the second gate insulating layer are all silicon dioxide, At least one of silicon nitride and aluminum oxide; the material of the first semiconductor layer and the second semiconductor layer is at least one of IZO and IZTO; the first top gate electrode and the second The material of the two top gate electrodes is the same as the material of the first metal layer.
  • the S30 further includes:
  • the first through hole exposes the first bottom gate electrode
  • the second through hole exposes the first semiconductor layer
  • the third through hole exposes the first top gate electrode
  • the fourth through hole exposes the second semiconductor layer
  • the fifth through hole exposes the light shielding layer.
  • the first source metal layer and the first drain metal layer are connected to the first conductor via the second through hole. Two ends of the edge of the conductive layer are electrically connected, the second source metal layer and the second drain metal layer are electrically connected to both ends of the edge of the second conductive layer through the fourth through hole, The second drain metal layer is electrically connected to the light shielding layer through the fifth through hole.
  • the OLED display device and the TFT array substrate manufacturing method provided in the embodiments of the present application use six photomasks to design the driving thin film transistor as a double-gate oxide thin film transistor and the switching thin film transistor as a top-gate free Aligning the oxide thin film transistor reduces the channel width of the driving thin film transistor and reduces the parasitic effect of the switching thin film transistor, effectively improving the pixel aperture ratio of the OLED display device, and further improving the display effect of the OLED display device.
  • FIG. 1 is a circuit diagram of an OLED pixel driving circuit with a 3T1C structure of an OLED display device provided by an embodiment of the application.
  • FIG. 2 is a schematic structural diagram of a TFT array substrate in an OLED display device provided by an embodiment of the application.
  • FIG. 3 is a flow chart of a manufacturing method of a TFT array substrate provided by an embodiment of the application.
  • 4A-4F are schematic structural diagrams of a method for preparing a TFT array substrate provided by an embodiment of the application.
  • the OLED pixel driving circuit includes a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a storage capacitor (Cst) and an organic light emitting diode;
  • the drain of T1) is connected to the power supply voltage (Vdd)
  • the source is electrically connected to the anode of the organic light emitting diode
  • the cathode of the organic light emitting diode is connected to a common ground voltage
  • the electrode is connected to the first scan signal (Scan 1), the drain is connected to the data signal line (Data), the source is electrically connected to the gate of the first thin film transistor (T1) and one end of the storage capacitor (Cst) Connected; the other end of the storage capacitor (Cst) is
  • the potential of the gate g) the data signal Data continues to be a high potential since the rise of the high potential pulse of the scan signal Scan, and the data signal Data is written into the first thin film through the turned-on third thin film transistor (T3)
  • the scan signal Scan maintains a low potential again, so that both the second thin film transistor (T2) and the third thin film transistor (T3) are turned off, relying on the storage effect of the storage capacitor (Cst) to cause the organic light emitting diode to emit light To display.
  • the Cgs (parasitic capacitance between the gate and the source) and Cgd (the coupling capacitance between the gate and the drain) of the first thin film transistor (T1) used to drive the pixel circuit will only affect Data
  • the charging time of the data signal and the Cgs of the second thin film transistor (T2) used to switch the pixel circuit will affect the potential of the storage capacitor (Cst) and the gate g of the first thin film transistor (T1).
  • the first thin film transistor (T1) in the embodiment of the application adopts double-gate oxidation. Thin film transistors are used to reduce the channel width, and the second thin film transistor (T2) and the third thin film transistor (T3) use top-gate self-aligned oxide thin film transistors to reduce parasitic effects of the device.
  • FIG. 2 it is a schematic structural diagram of a TFT array substrate in an OLED display device provided by an embodiment of the application.
  • the first thin film transistor (T1), the second thin film transistor (T2), and the third thin film transistor (T3) are all disposed on a substrate 11 in the same layer, and the first thin film transistor (T1) It is a double-gate oxide thin film transistor, and the second thin film transistor (T2) and the third thin film transistor (T3) are both top-gate self-aligned oxide thin film transistors.
  • the double-gate oxide thin film transistor (T1) includes: the substrate 11; a first bottom gate electrode 121 formed above the substrate 11; a buffer layer formed above the first bottom gate electrode 121 13; a first semiconductor layer 141 formed above the buffer layer 13; a first gate insulating layer 151 formed above the first semiconductor layer 141; a first gate insulating layer 151 formed above the first gate insulating layer 151 A top gate electrode 123; formed on the buffer layer 13 and completely covering the first semiconductor layer 141, the first gate insulating layer 151, and the interlayer insulating layer 16 of the first top gate electrode 123; A first source metal layer 171 and a first drain metal layer 172 formed on the interlayer insulating layer 16; formed on the interlayer insulating layer 16 and completely covering the first source metal layer 171 and The passivation layer 18 of the first drain metal layer 172; the double-gate thin film transistor (T1) further includes a first pixel electrode 191 and a second pixel electrode 192, the first pixel electrode 191 and
  • the first pixel electrode 191 is electrically connected to the first bottom gate electrode 121 through a first via hole 21, and the first pixel electrode 191 is also connected to the first top gate electrode via a second via hole 22.
  • the electrode 123 is electrically connected;
  • the second pixel electrode 192 is electrically connected to the first drain metal layer 172 through the third via 23;
  • the layer 172 is electrically connected to the first semiconductor layer 1471 through the fourth via hole 24.
  • the top gate self-aligned oxide thin film transistor includes: the substrate 11, a light shielding layer 122 formed on the substrate 11, and the buffer layer 13; and the buffer layer 13 is formed on the buffer layer. 13 above the second semiconductor layer 142, the second gate insulating layer 152 formed above the second semiconductor layer 142, the second top gate electrode 124 formed above the second gate insulating layer 152, the The interlayer insulating layer 16, the second source metal layer 173 and the second drain metal layer 174 formed on the interlayer insulating layer 16, the passivation layer 18 and the second pixel electrode 192.
  • the second source metal layer 173 and the second drain metal layer 174 are electrically connected to the second semiconductor layer 142 through the fifth via 25, and the second drain metal layer 174 is also It is electrically connected to the light shielding layer 122 through the sixth via hole 26.
  • the materials of the buffer layer 13, the first gate insulating layer 151, the second gate insulating layer 152, the interlayer insulating layer 16 and the passivation layer 18 are all silicon dioxide. , At least one of silicon nitride and aluminum oxide.
  • the material of the first semiconductor layer 141 and the second semiconductor layer 142 is at least one of IZO (Indium Zinc Oxide) and IZTO (Indium Zinc Tin Oxide); the first pixel electrode 191 And the material of the second pixel electrode 192 is ITO (Indium Tin Oxide).
  • the first bottom gate electrode 121, the light shielding layer 122, the first top gate electrode 123, the first source metal layer 171, the first drain metal layer 172, the second The materials of the two top gate electrodes 124, the second source metal layer 173, and the second drain metal layer 174 are all at least one of Mo, Al, Ti, and Cu.
  • FIG. 3 it is a flow chart of the manufacturing method of the TFT array substrate provided by the embodiment of this application. Wherein, the method specifically includes:
  • a first metal layer 12 is prepared on a substrate 11, and the first metal layer 12 is patterned into a first bottom gate electrode 121 and a light shielding layer 122 with a first mask.
  • the S10 further includes:
  • a substrate 11 is provided, the substrate is a glass substrate or a flexible substrate; then a first metal layer 12 is deposited on the substrate 11, and the material of the first metal layer 12 is Mo, Al, Ti, and Cu. At least one; finally, the first metal layer 12 is patterned into a first bottom gate electrode 121 and a light shielding layer 122 through a mask with a first mask, as shown in FIG. 4A.
  • a first semiconductor layer 141, a second semiconductor layer 142, a first gate insulating layer 151, a second gate insulating layer 152, a first top gate electrode 123, and a second top gate electrode 124 are formed thereon.
  • the S20 further includes:
  • a buffer layer 13 is prepared on the substrate 11 by a chemical vapor deposition method or a sputtering method, and the buffer layer 13 completely covers the first bottom gate electrode 121 and the light shielding layer 122; then, on the buffer layer A semiconductor layer 14, a gate insulating layer 15 and the first metal layer 12 are sequentially fabricated on 13.
  • a halftone mask 21 is used as the second mask to form a semiconductor region pattern above the buffer layer 13 (that is, part of the semiconductor layer 14 outside the semiconductor region, part of the gate insulating layer 15 and part of the second mask)
  • a metal layer 12 is etched away by wet etching, dry etching and wet etching respectively), and then part of the gate insulating layer 15 and part of the first metal layer 12 in the source and drain regions are ashed, and formed
  • the first top gate electrode 123 and the second top gate electrode 124 that is, part of the first metal layer 12 and part of the gate insulating layer 15 in the source and drain regions are etched away by wet etching and dry etching, respectively).
  • a first semiconductor layer 141, a second semiconductor layer 142, a first gate insulating layer 151, a second gate insulating layer 152, a first top gate electrode 123, and a second top gate electrode are formed on the buffer layer 13. 124.
  • the materials of the buffer layer 13, the first gate insulating layer 151, and the second gate insulating layer 152 are all at least one of silicon dioxide, silicon nitride, and aluminum oxide;
  • the material of the first semiconductor layer 141 and the second semiconductor layer 142 is at least one of IZO (indium zinc oxide) and IZTO (indium zinc tin oxide);
  • the first top gate electrode 123 and the The material of the second top gate electrode 124 is at least one of Mo, Al, Ti, and Cu.
  • both ends of the edge of the first semiconductor layer 141 and both ends of the edge of the second semiconductor layer 142 are conducted through a plasma treatment process to reduce the parasitic resistance of the source and drain of the device.
  • the plasma treatment gas in the plasma treatment process is at least one of Ar, He and N 2 , as shown in FIG. 4B.
  • the S30 further includes:
  • an interlayer insulating layer 16 is prepared on the buffer layer 13 by a chemical vapor deposition method or a sputtering method, and the interlayer insulating layer 16 completely covers the first semiconductor layer 141, the second semiconductor layer 142, The first gate insulating layer 151, the second gate insulating layer 152, the first top gate electrode 123, and the second top gate electrode 124; the material of the interlayer insulating layer 16 is dioxide At least one of silicon, silicon nitride, and aluminum oxide; after that, a halftone mask 22 is used as a third mask to etch the upper portion of the open area of the buffer layer 13 (at this time, the buffer The interlayer insulating layer 16 will be carved out in the open area of layer 13, and then the open area corresponding to the interlayer insulating layer 16 will be ashed, where the interlayer insulating layer 16 corresponds to the opening The hole region is above the source and drain regions and above the first top gate electrode 123.
  • the buffer layer in the open area of the buffer layer 13 will also be etched away, so that the source and drain electrode regions of the three TFTs and the light shielding layer 122 will be etched away.
  • Both the first top gate electrode 123 and the first bottom gate electrode 121 leak out. That is, the halftone mask 22 is used as the third mask to form the first through hole 31, the second through hole 32, the third through hole 33, the fourth through hole 34, and the fifth through hole on the interlayer insulating layer 16. ⁇ 35.
  • the first through hole 31 exposes the first bottom gate electrode 121
  • the second through hole 32 exposes the first semiconductor layer 141
  • the third through hole 33 exposes the first top gate electrode.
  • the fourth through hole 34 exposes the second semiconductor layer 142
  • the fifth through hole 35 exposes the light shielding layer 122, as shown in FIG. 4C.
  • the S40 further includes:
  • a second metal layer 17 is deposited on the interlayer insulating layer 16, and the second metal layer is patterned into a first source metal layer 171, a first drain metal layer 172, and a second metal layer with a fourth mask.
  • the first source metal layer 171 and the first drain metal layer 172 are electrically connected to both ends of the edge of the first conductive layer 141 through the second through hole 32, and the second source The metal layer 173 and the second drain metal layer 174 are electrically connected to both ends of the edge of the second conductive layer 142 through the fourth through hole 34, and the second drain metal layer 174 is also connected through the
  • the fifth through hole 35 is electrically connected to the light shielding layer 22, as shown in FIG. 4D.
  • the first drain metal layer 172 forms a sixth through hole 36 above the first drain metal layer 172.
  • the S50 further includes:
  • a passivation layer 18 is prepared on the interlayer insulating layer 16 by a chemical vapor deposition method or a sputtering method, and the passivation layer 18 completely covers the first source metal layer 171 and the first drain electrode.
  • the metal layer 172, the second source metal layer 173, and the second drain metal layer 174, and the passivation layer 18 is made of at least one of silicon dioxide, silicon nitride, and aluminum oxide .
  • the first bottom gate electrode 121, the first top gate electrode 123, and the first drain metal layer 172 are exposed on the passivation layer 18 with a fifth photomask.
  • a sixth through hole 36 is formed above the electrode metal layer 172, as shown in FIG. 4E.
  • an oxide metal layer 19 is formed on the passivation layer 18, and the oxide metal layer 19 is patterned into a first pixel electrode 191 and a second pixel electrode 192 with a sixth photomask.
  • the pixel electrode 191 is electrically connected to the first bottom gate electrode 121 through the first through hole 31, and the first pixel electrode 191 is also electrically connected to the first top gate electrode 123 through the third through hole 33.
  • the second pixel electrode 192 is also electrically connected to the first drain metal layer 172 through the sixth through hole 36.
  • the S60 further includes:
  • an oxide metal layer 19 is formed on the passivation layer 18.
  • the material of the oxide metal layer 19 is ITO (Indium Tin Oxide); then the oxide metal layer 19 is patterned with a sixth mask Is a first pixel electrode 191 and a second pixel electrode 192.
  • the first pixel electrode 191 is electrically connected to the first bottom gate electrode 121 through the first through hole 31, and the first pixel electrode 191 is also electrically connected through
  • the third through hole 33 is electrically connected to the first top gate electrode 123, and the second pixel electrode 192 is also electrically connected to the first drain metal layer 172 through the sixth through hole 36,
  • the TFT array substrate is prepared, as shown in FIG. 4F.
  • the OLED display device and TFT array substrate manufacturing method uses six photomasks to design the driving thin film transistor as a double-gate oxide thin film transistor and the switching thin film transistor is designed as a top gate self-aligned
  • the oxide thin film transistor reduces the channel width of the driving thin film transistor and reduces the parasitic effect of the switching thin film transistor, effectively increases the pixel aperture ratio of the OLED display device, and further improves the display effect of the OLED display device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种OLED显示装置，包括OLED像素驱动电路，所述OLED像素驱动电路中的驱动薄膜晶体管设置为双栅氧化物薄膜晶体管，开关薄膜晶体管设置为顶栅自对准氧化物薄膜晶体管。本申请还公开了一种TFT阵列基板的制备方法，所述TFT阵列基板用于制备所述OLED显示装置。

Description

OLED显示装置及TFT阵列基板的制备方法 技术领域
本申请涉及显示技术领域，尤其涉及一种OLED显示装置及TFT阵列基板的制备方法。
 背景技术
有机发光二极管(Organic Light Emitting Display，OLED)显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
目前的OLED像素驱动电路中，一般采用顶栅自对准型非晶氧化物TFT构成的3T1C（即三个薄膜晶体管加一个电容的结构）电路来驱动OLED发光，但由于非晶氧化物对短波光非常敏感，器件的阈值电压会在光照的作用下减小，从而严重影响OLED的发光强度，因此制作背板时会先沉积金属遮光层保护TFT（薄膜晶体管）器件不受底部环境光影响。然而单纯引入遮光层增加了额外的黄光制程，却不能增大器件的开态电流。
因此，现有的OLED显示装置及TFT阵列基板的制备方法采用3T1C像素电路时，使用顶栅自对准型非晶氧化物TFT结构会引入遮光层，增加了额外的黄光制程，却不能增大器件的开态电流。
 技术问题
现有的OLED显示装置及TFT阵列基板的制备方法采用3T1C像素电路时，使用顶栅自对准型非晶氧化物TFT结构会引入遮光层，增加了额外的黄光制程，却不能增大器件的开态电流。
 技术解决方案
第一方面，本申请实施例提供一种OLED显示装置，包括OLED像素驱动电路，所述OLED像素驱动电路包括第一薄膜晶体管(T1)、第二薄膜晶体管 (T2)、第三薄膜晶体管(T3)、存储电容(Cst)以及有机发光二极管；所述第一薄膜晶体管(T1)的漏极接入电源电压(Vdd)，源极电性连接所述有机发光二极管的阳极；所述有机发光二极管的阴极接入公共接地电压；所述第二薄膜晶体管(T2)的栅极接入第一扫描信号(Scan 1)，漏极接入数据信号线(Data)，源极与所述第一薄膜晶体管(T1)的栅极以及所述存储电容(Cst)的一端电性连接；所述存储电容(Cst)的另一端电性连接所述第一薄膜晶体管(T1)的源极；所述第三薄膜晶体管(T3)的栅极接入第二扫描信号(Scan 2)，源极电性连接所述第一薄膜晶体管(T1)的源极，漏极电性连接电路开关(K)；
其中，所述第一薄膜晶体管(T1)、所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均同层设置于一基板上；所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。在所述的用于测量显示面板闪烁度的检测装置中，所述测量探头包括多个光电二极管以及测量子单元；其中，多个所述光电二极管用于获得所述显示面板的亮度信号，所述测量子单元用于将所述至少一个亮度信号取平均值，获得所述显示面板的模拟亮度波形信号。
在本申请实施例提供的OLED显示装置中，所述双栅氧化物薄膜晶体管包括：所述基板；形成于所述基板上方的第一底栅电极；形成于所述第一底栅电极上方的缓冲层；形成于所述缓冲层上方的第一半导体层；形成于所述第一半导体层上方的第一栅极绝缘层；形成于所述第一栅极绝缘层上方的第一顶栅电极；形成于所述缓冲层上并完全覆盖所述第一半导体层、所述第一栅极绝缘层以及所述第一顶栅电极的层间绝缘层；形成于所述层间绝缘层上的第一源极金属层以及第一漏极金属层；形成于所述层间绝缘层上并完全覆盖所述第一源极金属层以及所述第一漏极金属层的钝化层；所述双栅薄膜晶体管还包括第一像素电极以及第二像素电极，所述第一像素电极以及所述第二像素电极形成于所述钝化层上。
在本申请实施例提供的OLED显示装置中，所述第一像素电极经由第一过孔与所述第一底栅电极电性连接，所述第一像素电极还经由第二过孔与所述第一顶栅电极电性连接；所述第二像素电极经由第三过孔与所述第一漏极金属层电性连接；所述第一源极金属层以及所述第一漏极金属层经由第四过孔与所述第一半导体层电性连接。
在本申请实施例提供的OLED显示装置中，所述顶栅自对准氧化物薄膜晶体管包括：所述基板、形成于所述基板上方的遮光层、所述缓冲层；形成于所述缓冲层上方的第二半导体层、形成于所述第二半导体层上方的第二栅极绝缘层、形成于所述第二栅极绝缘层上方的第二顶栅电极、所述层间绝缘层、形成于所述层间绝缘层上的第二源极金属层以及第二漏极金属层、所述钝化层以及所述第二像素电极。
在本申请实施例提供的OLED显示装置中，所述第二源极金属层以及所述第二漏极金属层经由第五过孔与所述第二半导体层电性连接，所述第二漏极金属层还经由第六过孔与所述遮光层电性连接。
在本申请实施例提供的OLED显示装置中，所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述层间绝缘层以及所述钝化层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。
在本申请实施例提供的OLED显示装置中，所述第一底栅电极所述遮光层、所述第一顶栅电极、所述第一源极金属层、所述第一漏极金属层、所述第二顶栅电极、所述第二源极金属层以及所述第二漏极金属层的材料均为Mo、Al、Ti以及Cu中的至少一种。
第二方面，本申请实施例还提供一种OLED显示装置，包括OLED像素驱动电路，所述OLED像素驱动电路包括第一薄膜晶体管(T1)、第二薄膜晶体管 (T2)、第三薄膜晶体管(T3)、存储电容(Cst)以及有机发光二极管；所述第一薄膜晶体管(T1)的漏极接入电源电压(Vdd)，源极电性连接所述有机发光二极管的阳极；所述有机发光二极管的阴极接入公共接地电压；所述第二薄膜晶体管(T2)的栅极接入第一扫描信号(Scan 1)，漏极接入数据信号线(Data)，源极与所述第一薄膜晶体管(T1)的栅极以及所述存储电容(Cst)的一端电性连接；所述存储电容(Cst)的另一端电性连接所述第一薄膜晶体管(T1)的源极；所述第三薄膜晶体管(T3)的栅极接入第二扫描信号(Scan 2)，源极电性连接所述第一薄膜晶体管(T1)的源极，漏极电性连接电路开关(K)；
其中，所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。
在本申请实施例提供的OLED显示装置中，所述双栅氧化物薄膜晶体管包括：所述基板；形成于所述基板上方的第一底栅电极；形成于所述第一底栅电极上方的缓冲层；形成于所述缓冲层上方的第一半导体层；形成于所述第一半导体层上方的第一栅极绝缘层；形成于所述第一栅极绝缘层上方的第一顶栅电极；形成于所述缓冲层上并完全覆盖所述第一半导体层、所述第一栅极绝缘层以及所述第一顶栅电极的层间绝缘层；形成于所述层间绝缘层上的第一源极金属层以及第一漏极金属层；形成于所述层间绝缘层上并完全覆盖所述第一源极金属层以及所述第一漏极金属层的钝化层；所述双栅薄膜晶体管还包括第一像素电极以及第二像素电极，所述第一像素电极以及所述第二像素电极形成于所述钝化层上。
在本申请实施例提供的OLED显示装置中，所述第一像素电极经由第一过孔与所述第一底栅电极电性连接，所述第一像素电极还经由第二过孔与所述第一顶栅电极电性连接；所述第二像素电极经由第三过孔与所述第一漏极金属层电性连接；所述第一源极金属层以及所述第一漏极金属层经由第四过孔与所述第一半导体层电性连接。
在本申请实施例提供的OLED显示装置中，所述顶栅自对准氧化物薄膜晶体管包括：所述基板、形成于所述基板上方的遮光层、所述缓冲层；形成于所述缓冲层上方的第二半导体层、形成于所述第二半导体层上方的第二栅极绝缘层、形成于所述第二栅极绝缘层上方的第二顶栅电极、所述层间绝缘层、形成于所述层间绝缘层上的第二源极金属层以及第二漏极金属层、所述钝化层以及所述第二像素电极。
在本申请实施例提供的OLED显示装置中，所述第二源极金属层以及所述第二漏极金属层经由第五过孔与所述第二半导体层电性连接，所述第二漏极金属层还经由第六过孔与所述遮光层电性连接。
在本申请实施例提供的OLED显示装置中，所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述层间绝缘层以及所述钝化层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。
在本申请实施例提供的OLED显示装置中，所述第一底栅电极所述遮光层、所述第一顶栅电极、所述第一源极金属层、所述第一漏极金属层、所述第二顶栅电极、所述第二源极金属层以及所述第二漏极金属层的材料均为Mo、Al、Ti以及Cu中的至少一种。
第三方面，本申请实施例又提供一种TFT阵列基板的制备方法，所述TFT阵列基板用于制备所述OLED显示装置，所述方法包括：
S10，在一基板上制备第一金属层，以第一道光罩将所述第一金属层图形化为第一底栅电极以及遮光层；
S20，在所述基板上依次制备缓冲层、半导体层、栅极绝缘层以及所述第一金属层，采用半色调掩膜版为第二道光罩在所述缓冲层上形成第一半导体层、第二半导体层、第一栅极绝缘层、第二栅极绝缘层、第一顶栅电极以及第二顶栅电极；
S30，在所述缓冲层上制备层间绝缘层，采用半色调掩膜版为第三道光罩在所述层间绝缘层上形成第一通孔、第二通孔、第三通孔、第四通孔以及第五通孔；
S40，在所述层间绝缘层上沉积第二金属层，以第四道光罩将所述第二金属层图形化为第一源极金属层、第一漏极金属层、第二源极金属层以及第二漏极金属层；
S50，在所述层间绝缘层上制备钝化层，以第五道光罩在所述钝化层上暴露出所述第一底栅电极、所述第一顶栅电极以及所述第一漏极金属层，在所述第一漏极金属层上方形成第六通孔；
S60，在所述钝化层上形成一氧化物金属层，以第六道光罩将所述氧化物金属层图形化为第一像素电极以及第二像素电极，所述第一像素电极经由所述第一通孔与所述第一底栅电极电性连接，所述第一像素电极还经由所述第三通孔与所述第一顶栅电极电性连接，所述第二像素电极还经由所述第六通孔与所述第一漏极金属层电性连接。
在本申请实施例提供的TFT阵列基板的制备方法中，所述S20中，所述第一半导体层的边缘两端以及所述第二半导体层的边缘两端均通过等离子体处理工艺进行导体化处理；所述等离子体处理工艺中的等离子处理气体为Ar、He以及N 2中的至少一种。
在本申请实施例提供的TFT阵列基板的制备方法中，所述S20中，所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种；所述第一半导体层以及所述第二半导体层的材料为IZO以及IZTO中的至少一种；所述第一顶栅电极以及所述第二顶栅电极的材料与所述第一金属层的材料相同。
在本申请实施例提供的TFT阵列基板的制备方法中，所述S30还包括：
S301，在所述缓冲层上通过化学气相沉积法或溅射方法制备层间绝缘层，所述层间绝缘层完全覆盖所述第一半导体层、所述第二半导体层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述第一顶栅电极以及所述第二顶栅电极；
S302，采用半色调掩膜版为第三道光罩对所述缓冲层的开孔区域上方进行刻蚀，并灰化掉所述层间绝缘层对应的开孔区域，所述层间绝缘层对应的开孔区域为源漏极区域的上方以及所述第一顶栅电极的上方；
S303，最后在所述层间绝缘层上形成第一通孔、第二通孔、第三通孔、第四通孔以及第五通孔。
在本申请实施例提供的TFT阵列基板的制备方法中，所述S303中，所述第一通孔暴露出所述第一底栅电极，所述第二通孔暴露出所述第一半导体层，所述第三通孔暴露出所述第一顶栅电极，所述第四通孔暴露出所述第二半导体层，所述第五通孔暴露出所述遮光层。
在本申请实施例提供的TFT阵列基板的制备方法中，所述S40中，所述第一源极金属层以及所述第一漏极金属层经由所述第二通孔与所述第一导体化层的边缘两端电性相连，所述第二源极金属层以及所述第二漏极金属层经由所述第四通孔与所述第二导体化层的边缘两端电性相连，所述第二漏极金属层经由所述第五通孔与所述遮光层电性相连。
 有益效果
相较于现有技术，本申请实施例所提供的OLED显示装置及TFT阵列基板的制备方法，采用六道光罩将驱动薄膜晶体管设计为双栅氧化物薄膜晶体管且开关薄膜晶体管设计为顶栅自对准氧化物薄膜晶体管，减小了驱动薄膜晶体管的沟道宽度以及减小了开关薄膜晶体管的寄生效应，有效提高了OLED显示装置的像素开口率，进一步提升了OLED显示装置的显示效果。
 附图说明
图1为本申请实施例提供的OLED显示装置的3T1C结构的OLED像素驱动电路的电路图。
图2为本申请实施例提供的OLED显示装置中TFT阵列基板的结构示意图。
图3为本申请实施例提供的TFT阵列基板的制备方法流程图。
图4A-图4F为本申请实施例提供的TFT阵列基板的制备方法的结构示意图。
 本发明的实施方式
本申请实施例针对现有的OLED显示装置及TFT阵列基板的制备方法采用3T1C像素电路时，使用顶栅自对准型非晶氧化物TFT结构会引入遮光层，增加了额外的黄光制程，却不能增大器件的开态电流的技术问题，本实施例能够解决该缺陷。
如图1所示，为本申请实施例提供的OLED显示装置的3T1C结构的OLED像素驱动电路的电路图。其中，所述OLED像素驱动电路包括第一薄膜晶体管(T1)、第二薄膜晶体管 (T2)、第三薄膜晶体管(T3)、存储电容(Cst)以及有机发光二极管；所述第一薄膜晶体管(T1)的漏极接入电源电压(Vdd)，源极电性连接所述有机发光二极管的阳极；所述有机发光二极管的阴极接入公共接地电压；所述第二薄膜晶体管(T2)的栅极接入第一扫描信号(Scan 1)，漏极接入数据信号线(Data)，源极与所述第一薄膜晶体管(T1)的栅极以及所述存储电容(Cst)的一端电性连接；所述存储电容(Cst)的另一端电性连接所述第一薄膜晶体管(T1)的源极；所述第三薄膜晶体管(T3)的栅极接入第二扫描信号(Scan 2)，源极电性连接所述第一薄膜晶体管(T1)的源极，漏极电性连接电路开关(K)；所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。
由图1可知，当所述电路开关(K)连通时，所述第一扫描信号(Scan 1)以及所述第二扫描信号(Scan 2)首先提供一高电位脉冲，使得所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均导通。在这一阶段，电源电压Vdd经导通的所述第二薄膜晶体管(T2)进入所述第一薄膜晶体管(T1)的栅极g，即Vg＝Vdd(Vg表示第一薄膜晶体管(T1)的栅极g的电位)；数据信号Data自扫描信号Scan的高电位脉冲的上升开始持续为高电位，数据信号Data经导通的所述第三薄膜晶体管(T3)写入所述第一薄膜晶体管(T1)的源极s，即Vs＝VData(Vs表示所述第一薄膜晶体管(T1)的源极s的电位，VData表示数据信号Data的电位)。之后，扫描信号Scan再保持低电位，使得所述第二薄膜晶体管(T2)和所述第三薄膜晶体管(T3)均截止，依靠存储电容(Cst)的存储作用，使得所述有机发光二极管发光进行显示。
具体地，用于驱动像素电路的所述第一薄膜晶体管(T1)的Cgs（栅极与源极之间的寄生电容）和Cgd（栅极与漏极之间的耦合电容）仅会影响Data数据信号的充电时间，而用于开关像素电路的所述第二薄膜晶体管(T2)的Cgs则会影响到存储电容(Cst)和所述第一薄膜晶体管(T1)的栅极g的电位。
由于双栅氧化物薄膜晶体管会增大TFT器件的开态电流，从而减小器件的沟道宽度，增加像素开口率，因此本申请实施例中所述第一薄膜晶体管(T1)采用双栅氧化物薄膜晶体管来减小沟道宽度，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)采用顶栅自对准氧化物薄膜晶体管来减小器件的寄生效应。
如图2所示，为本申请实施例提供的OLED显示装置中TFT阵列基板的结构示意图。其中，所述第一薄膜晶体管(T1)、所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均同层设置于一基板11上，所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。
具体地，所述双栅氧化物薄膜晶体管(T1)包括：所述基板11；形成于所述基板11上方的第一底栅电极121；形成于所述第一底栅电极121上方的缓冲层13；形成于所述缓冲层13上方的第一半导体层141；形成于所述第一半导体层141上方的第一栅极绝缘层151；形成于所述第一栅极绝缘层151上方的第一顶栅电极123；形成于所述缓冲层13上并完全覆盖所述第一半导体层141、所述第一栅极绝缘层151以及所述第一顶栅电极123的层间绝缘层16；形成于所述层间绝缘层16上的第一源极金属层171以及第一漏极金属层172；形成于所述层间绝缘层16上并完全覆盖所述第一源极金属层171以及所述第一漏极金属层172的钝化层18；所述双栅薄膜晶体管(T1)还包括第一像素电极191以及第二像素电极192，所述第一像素电极191以及所述第二像素电极192形成于所述钝化层18上。
具体地，所述第一像素电极191经由第一过孔21与所述第一底栅电极121电性连接，所述第一像素电极191还经由第二过孔22与所述第一顶栅电极123电性连接；所述第二像素电极192经由第三过孔23与所述第一漏极金属层172电性连接；所述第一源极金属层171以及所述第一漏极金属层172经由第四过孔24与所述第一半导体层1471电性连接。
具体地，所述顶栅自对准氧化物薄膜晶体管(T2或T3)包括：所述基板11、形成于所述基板11上方的遮光层122、所述缓冲层13；形成于所述缓冲层13上方的第二半导体层142、形成于所述第二半导体层142上方的第二栅极绝缘层152、形成于所述第二栅极绝缘层152上方的第二顶栅电极124、所述层间绝缘层16、形成于所述层间绝缘层16上的第二源极金属层173以及第二漏极金属层174、所述钝化层18以及所述第二像素电极192。
具体地，所述第二源极金属层173以及所述第二漏极金属层174经由第五过孔25与所述第二半导体层142电性连接，所述第二漏极金属层174还经由第六过孔26与所述遮光层122电性连接。
具体地，所述缓冲层13、所述第一栅极绝缘层151、所述第二栅极绝缘层152、所述层间绝缘层16以及所述钝化层18的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。
具体地，所述第一半导体层141以及所述第二半导体层142的材料为IZO（铟锌氧化物）以及IZTO（铟锌锡氧化物）中的至少一种；所述第一像素电极191以及所述第二像素电极192的材料为ITO（铟锡氧化物）。
具体地，所述第一底栅电极121、所述遮光层122、所述第一顶栅电极123、所述第一源极金属层171、所述第一漏极金属层172、所述第二顶栅电极124、所述第二源极金属层173以及所述第二漏极金属层174的材料均为Mo、Al、Ti、Cu中的至少一种。
如图3所示，为本申请实施例提供的TFT阵列基板的制备方法流程图。其中，所述方法具体包括：
S10，在一基板11上制备第一金属层12，以第一道光罩将所述第一金属层12图形化为第一底栅电极121以及遮光层122。
具体地，所述S10还包括：
首先提供一基板11，所述基板为玻璃基板或者柔性衬底；之后在所述基板11上沉积第一金属层12，所述第一金属层12的材料为Mo、Al、Ti、Cu中的至少一种；最后，通过一掩膜版以第一道光罩将所述第一金属层12图形化为第一底栅电极121以及遮光层122，如图4A所示。
S20，在所述基板11上依次制备缓冲层13、半导体层14、栅极绝缘层15以及所述第一金属层12，采用半色调掩膜版21为第二道光罩在所述缓冲层13上形成第一半导体层141、第二半导体层142、第一栅极绝缘层151、第二栅极绝缘层152、第一顶栅电极123以及第二顶栅电极124。
具体地，所述S20还包括：
首先在所述基板11上通过化学气相沉积法或溅射方法制备缓冲层13，所述缓冲层13完全覆盖所述第一底栅电极121以及所述遮光层122；之后，在所述缓冲层13上依次制作半导体层14、栅极绝缘层15以及所述第一金属层12。接着采用半色调掩膜版21为第二道光罩在所述缓冲层13上方形成半导体区图形（即将半导体区外的部分所述半导体层14、部分所述栅极绝缘层15以及部分所述第一金属层12分别用湿法蚀刻、干法蚀刻以及湿法蚀刻腐蚀掉），接着灰化掉源漏极区域的部分所述栅极绝缘层15以及部分所述第一金属层12，并形成第一顶栅电极123以及第二顶栅电极124（即将源漏区域的部分所述第一金属层12、部分所述栅极绝缘层15分别用湿法蚀刻以及干法蚀刻腐蚀掉）。之后，在所述缓冲层13上形成第一半导体层141、第二半导体层142、第一栅极绝缘层151、第二栅极绝缘层152、第一顶栅电极123以及第二顶栅电极124。具体地，所述缓冲层13、所述第一栅极绝缘层151以及所述第二栅极绝缘层152的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种；所述第一半导体层141以及所述第二半导体层142的材料为IZO（铟锌氧化物）以及IZTO（铟锌锡氧化物）中的至少一种；所述第一顶栅电极123以及所述第二顶栅电极124、的材料均为Mo、Al、Ti、Cu中的至少一种。
最后，所述第一半导体层141的边缘两端以及所述第二半导体层142的边缘两端均通过等离子体处理工艺进行导体化处理，以减小器件的源漏寄生电阻。所述等离子体处理工艺中的等离子处理气体为Ar、He以及N 2中的至少一种，如图4B所示。
S30，在所述缓冲层13上制备层间绝缘层16，采用半色调掩膜版22为第三道光罩在所述层间绝缘层16上形成第一通孔31、第二通孔32、第三通孔33、第四通孔34以及第五通孔35。
具体地，所述S30还包括：
首先，在所述缓冲层13上通过化学气相沉积法或溅射方法制备层间绝缘层16，所述层间绝缘层16完全覆盖所述第一半导体层141、所述第二半导体层142、所述第一栅极绝缘层151、所述第二栅极绝缘层152、所述第一顶栅电极123以及所述第二顶栅电极124；所述层间绝缘层16的材料为二氧化硅、硅氮化物以及三氧化二铝中的至少一种；之后，采用半色调掩膜版22为第三道光罩对所述缓冲层13的开孔区域上方进行刻蚀（此时所述缓冲层13的开孔区域的部分所述层间绝缘层16将被刻开），接着灰化掉所述层间绝缘层16对应的开孔区域，此处所述层间绝缘层16对应的开孔区域为源漏极区域的上方以及所述第一顶栅电极123的上方。在第二次刻蚀所述层间绝缘层16的同时，所述缓冲层13的开孔区域的缓冲层也将被刻掉，从而将三个TFT的源漏电极区域、所述遮光层122、所述第一顶栅电极123和所述第一底栅电极121都漏出。即采用半色调掩膜版22为第三道光罩在所述层间绝缘层16上形成第一通孔31、第二通孔32、第三通孔33、第四通孔34以及第五通孔35。所述第一通孔31暴露出所述第一底栅电极121，所述第二通孔32暴露出所述第一半导体层141，所述第三通孔33暴露出所述第一顶栅电极123，所述第四通孔34暴露出所述第二半导体层142，所述第五通孔35暴露出所述遮光层122，如图4C所示。
S40，在所述层间绝缘层16上沉积第二金属层17，以第四道光罩将所述第二金属层图形化为第一源极金属层171、第一漏极金属层172、第二源极金属层173以及第二漏极金属层174。
具体地，所述S40还包括：
首先，在所述层间绝缘层16上沉积第二金属层17，以第四道光罩将所述第二金属层图形化为第一源极金属层171、第一漏极金属层172、第二源极金属层173以及第二漏极金属层174。所述第一源极金属层171以及所述第一漏极金属层172经由所述第二通孔32与所述第一导体化层141的边缘两端电性相连，所述第二源极金属层173以及所述第二漏极金属层174经由所述第四通孔34与所述第二导体化层142的边缘两端电性相连，所述第二漏极金属层174还经由所述第五通孔35与所述遮光层22电性相连，如图4D所示。
S50，在所述层间绝缘层16上制备钝化层18，以第五道光罩在所述钝化层18上暴露出所述第一底栅电极121、所述第一顶栅电极123以及所述第一漏极金属层172，在所述第一漏极金属层172上方形成第六通孔36。
具体地，所述S50还包括：
首先，在所述层间绝缘层16上通过化学气相沉积法或溅射方法制备钝化层18，所述钝化层18完全覆盖所述第一源极金属层171、所述第一漏极金属层172、所述第二源极金属层173以及所述第二漏极金属层174，所述钝化层18的材料为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。之后以第五道光罩在所述钝化层18上暴露出所述第一底栅电极121、所述第一顶栅电极123以及所述第一漏极金属层172，在所述第一漏极金属层172上方形成第六通孔36，如图4E所示。
S60，在所述钝化层18上形成一氧化物金属层19，以第六道光罩将所述氧化物金属层19图形化为第一像素电极191以及第二像素电极192，所述第一像素电极191经由所述第一通孔31与所述第一底栅电极121电性连接，所述第一像素电极191还经由所述第三通孔33与所述第一顶栅电极123电性连接，所述第二像素电极192还经由所述第六通孔36与所述第一漏极金属层172电性连接。
具体地，所述S60还包括：
首先在所述钝化层18上形成一氧化物金属层19，所述氧化物金属层19的材料为ITO（氧化铟锡）；之后以第六道光罩将所述氧化物金属层19图形化为第一像素电极191以及第二像素电极192，所述第一像素电极191经由所述第一通孔31与所述第一底栅电极121电性连接，所述第一像素电极191还经由所述第三通孔33与所述第一顶栅电极123电性连接，所述第二像素电极192还经由所述第六通孔36与所述第一漏极金属层172电性连接，最后制备成所述TFT阵列基板，如图4F所示。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
综上所述，本申请实施例所提供的OLED显示装置及TFT阵列基板的制备方法，采用六道光罩将驱动薄膜晶体管设计为双栅氧化物薄膜晶体管且开关薄膜晶体管设计为顶栅自对准氧化物薄膜晶体管，减小了驱动薄膜晶体管的沟道宽度以及减小了开关薄膜晶体管的寄生效应，有效提高了OLED显示装置的像素开口率，进一步提升了OLED显示装置的显示效果。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种OLED显示装置，其中，包括OLED像素驱动电路，所述OLED像素驱动电路包括第一薄膜晶体管(T1)、第二薄膜晶体管 (T2)、第三薄膜晶体管(T3)、存储电容(Cst)以及有机发光二极管；所述第一薄膜晶体管(T1)的漏极接入电源电压(Vdd)，源极电性连接所述有机发光二极管的阳极；所述有机发光二极管的阴极接入公共接地电压；所述第二薄膜晶体管(T2)的栅极接入第一扫描信号(Scan 1)，漏极接入数据信号线(Data)，源极与所述第一薄膜晶体管(T1)的栅极以及所述存储电容(Cst)的一端电性连接；所述存储电容(Cst)的另一端电性连接所述第一薄膜晶体管(T1)的源极；所述第三薄膜晶体管(T3)的栅极接入第二扫描信号(Scan 2)，源极电性连接所述第一薄膜晶体管(T1)的源极，漏极电性连接电路开关(K)；
    其中，所述第一薄膜晶体管(T1)、所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均同层设置于一基板上；所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。
  2. 根据权利要求1所述的OLED显示装置，其中，所述双栅氧化物薄膜晶体管包括：所述基板；形成于所述基板上方的第一底栅电极；形成于所述第一底栅电极上方的缓冲层；形成于所述缓冲层上方的第一半导体层；形成于所述第一半导体层上方的第一栅极绝缘层；形成于所述第一栅极绝缘层上方的第一顶栅电极；形成于所述缓冲层上并完全覆盖所述第一半导体层、所述第一栅极绝缘层以及所述第一顶栅电极的层间绝缘层；形成于所述层间绝缘层上的第一源极金属层以及第一漏极金属层；形成于所述层间绝缘层上并完全覆盖所述第一源极金属层以及所述第一漏极金属层的钝化层；所述双栅薄膜晶体管还包括第一像素电极以及第二像素电极，所述第一像素电极以及所述第二像素电极形成于所述钝化层上。
  3. 根据权利要求2所述的OLED显示装置，其中，所述第一像素电极经由第一过孔与所述第一底栅电极电性连接，所述第一像素电极还经由第二过孔与所述第一顶栅电极电性连接；所述第二像素电极经由第三过孔与所述第一漏极金属层电性连接；所述第一源极金属层以及所述第一漏极金属层经由第四过孔与所述第一半导体层电性连接。
  4. 根据权利要求2所述的OLED显示装置，其中，所述顶栅自对准氧化物薄膜晶体管包括：所述基板、形成于所述基板上方的遮光层、所述缓冲层；形成于所述缓冲层上方的第二半导体层、形成于所述第二半导体层上方的第二栅极绝缘层、形成于所述第二栅极绝缘层上方的第二顶栅电极、所述层间绝缘层、形成于所述层间绝缘层上的第二源极金属层以及第二漏极金属层、所述钝化层以及所述第二像素电极。
  5. 根据权利要求4所述的OLED显示装置，其中，所述第二源极金属层以及所述第二漏极金属层经由第五过孔与所述第二半导体层电性连接，所述第二漏极金属层还经由第六过孔与所述遮光层电性连接。
  6. 根据权利要求4所述的OLED显示装置，其中，所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述层间绝缘层以及所述钝化层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。
  7. 根据权利要求4所述的OLED显示装置，其中，所述第一底栅电极所述遮光层、所述第一顶栅电极、所述第一源极金属层、所述第一漏极金属层、所述第二顶栅电极、所述第二源极金属层以及所述第二漏极金属层的材料均为Mo、Al、Ti以及Cu中的至少一种。
  8. 一种OLED显示装置，其中，包括OLED像素驱动电路，所述OLED像素驱动电路包括第一薄膜晶体管(T1)、第二薄膜晶体管 (T2)、第三薄膜晶体管(T3)、存储电容(Cst)以及有机发光二极管；所述第一薄膜晶体管(T1)的漏极接入电源电压(Vdd)，源极电性连接所述有机发光二极管的阳极；所述有机发光二极管的阴极接入公共接地电压；所述第二薄膜晶体管(T2)的栅极接入第一扫描信号(Scan 1)，漏极接入数据信号线(Data)，源极与所述第一薄膜晶体管(T1)的栅极以及所述存储电容(Cst)的一端电性连接；所述存储电容(Cst)的另一端电性连接所述第一薄膜晶体管(T1)的源极；所述第三薄膜晶体管(T3)的栅极接入第二扫描信号(Scan 2)，源极电性连接所述第一薄膜晶体管(T1)的源极，漏极电性连接电路开关(K)；
    其中，所述第一薄膜晶体管(T1)为双栅氧化物薄膜晶体管，所述第二薄膜晶体管 (T2)以及所述第三薄膜晶体管(T3)均为顶栅自对准氧化物薄膜晶体管。
  9. 根据权利要求8所述的OLED显示装置，其中，所述双栅氧化物薄膜晶体管包括：所述基板；形成于所述基板上方的第一底栅电极；形成于所述第一底栅电极上方的缓冲层；形成于所述缓冲层上方的第一半导体层；形成于所述第一半导体层上方的第一栅极绝缘层；形成于所述第一栅极绝缘层上方的第一顶栅电极；形成于所述缓冲层上并完全覆盖所述第一半导体层、所述第一栅极绝缘层以及所述第一顶栅电极的层间绝缘层；形成于所述层间绝缘层上的第一源极金属层以及第一漏极金属层；形成于所述层间绝缘层上并完全覆盖所述第一源极金属层以及所述第一漏极金属层的钝化层；所述双栅薄膜晶体管还包括第一像素电极以及第二像素电极，所述第一像素电极以及所述第二像素电极形成于所述钝化层上。
  10. 根据权利要求8所述的OLED显示装置，其中，所述第一像素电极经由第一过孔与所述第一底栅电极电性连接，所述第一像素电极还经由第二过孔与所述第一顶栅电极电性连接；所述第二像素电极经由第三过孔与所述第一漏极金属层电性连接；所述第一源极金属层以及所述第一漏极金属层经由第四过孔与所述第一半导体层电性连接。
  11. 根据权利要求8所述的OLED显示装置，其中，所述顶栅自对准氧化物薄膜晶体管包括：所述基板、形成于所述基板上方的遮光层、所述缓冲层；形成于所述缓冲层上方的第二半导体层、形成于所述第二半导体层上方的第二栅极绝缘层、形成于所述第二栅极绝缘层上方的第二顶栅电极、所述层间绝缘层、形成于所述层间绝缘层上的第二源极金属层以及第二漏极金属层、所述钝化层以及所述第二像素电极。
  12. 根据权利要求11所述的OLED显示装置，其中，所述第二源极金属层以及所述第二漏极金属层经由第五过孔与所述第二半导体层电性连接，所述第二漏极金属层还经由第六过孔与所述遮光层电性连接。
  13. 根据权利要求11所述的OLED显示装置，其中，所述缓冲层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述层间绝缘层以及所述钝化层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种。
  14. 根据权利要求11所述的OLED显示装置，其中，所述第一底栅电极所述遮光层、所述第一顶栅电极、所述第一源极金属层、所述第一漏极金属层、所述第二顶栅电极、所述第二源极金属层以及所述第二漏极金属层的材料均为Mo、Al、Ti以及Cu中的至少一种。
  15. 一种TFT阵列基板的制备方法，所述TFT阵列基板用于制备如权利要求1所述的OLED显示装置，其中，所述方法包括：
    S10，在一基板上制备第一金属层，以第一道光罩将所述第一金属层图形化为第一底栅电极以及遮光层；
    S20，在所述基板上依次制备缓冲层、半导体层、栅极绝缘层以及所述第一金属层，采用半色调掩膜版为第二道光罩在所述缓冲层上形成第一半导体层、第二半导体层、第一栅极绝缘层、第二栅极绝缘层、第一顶栅电极以及第二顶栅电极；
    S30，在所述缓冲层上制备层间绝缘层，采用半色调掩膜版为第三道光罩在所述层间绝缘层上形成第一通孔、第二通孔、第三通孔、第四通孔以及第五通孔；
    S40，在所述层间绝缘层上沉积第二金属层，以第四道光罩将所述第二金属层图形化为第一源极金属层、第一漏极金属层、第二源极金属层以及第二漏极金属层；
    S50，在所述层间绝缘层上制备钝化层，以第五道光罩在所述钝化层上暴露出所述第一底栅电极、所述第一顶栅电极以及所述第一漏极金属层，在所述第一漏极金属层上方形成第六通孔；
    S60，在所述钝化层上形成一氧化物金属层，以第六道光罩将所述氧化物金属层图形化为第一像素电极以及第二像素电极，所述第一像素电极经由所述第一通孔与所述第一底栅电极电性连接，所述第一像素电极还经由所述第三通孔与所述第一顶栅电极电性连接，所述第二像素电极还经由所述第六通孔与所述第一漏极金属层电性连接。
  16. 根据权利要求15所述的TFT阵列基板的制备方法，其中，所述S20中，所述第一半导体层的边缘两端以及所述第二半导体层的边缘两端均通过等离子体处理工艺进行导体化处理；所述等离子体处理工艺中的等离子处理气体为Ar、He以及N 2中的至少一种。
  17. 根据权利要求15所述的TFT阵列基板的制备方法，其中，所述S20中，所述缓冲层、所述第一栅极绝缘层以及所述第二栅极绝缘层的材料均为二氧化硅、硅氮化物以及三氧化二铝中的至少一种；所述第一半导体层以及所述第二半导体层的材料为IZO以及IZTO中的至少一种；所述第一顶栅电极以及所述第二顶栅电极的材料与所述第一金属层的材料相同。
  18. 根据权利要求15所述的TFT阵列基板的制备方法，其中，所述S30还包括：
    S301，在所述缓冲层上通过化学气相沉积法或溅射方法制备层间绝缘层，所述层间绝缘层完全覆盖所述第一半导体层、所述第二半导体层、所述第一栅极绝缘层、所述第二栅极绝缘层、所述第一顶栅电极以及所述第二顶栅电极；
    S302，采用半色调掩膜版为第三道光罩对所述缓冲层的开孔区域上方进行刻蚀，并灰化掉所述层间绝缘层对应的开孔区域，所述层间绝缘层对应的开孔区域为源漏极区域的上方以及所述第一顶栅电极的上方；
    S303，最后在所述层间绝缘层上形成第一通孔、第二通孔、第三通孔、第四通孔以及第五通孔。
  19. 根据权利要求18所述的TFT阵列基板的制备方法，其中，所述S303中，所述第一通孔暴露出所述第一底栅电极，所述第二通孔暴露出所述第一半导体层，所述第三通孔暴露出所述第一顶栅电极，所述第四通孔暴露出所述第二半导体层，所述第五通孔暴露出所述遮光层。
  20. 根据权利要求15所述的TFT阵列基板的制备方法，其中，所述S40中，所述第一源极金属层以及所述第一漏极金属层经由所述第二通孔与所述第一导体化层的边缘两端电性相连，所述第二源极金属层以及所述第二漏极金属层经由所述第四通孔与所述第二导体化层的边缘两端电性相连，所述第二漏极金属层经由所述第五通孔与所述遮光层电性相连。
PCT/CN2020/079107 2020-02-21 2020-03-13 Oled 显示装置及 tft 阵列基板的制备方法 WO2021164075A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/757,510 US11335756B2 (en) 2020-02-21 2020-03-13 OLED display device and manufacturing method of TFT array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010107341.4 2020-02-21
CN202010107341.4A CN111192884A (zh) 2020-02-21 2020-02-21 Oled显示装置及tft阵列基板的制备方法

Publications (1)

Publication Number Publication Date
WO2021164075A1 true WO2021164075A1 (zh) 2021-08-26

Family

ID=70710189

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/079107 WO2021164075A1 (zh) 2020-02-21 2020-03-13 Oled 显示装置及 tft 阵列基板的制备方法

Country Status (3)

Country Link
US (1) US11335756B2 (zh)
CN (1) CN111192884A (zh)
WO (1) WO2021164075A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114721553A (zh) * 2022-06-06 2022-07-08 惠科股份有限公司 触控结构、oled触控显示面板及制作方法
CN115036271A (zh) * 2022-06-21 2022-09-09 昆山龙腾光电股份有限公司 金属氧化物半导体薄膜晶体管阵列基板及其制作方法、显示装置

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111739416A (zh) * 2020-06-19 2020-10-02 武汉华星光电半导体显示技术有限公司 显示装置
KR20220037541A (ko) * 2020-09-17 2022-03-25 삼성디스플레이 주식회사 표시 장치
KR102697120B1 (ko) * 2020-11-06 2024-08-22 삼성디스플레이 주식회사 유기 발광 표시 장치
CN112466948B (zh) * 2020-11-27 2024-05-28 合肥鑫晟光电科技有限公司 栅极驱动电路及其制造方法、阵列基板、显示装置
US11973084B2 (en) * 2021-04-12 2024-04-30 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate, manufacturing method thereof, and display device thereof
CN113192988A (zh) * 2021-04-23 2021-07-30 深圳市华星光电半导体显示技术有限公司 一种显示器件
CN113327936B (zh) * 2021-05-24 2022-08-23 武汉华星光电技术有限公司 阵列基板及其制备方法
US20240172490A1 (en) * 2021-06-23 2024-05-23 Chengdu Boe Optoelectronics Technology Co., Ltd. Display Substrate, Preparation Method thereof, and Display Apparatus
CN114068589A (zh) * 2021-08-09 2022-02-18 Tcl华星光电技术有限公司 阵列基板、阵列基板的制作方法及显示面板
CN114220865A (zh) * 2021-12-13 2022-03-22 深圳市华星光电半导体显示技术有限公司 薄膜晶体管及其制作方法、显示面板
CN114335183A (zh) * 2021-12-17 2022-04-12 Tcl华星光电技术有限公司 阵列基板及显示面板
CN114335013A (zh) * 2021-12-24 2022-04-12 Tcl华星光电技术有限公司 阵列基板及其制备方法
CN114584132B (zh) * 2022-02-09 2023-05-26 香港科技大学 电子单元阵列及器件、人工神经网络
CN114566505A (zh) * 2022-02-17 2022-05-31 深圳市华星光电半导体显示技术有限公司 驱动基板及其制作方法、显示面板
CN114823808A (zh) * 2022-03-07 2022-07-29 武汉华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN114883344B (zh) * 2022-04-24 2023-06-30 绵阳惠科光电科技有限公司 显示面板及显示装置
CN117080222B (zh) * 2023-07-28 2024-09-20 惠科股份有限公司 阵列基板及其制备方法、显示装置
CN116709833A (zh) * 2023-08-08 2023-09-05 惠科股份有限公司 屏下摄像显示屏和显示装置
CN116709832A (zh) * 2023-08-08 2023-09-05 惠科股份有限公司 屏下摄像显示屏和显示装置
CN117580394B (zh) * 2023-12-13 2024-10-18 惠科股份有限公司 像素结构及其制备方法、显示基板及显示装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030109086A1 (en) * 2001-10-31 2003-06-12 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
CN107452809A (zh) * 2017-09-04 2017-12-08 深圳市华星光电半导体显示技术有限公司 薄膜晶体管结构及amoled驱动电路
CN109326609A (zh) * 2018-09-12 2019-02-12 深圳市华星光电技术有限公司 一种阵列基板及其制作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402982B (zh) * 2009-03-02 2013-07-21 Innolux Corp 影像顯示系統及其製造方法
CN104867961B (zh) * 2015-04-24 2020-06-30 京东方科技集团股份有限公司 阵列基板、其制造方法及显示装置
US20190074383A1 (en) 2017-09-04 2019-03-07 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor structure and driving circuit of amoled

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030109086A1 (en) * 2001-10-31 2003-06-12 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
CN107452809A (zh) * 2017-09-04 2017-12-08 深圳市华星光电半导体显示技术有限公司 薄膜晶体管结构及amoled驱动电路
CN109326609A (zh) * 2018-09-12 2019-02-12 深圳市华星光电技术有限公司 一种阵列基板及其制作方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114721553A (zh) * 2022-06-06 2022-07-08 惠科股份有限公司 触控结构、oled触控显示面板及制作方法
CN115036271A (zh) * 2022-06-21 2022-09-09 昆山龙腾光电股份有限公司 金属氧化物半导体薄膜晶体管阵列基板及其制作方法、显示装置
CN115036271B (zh) * 2022-06-21 2024-04-30 昆山龙腾光电股份有限公司 金属氧化物半导体薄膜晶体管阵列基板及其制作方法、显示装置

Also Published As

Publication number Publication date
US11335756B2 (en) 2022-05-17
CN111192884A (zh) 2020-05-22
US20210408192A1 (en) 2021-12-30

Similar Documents

Publication Publication Date Title
WO2021164075A1 (zh) Oled 显示装置及 tft 阵列基板的制备方法
US10553727B2 (en) Thin film transistor, method of manufacturing the same, and organic light emitting display device including the same
TWI683164B (zh) 顯示背板及其製作方法、顯示面板和顯示裝置
US11489029B2 (en) Transparent display substrate including capacitor overlapping driving and switching TFTs, and manufacturing method therefor
CN109326624B (zh) 像素电路、其制造方法及显示装置
US9082792B2 (en) Complementary metal oxide semiconductor transistor and fabricating method thereof
US9960188B2 (en) Thin film transistor, array substrate, and fabrication method there of, and display apparatus
KR20150073611A (ko) 유기발광다이오드 표시장치 및 그 제조방법
WO2015051646A1 (zh) 有源矩阵有机电致发光显示器件、显示装置及其制作方法
WO2018049744A1 (zh) Amoled像素驱动电路的制作方法
US20210366943A1 (en) Manufacturing method of thin film transistor substrate and thin film transistor substrate
WO2020220423A1 (zh) 显示面板及制作方法
WO2023044867A1 (zh) 一种显示面板及电子显示设备
WO2020215602A1 (zh) Oled显示面板的制备方法及oled显示面板
CN109728001A (zh) 一种阵列基板及其制备方法、显示面板
US11678530B2 (en) Display substrate and preparation method thereof, and display apparatus
US10879329B2 (en) Semiconductor device, semiconductor substrate, luminescent unit, and display unit
WO2018023955A1 (zh) Oled显示装置的阵列基板及其制造方法
CN114335015A (zh) 显示装置及显示装置的制备方法
TW201503374A (zh) 氧化物半導體薄膜電晶體
WO2020037850A1 (zh) 阵列基板及其制造方法、显示面板
CN210403734U (zh) 一种显示基板、显示装置
KR20170078394A (ko) 표시장치용 어레이기판 및 그 제조방법
KR20160084546A (ko) 유기 발광 표시 장치 및 그 제조 방법
WO2023197363A1 (zh) 阵列基板及其制作方法、显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20919600

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20919600

Country of ref document: EP

Kind code of ref document: A1