WO2023044867A1 - 一种显示面板及电子显示设备 - Google Patents

一种显示面板及电子显示设备 Download PDF

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Publication number
WO2023044867A1
WO2023044867A1 PCT/CN2021/120760 CN2021120760W WO2023044867A1 WO 2023044867 A1 WO2023044867 A1 WO 2023044867A1 CN 2021120760 W CN2021120760 W CN 2021120760W WO 2023044867 A1 WO2023044867 A1 WO 2023044867A1
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Prior art keywords
layer
source
drain
substrate
film transistor
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PCT/CN2021/120760
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English (en)
French (fr)
Inventor
卢马才
刘念
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Tcl华星光电技术有限公司
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Priority to US17/607,446 priority Critical patent/US20240030223A1/en
Priority to JP2021559744A priority patent/JP2023547741A/ja
Publication of WO2023044867A1 publication Critical patent/WO2023044867A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and an electronic display device.
  • OLED full name in English: Organic Light-Emitting Diode
  • Chinese organic light-emitting display device
  • Micro LED Choinese: Micron Light Emitting Diode
  • mini LED Choinese: Submillimeter Light Emitting Diode
  • TFT Thin Film Transistor
  • the top-gate self-aligned oxide semiconductor thin film transistor has characteristics such as high mobility, small parasitic capacitance and low leakage current, and is more suitable as a current-driven display circuit.
  • AM micro LEDs and AM mini LEDs also require high weather resistance driving substrates. Since the top of the channel of the top-gate thin film transistor has a gate insulating layer (GI) and a gate layer as a protective layer, its weather resistance is better than that of the back channel etching structure (English full name: back channel etch, referred to as BCE), etch barrier layer structure (English full name: etch stop layer, referred to as ESL).
  • GI gate insulating layer
  • BCE back channel etch
  • ESL etch barrier layer structure
  • the top surface of the gate layer is not covered by a metal film layer, which causes water vapor to permeate and affect the characteristics of the TFT device during its operation, resulting in an unoptimized weather resistance.
  • the object of the present invention is to provide a display panel and an electronic display device, which can solve the problems existing in the existing top-gate thin film transistors such as water vapor penetration affecting the weather resistance of the TFT.
  • the present invention provides a display panel, which includes a substrate and a plurality of pixel units arranged in an array; each of the pixel units includes: a buffer layer disposed on the substrate; a driving thin film transistor, disposed on the surface of the buffer layer away from the substrate; and a switching thin film transistor, disposed on the same layer as the driving thin film transistor, and electrically connected to the driving thin film transistor;
  • the driving thin film transistor includes: a first An active layer disposed on the surface of the buffer layer away from the substrate; a first gate insulating layer disposed on the surface of the first active layer far away from the substrate; A gate layer disposed on the surface of the first gate insulating layer away from the substrate; an interlayer insulating layer covering the surface of the first gate layer away from the substrate , and extend to cover the surface of the buffer layer on the side away from the substrate; and the first source-drain layer is disposed on the surface of the interlayer insulating layer on the side away from the substrate; the first A source-drain layer is disposed
  • the projection of the first source on the substrate has a first side close to the first drain; the projection of the first gate layer on the substrate has a first side close to the first drain.
  • the second side of the drain; the projection of the first drain on the substrate has a third side close to the first source; the first side, the second side and the The third sides are parallel to each other, and the first side is located between the second side and the third side.
  • the distance between the first side and the second side ranges from 0.5 ⁇ m to 10 ⁇ m.
  • the switching thin film transistor includes: a second active layer arranged on the same layer as the first active layer and arranged at intervals from the first active layer; a second gate insulating layer arranged on the same layer as the first active layer; The first gate insulating layer is arranged in the same layer, and is arranged at intervals from the first gate insulating layer; The second gate layer is disposed on the same layer as the first gate layer and is spaced apart from the first gate layer; and wherein the interlayer insulating layer extends to cover the second gate layer away from On the surface of one side of the substrate; the second source and drain layer is arranged on the same layer as the first source and drain layer, and is arranged at intervals from the first source and drain layer; the second source and drain layer The layer includes a second source and a second drain spaced apart from each other.
  • each of the pixel units further includes: a scanning wiring unit, which is arranged on the same layer as the second source-drain layer, and is arranged at intervals from the second source and the second drain, And electrically connected to the second gate layer, and corresponding to the second gate layer.
  • the projection of the scan line unit on the substrate has a fourth side close to the second drain; the projection of the second gate layer on the substrate has a fourth side close to the second drain.
  • the fifth side of the drain; the projection of the second drain on the substrate has a sixth side close to the second source; the fourth side, the fifth side and the The sixth sides are parallel to each other, and the fourth side is located between the fifth side and the sixth side.
  • the distance between the fourth side and the fifth side is in the range of 0.5 ⁇ m-10 ⁇ m.
  • each of the pixel units also includes: a high-voltage access source, disposed between the substrate and the buffer layer, and electrically connected to the driving thin film transistor; a low-voltage access source, connected to the high-voltage
  • the access source is arranged on the same layer as the high voltage access source, and is electrically connected to the driving thin film transistor; and the data wiring unit is arranged on the same layer as the high voltage access source, and is connected to the high voltage access source.
  • the access sources are arranged at intervals and electrically connected to the switching thin film transistors.
  • each of the pixel units also includes a first capacitor and a sensing thin film transistor; wherein, the first gate layer is electrically connected to the second drain, and is electrically connected to the first capacitor, so The first source is electrically connected to the low-voltage access source, and the first drain is electrically connected to the high-voltage access source; wherein, the second gate layer is electrically connected to the scanning wiring unit, The second source is electrically connected to the data wiring unit, the second drain is electrically connected to the first capacitor; the sensing thin film transistor includes a third source, and the third source is electrically connected to the the first capacitor.
  • the present invention provides an electronic display device, including the display panel described in the present invention.
  • the first source of the driving thin film transistor is extended and covered on the first gate layer, and the first source is used to block water vapor, prevent water vapor from invading and reduce the weather resistance of the driving thin film transistor, improve the service life of the driving thin film transistor, and prevent The degradation of the driving thin film transistor during use leads to a decrease in display quality or failure, and improves the display stability of the display panel.
  • the first source electrode is used as the top light-shielding layer to prevent light from entering the first active layer.
  • the scanning wiring unit is arranged on the second gate layer of the switching thin film transistor, which increases the distance between the scanning wiring unit and the data wiring unit, and prevents short circuit between the scanning wiring unit and the data wiring unit, Reduce the capacitance generated by the coupling between the scan line unit and the data line unit.
  • the scanning line unit is used to cover the second gate layer to prevent moisture intrusion and improve the stability of the switching thin film transistor.
  • FIG. 1 is a schematic plan view of a display panel of the present invention
  • FIG. 2 is a schematic structural view of a pixel unit of a display panel of the present invention.
  • FIG. 3 is a partial plan view of a pixel unit of a display panel of the present invention.
  • FIG. 4 is a schematic circuit diagram of a pixel unit of a display panel of the present invention.
  • Fig. 5 is a schematic structural diagram of forming a first light-shielding layer, a high-voltage access source, a low-voltage access source, a data routing unit, and a buffer layer on a substrate;
  • Fig. 6 is a schematic structural diagram of forming a first active layer and a second active layer on the basis of Fig. 5;
  • Fig. 7 is a schematic structural diagram of forming a first gate insulating layer, a second gate insulating layer, a first gate layer and a second gate layer on the basis of Fig. 6;
  • FIG. 8 is a schematic structural diagram of forming an interlayer insulating layer on the basis of FIG. 7;
  • FIG. 9 is a schematic structural diagram of forming a first source-drain layer, a second source-drain layer, and a scanning line unit on the basis of FIG. 8;
  • Fig. 10 is a schematic structural view of forming a passivation layer on the basis of Fig. 9;
  • Fig. 11 is a schematic structural diagram of forming a first electrode and a second electrode on the basis of Fig. 10;
  • Fig. 12 is a schematic diagram of the mobility change of the display panel of the present invention under a high-temperature and high-humidity storage test
  • FIG. 13 is a schematic diagram of threshold voltage changes of the display panel of the present invention under high temperature and high humidity storage test.
  • Substrate 2. The first shading layer;
  • the first gate insulating layer 8. The first gate layer;
  • the first source and drain layer 10. Interlayer insulating layer;
  • Scanning wiring unit 18. The first electrode;
  • the present invention provides an electronic display device, which includes a display panel 100 .
  • the electronic display device includes mobile phone, computer, MP3, MP4, tablet computer, TV or digital camera and so on.
  • the display panel 100 includes a substrate 1 and a plurality of pixel units 101 arranged in an array on the substrate 1 .
  • the material of the substrate 1 includes polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate and the like. Therefore, the substrate 1 has better impact resistance and can effectively protect the display panel 100 .
  • each pixel unit 101 includes: a first light shielding layer 2 , a high voltage access source 3 , a low voltage access source 4 , a buffer layer 5 , a driving thin film transistor 1011 and a switching thin film transistor 1012 .
  • the first light-shielding layer 2 is disposed on the surface of one side of the substrate 1 , and the first light-shielding layer 2 is mainly used to prevent light from entering the first active layer 6 of the driving thin film transistor 1011 .
  • the material of the first light-shielding layer 2 can be Mo or the combined structure of Mo and Al or the combined structure of Mo and Cu or the combined structure of Mo, Cu and IZO or the combined structure of IZO, Cu and IZO or Mo, Cu and ITO The combined structure of Ni, Cu and Ni or the combined structure of MoTiNi, Cu and MoTiNi or the combined structure of NiCr, Cu and NiCr or CuNb.
  • the high-voltage access source 3 is arranged on the surface of one side of the first substrate 1, and is arranged on the same layer as the first light-shielding layer 2, and is spaced apart from the first light-shielding layer 2, and is electrically connected to the first light-shielding layer 2. connected to the driving thin film transistor 1011.
  • the material of the high-voltage access source 3 can be Mo or a combined structure of Mo and Al or a combined structure of Mo and Cu or a combined structure of Mo, Cu and IZO or a combined structure of IZO, Cu and IZO or a combination of Mo, Cu and ITO Structure or combined structure of Ni, Cu and Ni or combined structure of MoTiNi, Cu and MoTiNi or combined structure of NiCr, Cu and NiCr or CuNb, etc.
  • the low-voltage access source 4 is arranged on the surface of one side of the first substrate 1, and is arranged on the same layer as the high-voltage access source 3, and is connected to the first light-shielding layer 2 and the high-voltage access source.
  • the sources 3 are arranged at intervals and electrically connected to the driving thin film transistor 1011 . That is, the first light-shielding layer 2 , the high-voltage access source 3 and the low-voltage access source 4 are arranged on the same layer, and the three are arranged at intervals from each other.
  • the material of the low-voltage access source 4 can be Mo or a combined structure of Mo and Al or a combined structure of Mo and Cu or a combined structure of Mo, Cu and IZO or a combined structure of IZO, Cu and IZO or a combination of Mo, Cu and ITO Structure or combined structure of Ni, Cu and Ni or combined structure of MoTiNi, Cu and MoTiNi or combined structure of NiCr, Cu and NiCr or CuNb, etc.
  • the buffer layer 5 covers the first light-shielding layer 2, the high-voltage access source 3 and the low-voltage access source 4, and extends to cover the first light-shielding layer 2, the high-voltage access source 3 and the low-voltage access source 4 on the substrate 1 between the three.
  • the buffer layer 5 mainly serves as a buffer, and its material can be SiOx, SiNx, SiNOx, or a combined structure of SiNx and SiOx.
  • the driving thin film transistor 1011 is disposed on the surface of the buffer layer 5 away from the substrate 1 .
  • the driving thin film transistor includes: a first active layer 6 , a first gate insulating layer 7 , a first gate layer 8 , an interlayer insulating layer 10 and a first source-drain layer 9 .
  • the first active layer 6 is disposed on the surface of the buffer layer 5 away from the substrate 1 .
  • the first active layer 6 can be an oxide semiconductor or other types of semiconductors, such as IGZO, IGTO, IGO, IZO and AIZO.
  • the first gate insulating layer 7 is disposed on the surface of the first active layer 6 away from the substrate 1 .
  • the first gate insulating layer 7 is mainly used to prevent a short circuit between the first active layer 6 and the first gate layer 8 .
  • the material of the first gate insulating layer 7 can be SiOx or SiNx or Al2O3 or a combined structure of SiNx and SiOx or a combined structure of SiOx, SiNx and SiOx, etc.
  • the first gate layer 8 is disposed on the surface of the first gate insulating layer 7 away from the substrate 1 .
  • the material of the first gate layer 8 can be a combination structure of Mo or Mo and Al or a combination structure of Mo and Cu or a combination structure of Mo, Cu and IZO or a combination structure of IZO, Cu and IZO or a combination structure of Mo, Cu and ITO.
  • the interlayer insulating layer 10 covers the surface of the first gate layer 8 away from the substrate 1 , and extends to cover the surface of the buffer layer 5 away from the substrate 1 .
  • the material of the interlayer insulating layer 10 can be SiOx, SiNx, or SiNOx, etc.
  • the first source-drain layer 9 is disposed on the surface of the interlayer insulating layer 10 away from the substrate 1 .
  • the material of the first source and drain layer 9 can be Mo or a combined structure of Mo and Al or a combined structure of Mo and Cu or a combined structure of Mo, Cu and IZO or a combined structure of IZO, Cu and IZO or Mo, Cu And the combined structure of ITO or the combined structure of Ni, Cu and Ni or the combined structure of MoTiNi, Cu and MoTiNi or the combined structure of NiCr, Cu and NiCr or CuNb, etc.
  • the first source-drain layer 9 includes a first source 91 and a first drain 92 spaced apart from each other.
  • the first source 91 extends toward the first drain and covers the first gate layer 8 .
  • the projection of the first source 91 on the substrate 1 has a first side 911 close to the first drain 92;
  • the projection on the substrate 1 has a second side 81 close to the first drain 92;
  • the projection of the first drain 92 on the substrate 1 has a third side close to the first source 91 Side 921;
  • the first side 911, the second side 81 and the third side 921 are parallel to each other, and the first side 911 is located between the second side 81 and the third side Between the sides 921 .
  • the distance L1 between the first side 911 and the second side 81 ranges from 0.5 ⁇ m to 10 ⁇ m.
  • the L1 is preferably 2 ⁇ m.
  • the first source 91 is used as a top light-shielding layer to prevent light from entering the first active layer 6 .
  • the switching thin film transistor 1012 is disposed on the same layer as the driving thin film transistor 1011 and is electrically connected to the driving thin film transistor 1011 .
  • the switching thin film transistor 1012 includes: a second active layer 13 , a second gate insulating layer 14 , a second gate layer 15 , and a second source-drain layer 16 .
  • the second active layer 13 is disposed on the surface of the buffer layer 5 away from the substrate 1, and is disposed on the same layer as the first active layer 6, and is connected to the first active layer 6 interval settings.
  • the second active layer 13 can be an oxide semiconductor or other types of semiconductors, such as IGZO, IGTO, IGO, IZO and AIZO.
  • the second gate insulating layer 14 is disposed on the surface of the second active layer 13 away from the substrate 1 , and is disposed on the same layer as the first gate insulating layer 7 , and is disposed on the same layer as the first gate insulating layer 7 .
  • the first gate insulating layers 7 are arranged at intervals.
  • the second gate insulating layer 14 is mainly used to prevent the short circuit between the second active layer 13 and the second gate layer 15 .
  • the material of the second gate insulating layer 14 can be SiOx or SiNx or Al2O3 or a combined structure of SiNx and SiOx or a combined structure of SiOx, SiNx and SiOx, etc.
  • the second gate layer 15 is disposed on the surface of the second gate insulating layer 14 away from the substrate 1, and is disposed on the same layer as the first gate layer 8, and is disposed on the same layer as the first gate layer 8.
  • a gate layer 8 is spaced apart from each other.
  • the material of the second gate layer 15 can be a combination structure of Mo or Mo and Al or a combination structure of Mo and Cu or a combination structure of Mo, Cu and IZO or a combination structure of IZO, Cu and IZO or a combination structure of Mo, Cu and ITO.
  • the interlayer insulating layer 10 extends to cover the surface of the second gate layer 15 on a side away from the substrate 1 .
  • the second source-drain layer 16 is disposed on the surface of the interlayer insulating layer 10 away from the substrate 1, and is disposed on the same layer as the first source-drain layer 9, and is disposed on the same layer as the first A source-drain layer 9 is spaced apart from each other.
  • the material of the second source and drain layer 16 can be Mo or a combined structure of Mo and Al or a combined structure of Mo and Cu or a combined structure of Mo, Cu and IZO or a combined structure of IZO, Cu and IZO or Mo, Cu And the combined structure of ITO or the combined structure of Ni, Cu and Ni or the combined structure of MoTiNi, Cu and MoTiNi or the combined structure of NiCr, Cu and NiCr or CuNb, etc.
  • the second source and drain layer 16 includes a second source 161 and a second drain 162 spaced apart from each other.
  • each pixel unit further includes: a passivation layer 11 , a data wiring unit 12 and a scanning wiring unit 17 .
  • the passivation layer 11 covers the first source-drain layer 9 and extends to cover the interlayer insulating layer 10 .
  • the material of the passivation layer 11 can be SiOx or SiNx or SiNOx or a combined structure of SiNx and SiOx, etc.
  • the data routing unit 12 is arranged on the same layer as the high-voltage access source 3 , and is spaced apart from the high-voltage access source 3 , and is electrically connected to the switching thin film transistor 1012 .
  • the material of the data wiring unit 12 can be Mo or a combined structure of Mo and Al or a combined structure of Mo and Cu or a combined structure of Mo, Cu and IZO or a combined structure of IZO, Cu and IZO or Mo, Cu and ITO
  • the scanning wiring unit 17 is arranged on the same layer as the second source-drain layer 16, and is arranged at intervals from the second source electrode 161 and the second drain electrode 162, and is electrically connected to the second
  • the gate layer 15 is arranged corresponding to the second gate layer 15 .
  • the projection of the scan line unit 17 on the substrate 1 has a fourth side close to the second drain 162; the projection of the second gate layer 15 on the substrate 1 has a fourth side close to the second drain 162; The fifth side of the second drain 162; the projection of the second drain 162 on the substrate 1 has a sixth side close to the second source 161; the fourth side, The fifth side and the sixth side are parallel to each other, and the fourth side is located between the fifth side and the sixth side.
  • the distance L2 between the fourth side and the fifth side is in a range of 0.5 ⁇ m-10 ⁇ m. In this embodiment, the L2 is 2 ⁇ m.
  • the scanning wiring unit 17 is arranged on the second gate layer 15 of the switching thin film transistor 1012, which increases the distance between the scanning wiring unit 17 and the data wiring unit 12, and prevents the scanning wiring unit 17 from being connected to the data wiring unit.
  • the line units 12 are short-circuited to reduce the capacitance generated by the coupling between the scanning line unit 17 and the data line unit 12 .
  • the scanning line unit 17 is used to cover the second gate layer 15 to prevent moisture intrusion and improve the stability of the switching thin film transistor 1012 .
  • each pixel unit 101 further includes: a first electrode 18 , a second electrode 19 and a light emitting diode 1013 .
  • the first electrode 18 is electrically connected to the low-voltage access source 4; the second electrode 19 is electrically connected to the first source 91; one end of the light emitting diode 1013 is electrically connected to the first electrode 18, and the light emitting diode 1013 The other end is electrically connected to the second electrode 19.
  • each of the pixel units 101 further includes a first capacitor C1.
  • the first capacitor C1 is formed by the coupling between the first source 91 and the first gate layer 8 .
  • the first gate layer 8 of the driving thin film transistor 1011 ie T1 in FIG. 4
  • the second drain 162 is electrically connected to the first capacitor
  • the left end of C1; the first source 91 of the driving thin film transistor 1011 (that is, T1 in FIG. 4 ) is electrically connected to the low-voltage access source 4 (that is, Vss in FIG.
  • the first drain 92 of T1 in 4) is electrically connected to the high voltage access source 3 (ie Vdd in FIG. 4 ).
  • the second gate layer 15 of the switching thin film transistor 1012 (ie T2 in Figure 4) is electrically connected to the scanning line unit 17 (ie Vgate in Figure 4), and the switching thin film transistor (that is, T2 in FIG. 4 ) is electrically connected to the data wiring unit (that is, Vdata in FIG. 4 ), and switches the second drain of the thin film transistor (that is, T2 in FIG. 4 ).
  • the pole 162 is electrically connected to the left end of the first capacitor C1.
  • each pixel unit 101 further includes a sensing thin film transistor T3.
  • the sensing TFT T3 includes a third source.
  • the third source of the sensing TFT T3 is electrically connected to the right end of the first capacitor C1.
  • this embodiment also provides a method for manufacturing the display panel described in this embodiment, which specifically includes the following steps.
  • a first light-shielding layer 2 , a high-voltage access source 3 , a low-voltage access source 4 and a data wiring unit 12 are prepared on the substrate 1 .
  • the first light-shielding layer 2, the high-voltage access source 3, the low-voltage access source 4, and the data wiring unit 12 can be formed synchronously, thereby improving production efficiency and saving production costs.
  • a buffer layer 5 is prepared on the first light shielding layer 2 , the high voltage access source 3 , the low voltage access source 4 and the data wiring unit 12 .
  • a first active layer 6 and a second active layer 13 are formed on the surface of the buffer layer 5 away from the substrate 1 .
  • the first active layer 6 and the second active layer 13 can be formed synchronously, thereby improving production efficiency and saving production cost.
  • a first gate insulating layer 7 is formed on the surface of the first active layer 6 away from the substrate 1, and a first gate insulating layer 7 is formed on the surface of the second active layer 13 away from the substrate 1.
  • a second gate insulating layer 14 is formed on one surface. Wherein, the first gate insulating layer 7 and the second gate insulating layer 14 can be formed synchronously, thereby improving production efficiency and saving production cost.
  • a first gate layer 8 is formed on the surface of the first gate insulating layer 7 away from the substrate 1, and a first gate layer 8 is formed on the surface of the second gate insulating layer 14 away from the substrate 1. the second gate layer 15 . Wherein, the first gate layer 8 and the second gate layer 15 can be formed synchronously, thereby improving production efficiency and saving production cost.
  • an interlayer insulating layer 10 is formed on the surfaces of the first gate layer 8 , the second gate layer 15 and the buffer layer 5 away from the substrate 1 .
  • a first source-drain layer 9 , a second source-drain layer 16 , and a scanning line unit 17 are formed on the surface of the interlayer insulating layer 10 away from the substrate 1 .
  • the first source-drain layer 9 , the second source-drain layer 16 , and the scanning line unit 17 can be formed synchronously, thereby improving production efficiency and saving production cost.
  • a passivation layer 11 is formed on the surface of the first source-drain layer 9 , the second source-drain layer 16 , and the scanning wiring unit 17 away from the substrate.
  • a first electrode 18 and a second electrode 19 are formed on the surface of the passivation layer 11 away from the substrate 1 .
  • one end of the LED 1013 is electrically connected to the first electrode 18
  • the other end of the LED 1013 is electrically connected to the second electrode 19 .

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Abstract

一种显示面板（100）及电子显示设备。通过将驱动薄膜晶体管（1011）的第一源极（91）延伸覆盖于第一栅极层（8）上，利用第一源极（91）阻挡水汽，防止水汽入侵降低驱动薄膜晶体管（1011）的耐候性，提升驱动薄膜晶体管（1011）的使用寿命，防止驱动薄膜晶体管（1011）使用过程中出现衰退导致显示质量下降或失效，提升显示面板（100）的显示稳定性。

Description

一种显示面板及电子显示设备 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及电子显示设备。
 背景技术
目前，OLED（英文全称：Organic Light-Emitting Diode，中文：有机发光显示装置）、Micro LED（中文：微米发光二极管）及mini LED（中文：次毫米发光二极管）作为电流驱动显示，其驱动薄膜晶体管（英文全称：Thin Film Transistor，简称TFT）需要较大的电流通过能力，较好的器件稳定性、面内Vth（阈值电压）均匀性、较低的漏电流。
顶栅自对准氧化物半导体薄膜晶体管具有较高的迁移率，较小的寄生电容和较低的漏电流等特性，比较适合作为电流驱动显示电路。为防止使用过程中TFT出现衰退导致显示质量下降或失效，AM micro LED及AM mini LED还需要高的耐候性驱动基板。由于顶栅型薄膜晶体管的沟道顶部有栅极绝缘层（GI）及栅极层作为保护层，其耐候性优于背通道刻蚀结构（英文全称：back channel etch，简称BCE）、刻蚀阻挡层结构（英文全称：etch stop layer，简称ESL）。
 技术问题
目前的顶栅型薄膜晶体管中，栅极层顶面无金属膜层覆盖，导致其工作过程中，水气渗透进而影响TFT器件特性，导致其耐候性无法达到最佳。
 技术解决方案
本发明的目的是提供一种显示面板及电子显示设备，其能够解决现有顶栅型薄膜晶体管中存在的水气渗透影响TFT耐候性等问题。
为了解决上述问题，本发明提供了一种显示面板，其包括基板及多个阵列排布的像素单元；每一所述像素单元均包括：缓冲层，设置于所述基板上；驱动薄膜晶体管，设置于所述缓冲层远离所述基板的一侧的表面上；以及切换薄膜晶体管，与所述驱动薄膜晶体管同层设置，且电连接至所述驱动薄膜晶体管；所述驱动薄膜晶体管包括：第一有源层，设置于所述缓冲层远离所述基板的一侧的表面上；第一栅极绝缘层，设置于所述第一有源层远离所述基板的一侧的表面上；第一栅极层，设置于所述第一栅极绝缘层远离所述基板的一侧的表面上；层间绝缘层，覆盖于所述第一栅极层远离所述基板的一侧的表面上，且延伸覆盖于所述缓冲层远离所述基板的一侧的表面上；以及第一源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上；所述第一源漏极层包括相互间隔的第一源极和第一漏极，所述第一源极朝向所述第一漏极延伸并覆盖于所述第一栅极层上。
进一步的，所述第一源极在所述基板上的投影具有靠近所述第一漏极的第一侧边；所述第一栅极层在所述基板上的投影具有靠近所述第一漏极的第二侧边；所述第一漏极在所述基板上的投影具有靠近所述第一源极的第三侧边；所述第一侧边、所述第二侧边及所述第三侧边相互平行，且所述第一侧边位于所述第二侧边与所述第三侧边之间。
进一步的，所述第一侧边与所述第二侧边之间的间距的范围为0.5μm-10μm。
进一步的，所述切换薄膜晶体管包括：第二有源层，与所述第一有源层同层设置，且与所述第一有源层间隔设置；第二栅极绝缘层，与所述第一栅极绝缘层同层设置，且与所述第一栅极绝缘层间隔设置； 第二栅极层，与所述第一栅极层同层设置，且与所述第一栅极层间隔设置；以及其中，所述层间绝缘层延伸覆盖于所述第二栅极层远离所述基板的一侧的表面上；第二源漏极层，与所述第一源漏极层同层设置，且与所述第一源漏极层间隔设置；所述第二源漏极层包括相互间隔的第二源极和第二漏极。
进一步的，每一所述像素单元均还包括：扫描走线单元，与所述第二源漏极层同层设置，且与所述第二源极和所述第二漏极相互间隔设置，且电连接至所述第二栅极层，且与所述第二栅极层对应设置。
进一步的，所述扫描走线单元在所述基板上的投影具有靠近所述第二漏极的第四侧边；所述第二栅极层在所述基板上的投影具有靠近所述第二漏极的第五侧边；所述第二漏极在所述基板上的投影具有靠近所述第二源极的第六侧边；所述第四侧边、所述第五侧边及所述第六侧边相互平行，且所述第四侧边位于所述第五侧边与所述第六侧边之间。
进一步的，所述第四侧边与所述第五侧边之间的间距的范围为0.5μm-10μm。
进一步的，每一所述像素单元均还包括：高压接入源，设置于所述基板与所述缓冲层之间，且电连接至所述驱动薄膜晶体管；低压接入源，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述驱动薄膜晶体管；以及数据走线单元，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述切换薄膜晶体管。
进一步的，每一所述像素单元均还包括第一电容及感应薄膜晶体管；其中，所述第一栅极层电连接至所述第二漏极，且电连接至所述第一电容，所述第一源极电连接至所述低压接入源，所述第一漏极电连接至所述高压接入源；其中，所述第二栅极层电连接至所述扫描走线单元，所述第二源极电连接至所述数据走线单元，所述第二漏极电连接至第一电容；所述感应薄膜晶体管包括第三源极，所述第三源极电连接至所述第一电容。
为了解决上述问题，本发明提供了一种电子显示设备，包括本发明所述的显示面板。
 有益效果
本发明通过将驱动薄膜晶体管的第一源极延伸覆盖于第一栅极层上，利用第一源极阻挡水汽，防止水汽入侵降低驱动薄膜晶体管的耐候性，提升驱动薄膜晶体管的使用寿命，防止驱动薄膜晶体管使用过程中出现衰退导致显示质量下降或失效，提升显示面板的显示稳定性。利用第一源极作为顶部遮光层，防止光线进入第一有源层。将扫描走线单元设置于所述切换薄膜晶体管的第二栅极层上，增加了扫描走线单元与数据走线单元之间的间距，防止扫描走线单元与数据走线单元之间短路、降低扫描走线单元与数据走线单元之间耦合产生的电容。利用扫描走线单元覆盖第二栅极层，防止水汽入侵，提升切换薄膜晶体管的稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明的显示面板的平面示意图；
图2是本发明的显示面板的像素单元的结构示意图；
图3是本发明的显示面板的像素单元的局部平面示意图；
图4是本发明的显示面板的像素单元的电路示意图；
图5是在基板上形成第一遮光层、高压接入源、低压接入源、数据走线单元、缓冲层的结构示意图；
图6是在图5的基础上形成第一有源层和第二有源层的结构示意图；
图7是在图6的基础上形成第一栅极绝缘层、第二栅极绝缘层、第一栅极层和第二栅极层的结构示意图；
图8是在图7的基础上形成层间绝缘层的结构示意图；
图9是在图8的基础上形成第一源漏极层、第二源漏极层、扫描走线单元的结构示意图；
图10是在图9的基础上形成钝化层的结构示意图；
图11是在图10的基础上形成第一电极和第二电极的结构示意图；
图12是本发明的显示面板在高温高湿储存测试下的迁移率变化示意图；
图13是本发明的显示面板在高温高湿储存测试下的阈值电压变化示意图。
附图标记说明：
100、显示面板；                     101、像素单元；
1011、驱动薄膜晶体管；              1012、切换薄膜晶体管；
1013、发光二极管；
1、基板；                           2、第一遮光层；
3、高压接入源；                     4、低压接入源；
5、缓冲层；                         6、第一有源层；
7、第一栅极绝缘层；                 8、第一栅极层；
9、第一源漏极层；                   10、层间绝缘层；
11、钝化层；                        12、数据走线单元；
13、第二有源层；                    14、第二栅极绝缘层；
15、第二栅极层；                    16、第二源漏极层；
17、扫描走线单元；                  18、第一电极；
19、第二电极；
91、第一源极；                      92、第一漏极；
161、第二源极；                     162、第二漏极；
911、第一侧边；                     81、第二侧边；
921、第三侧边。
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的，本发明并没有限定每个组件的尺寸和厚度。
本发明提供了一种电子显示设备，其包括显示面板100。所述电子显示设备包括手机、电脑、MP3、MP4、平板电脑、电视或数码相机等。
如图1所示，所述显示面板100包括基板1及多个阵列排布于所述基板1上的像素单元101。
其中，基板1的材质包括聚酰亚胺、聚碳酸酯、聚对苯二甲酸乙二醇酯以及聚萘二甲酸乙二醇酯等。由此基板1具有较好的抗冲击能力，可以有效保护显示面板100。
如图2所示，每一所述像素单元101均包括：第一遮光层2、高压接入源3、低压接入源4、缓冲层5、驱动薄膜晶体管1011及切换薄膜晶体管1012。
其中，第一遮光层2设置于所述基板1的一侧的表面上，所述第一遮光层2主要用于防止光线进入所述驱动薄膜晶体管1011的第一有源层6。其中，第一遮光层2的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，高压接入源3设置于所述第一基板1的一侧的表面上，且与所述第一遮光层2同层设置，且与所述第一遮光层2相互间隔设置，且电连接至所述驱动薄膜晶体管1011。高压接入源3的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，低压接入源4设置于所述第一基板1的一侧的表面上，且与所述高压接入源3同层设置，且与所述第一遮光层2及所述高压接入源3相互间隔设置，且电连接至所述驱动薄膜晶体管1011。即，所述第一遮光层2、高压接入源3及低压接入源4三者同层设置，且三者相互间隔设置。低压接入源4的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，缓冲层5覆盖于所述第一遮光层2、高压接入源3及低压接入源4上，且延伸覆盖于所述第一遮光层2、高压接入源3及低压接入源4三者间的所述基板1上。缓冲层5主要是起缓冲作用，其材质可为SiOx或SiNx或SiNOx或SiNx与SiOx的组合结构等。
其中，所述驱动薄膜晶体管1011设置于所述缓冲层5远离所述基板1的一侧的表面上。所述驱动薄膜晶体管包括：第一有源层6、第一栅极绝缘层7、第一栅极层8、层间绝缘层10以及第一源漏极层9。
其中，第一有源层6设置于所述缓冲层5远离所述基板1的一侧的表面上。所述第一有源层6可以为氧化物半导体或其他类型半导体，如IGZO、IGTO、IGO、IZO及AIZO等。
其中，第一栅极绝缘层7设置于所述第一有源层6远离所述基板1的一侧的表面上。所述第一栅极绝缘层7主要用于防止所述第一有源层6与所述第一栅极层8之间接触发生短路现象。第一栅极绝缘层7的材质可为SiOx或SiNx或Al2O3或SiNx及SiOx的组合结构或SiOx、SiNx及SiOx的组合结构等。
其中，第一栅极层8设置于所述第一栅极绝缘层7远离所述基板1的一侧的表面上。第一栅极层8的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，层间绝缘层10覆盖于所述第一栅极层8远离所述基板1的一侧的表面上，且延伸覆盖至所述缓冲层5远离所述基板1的一侧的表面上。其中，层间绝缘层10的材质可为SiOx或SiNx或SiNOx等。
其中，第一源漏极层9设置于所述层间绝缘层10远离所述基板1的一侧的表面上。所述第一源漏极层9的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
如图2所示，所述第一源漏极层9包括相互间隔的第一源极91和第一漏极92。
如图2、图3所示，所述第一源极91朝向所述第一漏极延伸并覆盖于所述第一栅极层8上。
如图2、图3所示，所述第一源极91在所述基板1上的投影具有靠近所述第一漏极92的第一侧边911；所述第一栅极层8在所述基板1上的投影具有靠近所述第一漏极92的第二侧边81；所述第一漏极92在所述基板1上的投影具有靠近所述第一源极91的第三侧边921；所述第一侧边911、所述第二侧边81及所述第三侧边921相互平行，且所述第一侧边911位于所述第二侧边81与所述第三侧边921之间。其中，所述第一侧边911与所述第二侧边81之间的间距L1的范围为0.5μm-10μm。
如图12、图13所示，当L1=2μm时，迁移率与阈值电压的变化曲线图趋于平稳，所以本实施例中，所述L1优选为2μm。
利用第一源极91阻挡水汽，防止水汽入侵降低驱动薄膜晶体管1011的耐候性，提升驱动薄膜晶体管1011的使用寿命，防止驱动薄膜晶体管1011使用过程中出现衰退导致显示质量下降或失效，提升显示面板100的显示稳定性。利用第一源极91作为顶部遮光层，防止光线进入第一有源层6。
如图2所示，所述切换薄膜晶体管1012与所述驱动薄膜晶体管1011同层设置，且电连接至所述驱动薄膜晶体管1011。所述切换薄膜晶体管1012包括：第二有源层13、第二栅极绝缘层14、第二栅极层15、及第二源漏极层16 。其中，第二有源层13设置于所述缓冲层5远离所述基板1的一侧的表面上，且与所述第一有源层6同层设置，且与所述第一有源层6间隔设置。所述第二有源层13可以为氧化物半导体或其他类型半导体，如IGZO、IGTO、IGO、IZO及AIZO等。
其中，第二栅极绝缘层14设置于所述第二有源层13远离所述基板1的一侧的表面上，且与所述第一栅极绝缘层7同层设置，且与所述第一栅极绝缘层7间隔设置。所述第二栅极绝缘层14主要用于防止所述第二有源层13与所述第二栅极层15之间接触发生短路现象。第二栅极绝缘层14的材质可为SiOx或SiNx或Al2O3或SiNx及SiOx的组合结构或SiOx、SiNx及SiOx的组合结构等。
其中，第二栅极层15设置于所述第二栅极绝缘层14远离所述基板1的一侧的表面上，且与所述第一栅极层8同层设置，且与所述第一栅极层8相互间隔设置。第二栅极层15的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，所述层间绝缘层10延伸覆盖于所述第二栅极层15远离所述基板1的一侧的表面上。
其中，第二源漏极层16设置于所述层间绝缘层10远离所述基板1的一侧的表面上，且与所述第一源漏极层9同层设置，且与所述第一源漏极层9相互间隔设置。所述第二源漏极层16的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
如图2所示，所述第二源漏极层16包括相互间隔的第二源极161和第二漏极162。
如图2所示，每一所述像素单元均还包括：钝化层11、数据走线单元12及扫描走线单元17。
其中，钝化层11覆盖于所述第一源漏极层9上，且延伸覆盖于所述层间绝缘层10上。所述钝化层11的材质可为SiOx或SiNx或SiNOx或SiNx与SiOx的组合结构等。
其中，数据走线单元12与高压接入源3同层设置，且与高压接入源3相互间隔设置，且电连接至所述切换薄膜晶体管1012。所述数据走线单元12的材质可为Mo或Mo和Al的组合结构或Mo和Cu的组合结构或Mo、Cu及IZO的组合结构或IZO、Cu及IZO的组合结构或Mo、Cu及ITO的组合结构或Ni、Cu及Ni的组合结构或MoTiNi、Cu及MoTiNi的组合结构或NiCr、Cu及NiCr的组合结构或CuNb等。
其中，扫描走线单元17与所述第二源漏极层16同层设置，且与所述第二源极161和所述第二漏极162相互间隔设置，且电连接至所述第二栅极层15，且与所述第二栅极层15对应设置。
其中，所述扫描走线单元17在所述基板1上的投影具有靠近所述第二漏极162的第四侧边；所述第二栅极层15在所述基板1上的投影具有靠近所述第二漏极162的第五侧边；所述第二漏极162在所述基板1上的投影具有靠近所述第二源极161的第六侧边；所述第四侧边、所述第五侧边及所述第六侧边相互平行，所述第四侧边位于所述第五侧边与所述第六侧边之间。其中，所述第四侧边与所述第五侧边之间的间距L2的范围为0.5μm-10μm。本实施例中，所述L2为2μm。将扫描走线单元17设置于所述切换薄膜晶体管1012的第二栅极层15上，增加了扫描走线单元17与数据走线单元12之间的间距，防止扫描走线单元17与数据走线单元12之间短路、降低扫描走线单元17与数据走线单元12之间耦合产生的电容。利用扫描走线单元17覆盖第二栅极层15，防止水汽入侵，提升切换薄膜晶体管1012的稳定性。
如图2所示，每一所述像素单元101均还包括：第一电极18、第二电极19以及发光二极管1013。
其中，第一电极18电连接至所述低压接入源4；第二电极19电连接至所述第一源极91；发光二极管1013的一端电连接至所述第一电极18，发光二极管1013的另一端电连接至所述第二电极19。
如图2、图4所示，所述每一所述像素单元101均还包括第一电容C1。所述第一电容C1由所述第一源极91与所述第一栅极层8耦合形成。如图2、图4所示，驱动薄膜晶体管1011（即图4中的T1）的所述第一栅极层8电连接至所述第二漏极162，且电连接至所述第一电容C1的左端；驱动薄膜晶体管1011（即图4中的T1）的所述第一源极91电连接至所述低压接入源4（即图4中的Vss），驱动薄膜晶体管1011（即图4中的T1）的所述第一漏极92电连接至所述高压接入源3（即图4中的Vdd）。
如图2、图4所示，切换薄膜晶体管1012（即图4中的T2）的第二栅极层15电连接至所述扫描走线单元17（即图4中的Vgate），切换薄膜晶体管（即图4中的T2）的所述第二源极161电连接所述数据走线单元（即图4中的Vdata），切换薄膜晶体管（即图4中的T2）的所述第二漏极162电连接第一电容C1的左端。
如图4所示，每一所述像素单元101均还包括感应薄膜晶体管T3。所述感应薄膜晶体管T3包括第三源极。所述感应薄膜晶体管T3的所述第三源极电连接至所述第一电容C1的右端。
如图5-图11所示，本实施例还提供了本实施例所述的显示面板的制备方法，具体包括以下步骤。
如图5所示，在所述基板1上制备第一遮光层2、高压接入源3、低压接入源4以及数据走线单元12。其中第一遮光层2、高压接入源3、低压接入源4以及数据走线单元12可以同步形成，由此可以提升生产效率，节约生产成本。然后在所述第一遮光层2、高压接入源3、低压接入源4以及数据走线单元12制备缓冲层5。
如图6所示，在所述缓冲层5远离所述基板1的一侧的表面上形成第一有源层6和第二有源层13。其中，第一有源层6和第二有源层13可以同步形成，由此可以提升生产效率，节约生产成本。
如图7所示，在所述第一有源层6远离所述基板1的一侧的表面上形成第一栅极绝缘层7，在所述第二有源层13远离所述基板1的一侧的表面上形成第二栅极绝缘层14。其中，第一栅极绝缘层7和第二栅极绝缘层14可以同步形成，由此可以提升生产效率，节约生产成本。然后在所述第一栅极绝缘层7远离基板1的一侧的表面上形成第一栅极层8，在所述第二栅极绝缘层14远离所述基板1的一侧的表面上形成第二栅极层15。其中，第一栅极层8和第二栅极层15可以同步形成，由此可以提升生产效率，节约生产成本。
如图8所示，在所述第一栅极层8、第二栅极层15及缓冲层5远离所述基板1的一侧的表面上形成层间绝缘层10。
如图9所示，在所述层间绝缘层10远离所述基板1的一侧的表面上形成第一源漏极层9、第二源漏极层16、扫描走线单元17。其中，第一源漏极层9、第二源漏极层16、扫描走线单元17可以同步形成，由此可以提升生产效率，节约生产成本。
如图10所示，在所述第一源漏极层9、第二源漏极层16、扫描走线单元17远离所述基板的一侧的表面上形成钝化层11。
如图11所示，在所述钝化层11远离所述基板1的一侧的表面上形成第一电极18和第二电极19。
如图2所示，将所述发光二极管1013的一端电连接至所述第一电极18，发光二极管1013的另一端电连接至所述第二电极19。
以上对本申请所提供的一种显示面板及电子显示设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种显示面板，包括基板及多个阵列排布的像素单元；每一所述像素单元均包括：
    缓冲层，设置于所述基板上；
    驱动薄膜晶体管，设置于所述缓冲层远离所述基板的一侧的表面上；以及
    切换薄膜晶体管，与所述驱动薄膜晶体管同层设置，且电连接至所述驱动薄膜晶体管；
    所述驱动薄膜晶体管包括：
    第一有源层，设置于所述缓冲层远离所述基板的一侧的表面上；
    第一栅极绝缘层，设置于所述第一有源层远离所述基板的一侧的表面上；
    第一栅极层，设置于所述第一栅极绝缘层远离所述基板的一侧的表面上；
    层间绝缘层，覆盖于所述第一栅极层远离所述基板的一侧的表面上，且延伸覆盖于所述缓冲层远离所述基板的一侧的表面上；以及
    第一源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上；
    所述第一源漏极层包括相互间隔的第一源极和第一漏极，所述第一源极朝向所述第一漏极延伸并覆盖于所述第一栅极层上。
  2. 根据权利要求1所述的显示面板，
    所述第一源极在所述基板上的投影具有靠近所述第一漏极的第一侧边；
    所述第一栅极层在所述基板上的投影具有靠近所述第一漏极的第二侧边；
    所述第一漏极在所述基板上的投影具有靠近所述第一源极的第三侧边；
    所述第一侧边、所述第二侧边及所述第三侧边相互平行，且所述第一侧边位于所述第二侧边与所述第三侧边之间。
  3. 根据权利要求2所述的显示面板，所述第一侧边与所述第二侧边之间的间距的范围为0.5μm-10μm。
  4. 根据权利要求1所述的显示面板，所述切换薄膜晶体管包括：
    第二有源层，与所述第一有源层同层设置，且与所述第一有源层间隔设置；
    第二栅极绝缘层，与所述第一栅极绝缘层同层设置，且与所述第一栅极绝缘层间隔设置；
    第二栅极层，与所述第一栅极层同层设置，且与所述第一栅极层间隔设置；以及
    其中，所述层间绝缘层延伸覆盖于所述第二栅极层远离所述基板的一侧的表面上；
    第二源漏极层，与所述第一源漏极层同层设置，且与所述第一源漏极层间隔设置；所述第二源漏极层包括相互间隔的第二源极和第二漏极。
  5. 根据权利要求4所述的显示面板，每一所述像素单元均还包括：
    扫描走线单元，与所述第二源漏极层同层设置，且与所述第二源极和所述第二漏极相互间隔设置，且电连接至所述第二栅极层，且与所述第二栅极层对应设置。
  6. 根据权利要求5所述的显示面板，
    所述扫描走线单元在所述基板上的投影具有靠近所述第二漏极的第四侧边；
    所述第二栅极层在所述基板上的投影具有靠近所述第二漏极的第五侧边；
    所述第二漏极在所述基板上的投影具有靠近所述第二源极的第六侧边；
    所述第四侧边、所述第五侧边及所述第六侧边相互平行，且所述第四侧边位于所述第五侧边与所述第六侧边之间。
  7. 根据权利要求6所述的显示面板，
    所述第四侧边与所述第五侧边之间的间距的范围为0.5μm-10μm。
  8. 根据权利要求5所述的显示面板，每一所述像素单元均还包括：
    高压接入源，设置于所述基板与所述缓冲层之间，且电连接至所述驱动薄膜晶体管；
    低压接入源，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述驱动薄膜晶体管；以及
    数据走线单元，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述切换薄膜晶体管。
  9. 根据权利要求8所述的显示面板，每一所述像素单元均还包括第一电容及感应薄膜晶体管；
    其中，所述第一栅极层电连接至所述第二漏极，且电连接至所述第一电容，所述第一源极电连接至所述低压接入源，所述第一漏极电连接至所述高压接入源；
    其中，所述第二栅极层电连接至所述扫描走线单元，所述第二源极电连接至所述数据走线单元，所述第二漏极电连接至第一电容；
    所述感应薄膜晶体管包括第三源极，所述第三源极电连接至所述第一电容。
  10. 一种电子显示设备，包括显示面板；
    所述显示面板，包括基板及多个阵列排布的像素单元；每一所述像素单元均包括：
    缓冲层，设置于所述基板上；
    驱动薄膜晶体管，设置于所述缓冲层远离所述基板的一侧的表面上；以及
    切换薄膜晶体管，与所述驱动薄膜晶体管同层设置，且电连接至所述驱动薄膜晶体管；
    所述驱动薄膜晶体管包括：
    第一有源层，设置于所述缓冲层远离所述基板的一侧的表面上；
    第一栅极绝缘层，设置于所述第一有源层远离所述基板的一侧的表面上；
    第一栅极层，设置于所述第一栅极绝缘层远离所述基板的一侧的表面上；
    层间绝缘层，覆盖于所述第一栅极层远离所述基板的一侧的表面上，且延伸覆盖于所述缓冲层远离所述基板的一侧的表面上；以及
    第一源漏极层，设置于所述层间绝缘层远离所述基板的一侧的表面上；
    所述第一源漏极层包括相互间隔的第一源极和第一漏极，所述第一源极朝向所述第一漏极延伸并覆盖于所述第一栅极层上。
  11. 根据权利要求10所述的电子显示设备，
    所述第一源极在所述基板上的投影具有靠近所述第一漏极的第一侧边；
    所述第一栅极层在所述基板上的投影具有靠近所述第一漏极的第二侧边；
    所述第一漏极在所述基板上的投影具有靠近所述第一源极的第三侧边；
    所述第一侧边、所述第二侧边及所述第三侧边相互平行，且所述第一侧边位于所述第二侧边与所述第三侧边之间。
  12. 根据权利要求11所述的电子显示设备，所述第一侧边与所述第二侧边之间的间距的范围为0.5μm-10μm。
  13. 根据权利要求10所述的电子显示设备，所述切换薄膜晶体管包括：
    第二有源层，与所述第一有源层同层设置，且与所述第一有源层间隔设置；
    第二栅极绝缘层，与所述第一栅极绝缘层同层设置，且与所述第一栅极绝缘层间隔设置；
    第二栅极层，与所述第一栅极层同层设置，且与所述第一栅极层间隔设置；以及
    其中，所述层间绝缘层延伸覆盖于所述第二栅极层远离所述基板的一侧的表面上；
    第二源漏极层，与所述第一源漏极层同层设置，且与所述第一源漏极层间隔设置；所述第二源漏极层包括相互间隔的第二源极和第二漏极。
  14. 根据权利要求13所述的电子显示设备，每一所述像素单元均还包括：
    扫描走线单元，与所述第二源漏极层同层设置，且与所述第二源极和所述第二漏极相互间隔设置，且电连接至所述第二栅极层，且与所述第二栅极层对应设置。
  15. 根据权利要求14所述的电子显示设备，
    所述扫描走线单元在所述基板上的投影具有靠近所述第二漏极的第四侧边；
    所述第二栅极层在所述基板上的投影具有靠近所述第二漏极的第五侧边；
    所述第二漏极在所述基板上的投影具有靠近所述第二源极的第六侧边；
    所述第四侧边、所述第五侧边及所述第六侧边相互平行，且所述第四侧边位于所述第五侧边与所述第六侧边之间。
  16. 根据权利要求15所述的电子显示设备，
    所述第四侧边与所述第五侧边之间的间距的范围为0.5μm-10μm。
  17. 根据权利要求14所述的电子显示设备，每一所述像素单元均还包括：
    高压接入源，设置于所述基板与所述缓冲层之间，且电连接至所述驱动薄膜晶体管；
    低压接入源，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述驱动薄膜晶体管；以及
    数据走线单元，与所述高压接入源同层设置，且与所述高压接入源间隔设置，且电连接至所述切换薄膜晶体管。
  18. 根据权利要求17所述的电子显示设备，每一所述像素单元均还包括第一电容及感应薄膜晶体管；
    其中，所述第一栅极层电连接至所述第二漏极，且电连接至所述第一电容，所述第一源极电连接至所述低压接入源，所述第一漏极电连接至所述高压接入源；
    其中，所述第二栅极层电连接至所述扫描走线单元，所述第二源极电连接至所述数据走线单元，所述第二漏极电连接至第一电容；
    所述感应薄膜晶体管包括第三源极，所述第三源极电连接至所述第一电容。
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