Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
  • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06E—OPTICAL COMPUTING DEVICES
  • G06E3/00—Devices not provided for in group G06E1/00, e.g. for processing analogue or hybrid data
  • G06E3/001—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements
  • G06E3/005—Analogue devices in which mathematical operations are carried out with the aid of optical or electro-optical elements using electro-optical or opto-electronic means
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/16—Constructional details or arrangements
  • G06F1/18—Packaging or power distribution
  • G06F1/189—Power distribution
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N3/00—Computing arrangements based on biological models
  • G06N3/02—Neural networks
  • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
  • G06N3/067—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means
  • G06N3/0675—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using optical means using electro-optical, acousto-optical or opto-electronic means
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/18—Printed circuits structurally associated with non-printed electric components
  • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
  • H05K1/183—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components mounted in and supported by recessed areas of the PCBs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
  • H10W20/483—Interconnections over air gaps, e.g. air bridges
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W40/00—Arrangements for thermal protection or thermal control
  • H10W40/20—Arrangements for cooling
  • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/0198—Manufacture or treatment batch processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
• • G—PHYSICS
  • G02—OPTICS
  • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
  • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B6/24—Coupling light guides
  • G02B6/42—Coupling light guides with opto-electronic elements
  • G02B6/4201—Packages, e.g. shape, construction, internal or external details
  • G02B6/4274—Electrical aspects
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/63—Vias, e.g. via plugs
  • H10W70/635—Through-vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/68—Shapes or dispositions thereof
  • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• a photonic package comprising a substrate carrier having a recess formed therethrough; a photonic substrate disposed in the recess; a first electronic die disposed on top of the photonic substrate; and a power delivery substrate configured to convey electric power from the substrate carrier to the first electronic die.
• the power delivery substrate is configured to convey electric power from the substrate carrier to the first electronic die passing through the photonic substrate.
• the power delivery substrate rests in part on the substrate carrier and in part on the photonic substrate.
• the power delivery substrate is a first power delivery substrate
• the photonic package further comprises a second power delivery substrate disposed on top of the first power delivery substrate
• the power delivery substrate comprises a bridge die
• the bridge die comprises conductive traces configured to support propagation of the electric power
• the bridge die lacks transistors.
• the power delivery substrate comprises an interposer disposed between the photonic substrate and the first electronic die.
• the silicon interposer rests in part on the substrate carrier.
• the photonic package further comprises a material layer disposed in the recess between the substrate carrier and the photonic substrate.
• the photonic package further comprises a second electronic die, wherein the photonic substrate comprises first and second photonic modules, wherein the first electronic die is disposed on top of the first photonic module and the second electronic die is disposed on top of the second photonic module.
• the first and second photonic modules have at least one common layer pattern.
• the first electronic die is in contact with the photonic substrate.
• the photonic package further comprises a lid covering the photonic substrate, wherein the lid is in thermal contact with the first electronic die.
• the substrate carrier is made of ceramic.
• Some embodiments relate to a photonic-electronic computing system comprising a substrate carrier; a photonic substrate disposed on the substrate carrier and patterned with first and second photonic modules monolithically embedded in the photonic substrate, wherein the first and second photonic modules share at least one common layer pattern; a first electronic die disposed on top of the first photonic module and a second electronic die disposed on top of the second photonic module; and a first power delivery substrate configured to convey electric power to the first electronic die.
• the first power delivery substrate is further configured to convey electric power to the second electronic die.
• the photonic-electronic computing system further comprises a second power delivery substrate configured to convey electric power to the second electronic die.
• the first power delivery substrate is configured to receive the electric power from the substrate carrier.
• the first photonic module is optically coupled to the second photonic module.
• the substrate carrier has a recess formed therethrough, wherein the first power delivery substrate rests in part on a first side of the substrate carrier and in part on a second side of the substrate carrier, wherein the first side and the second side are separated from one another by the recess.
• the first power delivery substrate comprises an opening, wherein the first electronic die is disposed in the opening.
• the first power delivery substrate has a plurality of openings formed therethrough such that the first bridge die comprises a plurality of columns and a plurality of rows of semiconductor material.
• the first power delivery substrate comprises conductive traces configured to support propagation of the electric power, and the first power delivery substrate lacks transistors.
• the first and second electronic dies are in contact with the photonic substrate.
• Some embodiments relate to a method for manufacturing a photonic package comprising: placing an electronic die on a photonic substrate patterned with a plurality of photonic modules; forming a recess into a substrate carrier; placing the photonic substrate into the recess of the sub state carrier; and placing a power delivery substrate in part on the photonic substrate and in part on the substrate carrier so that the power delivery substrate is in electrical communication with the electronic die.
• the method further comprises attaching a laser die to the photonic substrate.
• the method further comprises, prior to placing the photonic substrate into the recess of the substate carrier, placing a material layer on a surface of the photonic substrate so that, upon placing the photonic substrate into the recess, the material layer is between the photonic substrate and the substrate carrier.
• the method further comprises covering the electronic die with a lid so that the lid is in thermal contact with the electronic die.
• FIG. 1 A is a schematic diagram of a computing system formed on a photonic substrate, in accordance with some embodiments.
• FIG. IB is a schematic diagram of a representative photonic substrate including a plurality of photonic modules, in accordance with some embodiments.
• FIG. 1C is a cross sectional side view of an electronic die mounted on a photonic module, in accordance with some embodiments.
• FIG. 2A is a cross sectional side view of a photonic package, in accordance with some embodiments.
• FIG. 2B is a cross sectional side view illustrating the substrate carrier of the photonic package of FIG. 2A, in accordance with some embodiments.
• FIG. 2C is a cross sectional side view illustrating a portion of the photonic package of FIG. 2A in additional detail, in accordance with some embodiments.
• FIG. 2D is a cross sectional side view of a photonic package mounted on a printed circuit board, in accordance with some embodiments.
• FIG. 2E is a top view of a photonic-electronic computing system, in accordance with some embodiments.
• FIG. 3 A is a cross sectional side view of another photonic package, in accordance with some embodiments.
• FIG. 3B is a cross sectional side view illustrating a portion of the photonic package of FIG. 3 A in additional detail, in accordance with some embodiments.
• FIG. 3C is a top view illustrating a bridge die arranged with a plurality of rows and a plurality of columns, in accordance with some embodiments.
• FIG. 3D is a top view of another photonic-electronic computing system, in accordance with some embodiments.
• FIG. 4 is a heat chart illustrating the electric power distribution delivered across a representative photonic-electronic computing system, in accordance with some embodiments.
• FIG. 5 is a flowchart illustrating a method for manufacturing a photonic package, in accordance with some embodiments.
• the inventors have developed communication platforms that enable scaling of memory capacity and bandwidth well beyond what is possible with conventional electronic computers.
• the communication platforms described herein overcome these limitations using optics.
• the physics according to which light propagates inside a waveguide makes optical communications inherently immune to parasitic impedance.
• the immunity to parasitic impedance leads to a major benefit — it removes the requirement that memory chips be positioned within a certain range of the processor.
• Photonic substrates for the distribution of data between different parts of a computing systems.
• Photonic substrates of the types include substrates (e.g., made of a semiconductor material such as silicon) lithographically patterned to have multiple photonic modules.
• the photonic modules are monolithically embedded in the photonic substrate.
• each photonic module is patterned as a reticle shot of a step-and-repeat semiconductor manufacturing process.
• the photonic modules are identical to one another (or have at least one common layer pattern, such as a common waveguide layer pattern).
• the photonic modules are arranged side-by-side, for example, in a grid-like configuration.
• Each node of the grid may be occupied by a photonic module.
• an electronic die such as a memory die or a processor die.
• Each photonic module includes programmable photonic circuits that can be configured based on the needs of a particular computer architecture.
• Some platforms are arranged according to 1- dimentional schemes, such as in blocks of 3x1 modules, in blocks of 5x1 modules, in blocks of 10x1 modules, 20x1 modules, etc.
• a 7x7 photonic substrate is provided having a total size equal to 182mm x 231mm, where each photonic module is 26mm x 33mm in size.
• the inventors have appreciated a challenge stemming from the large size of these photonic substrates: it is difficult to deliver electric power uniformly across the entire extension of the substrate. Nodes that are closer to the edge of the photonic substrate generally receive high power. However, nodes that are closer to the middle of the photonic substate (and farther away from the edge) receive less power. This can be obviated by increasing the overall power delivered to the substrate. The drawback, however, is that doing so leads to spots of large temperature, and as a result, to localized variations in refractive index, which alter the functionality of the optical network in an unpredictable fashion.
• the inventors have developed architectures for improving the uniformity with which electric power is delivered throughout a photonic substrate and the computing system that relies on it. These architectures rely on power delivery substrates (examples of which are described in detail further below) to convey power from the substrate carrier to the photonic modules and to the electronic dies.
• the power delivery substrates described herein deliver power not only to the periphery of the system, but also directly to the center.
• These substates can include bridge dies and/or interposers, and can be made by short looping wafer processing (which make them low cost). Short looping may involve processing a wafer with a reduced mask set (e.g., by skipping process steps associated with subsequent masks). This makes the cost per unit area very low, and opens the opportunity to deploy very large power substrates.
• the large area of the power substrate enables arbitrary power delivery networks, and thus, promotes uniform power distribution.
• Photonic substrates of the types described herein are designed to provide the fabric necessary to implement computing systems with arbitrary architectures. These photonics substrates may be arranged to form grids, where the nodes of the grid are occupied by photonic modules. Each photonic module communicates optically with the other photonic modules. Additionally, each photonic module interfaces with a respective electronic die, whether a memory die, a processor die, or other types of dies.
• FIG. 1 illustrates an example computing system based on a photonic communication platform with nine photonic modules arranged in a 3x3 grid, in accordance with one example.
• photonic substrate 20 is patterned with a photonic module 22.
• This photonic communication platform supports one processor die (30) positioned in the middle of photonic substrate 20, and seven memory nodes surrounding the processor die.
• Some of the memory nodes include a single memory chip (see for example memory die 32).
• Other memory nodes include a stacked memory including multiple vertically-stacked memory dies (see for example stacked memory 34).
• a laser die 36 is mounted on top of one of the photonic modules.
• the dies can communicate with the photonic module electronically (e.g., using through-silicon vias, copper pillars, micro-bumps, ball-grid arrays or other electrical interconnects) and/or optically (e.g., using grating couplers, prisms, lenses or other optical couplers).
• electronically e.g., using through-silicon vias, copper pillars, micro-bumps, ball-grid arrays or other electrical interconnects
• optically e.g., using grating couplers, prisms, lenses or other optical couplers.
• the photonic modules are patterned with optical waveguides and optical distribution networks.
• the optical distribution network of a photonic module can selectively place the die of that particular photonic module in optical communication with any other die of the computing system.
• the optical distribution network of the photonic module positioned under processor die 30 may be reconfigured depending on the needs of the processor.
• the processor may need to access data stored in a first memory node. This read operation involves configuring the respective optical distribution networks to place the processor in optical communication with the first memory node. Later in the routine, the processor may need to write data into a second memory node. This write operation involves reconfiguring the optical distribution networks to place the processor in optical communication with the second memory node.
• the photonic modules of photonic substrate 20 may be fabricated using a common photomask set (or at least one common photomask). This approach reduces costs in two ways. First, it reduces additional costs that would otherwise be incurred in procuring several different photomask sets. Second, it enables fabrication of photonic modules using standard semiconductor foundries, some of which require that the same photomask set (or at least one photomask) be used across an entire wafer. Designing photonic modules that share at least one photomask enables fabrication of many photonic modules on the same semiconductor wafer while leveraging standard, low-cost step-and-repeat manufacturing processes.
• FIG. IB illustrates an example 2x3 photonic substrate including six photonic modules 22.
• all the photonic modules are patterned according to the same template.
• only a sub-set of the layers of the photonic modules are patterned according to the same template. For instance, the layer in which optical waveguides are defined is patterned with the same template six times, while another layer (e.g., a metal layer) does not follow a periodic arrangement.
• the photonic modules 22 are arranged so that waveguide 111 of an optical module is aligned with waveguide 112 of the optical module to the left of that optical module, waveguide 112 of an optical module is aligned with waveguide 111 of the optical module to the right of that optical module, waveguide 113 of an optical module is aligned with waveguide 114 of the optical module above that optical module and waveguide 114 of an optical module is aligned with waveguide 113 of the optical module below that optical module.
• the optical modules form an optical network.
• Optical distribution networks 104 may be reconfigurable. Therefore, optical distribution networks 104 may route optical signals anywhere inside or outside the network.
• a read operation may involve reconfiguring the optical distribution networks to place the processor in optical communication with the memory.
• an optical communication path may be formed that 1) couples the processor to the out-of-plane coupler of the photonic module to which the processor is mounted, 2) couples the out-of-plane coupler of that photonic module to waveguide 112 of the same photonic module, 3) couples waveguide 112 of that photonic module to waveguide 111 of the adjacent photonic module (mid-uppermost photonic module), 4) couples waveguide 112 of the mid-uppermost photonic module to waveguide 111 of the next adjacent photonic module (north-east corner of the photonic substrate), 5) couples waveguide 114 of the photonic module positioned at north-east comer to waveguide 113 of the photonic module to which the memory is mounted, and 6) couples waveguide 113 of the photonic module to which the memory is mounted to the out-of-plane coupler of the same photonic module.
• an electronic die may be mounted on each (or at least some) photonic module.
• the manner in which an electronic die may be mounted on a photonic module is depicted in additional detail in FIG. 1C.
• an electric die 30 is mounted on a photonic module 22.
• Electronic die 30 communicates with photonic module 22 either electrically (by way of electrical connection 120) or optical (by way of out-of-plane optical couplers 105 and 107), or both.
• ODN optical distribution network
• Die 30 includes a waveguide 118 placing controller 31 in optical communication with out-of-plane coupler 107.
• Controller 31 is electrically coupled to optical distribution network 104 via electrical connection 120, which may include for example a ball- grid array, copper pillars, through silicon vias, micro-bumps, metals pads, etc. Controller 31 controls the operations of optical distribution network 104. For example, controller 31 controls the direction of routing of optical distribution network 104. Control signals are provided to optical distribution network 104 via electrical connection 120.
• FIG. 2A The package of FIG. 2A includes a substrate carrier 200, a photonic substrate 20, electronic dies 30 and 32, power delivery substrates 210 and lid 220. Photonic substrate 20 and the electronic dies that are mounted on it have been described in detail above.
• Substrate carrier 200 is illustrated on its own in FIG. 2B. As shown in this figure, substrate carrier 200 includes a recess 201 formed through a portion of the substrate carrier’s top surface. Referring back to FIG. 2A, photonic substrate 20 is disposed inside recess 201.
• substrate carrier 200 is made of a material having a coefficient of thermal expansion that is close to the coefficient of thermal expansion of photonic substrate 20.
• photonic substrate 20 may be made of silicon and substrate carrier 200 may be made of ceramic (including a ceramic laminate).
• photonic substrate 20 may be made of silicon and substrate carrier 200 may be made of a material having a coefficient of thermal expansion between 0.5 ppm/°C and 30 ppm/°C, between 0.5 ppm/°C and 20 ppm/°C, between 0.5 ppm/°C and 10 ppm/°C or between 0.5 ppm/°C and 5 ppm/°C, among other possible ranges.
• a material layer 206 is disposed between the bottom surface of recess 201 and the bottom surface of photonic substrate 20.
• substrate carrier 200 may be made of a ceramic laminate. Since ceramic laminates are formed using a co-firing process, shrinkage may result, and the position of the contacts may vary. To mitigate this effect, in some embodiments, material layer 206 is disposed on top of the ceramic laminate after co-firing using a standard lithography process. As the substrate carrier is in thermal contact with the photonic substrate (and the electronic dies through metallic lines), the substrate carrier can be used as a thermal sink (or source) to remove heat from the package or maintain a certain temperature of the package.
• Substrate carrier 200 includes conductive pads 202. When the carrier substrate is mounted on a printed circuit board, conductive pads 202 places the carrier substrate in electrical communication with the printed circuit board.
• memory dies 32 and processor die 30 are mounted on respective photonic modules of photonic substrate 20.
• Lid 220 covers the electronic dies and is placed in thermal contact with the electronic dies (either by direct contact or by way of a thermal material such as a thermal paste). Accordingly, lid 220 transfers heat generated by the dies outside the package.
• the package of FIG. 2 A relies on power delivery sub states 210 to convey power to the dies and to the photonic substrate.
• One such power delivery substrate is illustrated in FIG. 2C in additional detail.
• a power delivery substate 210 is disposed in part on the substrate carrier and in part on the photonic substrate.
• the height of the recess may substantially match the height of the photonic substrate (or may substantially match the height of the photonic substrate plus the height of material layer 206).
• Power delivery substrates 210 may be implemented using any suitable technology.
• a power delivery substrate is a bridge die (e.g., made of silicon) including metal traces 222.
• a bridge die may be fabricated using a relatively low-cost manufacturing process.
• a bridge die may be made with a relatively large fabrication node.
• a bridge die is fabricated using a small fabrication node, but is taken out of the fabrication process line before transistors may be fabricated on it. Accordingly, in some embodiments, a bridge die lacks transistors.
• Substrate carrier 200 includes connections 204 (e.g., vias and/or conductive traces) placing pads 202 in communication with power delivery substrate 210 (through connections 221).
• Photonic substrate 20 includes connections 25 (e.g., vias and/or conductive traces) placing power delivery substrate 210 in communication with electronic die 32 (through respective connections 221 and 33).
• Photonic substrate 20 further includes connections 26 placing power delivery substrate 210 in communication with one or more photonic modules.
• FIG. 2D illustrates how electric power may be delivered to the electronic dies, in accordance with some embodiments.
• substrate carrier 200 is mounted on a printed circuit board 260.
• a power supply 262 is also mounted on printed circuit board 260.
• An electrical power path 264 is formed from power supply 262 to electronic die 32.
• the electrical power path passes through printed circuit board 260, pad 202, connection 204, connection 221, traces 222, connection 25 and connection 33.
• power delivery substrate 210 may be viewed as conveying power from substrate carrier 200 to electronic die 32 and to photonic substate 20.
• a power delivery substrate conveys power to one electronic die.
• a power delivery substrate conveys power to multiple electronic dies.
• FIG. 2E One such embodiment is illustrated in FIG. 2E.
• a photonic-electronic computing system is formed that includes forty-nine dies disposed on a photonic substrate 20 having 7x7 photonic modules 22. Additionally, the photonic-electronic computing system includes eight power delivery substrates 210 disposed in parallel to one another. Each power delivery substrate 210 has an elongated shape (along the y-axis) in this example. Further, the power delivery substrates 210 rest on photonic substrate 20 and on two portions of the substrate carrier 200 that are on opposite sides of recess 201. In FIG. 2E, two power delivery substrates 210 are shown as conveying power to respective columns of electronic dies via electric power path 265. The other power delivery substrates 210 may convey power to the other die columns in a similar manner.
• bridge dies may serve as power delivery substrates.
• Bridge dies may be obtained by lithographically patterning a silicon wafer with conductive traces and vias and by dicing the wafer to form desired die shapes.
• bridge dies lack transistors, though not all embodiments are limited in this respect.
• Other types of power delivery substrates are also possible. Interposers are another example.
• FIG. 3 A illustrates a photonic package including an interposer serving as a power delivery substrate, in accordance with some embodiments. Similar to the arrangement of FIG. 2A, the arrangement of FIG. 3 A includes a substrate carrier 200 having a recess, a photonic substrate 20 disposed in the recess, electronic dies 30 and 32, multiple power delivery substrates 210 and a lid 220. In this example, power delivery substates 210 are implemented using bridge dies. The arrangement of FIG. 3A further includes power delivery substrate 300, which is implemented using an interposer.
• the interposer may be made, for example, of silicon or an organic material. In some embodiments, an interposer may be used to redistribute the heat within, and among, the electrical dies and the photonic substrate.
• the interposer rests in part on photonic substrate 20, in part on a first portion of substrate carrier 200 and in part on a second portion of the substrate carrier, where the first and second portions are separated by recess 201. It should be appreciated that, in some embodiments, there may be multiple interposers (arranged for example in parallel columns, in a manner similar to the power delivery substrates of FIG. 2E).
• the interposer may distribute signals among the electronic dies, and between the electronic dies and the photonic substrate. For example, the interposer may spread the connections to a wider pitch than it would be possible if the electronic dies were connected directly to the photonic substrate.
• an interposer removes the need for the electronic dies to have the same pin out arrangement as in the photonic substrate.
• the electronic dies 30 and 32 and the power delivery substrates 210 rest on the interposer in this example.
• the electronic dies may have different heights. This may be the case, for example, if some of the electronic die include a stack of chips (e.g., a 3D-stacked memory unit).
• Thermal materials 320 of different heights may be placed on top of the electronic dies to ensure thermal contact with lid 220 regardless of the heights of the electronic dies. Thermal materials may help remove heat and/or maintain a certain temperature of the electronic dies and the photonic substrate.
• power delivery substrate 300 conveys power to an electronic die through a power delivery substrate 210. Additionally, or alternatively, power delivery substrate 300 may convey power to an electronic die directly.
• FIG. 3B illustrates a portion of the package of FIG. 3A in additional detail. As shown in this figure, power delivery substrate 300 includes vias and metal layers 302 for routing electric power and signals across the various components of the photonic package. Power delivery substrate 300 receives electric power from connections 204 and delivers some of that power to power delivery substrate 210 and some of that power to photonic substrate 20. Power delivery substrate 210, in turn, conveys power to electronic die 32 via metal trace 222. In other embodiments (not shown in FIG. 3B), power delivery substrate 300 conveys power directly to electronic die 32 without having to pass through a power delivery substrate 210.
• a power delivery substrate may include a bridge die having a plurality of openings formed therethrough.
• one such power delivery substrate may be shaped to include multiple rows and columns of semiconductor material separated from each other by openings.
• FIG. 3C illustrates a bridge die 270 having multiple openings 272, where each opening is surrounded by semiconductor material.
• This type of bridge die may be used in some embodiments to enable arbitrary power distribution networks.
• FIG. 3D Here, each electronic die is disposed in a respective opening of the bridge die, either on an interposer (as in FIG. 3A) or directly on the photonic substrate (as in FIG. 2A).
• FIG. 3D illustrates a bridge die shaped with openings
• an interposer may be shaped with openings such that electronic dies may be disposed in the openings.
• a photonic package may include multiple interposers of the type illustrated in FIG. 3 A. Each interposer may interface a portion of the photonic substrate to a respective subset of the electronic dies.
• a wafer-level probe systems may be placed on the one or more edges of a photonic substrate to test the uniformity with which the various parts of the system receive power.
• This approach is useful for quickly testing the wafer-level system because it requires no irreversible special packaging process.
• the probe systems can be removed after testing is finished.
• the approach has a drawback because the amount of power supplied drops from the probed side of the wafer by distance. As a result, the photonic modules closest to the probe system will receive more power than the photonic modules furthest from the probe system.
• FIG. 4 shows an example analysis of such power drop through a photonic substrate having 7x7 photonic modules. As shown in this figure, the power distribution is relatively uniform across the photonic substrate, although it drops near the edge on the left-hand side of the photonic substrate and near the upper edge of the photonic substrate.
• FIG. 5 is a flowchart illustrating a representative fabrication method. The steps of method 500 may be performed in the order depicted in FIG. 5 or in any other suitable order.
• Method 500 begins at step 502, in which a substrate carrier, a photonic substrate, one or more electronic dies and one or more power delivery substrates are obtained.
• the power delivery substrate may be, for example, a ceramic laminate substrate.
• the photonic substrate may have been pre-patterned with a plurality of photonic modules, for example as discussed in connection with FIG. IB.
• the electronic die(s) may have been pre-patterned to form memories, processors, or other types of chips.
• the power delivery substrate(s) may be bridge die(s), interposer(s) or other types of substrate configured to route electric power.
• the power delivery substrate(s) may have been pre-patterned with vias and conductive traces.
• the electronic die(s) may be placed on the photonic substrate.
• the electronic die(s) may be mounted directly on the photonic substrate.
• an interposer may be mounted on the photonic substrate and the electronic die(s) may be mounted on the interposer.
• a recess is formed into the substrate carrier. This step may be performed, for example, using etching techniques.
• the photonic substrate may be placed in the recess. It should be noted that the photonic substrate may be placed in the recess before or after the electronic die(s) have been placed on the photonic substrate.
• one or more power delivery substrates may be placed in part on the photonic substrate and in part on the substrate carrier in such a way as to being configured to convey power to the electronic die(s).
• some aspects may be embodied as one or more methods.
• the acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
• the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements.
• This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.
• the terms “approximately” and “about” may be used to mean within ⁇ 20% of a target value in some embodiments, within ⁇ 10% of a target value in some embodiments, within ⁇ 5% of a target value in some embodiments, and yet within ⁇ 2% of a target value in some embodiments.
• the terms “approximately” and “about” may include the target value.

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• 2021
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