WO2021148007A1 - 显示基板母板、显示基板及其制备方法、显示装置 - Google Patents

显示基板母板、显示基板及其制备方法、显示装置 Download PDF

Info

Publication number
WO2021148007A1
WO2021148007A1 PCT/CN2021/073370 CN2021073370W WO2021148007A1 WO 2021148007 A1 WO2021148007 A1 WO 2021148007A1 CN 2021073370 W CN2021073370 W CN 2021073370W WO 2021148007 A1 WO2021148007 A1 WO 2021148007A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
retaining wall
display
area
substrate
Prior art date
Application number
PCT/CN2021/073370
Other languages
English (en)
French (fr)
Inventor
倪静凯
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/625,980 priority Critical patent/US20220384761A1/en
Publication of WO2021148007A1 publication Critical patent/WO2021148007A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/851—Division of substrate

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate mother board, a display substrate and a preparation method thereof, and a display device.
  • the display substrate includes a plurality of patterned inorganic insulating layers.
  • the method of preparing a patterned inorganic insulating layer in the prior art includes: a photolithography process; or, forming an inorganic insulating layer in a pre-prepared template, and then separating the inorganic insulating layer from the template to obtain a pattern with a certain pattern.
  • the inorganic insulating layer includes: a photolithography process; or, forming an inorganic insulating layer in a pre-prepared template, and then separating the inorganic insulating layer from the template to obtain a pattern with a certain pattern.
  • a display substrate mother board which has a plurality of display areas and a cutting area located between the plurality of display areas; the display substrate mother board includes a base substrate, a plurality of first retaining wall groups, An inert material layer and a first inorganic insulating layer.
  • a plurality of first retaining wall groups are arranged on the base substrate; each first retaining wall group is located on at least one side of a corresponding display area, and each first retaining wall group includes two first retaining wall groups arranged at intervals The area between the two first retaining walls is located in the cutting area; the inert material layer is provided in the area between the two first retaining walls; the first inorganic insulating layer is provided in the plurality of The first barrier wall group is far away from the base substrate, and the first inorganic insulating layer is also located in the plurality of display areas; the orthographic projection of the first inorganic insulating layer on the base substrate and the The orthographic projection of the inert material layer on the base substrate has no overlap.
  • the two first retaining walls are both arranged around the corresponding display area;
  • the first inorganic insulating layer includes a plurality of inorganic insulating sub-layers, and each inorganic insulating sub-layer is located in the corresponding display area and connected to the corresponding display area. The area where the first retaining wall group is located corresponding to the display area.
  • the display substrate mother board further includes: at least one sub-retaining wall, and the at least one sub-retaining wall is located in an area between the two first retaining walls in the at least one first retaining wall group The at least one sub-retaining wall and the two first retaining walls are arranged in the same layer; the inert material layer covers the at least one sub-retaining wall.
  • the first retaining wall set is disposed on the surface of the base substrate, and the surface of the base substrate close to the first retaining wall set has at least one groove; the at least one groove The area between the two first retaining walls; the inert material layer covers the at least one recess; or, the display substrate mother board further includes: The dielectric layer between the barrier wall groups; the first barrier wall group is disposed on the surface of the dielectric layer away from the base substrate, and the surface of the dielectric layer away from the base substrate has at least one Groove; the at least one groove is located in the area between the two first retaining walls; the inert material layer covers the at least one groove.
  • the display substrate mother board further includes a plurality of second barrier wall groups, a second inorganic insulating layer arranged on a side of the second barrier wall group away from the base substrate, and a second inorganic insulating layer arranged on the side of the base substrate.
  • a plurality of via holes in the second inorganic insulating layer is not limited to one of the second barrier wall groups, a second inorganic insulating layer, a second inorganic insulating layer arranged on a side of the second barrier wall group away from the base substrate, and a second inorganic insulating layer arranged on the side of the base substrate.
  • the plurality of second retaining wall groups are arranged on the base substrate, and the orthographic projection of the plurality of second retaining wall groups on the base substrate and the plurality of first retaining wall groups are in the The orthographic projections on the base substrate have no overlap; each second retaining wall group includes at least two adjacent second retaining walls, and a space is formed between the at least two adjacent second retaining walls; The spacer area overlaps with the orthographic projection of a via hole on the base substrate.
  • a display substrate having a display area; the display substrate includes: a base substrate, a first retaining wall arranged on the base substrate, a first retaining wall arranged on the first retaining wall and the lining An inert material layer between the edges of the base substrate and a first inorganic insulating sub-layer arranged on the side of the first retaining wall away from the base substrate.
  • the first retaining wall is located on at least one side of the display area, and on either side of the display area where the first retaining wall is provided, the first retaining wall and the first retaining wall are There is a distance between the edges of the base substrate; the first inorganic insulating sublayer is also located in the display area; on either side of the display area where the first barrier wall is provided, the first inorganic insulating sublayer
  • the orthographic projection of the edge on the base substrate is located within the orthographic projection range of the first retaining wall on the base substrate.
  • the first retaining wall is arranged around the display area, and the orthographic projection of each edge of the first inorganic insulator sublayer on the base substrate is located where the first retaining wall is located. Within the orthographic projection range on the base substrate.
  • the display substrate further includes a flat layer disposed on the base substrate and located in the display area, and the first retaining wall and the flat layer are disposed in the same layer; or, the display The substrate further includes a pixel defining layer arranged on the base substrate and located in the display area; the first retaining wall and the pixel defining layer are arranged in the same layer.
  • the display substrate further includes: at least one barrier dam disposed on the base substrate; the at least one barrier dam is disposed on a side of the first retaining wall close to the display area, And the at least one barrier dam is arranged around the display area.
  • the at least one barrier dam includes: a first barrier dam and a second barrier dam spaced apart from the first barrier dam in a direction perpendicular to the thickness of the base substrate; the first barrier dam; A barrier dam is arranged around the display area, and the second barrier dam is arranged around the first barrier dam, and the surface of the second barrier dam away from the base substrate is in the direction of the thickness of the substrate The minimum distance to the base substrate is greater than the minimum distance from the surface of the first barrier dam away from the base substrate in the direction of the thickness of the base substrate to the base substrate.
  • the display substrate further includes: at least one second barrier wall set on the base substrate, and a second barrier set on a side of the second barrier wall away from the base substrate.
  • the orthographic projection of the at least one second retaining wall group on the base substrate does not overlap with the orthographic projection of the first retaining wall on the base substrate; each second retaining wall group includes at least adjacent The two second retaining walls of, and a spacer area is formed between the at least two adjacent second retaining walls; the spacer area overlaps the orthographic projection of a via hole on the base substrate.
  • a display device including the display substrate described in any of the above embodiments.
  • a method for preparing a display substrate including: providing a base substrate; the base substrate has a plurality of display regions and Cutting area; on the base substrate and located on at least one side of each display area, a first retaining wall group including two first retaining walls is formed, and the area between the two first retaining walls is located The cutting area; forming an inert material layer in the area between the two first retaining walls in each first retaining wall group; forming on the side of the plurality of first retaining wall groups away from the base substrate A first inorganic insulating layer, the first inorganic insulating layer is also located in the plurality of display areas; the orthographic projection of the first inorganic insulating layer on the base substrate and the inert material layer on the substrate The orthographic projection on the substrate has no overlap; cut along the cutting area to obtain the display substrate.
  • forming an inert material layer in the area between the two first retaining walls in each first retaining wall group includes: The area between a retaining wall is filled with a first organic material to form the inert material layer.
  • the first retaining wall group is located on the surface of the base substrate; the area between the two first retaining walls in each first retaining wall group is filled with a first organic material Previously, forming the inert material layer further includes: preprocessing the surface of the base substrate so that the surface of the base substrate has hydroxyl groups, so that after the first organic material is filled, the first organic material is filled with the first organic material. The organic material reacts with the hydroxyl group to form an inert material layer.
  • the method further includes: forming a dielectric layer on the base substrate; wherein filling the area between the two first retaining walls in each first retaining wall group Before the first organic material, forming the inert material layer further includes: preprocessing the surface of the dielectric layer away from the base substrate so that the surface of the dielectric layer away from the base substrate has hydroxyl groups, After filling the first organic material, the first organic material is reacted with the hydroxyl group to form an inert material layer.
  • the first organic material includes one of vinyl triethoxy silane, vinyl triacetoxy silane, and chloromethyl triethoxy silane.
  • forming an inert material layer in the area between the two first retaining walls in each first retaining wall group includes: facing the two first retaining walls in each first retaining wall group.
  • the area between the walls is filled with a second organic material; the second organic material includes one of polystyrene, polyethylene oxide, polymethyl methacrylate, and polyvinylpyrrolidone.
  • the method further includes: forming a plurality of barrier dams on the base substrate; each display area is surrounded by at least one barrier dam, and the at least one barrier dam is disposed corresponding to the display area.
  • the first retaining wall group is close to one side of the display area.
  • the base substrate has a plurality of display substrate areas, one display area is located in a corresponding display substrate area, and the cutting area is located between the multiple display substrate areas;
  • the method further includes: forming at least one second retaining wall group in each display substrate area on the base substrate, each second retaining wall group including at least two adjacent second retaining walls, and A spacer area is formed between at least two adjacent second retaining walls; the orthographic projection of the at least one second retaining wall set on the base substrate and the first retaining wall set on the base substrate There is no overlap on the orthographic projection; an inert organic film layer is formed in the spacer area; a second inorganic insulation is formed in the display substrate area and on the side of the at least one second barrier wall away from the base substrate Layer; removing the inert organic film layer formed in the spacer area.
  • FIG. 1 is a schematic top view of a display substrate mother board according to some embodiments
  • FIG. 2 is a schematic cross-sectional structure diagram of a display substrate mother board based on the direction A-A1 in FIG. 1 according to some embodiments;
  • FIG. 3 is a schematic cross-sectional structure diagram of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 4A is a schematic diagram of a preparation process of an inert material layer according to some embodiments.
  • 4B is a schematic diagram of a preparation process of an inert material layer according to some embodiments.
  • 4C is a schematic diagram of a process of forming a first inorganic insulating layer on the side of the inert material layer away from the mother substrate according to some embodiments;
  • 5A is a schematic cross-sectional structure diagram of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 5B is a schematic cross-sectional view of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 6A is a schematic cross-sectional view of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 6B is a schematic cross-sectional view of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 6C is a schematic cross-sectional view of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • 6D is a schematic cross-sectional structure diagram of yet another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • FIG. 7 is a schematic cross-sectional view of another display substrate based on the direction A-A1 in FIG. 1 according to some embodiments;
  • FIG. 8 is a schematic top view of a display substrate according to some embodiments.
  • FIG. 9 is a schematic cross-sectional view of another display substrate based on the direction C-C1 in FIG. 8 according to some embodiments.
  • FIG. 10 is a schematic cross-sectional structure diagram of a display substrate based on the direction B-B1 in FIG. 8 according to some embodiments;
  • FIG. 11 is a schematic top view of a structure of a display device according to some embodiments.
  • FIG. 12 is a schematic flowchart of a method for manufacturing a display substrate according to some embodiments.
  • FIG. 13 is a manufacturing process diagram of a display substrate according to some embodiments.
  • Fig. 14A is a process diagram of a substrate according to some embodiments.
  • FIG. 14B is a diagram of a manufacturing process of a substrate according to some embodiments.
  • FIG. 15 is a schematic cross-sectional structure diagram of another display substrate based on the direction B-B1 in FIG. 8 according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • “same layer” refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a patterning process.
  • the patterning process may include exposure, development, and etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity.
  • the exemplary embodiments of the present disclosure should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • Some embodiments of the present disclosure provide a display substrate mother board 100, as shown in FIG. 1 and FIG. 2, having a plurality of display substrate regions 103, a plurality of display regions 101, and a cutting region 102 located at the periphery of the plurality of display regions 101;
  • the display area 101 is located in a corresponding display substrate area 103, and the cutting area 102 and the display substrate area 103 do not overlap.
  • the multiple display areas 101 are arranged in multiple rows and multiple columns on the display substrate mother board 100.
  • FIG. 1 takes the display substrate motherboard showing four display areas 101 as an example for illustration.
  • the four display areas 101 are arranged on the display substrate motherboard into 2 rows along the X direction and 2 columns along the Y direction.
  • the cutting area 102 is located at the periphery of each display area 101.
  • the cutting area 102 is located between every two adjacent display areas 101.
  • the cutting area 102 is located on the side of the display area 101 close to the edge of the display substrate motherboard.
  • the display substrate mother board 100 includes a base substrate 10 and a plurality of first wall groups 11 arranged on the base substrate 10.
  • Each first retaining wall group 11 is located on at least one side of a corresponding display area 101, and each first retaining wall group 11 includes two first retaining walls 111.
  • the two first retaining walls 111 in each first retaining wall group 11 are arranged on the same layer and spaced apart, and the area between the two first retaining walls 111 in each first retaining wall group 11 is located in the cutting area 102.
  • each first retaining wall group 11 is arranged around a corresponding display area 101 in a circle. In other examples, each first retaining wall group 11 is arranged on one side of a corresponding display area 101. In still other examples, each first retaining wall group 11 is disposed on opposite sides or adjacent sides of a corresponding display area 101.
  • multiple barrier wall groups 11 may be located on different sides of the same display area 101, and multiple barrier wall groups 11 located on different sides of the same display area 101 may be connected end to end or not connected. The present disclosure does not specifically limit this, as long as the two first retaining walls 111 in each retaining wall group 11 are arranged at intervals.
  • the display substrate mother board 100 also includes an inert material layer 12 arranged in the area between the two first barrier walls 111 and a first inorganic insulating layer arranged on the side of each first barrier wall group 11 away from the base substrate 10 13.
  • the first inorganic insulating layer 13 is also located in each display area 101; the orthographic projection of the first inorganic insulating layer 12 on the base substrate 10 and the orthographic projection of the inert material layer 12 on the base substrate 10 do not overlap.
  • An inert material layer 12 is arranged between the two first retaining walls 111 of each first retaining wall group 11.
  • the material of the inert material layer is an inert organic material.
  • the first inorganic insulating layer 13 with a certain pattern can be directly obtained by the deposition process.
  • the patterned first inorganic insulating layer 13 is prepared by the present disclosure. The process can omit exposure, development, etching, stripping and other processes.
  • the display substrate mother board 100 includes a first inorganic encapsulation layer 132 and a second inorganic encapsulation layer 133 that are stacked.
  • the first inorganic encapsulation layer 132 and the second inorganic encapsulation layer 133 can prevent water vapor and oxygen entering from the side of the display substrate mother board away from the base substrate from entering the display substrate and affecting the light emitting devices inside the display substrate.
  • the materials of the first inorganic encapsulation layer 132 and the second inorganic encapsulation layer 133 are inorganic substances, such as silicon nitride and/or silicon oxide.
  • the first inorganic encapsulation layer 132 and the second inorganic encapsulation layer 133 may use the same material or different materials.
  • the first inorganic insulating layer 13 includes the above-mentioned first inorganic encapsulating layer 132 and the second inorganic encapsulating layer 133, that is, the first inorganic insulating layer 13 in the present disclosure can be used for encapsulation of a display substrate.
  • the display substrate mother board 100 is cut to form In the case of multiple display substrates, cutting can be performed in the area between the two first retaining walls 111 in the first retaining wall group 11, so that the organic inert material layer 12 is actually cut. Since the flexibility of organic materials is greater than that of inorganic materials, the problem of cracking of inorganic insulating materials during cutting can be improved.
  • the film formation area of the inorganic insulating film is much larger than the design size of the first inorganic insulating layer 13, which will cause the edge of the first inorganic insulating layer 13
  • the shadow is too large, when the display substrate is applied to the display device, it is not conducive to the narrow frame design of the display device.
  • the patterned first inorganic insulating layer is formed on the side of the first barrier wall group 11 away from the base substrate, the mask is not used, and there is no edge shadow, which is beneficial to the narrow frame design of the display device.
  • the display substrate mother board 100 further includes a flat layer 22 disposed on the base substrate 10 and located in the display area 101, and the first barrier 111 and the flat layer 22 are disposed in the same layer, namely , The first retaining wall 111 and the flat layer 22 are formed through the same patterning process.
  • the material of the flat layer 22 includes, but is not limited to, polysiloxane-based, acrylic-based, or polyimide-based materials.
  • the display substrate mother board 100 further includes a pixel defining layer 24 disposed on the base substrate 10 and located in the display area 101.
  • the first retaining wall 111 and the pixel defining layer 24 are arranged in the same layer, that is, the first retaining wall 111 and the pixel defining layer 24 are formed by the same patterning process.
  • the pixel defining layer 24 is disposed on a side of the flat layer 22 away from the base substrate 10.
  • the material of the pixel defining layer 24 is photoresist.
  • the photoresist includes one or more of polyimide, organosilane, and polymethyl methacrylate.
  • the patterned first inorganic insulating layer 13 when the patterned first inorganic insulating layer 13 is formed through the first barrier wall group 11, it not only omits the exposure, development, etching, and peeling processes during the formation of the conventional patterned inorganic insulating layer, but also Moreover, no additional process is added, which greatly saves the preparation cost of the display substrate.
  • the two first retaining walls 11 in each first retaining wall group 11 are arranged around a corresponding one of the display areas 101.
  • the first inorganic insulating layer 13 disposed on the surface of the first retaining wall group 11 away from the base substrate 10 is in the two first retaining walls 11 in each first retaining wall group 11
  • the first inorganic insulating layer 13 is divided into a plurality of first inorganic insulating sub-layers 131, each of the first inorganic insulating sub-layers 131 is located in the corresponding display area 101 and the first retaining wall group corresponding to the display area 101 In 11, an area where a first retaining wall 111 is closer to the display area. That is, each display area corresponds to one first inorganic insulating sub-layer 131.
  • the present disclosure does not limit the shape of the orthographic projection of the two first retaining walls 111 in each first retaining wall group 11 on the base substrate 10, as long as they are arranged in a closed shape around the display area.
  • the shape of the orthographic projection of each first retaining wall 111 of the plurality of first retaining wall groups 11 on the base substrate 10 is the same, for example, two first retaining wall groups 11 in each first retaining wall group 11 have the same shape.
  • the shape of the orthographic projection of a retaining wall 111 on the base substrate 10 is a closed rectangular ring, a circular ring, or an irregular closed ring.
  • the shape of the orthographic projection of the two first retaining walls 111 in each first retaining wall group 11 on the base substrate 10 is a closed rectangular ring shape as an example.
  • the shapes of the orthographic projections of the plurality of first retaining walls 111 of the plurality of first retaining wall groups 11 on the base substrate 10 are not completely the same, which can be based on the requirements of each display substrate in the display substrate mother board. Make settings.
  • "not exactly the same” means that some are the same and some are not the same; or all are not the same.
  • the orthographic projection of two first retaining walls in the same first retaining wall group 11 on the base substrate 10 has the same shape, and the first retaining walls 111 in different first retaining wall groups 11 are lining The shape of the orthographic projection on the base substrate 10 is different.
  • the orthographic projections of the two first retaining walls in each first retaining wall group 11 on the base substrate 10 are different in shape, for example, one of the first retaining walls in each first retaining wall group 11
  • the shape of the orthographic projection of the barrier wall 111 on the base substrate 10 is a closed rectangular ring shape, and the shape of the orthographic projection of the other first barrier wall 111 on the base substrate 10 is a closed ring shape.
  • the present disclosure does not limit the size of each first retaining wall 111, and the size of the first retaining wall 111 can be set according to the use of the display substrate.
  • the sizes of the plurality of first retaining walls 111 may be completely the same or not.
  • the two first retaining walls 11 in the same first retaining wall group 11 can prevent the material used to form the inert material layer 12 filled between them from overflowing, that is, as long as they are installed in the same first retaining wall 11
  • the orthographic projection of the inert material layer 12 between the two first retaining walls 111 in the retaining wall group 11 on the base substrate 10 does not overlap with the orthographic projection of any one of the first retaining walls 111 on the base substrate 10. .
  • the size of the first retaining wall 111 along the thickness direction of the base substrate 10 is 0.5-5 ⁇ m, and the size of the first retaining wall 111 along the direction perpendicular to the thickness of the base substrate 10 is 5-30 ⁇ m.
  • the two first retaining walls 111 in each first retaining wall group 11 are arranged at intervals, that is, the two first retaining walls in each first retaining wall group 11 have a first distance between them.
  • the size of the gap is not limited.
  • the first distance between the two first retaining walls 111 in each first retaining wall group 11 is 20-300 ⁇ m.
  • the first distance between the two first retaining walls 111 in each first retaining wall group 11 is equal.
  • the first distance between the two first retaining walls 111 in different first retaining wall groups 11 may not be completely equal.
  • "not completely equal” refers to partial equal, partial unequal; or, all unequal.
  • first barrier wall there is a second distance between the first barrier wall closest to the display area 101 and the edge of the display area 101 in each first barrier wall group 11, and a first inorganic insulating layer is disposed in the second distance.
  • the present disclosure does not limit the size of the second pitch, as long as the first inorganic insulating layer disposed in the second pitch can protect the light emitting device 23 in the display substrate, that is, prevent water and oxygen from passing through.
  • the first retaining wall invades into the display substrate and affects the light-emitting device.
  • the range of the second distance between the first barrier wall 111 closest to the display area 101 and the edge of the display area 101 in each first barrier wall group 11 is 15-300 ⁇ m.
  • the second spacing between the first retaining wall 111 closest to the display area 101 and the edge of the display area 101 among the two first retaining walls 111 in each first retaining wall group 11 is equal .
  • the second distance between a first retaining wall 111 closest to a corresponding display area 101 in different first retaining wall groups 11 and the edge of the display area 101 may not be completely equal.
  • the minimum distance between the surface of the inert material layer 12 away from the base substrate 10 and the base substrate 10 in the thickness direction of the base substrate 10 is not greater than that of the first retaining wall 111 away from the substrate.
  • the surface of the substrate 10 has a maximum distance from the base substrate 10 in the thickness direction of the base substrate 10.
  • the material formed by the inert material layer 12 is an organic material whose end groups are inert groups, and the material does not react with any chemical groups.
  • the raw material of the inert material layer 12 is a first organic material
  • the first organic material may be an existing film layer in contact with the base substrate 10 or with the first retaining wall 111 near the surface of the base substrate 10.
  • the group undergoes a hydrolysis reaction or alcoholysis reaction to generate an inert group under normal temperature and normal pressure, thereby forming the inert material layer 12.
  • the first organic material includes one of vinyl triethoxy silane, vinyl triacetoxy silane, and chloromethyl triethoxy silane.
  • the first organic material is filled between the two first retaining walls 111 in the first retaining wall group 11, and the first The -(OEt) 3 group connected to Si in the molecular formula of the organic material can undergo a hydrolysis reaction with the existing -OH on the base substrate 10 to form an inert group
  • an inert material layer 12 is obtained.
  • the reaction process can be expressed as:
  • Et represents an ethyl group.
  • the existing -OH on the base substrate 10 comes from water vapor during the preparation of the display substrate, or the surface of the base substrate 10 close to the first retaining wall 111 is pretreated to make it have active -OH.
  • the existing -OH on a film layer in contact with the surface of the first retaining wall 111 close to the base substrate 10 comes from water vapor during the preparation of the film layer, or the surface of the film layer away from the base substrate 10 is pre-prepared. Treatment to make it have active -OH.
  • the material of the inert material layer 12 is a second organic material, and the end groups of the second organic material are all inert groups.
  • the second organic material includes polystyrenes (such as polystyrene or polymethylstyrene, etc.), polyethylene oxides (such as polyethylene oxide or polypropylene oxide, etc.), polymethyl One of methyl acrylate (for example, polymethyl methacrylate or polybutyl methacrylate, etc.) and polyvinylpyrrolidone (for example, polyvinyl chloride or polyvinylpyrrolidone, etc.).
  • polystyrenes such as polystyrene or polymethylstyrene, etc.
  • polyethylene oxides such as polyethylene oxide or polypropylene oxide, etc.
  • polymethyl One of methyl acrylate for example, polymethyl methacrylate or polybutyl methacrylate, etc.
  • polyvinylpyrrolidone for example, polyvinyl chloride or polyvinylpyrrolidone, etc.
  • the display substrate mother board further includes at least one sub-retaining wall 112. At least one sub-retaining wall 112 is located in the area between two first retaining walls 111 in at least one first retaining wall group 11; at least one sub-retaining wall 112 and two first retaining walls 111 are arranged on the same layer, and an inert material layer 12 Cover each sub-retaining wall 112.
  • At least one sub-retaining wall 112 is provided between the two first retaining walls 111 in each first retaining wall group 11.
  • At least one sub-retaining wall 112 is provided between the two first retaining walls 111 in part of the first retaining wall group 11.
  • the number of sub-retaining walls 112 between the two first retaining walls 111 in the first retaining wall group 11 is one. In other examples, as shown in FIGS. 5A and 5B, the number of sub-retaining walls 112 between the two first retaining walls 111 in the first retaining wall group 11 is multiple, and there are multiple sub-retaining walls 112. Interval settings.
  • the present disclosure does not limit the size of the sub-retaining wall 112, and the size of the sub-retaining wall 112 can be set according to actual conditions. In the case where there are multiple sub-retaining walls 112, the sizes of the multiple sub-retaining walls 112 may be completely the same or not.
  • the size of the sub-retaining wall 112 along the thickness direction of the base substrate 10 and the size along the direction perpendicular to the thickness of the base substrate 10 have no absolute relationship with the corresponding size of the first barrier wall 111.
  • the size of the sub-retaining wall 112 along the thickness direction of the base substrate 10 is less than or equal to the size of the first barrier wall 111 in the thickness direction of the base substrate 10. In this way, the sub-retaining wall 112 can be prevented from affecting the display substrate.
  • the overall thickness is less than or equal to the size of the first barrier wall 111 in the thickness direction of the base substrate 10.
  • the size of the sub-blocking wall 112 along the thickness direction of the base substrate 10 ranges from 0.5 to 2.5 ⁇ m, and the size of the sub-blocking wall 112 along the direction perpendicular to the thickness of the base substrate 10 ranges from 5 to 15 ⁇ m.
  • the present disclosure does not limit the size of the third distance between two adjacent sub-retaining walls 112.
  • the range of the third distance between two adjacent sub-retaining walls 112 is 5-15 ⁇ m.
  • the overflow of the material used to form the inert material 12 can be further avoided, and the inert material layer 12 can be added at the same time. Shows the stability on the substrate.
  • a plurality of first retaining walls 111 and a plurality of sub-blocking walls 112 with different heights can be fabricated by using a halftone mask.
  • the first barrier wall group 11 is disposed on the surface of the base substrate 10.
  • the base substrate 10 has at least one groove 113 on the surface close to the first barrier wall group 11, and the at least one The groove 113 is located in the area between the two first retaining walls 111 in the first retaining wall group 11, and the inert material layer 12 covers the at least one groove 113.
  • the base substrate 10 includes a base 01 and a buffer layer 02 disposed between the base 01 and the first retaining wall 111 in a stack.
  • the groove 113 is provided on the surface where the buffer layer 02 is in contact with the first retaining wall 111. As another example, as shown in FIG. 6C, the groove 113 penetrates the buffer layer 02 and is disposed on the surface of the substrate 01.
  • the material of the substrate 01 is, for example, glass or polyimide (PI for short).
  • the material of the buffer layer 02 is, for example, silicon nitride (SiN x ), silicon oxide (SiO x ), or aluminum oxide (Al 2 O 3 ).
  • the display substrate mother board 100 further includes a dielectric layer 25 disposed between the base substrate 10 and the first wall group 11, and the first wall group 11 is disposed on the dielectric layer.
  • the layer 25 is away from the surface of the base substrate 10, and the surface of the dielectric layer 25 away from the base substrate 10 has at least one groove 113.
  • the dielectric layer 25 is the above-mentioned film layer that is in contact with the surface of the first retaining wall 111 close to the base substrate 10.
  • the dielectric layer 25 is a gate insulating layer.
  • the material of the gate insulating layer is, for example, any one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the dielectric layer 25 is an interlayer dielectric layer.
  • the material of the interlayer insulating layer 15 is, for example, any one of polybenzobisoxazole, photosensitive polyimide, styrene-acrylic cyclobutene, or inorganic materials.
  • at least one groove 113 is provided on the surface of the base substrate 10 or the surface of the dielectric layer 25 between the two first barrier walls 111 in each first barrier wall group 11.
  • At least one groove 113 is provided on the surface of the base substrate 10 or the surface of the dielectric layer 25 between the two first barrier walls 111 in a part of the first barrier wall group 11.
  • the number of grooves 113 on the surface of the base substrate 10 or the surface of the dielectric layer 25 located between the two first retaining walls 111 in the first retaining wall group 11 is one.
  • the number of grooves 113 on the surface of the base substrate 10 or the surface of the dielectric layer 25 between the two first retaining walls 111 in the first retaining wall group 11 is multiple, and there are multiple recesses.
  • the grooves 113 are arranged at intervals.
  • the present disclosure does not limit the size of the groove, and the size of the groove 113 can be set according to actual conditions.
  • the sizes of the multiple grooves 113 may be completely the same or not.
  • the size of the groove 113 along the thickness direction of the base substrate 10 ranges from 0.5 ⁇ m to 2.5 ⁇ m.
  • the size of the groove 113 along the direction perpendicular to the thickness of the base substrate 10 ranges from 5 to 15 ⁇ m.
  • the present disclosure deals with two adjacent ones.
  • the size of the fourth distance between the grooves 113 is not limited.
  • the range of the fourth distance between adjacent grooves 113 is 5-15 ⁇ m.
  • the groove 113 is formed by a dry etching process.
  • the display substrate mother board 100 further includes an organic encapsulation layer 134 disposed between the first inorganic encapsulation layer 132 and the second inorganic encapsulation layer 133.
  • the organic encapsulation layer 134 is located in the plurality of display areas 101.
  • the organic encapsulation layer 134 can prevent the inorganic particles in the first inorganic encapsulation layer 132 from affecting the preparation of the second inorganic encapsulation layer 133, and prevent the film of the second inorganic encapsulation layer 133 from cracking, that is, the organic encapsulation layer 134 can interfere with the first inorganic encapsulation layer 133.
  • the inorganic encapsulation layer 132 has a planarization effect.
  • the material of the organic encapsulation layer 134 is acrylic, for example.
  • the display substrate mother board 100 further includes a plurality of barrier dams 32 disposed on the base substrate 10, and at least one barrier dam 32 is disposed near the first retaining wall group 11 One side of the display area 101, and each barrier dam 32 is arranged around the display area 101. Since the organic material of the organic encapsulation layer 134 has certain fluidity, the barrier dam 32 can prevent the organic material of the organic encapsulation layer 134 from overflowing. In some examples, each display area 101 is surrounded by at least one barrier dam 32.
  • each display area 101 is surrounded by a barrier dam 32.
  • each display area 101 is surrounded by multiple barrier dams 32, and the multiple barrier dams 32 may be connected end to end or not connected, as long as the multiple barrier dams 32 are combined to surround one display area 101.
  • part of the display area 101 of the multiple display areas 101 is surrounded by a barrier dam 32, and the part of the display area 101 is surrounded by a combination of multiple barrier dams 32.
  • the present disclosure does not limit this, and can be set according to the requirements of each display substrate in the display substrate motherboard 100.
  • the at least one barrier dam 32 corresponding to each display area 101 includes a first barrier dam 321 and a distance perpendicular to the thickness of the base substrate 10 from the first barrier dam 321.
  • the second barrier dams 322 are arranged at intervals in the direction.
  • the first barrier dam 321 is arranged around the display area 101 in a circle, and the second barrier dam 322 is arranged around the first barrier dam 321 in a circle.
  • the minimum distance from the surface of the second barrier dam 322 away from the base substrate 10 along the thickness direction of the base substrate 10 to the base substrate 10 is greater than that of the surface of the first barrier dam away from the base substrate 10 along the substrate 10
  • the minimum distance from the surface of the second barrier dam 322 away from the base substrate 10 along the thickness direction of the base substrate 10 to the base substrate 10 can also be less than or equal to the surface of the first barrier dam 321 away from the base substrate 10 along the substrate 10
  • the minimum distance from the thickness direction of the substrate 10 to the base substrate 10 is not limited in the present disclosure, as long as the first barrier dam 321 and the second barrier dam 322 are spaced apart.
  • first barrier dam 321 and the second barrier dam 322 are both disposed on the surface of the dielectric layer 25.
  • the first barrier dam 321 and the second barrier dam 322 with different heights can be made by using a halftone mask.
  • the first barrier dam 321, the second barrier dam 322 and the pixel defining layer are arranged in the same layer.
  • the first barrier dam 321, the second barrier dam 322, and the pixel defining layer can be formed by masking, exposing, etching, and other processes based on a unified film layer. In this way, the manufacturing process of the display substrate can be simplified.
  • the first barrier dam 321 is provided on the surface of the dielectric layer 25, another film layer is provided on the surface of the dielectric layer at a position corresponding to the second barrier dam 322, and the second barrier dam 322 is provided on the surface of the other film layer. Surface, so that the height of the first barrier dam 321 is smaller than the height of the second barrier dam 322.
  • the height of the first barrier dam 321 is the minimum distance from the surface of the first barrier dam 321 away from the base substrate 10 along the thickness direction of the base substrate 10 to the base substrate 10; the height of the second barrier dam 322 is It is the minimum distance from the surface of the second barrier dam 322 away from the base substrate 10 to the base substrate 10 along the thickness direction of the base substrate 10.
  • the arrangement of the second barrier dam 322 spaced apart from the first barrier dam 231 can further prevent the organic encapsulation layer from overflowing out of the first sub-barrier dam 321.
  • the material overflowing the organic encapsulation layer of the first sub-barrier dam 321 may flow into the area between the adjacent first barrier dam 231 and the second barrier dam 322.
  • the present disclosure does not limit the material of the barrier dam 32, and the material of the barrier dam 32 is determined according to the formation process of the barrier dam 32. For example, if the barrier dam 32 and the pixel defining layer are formed synchronously, the material of the barrier dam 32 and the material of the pixel defining layer are the same material.
  • the display substrate mother board 100 further includes a plurality of second wall groups 41 disposed on the base substrate 10.
  • the orthographic projections of the plurality of second retaining wall groups 41 on the base substrate 10 do not overlap with the orthographic projections of the plurality of first retaining wall groups 11 on the base substrate 10.
  • Each second retaining wall group 41 includes at least two adjacent second retaining walls 411, and a space is formed between at least two adjacent second retaining walls 411.
  • the display substrate mother board 100 further includes a second inorganic insulating layer 14 disposed on the side of the second barrier wall group 41 away from the base substrate 10, and at least one of the second inorganic insulating layers 14
  • the via 142 and the spacer overlap the orthographic projection of a via 142 on the base substrate 10.
  • each second retaining wall group 41 includes two second retaining walls 411 with a space between the two second retaining walls 411.
  • the shapes of the orthographic projection of the two second retaining walls 411 on the base substrate 10 are block shapes, respectively.
  • the orthographic projection of the two second retaining walls 411 on the base substrate 10 has the same shape.
  • the shapes of the orthographic projections of the two second retaining walls 411 on the base substrate 10 are different.
  • the present disclosure does not limit the number of second retaining walls 411 in each second retaining wall group 41 and the shape of the orthographic projection of each second retaining wall on the base substrate 10, as long as each second retaining wall At least two adjacent second retaining walls 411 in the group 41 can form a spacer.
  • the number of the second retaining walls 411 in each second retaining wall group 41 is equal, and the shape of the orthographic projection of each second retaining wall 411 on the base substrate 10 is the same.
  • the number of second retaining walls 411 in each second retaining wall group 41 is not completely the same, and the shape of the orthographic projection of each second retaining wall 411 on the base substrate 10 is not completely the same.
  • the second retaining wall group 41 includes a plurality of second retaining walls 411, and the plurality of second retaining walls 411 are connected end to end to form a closed shape with a partition in the middle.
  • the second retaining wall group 41 includes four second retaining walls 411, and the shape of the orthographic projection of each second retaining wall 411 on the base substrate 10 is a long strip.
  • the two retaining walls 411 are connected end to end to form a closed rectangular ring with a partition in the middle.
  • it can also be encircled in a circular ring shape, which is not limited in the present disclosure.
  • the second retaining wall group 41 includes two second retaining walls 411, the two second retaining walls 411 are arranged at intervals, and the shape of the orthographic projection of each second retaining wall 411 on the base substrate 10 is a block shape. , A compartment is formed between the two second retaining walls 411.
  • an inert organic film layer is formed in the spacer area; then when the inorganic insulating film is deposited on the side of the second barrier wall group 41 away from the base substrate 10, since the inorganic insulating film does not chemically react with the inert organic film layer, it cannot be attached On the inert organic film layer, a via 142 is formed in the spacer region on the second inorganic insulating layer 14 (as shown in FIG. 9).
  • the first conductive layer 151 and the first conductive layer 151 respectively disposed on the side of the second inorganic insulating layer 14 away from the base substrate 10 can be realized by the via holes 142 disposed on the second inorganic insulating layer 14.
  • the inert organic film layer can be formed by the above-mentioned first organic material or the second organic material, and the formation process thereof is the same as the above-mentioned, and will not be repeated here.
  • the display substrate mother board 100 further includes an active layer 26 disposed on the base substrate, and the gate insulating layer 251 is disposed on the side of the active layer 26 away from the base substrate 10.
  • the display substrate mother board 100 further includes a source and drain metal layer 27 disposed on the side of the interlayer dielectric layer 252 away from the base substrate 10, and a gate 28 disposed between the gate insulating layer 251 and the interlayer dielectric layer 252.
  • the second retaining wall group 41 is arranged in the display area 101, and the second retaining wall group 41 can be arranged on the same layer as the active layer 26, that is, each second retaining wall 411 in the second retaining wall group 41 is connected to
  • the active layer 26 is formed by the same patterning process.
  • the material of the active layer 26 includes polysilicon (p-Si).
  • the second barrier wall 411 is disposed on the side of the active layer 26 away from the base substrate 10.
  • the active layer 26 and the second retaining wall 411 with different heights can be fabricated through a halftone mask.
  • the interlayer dielectric layer 252 when the interlayer dielectric layer 252 is deposited on the side of the second barrier wall 411 away from the substrate, the interlayer dielectric layer 252 can form vias, so that the source and drain provided on the side of the interlayer dielectric layer 252 away from the base substrate 10
  • the metal layer 27 can be electrically connected to the active layer 26 through the via 142.
  • the second inorganic insulating layer 14 includes the aforementioned interlayer dielectric layer 252.
  • the second inorganic insulating layer may also be another film layer in the mother board of the display substrate.
  • the present disclosure does not limit the position of the second retaining wall group 41 in the display substrate motherboard.
  • the position of the second retaining wall group 41 in the display substrate motherboard can be based on the requirements of each display substrate and each display substrate.
  • the via holes on the second inorganic insulating layer 14 in the substrate need to be set.
  • the second inorganic insulating layer 14 is divided into a plurality of second inorganic insulating sub-layers 141, and each display area 101 Corresponds to a second inorganic insulating sub-layer 141.
  • some embodiments of the present disclosure further provide a display substrate 1000, which includes a portion obtained by cutting along a cutting line in the cutting area 102 of the display substrate mother board 100 of any of the foregoing embodiments.
  • a laser cutting process may be used to cut the display substrate mother board 100.
  • the structures of the multiple display substrates 1000 obtained by cutting may be completely the same or not, depending on the manufacturing process of the display substrate mother board 100.
  • the display substrate 1000 has a display area 101, the display substrate 1000 includes a base substrate 10, a first retaining wall 111 disposed on the base substrate 10, and the first retaining wall 111 is located On at least one side of the display area 101, and on any side of the display area 101 where the first barrier wall 111 is provided, there is a fifth distance between the first barrier wall 111 and the edge of the base substrate 10.
  • the fifth distance between the first retaining wall 111 and the edge of the base substrate 10 is equal.
  • the fifth distance between the first retaining wall 111 and the edge of the base substrate 10 is not completely equal.
  • the size of the fifth distance between the first retaining wall 111 and the edge of the base substrate 10 depends on the size of the fifth distance between the first retaining wall 111 and the edge of the base substrate 10 The distance between the cutting lines on different sides of the display area 10 and the first retaining wall 111.
  • the display substrate 1000 further includes an inert material layer 12 arranged between the first barrier wall 111 and the edge of the base substrate 10, and a first inorganic insulating sub-layer 131 arranged on the side of the first barrier wall 111 away from the base substrate 10
  • the first inorganic insulating sub-layer 131 is also located in the display area 101; on either side of the display area 101 where the first barrier 111 is provided, the orthographic projection of the edge of the first inorganic insulating sub-layer 131 on the base substrate 10 is located in the first barrier.
  • the wall 111 is within the orthographic projection range on the base substrate 10.
  • the first retaining wall 111 is arranged around the display area 101, and the orthographic projection of each edge of the first inorganic insulating sub-layer 131 on the base substrate 10 is located on the first retaining wall 111. Within the orthographic projection range on the base substrate 10.
  • the display substrate 1000 is an organic light emitting diode (OLED) display substrate.
  • OLED organic light emitting diode
  • the display substrate 1000 is a Quantum Dot Light Emitting Diodes (QLED for short) display substrate.
  • QLED Quantum Dot Light Emitting Diodes
  • the display substrate 1000 of the present disclosure may also be other types of display substrates, and the present disclosure does not limit this, and the structure of the display substrate can be adjusted according to the use of the display substrate.
  • the display substrate 1000 further includes a plurality of light emitting devices 23 and a pixel driving circuit electrically connected to each light emitting device 23.
  • each pixel driving circuit includes at least one driving transistor, one switching transistor, and one storage capacitor.
  • each light emitting device 23 includes a first electrode 231, a light emitting function layer 232, and a second electrode 233 that are stacked.
  • the first electrode 231 is an anode
  • the second electrode 233 is a cathode.
  • the first electrode 231 is a cathode
  • the second electrode 233 is an anode.
  • the pixel defining layer 24 of the display substrate 1000 has a plurality of opening areas, and each light-emitting device 23 is disposed corresponding to one opening area.
  • the light-emitting functional layer 232 is an organic light-emitting functional layer.
  • the light-emitting functional layer 232 is a quantum dot light-emitting functional layer.
  • some embodiments of the present disclosure further provide a display device 1, including the display substrate 1000 of any of the above-mentioned embodiments.
  • the display device 1 can be used as a display, a TV, a digital camera, a mobile phone, a tablet computer, an augmented reality (AR)/virtual reality (VR) product or other products or components with any display function.
  • AR augmented reality
  • VR virtual reality
  • the embodiment does not specifically limit the use of 1 display device 1.
  • the display device 1 includes a display panel 1000, a frame 1001, a cover plate, a circuit board, and the like.
  • the display device 1 may include more or fewer components, and the relative positions between these components may be changed.
  • the circuit board is configured to provide the display panel 1000 with signals required for display.
  • the circuit board is a printed circuit board assembly (Printed Circuit Board Assembly, PCBA), and the PCBA includes a printed circuit board (Printed Circuit Board, PCB) and a timing controller (TCON) set on the PCB, and power management integration Circuits (Power Management IC, PMIC) and other ICs or circuits, etc.
  • the display device has the same description and technical effects as the aforementioned display substrate, and will not be repeated here.
  • Some embodiments of the present disclosure provide a method for preparing a display substrate, as shown in FIG. 12, including S10-S50.
  • the base substrate 10 has a plurality of display areas 101, a plurality of display substrate areas 103, and a cutting area 102 located at the periphery of the plurality of display areas; a display area 101 is located in a corresponding display substrate area 103, and the cutting area 102 is connected to The display substrate area 103 has no overlap.
  • a first barrier wall group 11 including two first barrier walls 111 is formed on the base substrate 10 and located on at least one side of each display area. And the area between the two first retaining walls 111 in each first retaining wall group 11 is located in the cutting area 102 corresponding to the first retaining wall group 11.
  • the plurality of first retaining walls 111 and the flat layer 22 are formed by the same patterning process.
  • the plurality of first retaining walls 111 and the pixel defining layer 24 are formed by the same patterning process.
  • an inert material layer 12 is formed in an area between the two first retaining walls 111 in each first retaining wall group 11.
  • S30 includes S302.
  • the process of filling the area between the two first retaining walls 11 in each first retaining wall group 11 with the first organic material is not limited, as long as the first organic material is only filled in each first retaining wall.
  • the area between the two first retaining walls 11 in the wall group 11 is sufficient.
  • an inkjet printing process is used to fill the area between the two first retaining walls 11 in each first retaining wall group 11 with a first organic material, and perform a baking and curing process.
  • the first retaining wall group 11 is located on the surface of the base substrate 10. Based on this, before S302, S30 further includes S301.
  • the present disclosure does not limit the process for pre-processing the surface of the base substrate 10, as long as the process can realize that the surface of the base substrate 10 has hydroxyl groups.
  • a plasma surface treatment method is used to preprocess the surface of the base substrate 10 so that the surface of the base substrate 10 has active hydroxyl groups.
  • the surface of the base substrate 10 is pretreated by the method of ultraviolet light irradiation, so that the surface of the base substrate 10 has active hydroxyl groups.
  • the preparation method of the display substrate before S20, further includes S11.
  • a gate insulating layer is formed on the base substrate 10.
  • an interlayer dielectric layer is formed on the base substrate.
  • S30 also includes S301'.
  • pretreatment is performed on the surface of the dielectric layer 25 away from the base substrate 10, so that the surface of the dielectric layer 25 away from the base substrate 10 has hydroxyl groups, so that the first organic material is filled with the hydroxyl groups.
  • the reaction forms an inert material layer 12.
  • the process of preprocessing the surface of the dielectric layer 25 away from the base substrate 10 is the same as the process of preprocessing the surface of the base substrate 10 in S301.
  • the process of pretreating the surface of the dielectric layer 25 away from the base substrate 10 may also adopt a plasma surface treatment method or an ultraviolet light irradiation method.
  • a plasma surface treatment method is used to preprocess the surface of the base substrate 10 so that the surface of the base substrate 10 has active hydroxyl groups.
  • the surface of the base substrate 10 is pretreated by the method of ultraviolet light irradiation, so that the surface of the base substrate 10 has active hydroxyl groups.
  • S30 includes S302'.
  • a first inorganic insulating layer 13 is formed on a side of the plurality of first barrier wall groups 11 away from the base substrate 10.
  • the present disclosure does not limit the process of forming the first inorganic insulating layer 13.
  • the first inorganic insulating layer 13 is formed by a chemical vapor deposition (chemical vapor deposition, CVD) process.
  • the first inorganic insulating layer 13 is formed by an atomic layer deposition (Atomic Layer Deposition, ALD for short) process.
  • ALD atomic layer deposition
  • the first inorganic insulating layer 13 is formed on the side of the first barrier group 11 away from the base substrate 10, and the process includes as follows:
  • the material of the inert material layer 12 is an inert organic material.
  • the Al 2 O 3 precursor, trimethyl aluminum is not It chemically reacts with inert organic materials, and therefore, the precursor trimethylaluminum cannot be attached to the inert material layer 12.
  • the gas in the vacuum device is evacuated, and an inert gas is passed into the vacuum device to blow away the unreacted precursor, and then the atmosphere in the vacuum device is restored to vacuum, and so on, until the precursor trimethyl aluminum
  • the thickness reaches the design requirement of Al 2 O 3.
  • the thickness of the inert material layer 12 is related to the use of the display substrate.
  • the thickness of the inert material layer 12 ranges from 1 to 10 ⁇ m.
  • the surface of the inert material layer 12 away from the base substrate 10 is in a direction along the thickness of the base substrate 10, and the distance from the base substrate 10 is smaller than the surface of the first inorganic insulating layer 12 away from the base substrate 10 The distance from the base substrate 10 in the direction of the thickness of the base substrate 10. In this way, forming the inert material layer 12 on the side of the first barrier wall group 11 away from the base substrate 10 will not affect the overall thickness of the display substrate.
  • the display substrate mother board 100 is cut using a laser cutting process.
  • the method for preparing the above-mentioned display substrate further includes S60.
  • a plurality of barrier dams 32 are formed on the base substrate 10; each display area 101 is surrounded by at least one barrier dam 32, and the at least one barrier dam 32 is disposed near the first barrier wall group 11 corresponding to the display area 101 One side of the display area 101.
  • a plurality of first barrier dams 321 and a plurality of second barrier dams 322 are formed on the base substrate 10.
  • S60 includes performing S601 while performing S11.
  • S601 Fabricate the first barrier dam 321 and the second barrier dam 322 with different heights through a halftone mask. That is, at the same time as the dielectric layer is formed, a plurality of barrier dams 32 are formed.
  • a plurality of barrier dams 32 are formed.
  • a plurality of barrier dams 32 are formed.
  • the method for preparing the above-mentioned display substrate further includes S70.
  • each display substrate area 103 on the base substrate 10 at least one second retaining wall group 41 is formed, and each second retaining wall group 41 includes at least two adjacent second retaining walls 411, and at least A spacer area is formed between two adjacent second retaining walls 411; the orthographic projection of at least one second retaining wall group 41 on the base substrate 10 and the orthographic projection of the first retaining wall group 11 on the base substrate 10 No overlap.
  • the second barrier wall group 41 and the active layer are formed by the same patterning process using a halftone mask.
  • S80 includes S802.
  • S802 Fill each interval area with a first organic material to form an inert organic film layer.
  • an inkjet printing process is used to fill each compartment with the first organic material, and perform a baking and curing process.
  • the second barrier wall group 41 is in the same layer as the active layer, and the second barrier wall group 41 is located on the surface of the active layer away from the base substrate 10. Based on this, before S802, S80 further includes S801.
  • S80 includes S802'.
  • a plasma surface treatment method is used to preprocess the surface of the active layer away from the base substrate 10 so that the surface of the active layer away from the base substrate 10 has active hydroxyl groups.
  • the surface of the active layer away from the base substrate 10 is pretreated by the method of ultraviolet light irradiation, so that the surface of the active layer away from the base substrate 10 has active hydroxyl groups.
  • the second inorganic insulating layer 14 is formed using a CVD process.
  • the second inorganic insulating layer 14 is formed using an ALD process.
  • the process of forming the second inorganic insulating layer 14 is the same as the process of forming the first inorganic insulating layer 13.
  • the second inorganic insulating film layer 14 is not deposited on the surface of the inert organic film layer away from the base substrate, so that the second inorganic The insulating layer 14 forms through holes at positions corresponding to the spacers.
  • the second inorganic insulating layer 14 is the aforementioned interlayer dielectric layer. Based on this, when S11 is to form an interlayer dielectric layer on the base substrate 10, S90 and S11 are performed simultaneously.
  • an ashing process is used to remove the inert organic film layer formed in each compartment.
  • other process methods can also be used to remove the inert organic film, which is not limited in the present disclosure.
  • a source/drain metal layer is deposited on the surface of the second inorganic insulating layer 14 away from the base substrate 10.
  • the source/drain metal layer is filled in the via holes of the second inorganic insulating layer 14 during the deposition process.
  • the source and drain metal layers are connected to the active layer.
  • the deposition process of the source and drain metal layers may be a CVD process or an ALD process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板母板，具有多个显示区和位于所述多个显示区之间的切割区；所述显示基板母板包括衬底基板、多个第一挡墙组、惰性材料层和第一无机绝缘层。多个第一挡墙组设置于所述衬底基板上；每个第一挡墙组位于对应的一个显示区的至少一侧，每个第一挡墙组包括间隔设置的两个第一挡墙，且所述两个第一挡墙之间的区域位于所述切割区；惰性材料层设置于所述两个第一挡墙之间的区域；第一无机绝缘层设置于所述多个第一挡墙组远离所述衬底基板一侧，所述第一无机绝缘层还位于所述多个显示区；所述第一无机绝缘层在所述衬底基板上的正投影与所述惰性材料层在所述衬底基板上的正投影无重叠。

Description

显示基板母板、显示基板及其制备方法、显示装置
本申请要求于2020年1月23日提交的、申请号为202010076888.2的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板母板、显示基板及其制备方法、显示装置。
背景技术
显示基板包括多个经过图案化处理的无机绝缘层。
目前，现有技术制备图案化的无机绝缘层的方法包括：光刻工艺；或者，在事先备好的模板中形成无机绝缘层，再将无机绝缘层与模板分离开来，以得到具有一定图案的无机绝缘层。
公开内容
第一方面，提供一种显示基板母板，具有多个显示区和位于所述多个显示区之间的切割区；所述显示基板母板包括衬底基板、多个第一挡墙组、惰性材料层和第一无机绝缘层。多个第一挡墙组设置于所述衬底基板上；每个第一挡墙组位于对应的一个显示区的至少一侧，每个第一挡墙组包括间隔设置的两个第一挡墙，且所述两个第一挡墙之间的区域位于所述切割区；惰性材料层设置于所述两个第一挡墙之间的区域；第一无机绝缘层设置于所述多个第一挡墙组远离所述衬底基板一侧，所述第一无机绝缘层还位于所述多个显示区；所述第一无机绝缘层在所述衬底基板上的正投影与所述惰性材料层在所述衬底基板上的正投影无重叠。
在一些实施例中，所述两个第一挡墙均围绕对应的显示区一周设置；所述第一无机绝缘层包括多个无机绝缘子层，每个无机绝缘子层位于对应的显示区以及与该显示区对应的所述第一挡墙组所在区域。
在一些实施例中，所述显示基板母板还包括：至少一个子挡墙，所述至少一个子挡墙位于至少一个第一挡墙组中的所述两个第一挡墙之间的区域；所述至少一个子挡墙与所述两个第一挡墙同层设置；所述惰性材料层覆盖所述至少一个子挡墙。
在一些实施例中，所述第一挡墙组设置于所述衬底基板的表面，所述衬底基板靠近所述第一挡墙组的表面具有至少一个凹槽；所述至少一个凹槽位于所述两个第一挡墙之间的区域；所述惰性材料层覆盖所述至少 一个凹糟；或，所述显示基板母板还包括：设置于所述衬底基板与所述第一挡墙组之间的介电层；所述第一挡墙组设置于所述介电层远离所述衬底基板的表面，且所述介电层远离所述衬底基板的表面具有至少一个凹槽；所述至少一个凹槽位于所述两个第一挡墙之间的区域；所述惰性材料层覆盖所述至少一个凹糟。
在一些实施例中，所述显示基板母板还包括多个第二挡墙组、设置于所述第二挡墙组远离所述衬底基板一侧的第二无机绝缘层和设置于所述第二无机绝缘层中的多个过孔。所述多个第二挡墙组设置于所述衬底基板上，所述多个第二挡墙组在所述衬底基板上的正投影与所述多个第一挡墙组在所述衬底基板上的正投影无重叠；每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；所述间隔区与一个过孔在所述衬底基板上的正投影重叠。
第二方面，提供一种显示基板，具有显示区；所述显示基板包括：衬底基板、设置于所述衬底基板上的第一挡墙、设置于所述第一挡墙与所述衬底基板的边缘之间的惰性材料层、以及设置于所述第一挡墙远离所述衬底基板一侧的第一无机绝缘子层。所述第一挡墙位于所述显示区的至少一侧，且在设置所述第一挡墙的所述显示区的任一侧，所述第一挡墙所述第一挡墙与所述衬底基板的边缘之间具有间距；所述第一无机绝缘子层还位于所述显示区；在设置所述第一挡墙的所述显示区的任一侧，所述第一无机绝缘子层的边缘在所述衬底基板上的正投影位于所述第一挡墙在所述衬底基板上的正投影范围内。
在一些实施例中，所述第一挡墙围绕所述显示区一周设置，且所述第一无机绝缘子层的各边缘在所述衬底基板上的正投影位于所述第一挡墙在所述衬底基板上的正投影范围内。
在一些实施例中，所述显示基板还包括设置于所述衬底基板上且位于所述显示区的平坦层，所述第一挡墙与所述平坦层同层设置；或，所述显示基板还包括设置于所述衬底基板上且位于所述显示区的像素界定层；所述第一挡墙与所述像素界定层同层设置。
在一些实施例中，所述显示基板还包括：设置于所述衬底基板上的至少一个阻隔坝；所述至少一个阻隔坝设置于所述第一挡墙靠近所述显示区的一侧，且所述至少一个阻隔坝均围绕所述显示区设置。
在一些实施例中，所述至少一个阻隔坝包括：第一阻隔坝和与所述第一阻隔坝在沿垂直于所述衬底基板厚度的方向上间隔设置的第二阻隔 坝；所述第一阻隔坝围绕所述显示区一周设置，且所述第二阻隔坝围绕所述第一阻隔坝一周设置，所述第二阻隔坝远离所述衬底基板的表面沿所述衬底厚度的方向到所述衬底基板的最小距离，大于所述第一阻隔坝远离所述衬底基板的表面沿所述衬底基板厚度的方向到所述衬底基板的最小距离。
在一些实施例中，所述显示基板还包括：设置于所述衬底基板上的至少一个第二挡墙组、设置于所述第二挡墙组远离所述衬底基板一侧的第二无机绝缘子层、以及设置于所述第二无机绝缘子层中的至少一个过孔。所述至少一个第二挡墙组在所述衬底基板上的正投影与所述第一挡墙在所述衬底基板上的正投影无重叠；每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；所述间隔区与一个过孔在所述衬底基板上的正投影重叠。
第三方面，提供一种显示装置，包括上述任一实施例所述的显示基板。
第四方面，提供一种如上述任一实施例所述的显示基板的制备方法，包括：提供衬底基板；所述衬底基板具有多个显示区和位于所述多个显示区之间的切割区；在所述衬底基板上且位于每个显示区的至少一侧，形成包括两个第一挡墙的第一挡墙组，且所述两个第一挡墙之间的区域位于所述切割区；在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层；在多个第一挡墙组远离所述衬底基板的一侧形成第一无机绝缘层，所述第一无机绝缘层还位于所述多个显示区；所述第一无机绝缘层在所述衬底基板上的正投影与所述惰性材料层在所述衬底基板上的正投影无重叠；沿所述切割区切割，获得所述显示基板。
在一些实施例中，在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层，包括：向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料，以形成所述惰性材料层。
在一些实施例中，所述第一挡墙组位于所述衬底基板的表面；在向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料之前，形成所述惰性材料层还包括：对所述衬底基板的表面进行预处理，使所述衬底基板的表面具有羟基，以在填充所述第一有机材料后，使所述第一有机材料与羟基反应，形成惰性材料层。
在一些实施例中，所述方法还包括：在所述衬底基板上形成介电层；其中，在向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料之前，形成所述惰性材料层还包括：对所述介电层远离所述衬 底基板的表面进行预处理，使所述介电层远离所述衬底基板的表面具有羟基，以在填充所述第一有机材料后，使所述第一有机材料与羟基反应，形成惰性材料层。
在一些实施例中，所述第一有机材料包括乙烯基三乙氧基硅烷、乙烯基三乙酰氧基硅烷、氯甲基三乙氧基硅烷中的一种。
在一些实施例中，在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层，包括：向每个第一挡墙组中的两个第一挡墙之间的区域填充第二有机材料；所述第二有机材料包括聚苯乙烯、聚环氧乙烷、聚甲基丙烯酸甲酯、聚乙烯吡咯烷酮中的一种。
在一些实施例中，所述方法还包括：在所述衬底基板上形成多个阻隔坝；每个显示区被至少一个阻隔坝围绕，且所述至少一个阻隔坝设置于该显示区对应的所述第一挡墙组靠近所述显示区的一侧。
在一些实施例中，其中，所述衬底基板具有多个显示基板区，一个显示区位于对应的一个显示基板区内，且所述切割区位于所述多个显示基板区之间；所述方法还包括：在所述衬底基板上的每个显示基板区内，形成至少一个第二挡墙组，每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；所述至少一个第二挡墙组在所述衬底基板上的正投影与所述第一挡墙组在所述衬底基板上的正投影无重叠；在所述间隔区内形成惰性有机膜层；在所述显示基板区内且所述至少一个第二挡墙组远离所述衬底基板的一侧形成第二无机绝缘层；去除形成于所述间隔区内的所述惰性有机膜层。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示基板母板的俯视示意图；
图2为根据一些实施例的基于图1中A-A1方向的一种显示基板母板的剖视结构示意图；
图3为根据一些实施例的基于图1中A-A1方向的另一种显示基板的剖视结构示意图；
图4A为根据一些实施例的一种惰性材料层的制备过程示意图；
图4B为根据一些实施例的一种惰性材料层的制备过程示意图；
图4C为根据一些实施例的一种在惰性材料层远离衬底母板的一侧形成第一无机绝缘层的过程示意图；
图5A为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图5B为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图6A为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图6B为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图6C为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图6D为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图7为根据一些实施例的基于图1中A-A1方向的又一种显示基板的剖视结构示意图；
图8为根据一些实施例的一种显示基板的俯视示意图；
图9为根据一些实施例的基于图8中C-C1方向的又一种显示基板的剖视结构示意图；
图10为根据一些实施例的基于图8中B-B1方向的一种显示基板的剖视结构示意图；
图11为根据一些实施例的一种显示装置的俯视结构示意图；
图12为根据一些实施例的一种显示基板的制备方法的流程示意图；
图13为根据一些实施例的一种显示基板的制备过程图；
图14A为根据一些实施例的一种基板的制备过程图；
图14B为根据一些实施例的一种基板的制备过程图；
图15为根据一些实施例的基于图8中B-B1方向的另一种显示基板的剖视结构示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实 施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
应当理解的是，当层或元件被称为在另一层或基板上时，其可以直接在 另一层或基板上，或者也可以存在中间层。
本公开中，“同层”是指采用同一成膜工艺形成用于形成特定图形的膜层，再利用同一掩模板通过构图工艺形成的层结构。其中，构图工艺可能包括曝光、显影和刻蚀工艺，而形成的层结构中的特定图形可以是连续的，也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。本公开示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开一些实施例提供一种显示基板母板100，如图1和图2所示，具有多个显示基板区103、多个显示区101和位于多个显示区101外围的切割区102；一个显示区101位于对应的一个显示基板区103内，且切割区102与显示基板区103无重叠。多个显示区101在显示基板母板100上排布成多行多列。
图1以显示基板母板示出4个显示区101为例进行示意，4个显示区101在显示基板母板上沿X方向排布为2行，沿Y方向排布为2列。切割区102位于每个显示区101的外围。例如，切割区102位于每相邻的两个显示区101之间。又例如，对于位于显示基板母板最外侧的显示区，切割区102位于该显示区101靠近所述显示基板母板的边缘的一侧。在切割区102内沿平行于X方向或平行于Y方向的切割线1021切割后，可得到多个单独的显示基板。
如图1和图2所示，该显示基板母板100包括衬底基板10、设置于衬底基板10上的多个第一挡墙组11。每个第一挡墙组11位于对应的一个显示区101的至少一侧，每个第一挡墙组11包括两个第一挡墙111。每个第一挡墙组11中的两个第一挡墙111同层且间隔设置，且每个第一挡墙组11中的两个第一挡墙111之间的区域位于切割区102。
在一些示例中，如图1所示，每个第一挡墙组11围绕对应的一个显示区101一周设置。在另一些示例中，每个第一挡墙组11设置于对应的一个显示区101的一侧。在又一些示例中，每个第一挡墙组11设置于对应的一个显示区101的相对的两侧或相邻的两侧。当然，也可以是多个 挡墙组11位于同一个显示区101的不同侧，位于同一个显示区101的不同侧的多个挡墙组11可以首尾连接，也可以不连接。本公开对此不作具体限定，只要每个挡墙组11中的两个第一挡墙111间隔设置即可。
该显示基板母板100还包括设置于两个第一挡墙111之间的区域的惰性材料层12和设置于每个第一挡墙组11背离衬底基板10一侧的第一无机绝缘层13，第一无机绝缘层13还位于每个显示区101；第一无机绝缘层12在衬底基板10上的正投影与惰性材料层12在衬底基板10上的正投影无重叠。
每个第一挡墙组11的两个第一挡墙111之间设置惰性材料层12。本公开中，惰性材料层的材料为惰性的有机材料，这样，在第一挡墙组11远离衬底基板10的一侧沉积无机绝缘薄膜时，由于无机绝缘薄膜不与惰性的有机材料发生化学反应，从而无法附着于惰性材料层12上，进而可直接通过沉积工艺得到具有一定图案的第一无机绝缘层13，与现有技术相比，本公开制备图案化的第一无机绝缘层13的工艺过程可省去曝光、显影、刻蚀、剥离等工艺。
在一些实施例中，如图3所示，显示基板母板100包括层叠设置的第一无机封装层132和第二无机封装层133。第一无机封装层132和第二无机封装层133可防止从显示基板母板的远离衬底基板的一侧进入的水汽和氧气进入到显示基板内部，影响显示基板内部的发光器件。第一无机封装层132和第二无机封装层133的材料为无机物，例如氮化硅和/或氧化硅。第一无机封装层132和第二无机封装层133可以采用相同的材料，也可以采用不同的材料。
本公开中，第一无机绝缘层13包括上述的第一无机封装层132和第二无机封装层133，也就是说，本公开中的第一无机绝缘层13可用于显示基板的封装。
由于第一无机绝缘层13在所述衬底基板10上的正投影与惰性材料层12在所述衬底基板10上的正投影不重叠，因此，在对显示基板母板100进行切割以形成多个显示基板时，可在第一挡墙组11中的两个第一挡墙111之间的区域进行切割，这样，实际切割的是有机的惰性材料层12。由于有机材料的柔韧性大于无机材料的柔韧性，因此，可以改善切割时无机绝缘材料crack的问题。
同时，若采用掩模板(mask)的方法形成第一无机绝缘层13，无机绝缘薄膜的成膜区域远远大于第一无机绝缘层13的设计尺寸，这会导致 第一无机绝缘层13的边缘阴影(shadow)过大，在将显示基板应用于显示装置时，不利于显示装置的窄边框设计。本公开通过在第一挡墙组11远离衬底基板的一侧形成图案化的第一无机绝缘层时，不采用mask，进而不会存在边缘shadow，有利于显示装置的窄边框设计。
在一些实施例中，如图3所示，显示基板母板100还包括设置于衬底基板10上且位于显示区101的平坦层22，第一挡墙111与平坦层22同层设置，即，第一挡墙111与平坦层22通过同一次构图工艺形成。示例的，平坦层22的材料包含但不限于聚硅氧烷系、亚克力系或聚酰亚胺系材料。
在另一些实施例中，如图3所示，显示基板母板100还包括设置于衬底基板10上且位于显示区101的像素界定层24。第一挡墙111与像素界定层24同层设置，即，第一挡墙111与像素界定层24通过同一次构图工艺形成。
在一些示例中，像素界定层24设置于平坦层22远离衬底基板10的一侧。
示例的，像素界定层24的材料为光刻胶。光刻胶包括聚酰亚胺、有机硅烷、聚甲基丙烯酸甲酯类中的一种或多种。
这样，本公开在通过第一挡墙组11形成图案化的第一无机绝缘层13时，不仅省略了常规的图案化的无机绝缘层形成时的曝光、显影、刻蚀、剥离等工艺过程，而且未额外增加任何工艺过程，大大节省了显示基板的制备成本。在一些实施例中，如图1所示，每个第一挡墙组11中的两个第一挡墙11均围绕对应的一个显示区101一周设置。这样，如图2所示，设置于第一挡墙组11远离所述衬底基板10的表面的第一无机绝缘层13在每个第一挡墙组11中的两个第一挡墙11之间断开，使第一无机绝缘层13被分为多个第一无机绝缘子层131，每个第一无机绝缘子层131位于对应的显示区101以及与该显示区101对应的第一挡墙组11中更靠近该显示区的一个第一挡墙111所在的区域。也就是说，每个显示区对应一个第一无机绝缘子层131。
本公开对每个第一挡墙组11中的两个第一挡墙111在衬底基板10上的正投影的形状不进行限定，只要其均呈封闭状围绕显示区一周设置即可。
在一些示例中，多个第一挡墙组11的每个第一挡墙111在衬底基板10上的正投影的形状均相同，例如，每个第一挡墙组11中的两个第一 挡墙111在衬底基板10上的正投影的形状均为封闭的矩形环状、圆形环状或不规则的封闭的环状等。图1以每个第一挡墙组11中的两个第一挡墙111在衬底基板10上的正投影的形状均为封闭的矩形环状进行示例。
在另一些示例中，多个第一挡墙组11的多个第一挡墙111在衬底基板10上的正投影的形状不完全相同，可根据显示基板母板中每个显示基板的需求进行设置。本公开中，“不完全相同”指的是部分相同，部分不相同；或者，全部不相同。
示例的，位于同一第一挡墙组11中的两个第一挡墙在衬底基板10上的正投影的形状相同，且不同的第一挡墙组11中的第一挡墙111在衬底基板10上的正投影的形状不相同。
又示例的，每个第一挡墙组11中的两个第一挡墙在衬底基板10上的正投影的形状不相同，例如，每个第一挡墙组11中的其中一个第一挡墙111在衬底基板10上的正投影的形状为封闭的矩形环状，另一个第一挡墙111在衬底基板10上的正投影的形状为封闭的圆环状。
本公开对每个第一挡墙111的尺寸不进行限定，第一挡墙111的尺寸可根据显示基板的用途进行设置。多个第一挡墙111的尺寸可以完全相同，也可以不完全相同。只要同一个第一挡墙组11中的两个第一挡墙11可以阻止填充于二者之间的用于形成惰性材料层12的材料外溢即可，即，只要保证设置于同一个第一挡墙组11中的两个第一挡墙111之间的惰性材料层12在衬底基板10上的正投影与任何一个第一挡墙111在衬底基板10上的正投影不重叠即可。
示例的，第一挡墙111沿衬底基板10厚度的方向的尺寸为0.5～5μm，第一挡墙111沿垂直于衬底基板10厚度的方向的尺寸为5～30μm。
每个第一挡墙组11中的两个第一挡墙111间隔设置，即每个第一挡墙组11中的两个第一挡墙之间具有第一间距，本公开对该第一间距的大小不进行限定。示例的，每个第一挡墙组11中的两个第一挡墙111之间的第一间距为20～300μm。例如，如图1所示，每个第一挡墙组11中的两个第一挡墙111之间的第一间距相等。当然，不同的第一挡墙组11中的两个第一挡墙111之间的第一间距也可以不完全相等。本公开中，“不完全相等”指的是部分相等，部分不相等；或者，全部不相等。
在一些示例中，每个第一挡墙组11中最靠近显示区101的一个第一挡墙与显示区101的边缘之间具有第二间距，该第二间距内设置有第一无机绝缘层。本公开对该第二间距的大小不进行限定，只要设置于该第 二间距内的第一无机绝缘层可对显示基板中的发光器件23起到保护作用即可，即，防止水氧透过第一挡墙入侵至显示基板内，对发光器件产生影响。
示例的，每个第一挡墙组11中最靠近显示区101的一个第一挡墙111与显示区101的边缘之间的第二间距的范围为15～300μm。例如，如图1所示，每个第一挡墙组11中的两个第一挡墙111中最靠近显示区101的第一挡墙111与显示区101的边缘之间的第二间距相等。当然，不同的第一挡墙组11中的最靠近对应的一个显示区101的一个第一挡墙111与该显示区101的边缘之间的第二间距也可以不完全相等。
在一些示例中，如图2所示，惰性材料层12远离衬底基板10的表面在沿衬底基板10的厚度方向上与衬底基板10的最小距离不大于第一挡墙111远离衬底基板10的表面在沿衬底基板10的厚度方向上与衬底基板10的最大距离。
在一些实施例中，惰性材料层12形成的材料为末端基团为惰性基团的有机材料，该材料不与任何化学基团发生反应。
在一些示例中，惰性材料层12的原材料为第一有机材料，第一有机材料可以与衬底基板10或与第一挡墙111靠近衬底基板10的表面接触的一个膜层上既有的基团在常温、常压下发生水解反应或醇解反应生成惰性基团，从而形成惰性材料层12。
示例的，第一有机材料包括乙烯基三乙氧基硅烷、乙烯基三乙酰氧基硅烷、氯甲基三乙氧基硅烷中的一种。
以第一有机材料为RSi-(OEt) 3为例，如图4A和图4B所示，向第一挡墙组11中的两个第一挡墙111之间填充第一有机材料，第一有机材料的分子式中与Si相连的的-(OEt) 3基团可以与衬底基板10上既有的-OH发生水解反应，生成惰性基团
Figure PCTCN2021073370-appb-000001
从而得到惰性材料层12。
反应过程可表示为：
Figure PCTCN2021073370-appb-000002
其中，Et表示乙基。
这里，衬底基板10上既有的-OH来自于显示基板制备过程中的水汽，或，对衬底基板10靠近第一挡墙111的表面进行预处理，使其具有活性 的-OH。与第一挡墙111靠近衬底基板10的表面接触的一个膜层上既有的-OH来自于该膜层制备过程中的水汽，或，对该膜层远离衬底基板10的表面进行预处理，使其具有活性的-OH。
在一些示例中，惰性材料层12的材料为第二有机材料，该第二有机材料的末端基团均为惰性基团。
示例的，第二有机材料包括聚苯乙烯类(例如聚苯乙烯或聚甲基苯乙烯等)、聚环氧乙烷类(例如聚环氧乙烷或聚环氧丙烷等)、聚甲基丙烯酸甲酯类(例如聚甲基丙烯酸甲酯或聚甲基丙烯酸丁酯等)、聚乙烯吡咯烷酮类(例如聚氯乙烯或聚乙烯吡咯烷酮等)中的一种。
在一些实施例中，如图5A和图5B所示，显示基板母板还包括至少一个子挡墙112。至少一个子挡墙112位于至少一个第一挡墙组11中的两个第一挡墙111之间的区域；至少一个子挡墙112与两个第一挡墙111同层设置，惰性材料层12覆盖每个子挡墙112。
在一些示例中，每个第一挡墙组11中的两个第一挡墙111之间均设置有至少一个子挡墙112。
在另一些示例中，部分第一挡墙组11中的两个第一挡墙111之间设置有至少一个子挡墙112。
在一些示例中，第一挡墙组11中的两个第一挡墙111之间的子挡墙112的个数为一个。在另一些示例中，如图5A和图5B所示，第一挡墙组11中的两个第一挡墙111之间的子挡墙112的个数为多个，且多个子挡墙112间隔设置。
本公开不对子挡墙112的尺寸进行限定，子挡墙112的尺寸可根据实际情况进行设置。在子挡墙112的个数为多个的情况下，多个子挡墙112的尺寸可以完全相同，也可以不完全相同。
本公开中，子挡墙112沿衬底基板10厚度的方向的尺寸、沿垂直于衬底基板10厚度的方向的尺寸均与第一挡墙111对应的尺寸无绝对关系。
在一些示例中，子挡墙112沿衬底基板10厚度的方向的尺寸小于或等于第一挡墙111沿衬底基板10厚度的方向的尺寸，这样，可避免子挡墙112影响显示基板的整体厚度。
示例的，子挡墙112沿衬底基板10厚度的方向的尺寸范围为0.5～2.5μm，子挡墙112沿垂直于衬底基板10厚度的方向的尺寸范围为5～15μm。
在第一挡墙组11中的两个第一挡墙之间设置多个子挡墙112的情况下，本公开对相邻两个子挡墙112之间的第三间距的大小不做限制。示例的，相邻两个子挡墙112之间的第三间距的范围为5～15μm。
本公开通过在第一挡墙组11中的两个第一挡墙111之间设置子挡墙112，可以进一步避免用于形成惰性材料12的材料溢流，同时还可以增加惰性材料层12在显示基板上的稳定性。
本公开中，可以通过半色调掩膜板来制作高度不同的多个第一挡墙111和多个子挡墙112。在一些实施例中，如图6A所示，第一挡墙组11设置于衬底基板10的表面，衬底基板10靠近第一挡墙组11的表面具有至少一个凹槽113，该至少一个凹槽113位于第一挡墙组11中的两个第一挡墙111之间的区域，惰性材料层12覆盖该至少一个凹槽113。在一些示例中，如图6B所示，衬底基板10包括层叠设置的基底01和设置于基底01与第一挡墙111之间的缓冲层02。基于此，示例的，凹槽113设置于缓冲层02与第一挡墙111接触的表面。又示例的，如图6C所示，凹槽113贯穿缓冲层02，设置于基底01的表面。在一些示例中，基底01的材料例如为玻璃或聚酰亚胺(Polyimide，简称PI)。缓冲层02的材料例如为氮化硅(SiN x)、氧化硅(SiO x)或三氧化二铝(Al 2O 3)。
在一些实施例中，如图6D所示，显示基板母板100还包括设置于衬底基板10与第一挡墙组11之间的介电层25，第一挡墙组11设置于介电层25远离衬底基板10的表面，介电层25远离衬底基板10的表面具有至少一个凹槽113。这里，介电层25即为上述的与第一挡墙111靠近衬底基板10的表面接触的膜层。
示例的，介电层25为栅绝缘层。栅绝缘层的材料例如为氧化硅、氮化硅或氮氧化硅中的任一种。
又示例的，介电层25为层间介质层。层间绝缘层15的材料例如为聚苯并双恶唑、感光型的聚酰亚胺、苯丙环丁烯或无机材料中的任一种。在一些示例中，位于每个第一挡墙组11中的两个第一挡墙111之间的衬底基板10的表面或介电层25的表面均设置有至少一个凹槽113。
在另一些示例中，位于部分第一挡墙组11中的两个第一挡墙111之间的衬底基板10的表面或介电层25的表面设置有至少一个凹槽113。
示例的，位于第一挡墙组11中两个第一挡墙111之间的衬底基板10的表面或介电层25的表面的凹槽113的个数为一个。
又示例的，位于第一挡墙组11中两个第一挡墙111之间的衬底基板 10的表面或介电层25的表面的凹槽113的个数为多个，且多个凹槽113间隔设置。本公开不对凹槽的尺寸进行限定，凹槽113的尺寸可根据实际情况进行设置。在凹槽113的个数为多个的情况下，多个凹槽113的尺寸可以完全相同，也可以不完全相同。
示例的，凹槽113沿衬底基板10厚度的方向的尺寸范围为0.5～2.5μm。
示例的，凹槽113沿垂直于衬底基板10厚度的方向的尺寸范围为5～15μm。
在同一个第一挡墙组11的两个第一挡墙111之间的衬底基板10的表面或介电层25的表面的凹槽113为多个的情况下，本公开对相邻两个凹槽113之间的第四间距的大小不做限制。示例的，相邻凹槽113之间的第四间距的范围为5～15μm。
本公开通过在第一挡墙组11的两个第一挡墙111之间的衬底基板10的表面或介电层25的表面上形成凹槽113，可以进一步避免用于形成惰性材料层12的材料溢流，同时还可以增加惰性材料层12在显示基板上的稳定性。在一些实施例中，凹槽113通过干法刻蚀的工艺形成。
在一些实施例中，如图3所示，显示基板母板100还包括设置于第一无机封装层132和第二无机封装层133之间的有机封装层134。有机封装层134位于多个显示区101。有机封装层134可以防止第一无机封装层132中的无机物颗粒影响第二无机封装层133的制备，避免造成第二无机封装层133的膜层破裂，即，有机封装层134可对第一无机封装层132起到平坦化的效果。示例的，有机封装层134的材料例如为亚克力。
在一些实施例中，如图3和图7所示，显示基板母板100还包括设置于衬底基板10上的多个阻隔坝32，至少一个阻隔坝32设置于第一挡墙组11靠近显示区101的一侧，且每个阻隔坝32均围绕显示区101设置。由于有机封装层134的有机材料具有一定的流动性，因此，阻隔坝32可防止有机封装层134的有机材料的溢流。在一些示例中，每个显示区101均被至少一个阻隔坝32围绕。
示例的，每个显示区101被一个阻隔坝32围绕一周。
另示例的，每个显示区101被多个阻隔坝32围绕，多个阻隔坝32可以首尾连接，也可以不连接，只要使多个阻隔坝32组合起来围绕一个显示区101即可。
又示例的，多个显示区101中的部分显示区101被一个阻隔坝32围绕一周，部分显示区101被多个阻隔坝32组合起来围绕。本公开对此不作限制，可根据显示基板母板100中每个显示基板的需求进行设置。
在一些示例中，如图3和图8所示，与每个显示区101对应的至少一个阻隔坝32包括第一阻隔坝321和与第一阻隔坝321在沿垂直于衬底基板10厚度的方向上间隔设置的第二阻隔坝322。第一阻隔坝321围绕显示区101一周设置，且第二阻隔坝322围绕第一阻隔坝321一周设置。
如图3所示，第二阻隔坝322远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离，大于第一阻隔坝远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离。当然，第二阻隔坝322远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离也可以小于或等于第一阻隔坝321远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离，本公开对此不做限制，只要第一阻隔坝321和第二阻隔坝322间隔设置即可。
示例的，第一阻隔坝321和第二阻隔坝322均设置于介质层25的表面。这里，可通过半色调掩膜板来制作高度不同的第一阻隔坝321和第二阻隔坝322。
例如，第一阻隔坝321、第二阻隔坝322和像素界定层同层设置。也就是说，第一阻隔坝321、第二阻隔坝322与像素界定层可基于统一膜层通过掩膜、曝光、刻蚀等工艺形成。这样，可简化显示基板的制作工艺。
另示例的，第一阻隔坝321设置在介质层25的表面，在介质层的表面上对应第二阻隔坝322的位置还设置有其他膜层，第二阻隔坝322设置于该其他膜层的表面，从而使得第一阻隔坝321的高度小于第二阻隔坝322的高度。这里，第一阻隔坝321的高度即为上述的第一阻隔坝321远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离；第二阻隔坝322的高度即为上述的第二阻隔坝322远离衬底基板10的表面沿衬底基板10厚度的方向到衬底基板10的最小距离。
这样，与第一阻隔坝231间隔设置的第二阻隔坝322的设置可进一步防止有机封装层溢流出第一子阻隔坝321。溢流出第一子阻隔坝321的有机封装层的材料可以流入相邻的第一阻隔坝231和第二阻隔坝322之间的区域中。本公开不对阻隔坝32的材料进行限定，阻隔坝32的材料根据阻隔坝的32的形成工艺而定。例如，阻隔坝32与像素界定层同 步形成，则阻隔坝32的材料与像素界定层的材料为同一材料。
在一些实施例中，如图8和图9所示，显示基板母板100还包括设置于衬底基板10上的多个第二挡墙组41。多个第二挡墙组41在衬底基板10上的正投影与多个第一挡墙组11在衬底基板10上的正投影无重叠。每个第二挡墙组41包括至少相邻的两个第二挡墙411，且至少相邻的两个第二挡墙411之间形成一个间隔区。
如图9所示，显示基板母板100还包括设置于第二挡墙组41远离衬底基板10一侧的第二无机绝缘层14，以及，设置于第二无机绝缘层14中的至少一个过孔142，间隔区与一个过孔142在衬底基板10上的正投影重叠。
在一些示例中，每个第二挡墙组41包括两个第二挡墙411，两个第二挡墙411之间具有间隔区。这里，两个第二挡墙411在衬底基板10上的正投影的形状分别为块状。示例的，两个第二挡墙411在衬底基板10上的正投影的形状相同。又示例的，两个第二挡墙411在衬底基板10上的正投影的形状不相同。本公开对每个第二挡墙组41中的第二挡墙411的数量，以及每个第二挡墙在衬底基板10上的正投影的形状不进行限定，只要每个第二挡墙组41中的至少相邻的两个第二挡墙411可形成一个间隔区即可。
在一些示例中，每个第二挡墙组41中的第二挡墙411的数量相等，且每个第二挡墙411在衬底基板10上的正投影的形状均相同。
在另一些示例中，每个第二挡墙组41中的第二挡墙411的数量不完全相等，且每个第二挡墙411在衬底基板10上的正投影的形状不完全相同。
示例的，第二挡墙组41包括多个第二挡墙411，多个第二挡墙411首尾相接，围成一个中间为间隔区的封闭的形状。例如，如图8所示，第二挡墙组41包括四个第二挡墙411，每个第二挡墙411在衬底基板10上的正投影的形状为长条状，该四个第二挡墙411首尾相接，围成一个中间为间隔区的封闭的矩形环状。当然，也可以围成圆环状，本公开对此不做限制。
又示例的，第二挡墙组41包括两个第二挡墙411，两个第二挡墙411间隔设置，每个第二挡墙411在衬底基板10上的正投影的形状为块状，两个第二挡墙411之间形成一个间隔区。
这样，在间隔区形成惰性有机膜层；然后在第二挡墙组41远离衬 底基板10的一侧沉积无机绝缘薄膜时，由于无机绝缘薄膜不与惰性有机膜层发生化学反应，从而无法附着于惰性有机膜层上，进而使得第二无机绝缘层14上在间隔区形成过孔142(如图9所示)。
基于此，如图15所示，可通过设置于第二无机绝缘层14上的过孔142实现分别设置于第二无机绝缘层14远离衬底基板10的一侧的第一导电层151和设置于第二无机绝缘层14靠近衬底基板10的一侧的第二导电层152之间的电连接。
在一些示例中，惰性有机膜层可通过上述的第一有机材料或第二有机材料形成，其形成的过程与上述一致，在此不再赘述。
在一些实施例中，如图10所示，显示基板母板100还包括设置于衬底基板上的有源层26，栅绝缘层251设置于有源层26远离衬底基板10的一侧，显示基板母板100还包括设置于层间介质层252远离衬底基板10一侧的源漏金属层27，以及设置于栅绝缘层251与层间介质层252之间的栅极28。
基于此，第二挡墙组41设置于显示区101内，第二挡墙组41可与有源层26同层设置，即，第二挡墙组41中的每个第二挡墙411与有源层26通过同一次构图工艺形成。示例的，有源层26的材料包括多晶硅(p-Si)。且第二挡墙411设置于有源层26远离衬底基板10的一侧。这里，在设置第二挡墙411的区域，可通过半色调掩膜板来制作高度不同的有源层26和第二挡墙411。
这样，在第二挡墙411远离衬底一侧沉积层间介质层252时，层间介质层252即可形成过孔，使得设置于层间介质层252远离衬底基板10一侧的源漏金属层27可通过该过孔142与有源层26电连接。
这里，第二无机绝缘层14包括上述的层间介质层252。
当然，第二无机绝缘层也可以是显示基板母板中的其他膜层。
本公开对第二挡墙组41设置于显示基板母板中的位置不做限定，第二挡墙组41设置于显示基板母板中的位置可根据每个显示基板的需求，以及每个显示基板中第二无机绝缘层14上的过孔需求进行设置。
本公开中，如图9所示，在显示基板母板100的切割区102内沿切割线切割后，第二无机绝缘层14被分为多个第二无机绝缘子层141，每个显示区101对应一个第二无机绝缘子层141。
如图8所示，本公开一些实施例还提供一种显示基板1000，该显示基板1000包括在上述任一实施例的显示基板母板100的切割区102内沿 切割线切割获得的部分。本公开中，可采用激光切割工艺对显示基板母板100进行切割。切割获得的多个显示基板1000的结构可以完全相同，也可以不完全相同，由显示基板母板100的制备过程而定。
在一些实施例中，如图8所示，该显示基板1000具有显示区101，显示基板1000包括衬底基板10，设置于衬底基板10上的第一挡墙111，第一挡墙111位于显示区101的至少一侧，且在设置该第一挡墙111的显示区101的任一侧，第一挡墙111与衬底基板10的边缘之间具有第五间距。
在一些示例中，如图8所示，在设置该第一挡墙111的显示区101的不同侧，该第一挡墙111与衬底基板10的边缘之间的第五间距均相等。
在另一些示例中，在设置该第一挡墙111的显示区101的不同侧，该第一挡墙111与衬底基板10的边缘之间的第五间距不完全相等。
这里，在设置该第一挡墙111的显示区101的不同侧，该第一挡墙111与衬底基板10的边缘之间的第五间距的大小，取决于在显示基板母板100上位于该显示区10不同侧的切割线距离该第一挡墙111的距离。
显示基板1000还包括设置于第一挡墙111与衬底基板10的边缘之间的惰性材料层12，以及，设置于第一挡墙111远离衬底基板10一侧的第一无机绝缘子层131，第一无机绝缘子层131还位于显示区101；在设置第一挡墙111的显示区101的任一侧，第一无机绝缘子层131的边缘在衬底基板10上的正投影位于第一挡墙111在衬底基板10上的正投影范围内。
在一些实施例中，如图8所示，第一挡墙111围绕显示区101一周设置，且第一无机绝缘子层131的各边缘在衬底基板10上的正投影位于第一挡墙111在衬底基板10上的正投影范围内。
在一些实施例中，显示基板1000是有机电致发光二极管(organic light emitting diode，简称OLED)显示基板。
在另一些实施例中显示基板1000是量子点电致(Quantum Dot Light Emitting Diodes，简称QLED)显示基板。当然，本公开的显示基板1000还可以是其他类型的显示基板，本公开对此不作限制，可根据显示基板的用途对显示基板的结构进行调整。在一些实施例中，如图3所示，显示基板1000还包括多个发光器件23以及与每个发光器件23电连接的像素驱动电路。
在一些示例中，每个像素驱动电路至少包括一个驱动晶体管、一个 开关晶体管和一个存储电容器。
在一些示例中，每个发光器件23包括层叠设置的第一电极231、发光功能层232、以及第二电极233。示例的，第一电极231为阳极，第二电极233为阴极。又示例的，第一电极231为阴极，第二电极233为阳极。
显示基板1000的像素界定层24具有多个开口区，每个发光器件23对应一个开口区进行设置。
在一些实施例中，发光功能层232为有机发光功能层。
在另一些实施例中，发光功能层232为量子点发光功能层。
如图11所示，本公开一些实施例还提供一种显示装置1，包括上述任一实施例的显示基板1000。该显示装置1可以用作显示器、电视、数码相机、手机、平板电脑、增强现实(Augmented Reality，AR)/虚拟现实(Virtual Reality，VR)产品等具有任何显示功能的产品或者部件，本公开的实施例对1显示装置1的用途不做特殊限制。
在一些实施例中，如图11所示，显示装置1包括显示面板1000、框架1001、盖板、电路板等。当然，显示装置1可以包括更多或更少的组件，并且这些组件之间的相对位置可以改变。
在一些示例中，电路板被配置为向显示面板1000提供显示所需的信号。示例的，电路板为印刷电路板组件(Printed Circuit Board Assembly，PCBA)，PCBA包括印刷电路板(Printed Circuit Board，PCB)和设置于PCB上的时序控制器(Timing Controller，TCON)、电源管理集成电路(Power Management IC，PMIC)以及其它IC或电路等。
所述显示装置具有与前述显示基板相同的说明和技术效果，在此不再赘述。
本公开一些实施例提供一种显示基板的制备方法，如图12所示，包括S10-S50。
S10、提供衬底基板10。该衬底基板10具有多个显示区101、多个显示基板区103、和位于多个显示区外围的切割区102；一个显示区101位于对应的一个显示基板区103内，且切割区102与显示基板区103无重叠。
S20、如图13所示，在衬底基板10上且位于每个显示区的至少一侧，形成包括两个第一挡墙111的第一挡墙组11。且每个第一挡墙组 11中的两个第一挡墙111之间的区域位于与该第一挡墙组11对应的切割区102。
在一些实施例中，多个第一挡墙111与平坦层22通过同一次构图工艺形成。
在另一些实施例中，多个第一挡墙111与像素界定层24通过同一次构图工艺形成。
S30、如图14A和图14B所示，在每个第一挡墙组11中的两个第一挡墙111之间的区域形成惰性材料层12。
在一些实施例中，S30包括S302。
S302、向每个第一挡墙组11中的两个第一挡墙11之间的区域填充第一有机材料，以形成惰性材料层12。
本公开中，不对向每个第一挡墙组11中的两个第一挡墙11之间的区域填充第一有机材料的工艺进行限定，只要第一有机材料仅填充于每个第一挡墙组11中的两个第一挡墙11之间的区域即可。
示例的，采用喷墨打印工艺向每个第一挡墙组11中的两个第一挡墙11之间的区域填充第一有机材料，并进行烘烤固化处理。
在一些实施例中，第一挡墙组11位于衬底基板10的表面，基于此，在S302之前，S30还包括S301。
S301、对衬底基板10的表面进行预处理，使衬底基板10的表面具有羟基，以在填充第一有机材料后，使第一有机材料与羟基发生水解反应或醇解反应，形成惰性材料层12。
本公开不对衬底基板10的表面进行预处理的工艺进行限定，只要该工艺能实现使衬底基板10的表面具有羟基即可。
示例的，采用等离子表面处理方法，对衬底基板10的表面进行预处理，使衬底基板10的表面具有活性羟基。
又示例的，采用紫外光照射的方法，对衬底基板10的表面进行预处理，使衬底基板10的表面具有活性羟基。
在一些实施例中，在S20之前，该显示基板的制备方法还包括S11。
S11、在衬底基板10上形成介电层25。
例如，在衬底基板10上形成栅绝缘层。
又例如，在衬底基板上形成层间介质层。
基于此，在S302之前，S30还包括S301’。
S301’、对介电层25远离衬底基板10的表面进行预处理，使介电层25远离衬底基板10的表面具有羟基，以在填充第一有机材料后，使第一有机材料与羟基反应，形成惰性材料层12。
这里，对介电层25远离衬底基板10的表面进行预处理的工艺与上述S301中对衬底基板10的表面进行预处理的工艺相同。例如，对介电层25远离衬底基板10的表面进行预处理的工艺也可以采用等离子表面处理方法或紫外光照射等方法。示例的，采用等离子表面处理方法，对衬底基板10的表面进行预处理，使衬底基板10的表面具有活性羟基。
又示例的，采用紫外光照射的方法，对衬底基板10的表面进行预处理，使衬底基板10的表面具有活性羟基。
在一些实施例中，S30包括S302’。
S302’、向每个第一挡墙组11中的两个第一挡墙111之间的区域填充第二有机材料，形成惰性材料层。
S40、如图2所示，在多个第一挡墙组11远离衬底基板10的一侧形成第一无机绝缘层13。
本公开不对形成第一无机绝缘层13的工艺进行限定。
在一些示例中，采用化学气相沉积(chemical vapor deposition，简称CVD)工艺形成第一无机绝缘层13。
在另一些示例中，采用原子层沉积(Atomic layer deposition，简称ALD)工艺形成第一无机绝缘层13。
如图4C所示，以第一无机绝缘层13的材料包括Al 2O 3为例，在第一挡墙组11远离衬底基板10的一侧形成第一无机绝缘层13，其工艺过程包括如下：
将衬底基板10放置于真空装置中，并向真空装置中输入Al 2O 3的前驱体三甲基铝，Al 2O 3的前驱体三甲基铝沉积于整个衬底基板上；而由于惰性材料层12的材料为惰性的有机材料，这样，在第一挡墙组11远离衬底基板10的一侧沉积第一无机绝缘层13时，Al 2O 3的前驱体三甲基铝不与惰性的有机材料发生化学反应，因此，前驱体三甲基铝无法附着在惰性材料层12上。
之后，将真空装置中的气体抽走，并向真空装置中通入惰性气体吹走未反应的前驱体，再将真空装置中的气氛恢复为真空，如此往复，直到前 驱体三甲基铝的厚度达到Al 2O 3的设计需求为止。
此处，惰性材料层12的厚度与显示基板的用途有关。示例的，惰性材料层12的厚度范围为1～10μm。
在一些实施例中，惰性材料层12远离衬底基板10的表面在沿衬底基板10厚度的方向上，与衬底基板10的距离小于第一无机绝缘层12远离衬底基板10的表面在沿衬底基板10厚度的方向上，与衬底基板10的距离。这样，在第一挡墙组11远离衬底基板10的一侧形成惰性材料层12，不会影响显示基板的整体厚度。
S50、在显示基板母板上的切割区内沿切割线进行切割，获得上述的显示基板。
在一些示例中，采用激光切割工艺对显示基板母板100进行切割。
在一些实施例中，上述显示基板的制备方法还包括S60。
S60、在衬底基板10上形成多个阻隔坝32；每个显示区101被至少一个阻隔坝32围绕，且该至少一个阻隔坝32设置于该显示区101对应的第一挡墙组11靠近该显示区101的一侧。
在一些示例中，在衬底基板10上形成多个第一阻隔坝321和多个第二阻隔坝322。S60包括在进行S11的同时，进行S601。
S601、通过半色调掩膜板来制作高度不同的第一阻隔坝321和第二阻隔坝322。即，在形成介电层的同时，形成多个阻隔坝32。
示例的，在形成栅绝缘层的同时，形成多个阻隔坝32。
又示例的，在形成层间介质层的同时，形成多个阻隔坝32。
在一些实施例中，上述显示基板的制备方法还包括S70。
S70、在衬底基板10上的每个显示基板区103内，形成至少一个第二挡墙组41，每个第二挡墙组41包括至少相邻的两个第二挡墙411，且至少相邻的两个第二挡墙411之间形成一个间隔区；至少一个第二挡墙组41在衬底基板10上的正投影与第一挡墙组11在衬底基板10上的正投影无重叠。
在一些实施例中，第二挡墙组41与有源层采用半色调掩膜板通过同一次构图工艺形成。
S80、在每个间隔区内形成惰性有机膜层；
在一些实施例中，S80包括S802。
S802、向每个间隔区内填充第一有机材料，以形成惰性有机膜层。
示例的，采用喷墨打印工艺向每个间隔区内填充第一有机材料，并进行烘烤固化处理。
在一些实施例中，第二挡墙组41与有源层同层，且第二挡墙组41位于有源层远离衬底基板10的表面，基于此，在S802之前，S80还包括S801。
S801、对有源层远离衬底基板10的表面进行预处理，使衬底基板10的表面具有羟基，以在填充第一有机材料后，使第一有机材料与羟基发生水解反应或醇解反应，形成惰性有机膜层。
在一些实施例中，S80包括S802’。
S802’、向每个间隔区内填充第二有机材料，第二有机材料成膜，形成惰性有机膜层。
示例的，采用等离子表面处理方法，对有源层远离衬底基板10的表面进行预处理，使有源层远离衬底基板10的表面具有活性羟基。
又示例的，采用紫外光照射的方法，对有源层远离衬底基板10的表面进行预处理，使有源层远离衬底基板10的表面具有活性羟基。
S90、在显示基板区103内，且位于至少一个第二挡墙组41远离衬底基板10的一侧形成第二无机绝缘层14。
在一些示例中，采用CVD工艺形成第二无机绝缘层14。
在另一些示例中，采用ALD工艺形成第二无机绝缘层14。
示例的，形成第二无机绝缘层14的工艺与形成第一无机绝缘层13的工艺相同。
基于此，由于惰性有机膜层不与形成第二无机绝缘层14的原材料发生反应，因此，第二无机绝缘膜层14不沉积于惰性有机膜层远离衬底基板的表面上，使得第二无机绝缘层14在间隔区对应的位置处形成通孔。
在一些实施例中，第二无机绝缘层14为上述的层间介质层。基于此，在S11为在衬底基板10上形成层间介质层的情况下，S90与S11同时进行。
S100、去除形成于每个间隔区内的惰性有机膜层。
示例的，采用灰化工艺去除形成于每个间隔区内的惰性有机膜层。 当然，也可以采用其他的工艺方法来去除惰性有机膜层，本公开对此不作限制。
在一些实施例中，在S100之后，在第二无机绝缘层14远离衬底基板10的表面沉积源漏金属层，源漏金属层在沉积过程中，填充于第二无机绝缘层14的过孔中，使得源漏金属层与有源层连接。
源漏金属层的沉积工艺可以为CVD工艺，也可以是ALD工艺。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板母板，具有多个显示区和位于所述多个显示区之间的切割区；所述显示基板母板包括：
    衬底基板；
    设置于所述衬底基板上的多个第一挡墙组；每个第一挡墙组位于对应的一个显示区的至少一侧，每个第一挡墙组包括间隔设置的两个第一挡墙，且所述两个第一挡墙之间的区域位于所述切割区；
    设置于所述两个第一挡墙之间的区域的惰性材料层；和
    设置于所述多个第一挡墙组远离所述衬底基板一侧的第一无机绝缘层，所述第一无机绝缘层还位于所述多个显示区；
    所述第一无机绝缘层在所述衬底基板上的正投影与所述惰性材料层在所述衬底基板上的正投影无重叠。
  2. 根据权利要求1所述的显示基板母板，其中，所述两个第一挡墙均围绕对应的显示区一周设置；
    所述第一无机绝缘层包括多个无机绝缘子层，每个无机绝缘子层位于对应的显示区以及与该显示区对应的所述第一挡墙组所在区域。
  3. 根据权利要求1或2所述的显示基板母板，还包括：
    至少一个子挡墙，所述至少一个子挡墙位于至少一个第一挡墙组中的所述两个第一挡墙之间的区域；所述至少一个子挡墙与所述两个第一挡墙同层设置；
    所述惰性材料层覆盖所述至少一个子挡墙。
  4. 根据权利要求1或2所述的显示基板母板，其中，所述第一挡墙组设置于所述衬底基板的表面，所述衬底基板靠近所述第一挡墙组的表面具有至少一个凹槽；
    所述至少一个凹槽位于所述两个第一挡墙之间的区域；
    所述惰性材料层覆盖所述至少一个凹糟；
    或，
    所述显示基板母板还包括：
    设置于所述衬底基板与所述第一挡墙组之间的介电层；所述第一挡墙组设置于所述介电层远离所述衬底基板的表面，且所述介电层远离所述衬底基板的表面具有至少一个凹槽；
    所述至少一个凹槽位于所述两个第一挡墙之间的区域；
    所述惰性材料层覆盖所述至少一个凹糟。
  5. 根据权利要求1-4任一项所述的显示基板母板，还包括：
    设置于所述衬底基板上的多个第二挡墙组，所述多个第二挡墙组在所述衬底基板上的正投影与所述多个第一挡墙组在所述衬底基板上的正投影无重叠；每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；
    设置于所述第二挡墙组远离所述衬底基板一侧的第二无机绝缘层；
    设置于所述第二无机绝缘层中的多个过孔，所述间隔区与一个过孔在所述衬底基板上的正投影重叠。
  6. 一种显示基板，具有显示区；所述显示基板包括：
    衬底基板，
    设置于所述衬底基板上的第一挡墙；所述第一挡墙位于所述显示区的至少一侧，且在设置所述第一挡墙的所述显示区的任一侧，所述第一挡墙所述第一挡墙与所述衬底基板的边缘之间具有间距；
    设置于所述第一挡墙与所述衬底基板的边缘之间的惰性材料层；
    设置于所述第一挡墙远离所述衬底基板一侧的第一无机绝缘子层，所述第一无机绝缘子层还位于所述显示区；在设置所述第一挡墙的所述显示区的任一侧，所述第一无机绝缘子层的边缘在所述衬底基板上的正投影位于所述第一挡墙在所述衬底基板上的正投影范围内。
  7. 根据权利要求6所述的显示基板，其中，所述第一挡墙围绕所述显示区一周设置，且所述第一无机绝缘子层的各边缘在所述衬底基板上的正投影位于所述第一挡墙在所述衬底基板上的正投影范围内。
  8. 根据权利要求6或7所述的显示基板，还包括：
    设置于所述衬底基板上且位于所述显示区的平坦层，所述第一挡墙与所述平坦层同层设置；或，
    设置于所述衬底基板上且位于所述显示区的像素界定层；所述第一挡墙与所述像素界定层同层设置。
  9. 根据权利要求6-8任一项所述的显示基板，还包括：
    设置于所述衬底基板上的至少一个阻隔坝；所述至少一个阻隔坝设置于所述第一挡墙靠近所述显示区的一侧，且所述至少一个阻隔坝均围绕所述显示区设置。
  10. 根据权利要求9所述的显示基板，其中，所述至少一个阻隔坝包括：第一阻隔坝和与所述第一阻隔坝在沿垂直于所述衬底基板厚度的方向上间隔设置的第二阻隔坝；
    所述第一阻隔坝围绕所述显示区一周设置，且所述第二阻隔坝围绕 所述第一阻隔坝一周设置，所述第二阻隔坝远离所述衬底基板的表面沿所述衬底厚度的方向到所述衬底基板的最小距离，大于所述第一阻隔坝远离所述衬底基板的表面沿所述衬底基板厚度的方向到所述衬底基板的最小距离。
  11. 根据权利要求6-10任一项所述的显示基板，还包括：
    设置于所述衬底基板上的至少一个第二挡墙组，所述至少一个第二挡墙组在所述衬底基板上的正投影与所述第一挡墙在所述衬底基板上的正投影无重叠；每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；
    设置于所述第二挡墙组远离所述衬底基板一侧的第二无机绝缘子层；
    设置于所述第二无机绝缘子层中的至少一个过孔，所述间隔区与一个过孔在所述衬底基板上的正投影重叠。
  12. 一种显示装置，包括权利要求6-11任一项所述的显示基板。
  13. 一种如权利要求6-11任一项所述的显示基板的制备方法，包括：
    提供衬底基板；所述衬底基板具有多个显示区和位于所述多个显示区之间的切割区；
    在所述衬底基板上且位于每个显示区的至少一侧，形成包括两个第一挡墙的第一挡墙组，且所述两个第一挡墙之间的区域位于所述切割区；
    在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层；
    在多个第一挡墙组远离所述衬底基板的一侧形成第一无机绝缘层，所述第一无机绝缘层还位于所述多个显示区；所述第一无机绝缘层在所述衬底基板上的正投影与所述惰性材料层在所述衬底基板上的正投影无重叠；
    沿所述切割区切割，获得所述显示基板。
  14. 根据权利要求13所述的方法，其中，在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层，包括：
    向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料，以形成所述惰性材料层。
  15. 根据权利要求14所述的方法，其中，所述第一挡墙组位于所 述衬底基板的表面；
    在向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料之前，形成所述惰性材料层还包括：
    对所述衬底基板的表面进行预处理，使所述衬底基板的表面具有羟基，以在填充所述第一有机材料后，使所述第一有机材料与羟基反应，形成惰性材料层。
  16. 根据权利要求14所述的方法，其中，在形成所述第一挡墙组之前，所述方法还包括：
    在所述衬底基板上形成介电层；
    其中，在向每个第一挡墙组中的所述两个第一挡墙之间的区域填充第一有机材料之前，形成所述惰性材料层还包括：
    对所述介电层远离所述衬底基板的表面进行预处理，使所述介电层远离所述衬底基板的表面具有羟基，以在填充所述第一有机材料后，使所述第一有机材料与羟基反应，形成惰性材料层。
  17. 根据权利要求14-16任一项所述的方法，其中，所述第一有机材料包括乙烯基三乙氧基硅烷、乙烯基三乙酰氧基硅烷、氯甲基三乙氧基硅烷中的一种。
  18. 根据权利要求13所述的方法，其中，在每个第一挡墙组中的所述两个第一挡墙之间的区域形成惰性材料层，包括：
    向每个第一挡墙组中的两个第一挡墙之间的区域填充第二有机材料；所述第二有机材料包括聚苯乙烯、聚环氧乙烷、聚甲基丙烯酸甲酯、聚乙烯吡咯烷酮中的一种。
  19. 根据权利要求13-18任一项所述的方法，还包括：
    在所述衬底基板上形成多个阻隔坝；每个显示区被至少一个阻隔坝围绕，且所述至少一个阻隔坝设置于该显示区对应的所述第一挡墙组靠近所述显示区的一侧。
  20. 根据权利要求13-19任一项所述的方法，其中，所述衬底基板具有多个显示基板区，一个显示区位于对应的一个显示基板区内，且所述切割区位于所述多个显示基板区之间；
    所述方法还包括：
    在所述衬底基板上的每个显示基板区内，形成至少一个第二挡墙组，每个第二挡墙组包括至少相邻的两个第二挡墙，且所述至少相邻的两个第二挡墙之间形成一个间隔区；所述至少一个第二挡墙组在所述衬 底基板上的正投影与所述第一挡墙组在所述衬底基板上的正投影无重叠；
    在所述间隔区内形成惰性有机膜层；
    在所述显示基板区内且所述至少一个第二挡墙组远离所述衬底基板的一侧形成第二无机绝缘层；
    去除形成于所述间隔区内的所述惰性有机膜层。
PCT/CN2021/073370 2020-01-23 2021-01-22 显示基板母板、显示基板及其制备方法、显示装置 WO2021148007A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/625,980 US20220384761A1 (en) 2020-01-23 2021-01-22 Display substrate motherboard, display substrate and manufacturing method therefor, and display apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010076888.2 2020-01-23
CN202010076888.2A CN111244327B (zh) 2020-01-23 2020-01-23 一种显示基板及其制备方法、显示装置

Publications (1)

Publication Number Publication Date
WO2021148007A1 true WO2021148007A1 (zh) 2021-07-29

Family

ID=70874949

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/073370 WO2021148007A1 (zh) 2020-01-23 2021-01-22 显示基板母板、显示基板及其制备方法、显示装置

Country Status (3)

Country Link
US (1) US20220384761A1 (zh)
CN (1) CN111244327B (zh)
WO (1) WO2021148007A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111244327B (zh) * 2020-01-23 2023-01-24 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置
CN112271196B (zh) * 2020-10-22 2024-04-23 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN112497930B (zh) * 2020-11-25 2022-01-25 合肥维信诺科技有限公司 喷墨打印装置及其操作方法
KR20220094264A (ko) * 2020-12-28 2022-07-06 삼성디스플레이 주식회사 표시 장치의 제조 방법 및 이를 사용하여 제조된 표시 장치
CN113314571B (zh) * 2021-05-17 2022-08-05 Oppo广东移动通信有限公司 电子设备、显示面板及其制作方法
CN113410418B (zh) * 2021-06-16 2024-02-20 京东方科技集团股份有限公司 封装方法、显示面板及显示装置
CN114188382B (zh) * 2021-12-03 2023-06-30 深圳市华星光电半导体显示技术有限公司 Oled显示面板及其封装方法
CN114335380B (zh) * 2021-12-16 2024-05-31 深圳市华星光电半导体显示技术有限公司 Oled显示面板和显示装置
CN114420869B (zh) * 2022-01-17 2024-03-12 京东方科技集团股份有限公司 一种显示基板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560114A (zh) * 2018-12-06 2019-04-02 京东方科技集团股份有限公司 显示面板的制造方法、显示面板和显示装置
CN110165081A (zh) * 2019-05-30 2019-08-23 京东方科技集团股份有限公司 显示背板及其制作方法
CN110690262A (zh) * 2019-10-16 2020-01-14 武汉华星光电半导体显示技术有限公司 有机发光二极管显示面板及其制造方法
CN111244327A (zh) * 2020-01-23 2020-06-05 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106775173B (zh) * 2017-02-07 2019-12-20 上海天马微电子有限公司 一种触控显示面板和触控显示装置
CN107403877B (zh) * 2017-06-19 2019-10-25 武汉华星光电半导体显示技术有限公司 Oled面板的封装方法
KR102457583B1 (ko) * 2017-12-21 2022-10-24 삼성디스플레이 주식회사 표시 장치 및 그것의 제조 방법
CN110718647A (zh) * 2019-09-25 2020-01-21 武汉华星光电半导体显示技术有限公司 薄膜的制备方法及显示装置的制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109560114A (zh) * 2018-12-06 2019-04-02 京东方科技集团股份有限公司 显示面板的制造方法、显示面板和显示装置
CN110165081A (zh) * 2019-05-30 2019-08-23 京东方科技集团股份有限公司 显示背板及其制作方法
CN110690262A (zh) * 2019-10-16 2020-01-14 武汉华星光电半导体显示技术有限公司 有机发光二极管显示面板及其制造方法
CN111244327A (zh) * 2020-01-23 2020-06-05 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
US20220384761A1 (en) 2022-12-01
CN111244327B (zh) 2023-01-24
CN111244327A (zh) 2020-06-05

Similar Documents

Publication Publication Date Title
WO2021148007A1 (zh) 显示基板母板、显示基板及其制备方法、显示装置
CN111128010B (zh) 显示面板及其制造方法及显示装置
WO2022057515A1 (zh) 显示基板及其制备方法、显示装置
US11839101B2 (en) Display substrate and preparation method thereof, and display device
WO2022111094A1 (zh) 显示基板及其制备方法、显示装置
WO2020253489A1 (zh) 显示基板、显示装置以及制作显示基板的方法
WO2020143552A1 (zh) 显示基板及其制备方法、显示装置
US9899430B2 (en) GOA unit and method for producing the same, gate driver circuit
EP3249687B1 (en) Manufacturing method of a display panel
EP3723150B1 (en) Electronic apparatus substrate and manufacturing method, and display apparatus
JP2019527843A (ja) 表示基板、表示パネル、表示装置、並びに表示基板及び表示パネルの製造方法
WO2021022594A1 (zh) 阵列基板、显示面板及阵列基板的制作方法
WO2017031940A1 (zh) 一种阵列基板、其制作方法及显示装置
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2021238926A1 (zh) 显示基板及其制备方法、显示面板、显示装置
WO2021136446A1 (zh) 驱动背板及其制备方法、显示面板、显示装置
JP4462775B2 (ja) パターン形成方法及びそれを用いた液晶表示装置の製造方法
CN111463243A (zh) 阵列基板及其制备方法
KR20190114962A (ko) 박막들을 캡슐화하는 방법 및 구조물, 디스플레이 디바이스
US20230137855A1 (en) Method of fabricating array substrate and array substrate thereof
WO2005057530A1 (ja) 薄膜トランジスタ集積回路装置、アクティブマトリクス表示装置及びそれらの製造方法
CN104952934A (zh) 薄膜晶体管及制造方法、阵列基板、显示面板
WO2020258465A1 (zh) 一种阵列基板及其制作方法、显示面板
WO2020177666A1 (zh) 像素单元及其制造方法、显示基板
WO2020233485A1 (zh) 发光器件及其制造方法、掩膜板、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21743889

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21743889

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 21743889

Country of ref document: EP

Kind code of ref document: A1