WO2021136395A1 - Procédé de fonctionnement pour réseau de stockage résistif - Google Patents

Procédé de fonctionnement pour réseau de stockage résistif Download PDF

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Publication number
WO2021136395A1
WO2021136395A1 PCT/CN2020/141479 CN2020141479W WO2021136395A1 WO 2021136395 A1 WO2021136395 A1 WO 2021136395A1 CN 2020141479 W CN2020141479 W CN 2020141479W WO 2021136395 A1 WO2021136395 A1 WO 2021136395A1
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Prior art keywords
initialization
voltage
switching device
memory cell
circuits
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PCT/CN2020/141479
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English (en)
Chinese (zh)
Inventor
潘立阳
孙婧瑶
吴华强
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清华大学
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Definitions

  • the embodiment of the present disclosure relates to an operation method of a resistive memory array.
  • Resistance changeable memory is a memory that uses the characteristics of the change in conductivity of the thin film resistive medium material under the action of an external electric field to realize the high-low conversion of the resistance value.
  • the resistive random access memory has the advantages of simple structure, fast working speed, low power consumption, stable information, non-volatile, etc., and has huge development and application prospects.
  • At least one embodiment of the present disclosure provides a resistive memory array, which includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a plurality of block selection circuits, and a plurality of initialization circuits.
  • the plurality of memory cells are arranged in a plurality of memory cell rows and a plurality of memory cell columns along a first direction and a second direction, each memory cell includes a resistive switching device and a switching device, and the resistive switching device includes a first electrode and The second electrode, and the first electrode of the resistive switching device is electrically connected to the switching device.
  • the plurality of bit lines extend along the second direction and are connected to the plurality of memory cell columns in a one-to-one correspondence, wherein each of the plurality of bit lines is connected to a corresponding memory cell column
  • the second electrode of the resistive switching device is electrically connected.
  • the plurality of word lines extend along the first direction and are connected to the plurality of memory cell rows in a one-to-one correspondence, wherein each of the plurality of word lines corresponds to a memory cell of a memory cell row
  • the switching devices are electrically connected.
  • the plurality of block selection circuits are respectively electrically connected to the plurality of bit lines in a one-to-one correspondence; the plurality of initialization circuits are respectively electrically connected to the plurality of bit lines in a one-to-one correspondence.
  • Each block selection circuit includes a control terminal, a first terminal, and a second terminal.
  • the control terminal of the block selection circuit is configured to receive a block selection voltage
  • the first terminal of the block selection circuit is configured to receive a read and write operation voltage.
  • the second end of the block selection circuit is electrically connected to a bit line corresponding to the block selection circuit, and the block selection circuit is configured to write the read and write operation voltage to the correspondingly connected bit line in response to the block selection voltage.
  • each initialization circuit includes a control terminal, a first terminal and a second terminal, the control terminal of the initialization circuit is configured to receive the initialization control voltage, the first terminal of the initialization circuit is configured to receive the initialization operation voltage, the The second end of the initialization circuit is electrically connected to a bit line corresponding to the initialization circuit, and the initialization circuit is configured to write the initialization operation voltage to the correspondingly connected bit line in response to the initialization control voltage.
  • each of the plurality of initialization circuits includes a switching transistor, and the gate, the first pole, and the second pole of the switching transistor are the control terminal, the first terminal, and the second terminal of the initialization circuit, respectively. End;
  • the switching transistor is a P-type transistor.
  • the switching device includes a control terminal, a first terminal, and a second terminal, and each word line is electrically connected to a control terminal of a switching device of a memory cell of a corresponding memory cell row;
  • the variable memory array also includes a plurality of source lines extending along the second direction, the plurality of source lines are electrically connected to the plurality of memory cell columns in a one-to-one correspondence, and each of the plurality of source lines is connected to the The second end of the switching device of the memory cell of a corresponding memory cell column is electrically connected.
  • the resistive memory array further includes a plurality of global bit lines extending along the second direction and electrically connected to the plurality of block selection circuits in a one-to-one correspondence, each One global bit line is electrically connected to the first end of the correspondingly connected block selection circuit.
  • the resistive memory array further includes an initialization operation line extending along the first direction and electrically connected to the first ends of the plurality of initialization circuits to provide the initialization operation Voltage.
  • At least one embodiment of the present disclosure also provides a resistive random access memory circuit, including the above-mentioned resistive random access memory array.
  • the resistive random access memory circuit further includes an initialization control circuit configured to be electrically connected to the plurality of initialization circuits to provide the initialization operation voltage and the initialization control voltage.
  • the resistive memory circuit further includes a column selection circuit configured to be connected to the plurality of block selection circuits to provide the read and write operation voltage to the resistive memory array.
  • the resistive memory circuit further includes a program control circuit and a read control circuit, and the read and write operation voltages include a program operation voltage and a read operation voltage.
  • the programming control circuit is connected to the column selection circuit and is configured to provide the programming operation voltage to the resistive memory array through the column selection circuit; the read control circuit is connected to the column selection circuit, And configured to provide the read operation voltage to the resistive memory array through the column selection circuit.
  • At least one embodiment of the present disclosure further provides an operating method for operating the above-mentioned resistive random access memory array.
  • the operating method includes: in an initialization operation phase, turning off the plurality of block selection circuits, and performing the initialization through the plurality of block selection circuits.
  • the circuit and the plurality of bit lines apply the initialization operation voltage to the memory cells of the selected at least one memory cell row.
  • At least one embodiment of the present disclosure also provides an operating method of a resistive random access memory array, the resistive random access memory array including a plurality of memory cells, a plurality of bit lines, a plurality of word lines, a plurality of block selection circuits, and a plurality of initialization circuits .
  • the plurality of memory cells are arranged in a plurality of memory cell rows and a plurality of memory cell columns along a first direction and a second direction, each memory cell includes a resistive switching device and a switching device, and the resistive switching device includes a first electrode and The second electrode, and the first electrode of the resistive switching device is electrically connected to the switching device.
  • the plurality of bit lines extend along the second direction and are respectively connected to the plurality of columns, wherein each of the plurality of bit lines corresponds to the resistance of a memory cell of a corresponding memory cell column
  • the second electrode of the device is electrically connected.
  • the plurality of word lines extend along the first direction and are respectively connected to the plurality of rows, and each of the plurality of word lines is electrically connected to a switching device of a memory cell of a corresponding memory cell row. connection.
  • the plurality of block selection circuits are respectively electrically connected to the plurality of bit lines in a one-to-one correspondence.
  • the plurality of initialization circuits are respectively electrically connected with the plurality of bit lines in a one-to-one correspondence.
  • the operation method includes: turning off the plurality of block selection circuits, and performing a first initialization operation and a second initialization operation on the memory cells of the selected at least one memory cell row through the plurality of initialization circuits and the plurality of bit lines.
  • the first initialization operation includes: applying a first initialization operation voltage V F 1 to the memory cells of the selected at least one memory cell row through the plurality of initialization circuits and the plurality of bit lines.
  • the second initialization operation includes: applying a second initialization operation voltage V F 2 to the memory cells of the selected at least one memory cell row through the plurality of initialization circuits and the plurality of bit lines.
  • the first initialization operation voltage V F 1 is greater than the second initialization operation voltage V F 2.
  • each initialization circuit includes a control terminal, a first terminal, and a second terminal, and the second terminal of each initialization circuit is electrically connected to a bit line corresponding to the initialization circuit;
  • the first initialization operation further includes : Applying a first initialization control voltage V FC 1 to the control terminals of the plurality of initialization circuits to turn on the plurality of initialization circuits, and the second initialization operation further includes: applying a second initialization control voltage to the plurality of initialization control circuits
  • the initialization control voltage V FC 2 is used to turn on the plurality of initialization circuits.
  • each of the plurality of initialization circuits includes a switching transistor, and the gate, the first pole, and the second pole of the switching transistor are the control terminal, the first terminal, and the second terminal of the initialization circuit, respectively.
  • the switching transistor is a P-type transistor, the first initialization control voltage V FC 1 is less than the first initialization operation voltage V F 1, and the second initialization control voltage V FC 2 is less than the second initialization operation Voltage V F 2.
  • is smaller than the difference between the second initialization operation voltage and the second initialization control voltage
  • the time of the first initialization operation is greater than the time of the second initialization operation.
  • the operation method further includes: after the second initialization operation, performing a first operation on the memory cells of the selected at least one memory cell row through the plurality of initialization circuits and the plurality of bit lines.
  • the third initialization operation includes: applying a third initialization operation voltage V F 3 to the memory cells of the selected at least one memory cell row through the plurality of initialization circuits and the plurality of bit lines.
  • the magnitudes of the first initialization operation voltage V F 1, the second initialization operation voltage V F 2, and the third initialization operation voltage V F 3 decrease in order.
  • the operation time of the first initialization operation, the second initialization operation, and the third initialization operation are sequentially reduced.
  • each initialization circuit includes a control terminal, a first terminal, and a second terminal, and the second terminal of each initialization circuit is electrically connected to a bit line corresponding to the initialization circuit; the first initialization operation further includes : Apply a first initialization control voltage V FC 1 to the control terminals of the plurality of initialization circuits to turn on the plurality of initialization circuits.
  • the second initialization operation further includes: applying a second initialization control voltage V FC 2 to the plurality of initialization control circuits to turn on the plurality of initialization circuits;
  • the third initialization operation further includes: applying a second initialization control voltage V FC 2 to the plurality of initialization control circuits;
  • the initialization control circuit applies a second initialization control voltage V FC 2 to turn on the plurality of initialization circuits, the difference between the first initialization operation voltage and the first initialization control voltage
  • At least one embodiment of the present disclosure also provides a resistive memory array, which includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines, and a plurality of block selection circuits.
  • the plurality of memory cells are arranged into a plurality of memory cell rows and a plurality of memory cell columns along the first direction and the second direction, wherein each memory cell includes a resistive switching device and a switching device, and the resistive switching device includes a first An electrode and a second electrode.
  • the switching device includes a control terminal, a first terminal, and a second terminal.
  • the first electrode of the resistive switching device is electrically connected to the first terminal of the switching device.
  • the plurality of bit lines extend along the second direction and are respectively connected to the plurality of memory cell columns in a one-to-one correspondence, and each of the plurality of bit lines corresponds to a memory cell of a corresponding memory cell column
  • the second electrode of the resistive switching device is electrically connected.
  • the plurality of word lines extend along the first direction and are respectively connected to the plurality of memory cell rows in a one-to-one correspondence, and each of the plurality of word lines corresponds to a memory cell of a corresponding memory cell row
  • the control terminal of the switching device is electrically connected.
  • the plurality of block selection circuits are electrically connected to the plurality of bit lines in a one-to-one correspondence, and each block selection circuit includes a control terminal, a first terminal, and a second terminal.
  • the control terminal of the block selection circuit is configured to receive the first terminal.
  • a control signal the first end of the block selection circuit is configured to receive a read and write operation voltage
  • the second end of the block selection circuit is electrically connected to a bit line corresponding to the block selection circuit
  • the block selection circuit is configured In response to the first control signal, the read and write operation voltage is written to the correspondingly connected bit line.
  • the second ends of the switching devices of the memory cells of each memory cell row are electrically connected to each other.
  • the resistive memory array further includes a plurality of source lines extending along the first direction and correspondingly connected to the plurality of memory cell rows.
  • the second ends of the switching devices of the memory cells of each memory cell row are electrically connected to each other through a corresponding source line.
  • the resistive memory array further includes a global source line, and the multiple source lines are electrically connected to the global source line, so that the global source line connects the memory cells of the multiple memory cell rows.
  • the second ends of the switching devices are electrically connected to each other.
  • the second ends of the switching devices of the memory cells of each memory cell row are all grounded.
  • the resistive random access memory array further includes a plurality of initialization circuits, the plurality of initialization circuits are respectively electrically connected to the plurality of bit lines in a one-to-one correspondence, and each initialization circuit includes a control terminal, a first terminal, and At the second end, the control end of the initialization circuit is configured to receive an initialization control voltage, the first end of the initialization circuit is configured to receive an initialization operation voltage, and the second end of the initialization circuit is connected to the bit corresponding to the initialization circuit.
  • the line is electrically connected, and the initialization circuit is configured to write the initialization operation voltage to the correspondingly connected bit line in response to the initialization control voltage.
  • At least one embodiment of the present disclosure also provides a resistive random access memory circuit, including the above-mentioned resistive random access memory array.
  • the resistive random access memory circuit further includes a source line control circuit configured to be electrically connected to the second end of the switching device of the memory cell of the one or more memory cell rows to provide Source line voltage.
  • the resistive memory circuit further includes a column selection circuit, a program and erase control circuit, and a read control circuit.
  • the read-write operation voltage includes a program operation voltage, an erase operation voltage, and a read operation voltage;
  • the column selection circuit is connected to the plurality of block selection circuits, and is configured to be connected to the plurality of block selection circuits to The resistive memory array provides the operating voltage;
  • the program and erase control circuit is connected to the column selection circuit and is configured to provide the resistive memory array with the program operating voltage through the column selection circuit And the erase operation voltage;
  • the read control circuit is connected to the column selection circuit and is configured to provide the read operation voltage to the resistive memory array through the column selection circuit.
  • At least one embodiment of the present disclosure further provides a driving method for driving the above-mentioned resistive random access memory array.
  • the driving method includes: applying a word line voltage through the plurality of word lines to select a row of memory cells, and A source line voltage is applied to the second end of the switching device of a row of memory cells to turn on the switching device and transfer the source line voltage to the first electrode of the resistive switching device of the selected row of memory cells, and through the multiple At least one of the bit lines applies an operating voltage to the second electrode of the resistive switching device of at least one memory cell in the selected row of memory cells.
  • the operating voltage includes the reading and writing operating voltage and the initializing operating voltage.
  • the source line voltage is a ground voltage.
  • Fig. 1A is a schematic diagram of a structure of a resistive switching device
  • Figure 1B is a graph of voltage-current characteristics of a resistive switching device
  • FIG. 2A is a schematic diagram of a structure of a resistive switching memory cell
  • FIG. 2B is a schematic diagram of the structure of a resistive random access memory array
  • 2C is a schematic diagram of the structure of a resistive random access memory circuit
  • FIG. 3 is a schematic structural diagram of a resistive memory array provided by at least one embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of signal waveforms of a method for operating a resistive memory array provided by at least one embodiment of the present disclosure
  • FIG. 5 is a flowchart of a method for operating a resistive memory array provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic structural diagram of a resistive random access memory circuit provided by at least one embodiment of the present disclosure
  • FIG. 7A is a schematic structural diagram of another resistive memory array provided by at least one embodiment of the present disclosure.
  • FIG. 7B is a schematic structural diagram of still another resistive memory array provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another resistive random access memory circuit provided by at least one embodiment.
  • the memory device used in the resistive random access memory (referred to as a resistive random access device or RRAM device) is, for example, a flat capacitor shape, including a metal-insulator-metal (MIM) structure.
  • Fig. 1A shows a schematic structural diagram of a resistive switching device
  • Fig. 1B shows a current-voltage (I-V) characteristic curve of the resistive switching device.
  • the resistive switching device 10 includes a first electrode 11, a second electrode 12, and a resistive switching medium layer 13 located between the first electrode 11 and the second electrode 12.
  • the first electrode 11 is The bottom electrode of the resistive switching device 10
  • the second electrode 12 is the top electrode of the resistive switching device.
  • the first electrode 11 and the second electrode 12 may include metal materials such as aluminum, silver, copper, platinum, titanium, or composite metal materials, or include semiconductor materials such as polysilicon.
  • the resistive dielectric layer 13 may include one or more composite dielectric layers; for example, the resistive dielectric layer 13 may include metal oxide materials such as hafnium oxide, copper oxide, titanium oxide, tantalum oxide, or other materials with resistive characteristics. Medium material.
  • the IV characteristic curve of the resistive switching device 10 has hysteresis characteristics, and the curve is divided into 4 regions: high resistance state (HRS), low resistance state (LRS) and two regions. A transition zone.
  • HRS high resistance state
  • LRS low resistance state
  • a transition zone When the voltage amplitude exceeds a certain threshold, the resistance of the resistive switching device can be changed, so that the newest resistive switching device 10 can be rewritten (including a programming operation and an erasing operation).
  • a forward voltage (V Set ) is applied to both ends of the resistive switching device 10 to change the resistance value from a high-resistance state to a low-resistance state, which is called Set operation, also called write operation or programming.
  • Set operation also called write operation or programming.
  • the voltage amplitude for realizing the programming operation and erasing operation is generally between 1.2V-3V.
  • the resistive switching device is generally in a high resistance state after the preparation is completed, and a higher initialization operating voltage (for example, higher than 3V) is required to initialize the resistive switching device.
  • a higher initialization operating voltage for example, higher than 3V
  • the resistive switching device can be reduced Complete the programming operation or erase operation under the voltage.
  • This initialization operation is also called the Forming operation.
  • a higher voltage soft breakdown (Soft Breakdown) initialization operation needs to be added.
  • the initialization operation voltage required for the initialization operation is higher than the voltage required for the Set/Reset operation, and the operation time is longer.
  • the initial operation voltage V F is between 2V-6V.
  • the resistive switching device is usually electrically connected (for example, in series) with a switching device to form a basic memory cell.
  • the switching device may be a two-terminal element (for example, a diode) or a three-terminal element (for example, a transistor).
  • FIG. 2A shows a schematic structural diagram of a memory cell.
  • the memory cell 30 includes a resistive switching device 10 and a switching device 20.
  • the switching device 20 is a three-terminal element including a control terminal 21, a first terminal 22 and a second terminal 23, and the first terminal 22 of the switching device 20 is electrically connected to the first electrode 11 of the resistive switching device 10.
  • the first electrode 11 is the negative electrode of the resistive switching device 10
  • the second electrode 12 is the positive electrode of the resistive switching device 10.
  • the resistive switching device is forward biased; when the voltage on the first electrode 11 is greater than the voltage on the second electrode 12, the resistive switching device is reverse biased.
  • the switching device 20 can also be connected to the second electrode (positive electrode) of the resistive switching device, and the magnitude relationship of the input signal is adjusted accordingly during operation to achieve the same function.
  • the switching device includes a diode or a triode to form a 1D1R or 1T1R memory cell structure.
  • the switching device includes a first transistor T1, including a Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET), so that the 1T1R memory cell has a good performance with the existing CMOS integrated circuit.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • the gate, the first pole and the second pole of the first transistor T1 serve as the control terminal, the first terminal and the second terminal of the switching device, respectively.
  • the storage unit 30 When the switching device 20 is turned on, the storage unit 30 is selected for reading and writing operations of the RRAM device, etc.; when the switching device 20 is turned off, the storage unit 30 is not selected.
  • the transistors used in the embodiments of the present disclosure may be field-effect transistors, thin-film transistors, or other switching devices with the same characteristics.
  • field-effect transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole in order to distinguish the two poles of the transistor other than the gate, for example, one pole can be directly described as the first pole and the other pole is the second pole.
  • a plurality of resistive memory cells can be integrated into an RRAM storage array in a crosswise manner, and the storage device can include one or more of the storage arrays.
  • FIG. 2B shows a schematic diagram of a resistive random access memory array structure.
  • the resistive random access memory array 40 includes an array of m columns and n rows (m, n is greater than or equal to 2) of memory cells 30, and multiple bit lines.
  • BL(BL ⁇ 0>-BL ⁇ m-1>) multiple word lines WL(WL ⁇ 0>-WL ⁇ n-1>) and multiple source lines SL(SL ⁇ 0>-SL ⁇ m-1>).
  • the second electrode 12 of the resistive switching device 10 in each memory cell 30 is connected to a bit line BL, and the control terminal 21 and the second terminal 23 of the switching device 20 are respectively connected to a word line WL and a source line SL.
  • the required memory cell 30 can be selected for the aforementioned initialization (Forming), programming (Set), erasing (Reset) and reading (Read) operating.
  • FIG. 2C shows a schematic structural diagram of a resistive random access memory circuit.
  • the resistive memory circuit includes one or more resistive memory arrays 40 and peripheral circuits.
  • the peripheral circuit includes a word line control circuit, a column selection circuit, an initialization control circuit, a programming control circuit, an erasing control circuit, a reading control circuit, etc.
  • the word line control circuit is connected to the word line WL.
  • a control voltage signal is applied to the word line WL in a row-by-row scanning manner, so that a row of memory cells 30 (that is, the storage connected to the same word line WL) is applied in each scanning period.
  • the switching device 20 in the cell performs control, so that a row of memory cells 30 can be selected.
  • the initialization control circuit generates an initialization operation voltage pulse V F and applies it to one or several bit lines BL through the column selection circuit to perform an initialization operation on the selected one or several memory cells 30.
  • the programming control circuit generates a programming operation voltage pulse (V Set ) and applies it to one or several bit lines BL through the column selection circuit to perform a programming operation on the selected one or several memory cells 30.
  • V Set a programming operation voltage pulse
  • the erase control circuit generates an erase operation voltage pulse (V RST ) and applies it to one or several source lines SL through a column selection circuit to perform an erase operation on the selected one or several memory cells 30.
  • V RST erase operation voltage pulse
  • the read control circuit generates a read operation voltage pulse V Read and applies it to one or several bit lines BL through the column selection circuit to perform a read operation on the selected one or several memory cells 30.
  • the column selection circuit may include an address decoder, and may be configured to receive an address signal.
  • the column selection circuit can receive the column address of the memory cell to be accessed, such as the bit line address, under the control of the controller, and decode the received bit line address.
  • the peripheral circuit that provides and transmits the initializing operation voltage and the resistive memory array 20 that receives the initializing operation voltage need to meet higher withstand voltage requirements.
  • the initialization control circuit since the initialization control circuit generates the initialization operating voltage and transmits it to the resistive memory array through the column selection circuit, the initialization control circuit, the column selection circuit, and the transistors in the resistive memory array need to have relatively high values.
  • a large size for example, the length and width of the channel region of the transistor is larger
  • to meet the higher withstand voltage requirements which not only increases the size and manufacturing cost of the circuit, but also reduces the read and write performance of the memory.
  • the initialization time required for different resistive switching devices to change the resistance value is different, and the resistance value after the initialization operation is also different.
  • This difference in resistance value will lead to the reliability of subsequent rewriting operations.
  • the performance deteriorates and the error rate of stored data increases.
  • At least one embodiment of the present disclosure provides a resistive random access memory array, including a plurality of block selection circuits and a plurality of initialization circuits, the plurality of block selection circuits are connected to a plurality of bit lines in a one-to-one correspondence, and the plurality of initialization circuits are also connected to the The multiple bit lines are electrically connected in a one-to-one correspondence.
  • the block selection circuit is configured to write the operation voltage to the correspondingly connected bit line in response to the block selection voltage; the initialization circuit is configured to write the initialization operation voltage to the correspondingly connected bit line in response to the initialization control voltage.
  • the transmission of the initialization circuit and the initialization operation voltage is separated from the transmission of other control circuits and the operation voltage, so that the initialization operation voltage is low Transmission may not go through the column selection circuit described above.
  • the block selection circuit can be controlled to be turned off to prevent the initialization operation voltage applied from the initialization circuit to the bit line from being applied to the column selection circuit, thereby reducing the withstand voltage requirements of the column selection circuit.
  • the resistive memory array provided by the embodiments of the present disclosure helps to reduce the circuit range involved in the higher initializing operation voltage, reduce the withstand voltage requirements of the circuit, and thereby help reduce the circuit size and manufacturing cost.
  • the entire row (one or more rows) of memory cells can be initialized at the same time, which significantly shortens the time of the initialization operation, improves the efficiency of the initialization test operation, and reduces the cost of the initialization test.
  • FIG. 3 is a schematic structural diagram of a resistive memory array 50 provided by at least one embodiment of the present disclosure.
  • the resistive memory array 50 includes a plurality of memory cells 30, a plurality of bit lines BL (BL ⁇ 0>-BL ⁇ m-1>), and a plurality of word lines WL (WL ⁇ 0>-WL). ⁇ n-1>), a plurality of block selection circuits 53 and a plurality of initialization circuits 54.
  • the plurality of memory cells 30 are arranged into n memory cell rows and m memory cell columns (m and n are greater than or equal to 2) along the first direction D1 and the second direction D2.
  • the first direction D1 and the second direction D2 are the row direction and the column direction of the array, respectively.
  • the plurality of bit lines BL extend along the second direction D2 and are connected to the plurality of memory cell columns in a one-to-one correspondence. Each of the plurality of bit lines BL is connected to each memory cell of a corresponding memory cell column.
  • the second electrode 12 of the resistive switching device 10 is electrically connected.
  • the plurality of word lines WL extend along the first direction D1 and are connected in a one-to-one correspondence with the plurality of memory cell rows. Each of the plurality of word lines WL corresponds to each memory cell of a corresponding memory cell row.
  • the switching device 20 is electrically connected. As shown in FIG. 3, each word line WL is electrically connected to the control terminal 21 of the correspondingly connected switching device 20 to provide a word line voltage V WL .
  • the plurality of block selection circuits 53 are respectively electrically connected to the plurality of bit lines BL in a one-to-one correspondence.
  • the plurality of block selection circuits 53 are arranged along the first direction D1 and located on the first side of the array formed by the plurality of memory cells.
  • the plurality of initialization circuits 54 are respectively electrically connected to the plurality of bit lines BL in a one-to-one correspondence.
  • the plurality of initialization circuits 54 are arranged along the first direction D1 and located on the second side of the array formed by the plurality of memory cells. The second side and the first side are opposite sides of the memory cell array in the second direction D2.
  • Each block selection circuit 53 includes a control terminal 530, a first terminal 531, and a second terminal 532.
  • the control terminal 530 of the block selection circuit 53 is configured to receive the block selection voltage V BS
  • the first terminal 531 of the block selection circuit 53 is configured
  • the second terminal 532 of the block selection circuit 53 is electrically connected to the bit line BL corresponding to the block selection circuit 53.
  • the block selection circuit 53 is configured to respond to the block selection voltage V BS to set the The read and write operation voltage is written to the bit line BL corresponding to the connection.
  • the read and write operation voltage includes the above-mentioned program operation voltage V Set and read operation voltage V Read .
  • the block selection circuit 53 includes a second transistor T2, and the gate, first pole, and second pole of the second transistor T2 serve as the control terminal 530, the first terminal 531, and the second terminal 532 of the block selection circuit, respectively.
  • Each initialization circuit 54 includes a control terminal 540, a first terminal 541, and a second terminal 542.
  • the control terminal 540 of the initialization circuit 54 is configured to receive the initialization control voltage V FC
  • the first terminal 541 of the initialization circuit 54 is configured to receive initialization.
  • Operating voltage V F the second terminal 542 of the initialization circuit 54 is electrically connected to the bit line BL corresponding to the initialization circuit 54
  • the block selection circuit is configured to respond to the initialization control voltage V FC , the initialization operation voltage V F Write the corresponding bit line BL connected.
  • the initialization circuit 54 includes a third transistor T3 (an example of the switching transistor in the embodiment of the present disclosure), and the gate, first electrode, and second electrode of the third transistor T3 are the control terminal 540 of the initialization circuit 54 respectively. , The first end 541 and the second end 542.
  • the resistive random access memory array 50 further includes a block selection line BSL, which extends along the first direction D1 and is connected to the control terminals of the plurality of block selection circuits to provide a block selection voltage V BS .
  • the resistive random access memory array 50 further includes a plurality of global bit lines GBL (GBL ⁇ 0>-GBL ⁇ m-1>), and the plurality of global bit lines GBL are along the first It extends in two directions D2 and is electrically connected to a plurality of block selection circuits 53 in a one-to-one correspondence.
  • Each global bit line GBL is electrically connected to the first end 531 of the correspondingly connected block selection circuit 53.
  • At least one embodiment of the present disclosure further provides a resistive random access memory array structure, including a plurality of the above-mentioned resistive random access memory arrays 50, the plurality of resistive random access memory arrays 50, for example, are arrayed along the first direction D1 and the second direction D2.
  • the upper-level array also includes multiple rows and multiple columns. For example, the memory cell columns of the resistive memory array in the same column in the upper-level array can be aligned with each other. Similarly, the memory of the resistive memory array in the same row The rows of cells can be aligned with each other.
  • the multiple global bit lines GBL correspond to the same column of memory cells of the multiple resistive memory arrays in the resistive memory array structure
  • each global bit line GBL corresponds to a plurality of memory cells in the resistive memory array structure.
  • the first terminals 531 of the block selection circuits 53 in the same column of the resistive memory array are connected correspondingly, that is, the first terminals 531 of the plurality of block selection circuits 53 in the same column in the plurality of resistive memory arrays are all connected to the same corresponding one.
  • the global bit line GBL is electrically connected.
  • the block selection voltage V BS can be applied to the resistive memory array 50 to be accessed to select the resistive memory array 50.
  • This block (division) operation can reduce the circuit load and improve the response speed of the circuit.
  • the resistive memory array 50 further includes a plurality of source lines SL (SL ⁇ 0>-SL ⁇ m-1>), and the plurality of source lines SL are along the second direction D2.
  • a plurality of source lines SL are electrically connected to a plurality of memory cell columns in a one-to-one correspondence, and each of the plurality of source lines SL is electrically connected to the second end 23 of the switching device 20 of the memory cell of a corresponding memory cell column.
  • the resistive memory array 50 further includes a plurality of initialization operation lines FL and a plurality of initialization control lines FCL, and the plurality of initialization operation lines FL and the plurality of initialization control lines FCL extend along the first direction D1.
  • the initialization operation line FL is connected to the first terminal of the initialization circuit 54 to provide the initialization operation voltage V F
  • the initialization control line FCL is connected to the control terminal of the initialization circuit 54 to provide the initialization control voltage V FC .
  • the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors or P-type transistors.
  • the third transistor T3 is a P-type transistor
  • the threshold voltage of the P-type transistor is less than 0. Therefore, the voltage applied to the gate is
  • the initialization control voltage V FC can be less than the initialization operation voltage V F applied to the first pole, which further reduces the withstand voltage requirements of the circuit.
  • the embodiment of the present disclosure also provides an operating method for operating the resistive random access memory array 50 described above.
  • the operation method includes: in the initialization operation stage, turning off a plurality of block selection circuits, and applying an initialization operation voltage to the selected at least one row of memory cells through a plurality of initialization circuits and a plurality of bit lines to initialize the at least one row of memory cells.
  • the first transistor T1 and the second transistor T2 are both N-type transistors
  • the third transistor T3 is a P-type transistor.
  • the embodiments of the present disclosure do not limit the types of the first to third transistors. When the type changes, adjust the size relationship between the signals accordingly to make the circuit achieve the same function.
  • a positive word line voltage V WL is applied through a selected word line WL (for example, corresponding to one or more rows of memory cells) and a plurality of source lines SL are controlled to be grounded, so that The switching device 20 (first transistor T1) in the one or more rows of memory cells 30 is turned on, that is, the one or more rows of memory cells are selected.
  • the block selection circuit 53 is turned off by applying the block selection voltage V BS to the block selection circuit 53 through the block selection line BSL.
  • the control block selection line BSL is grounded so that the second transistor T2 is turned off.
  • the block selection circuit is turned off to separate the transmission of the initialization circuit and the initialization operation voltage from the transmission of other control circuits and the operation voltage, thereby reducing the amount involved in the initialization operation voltage.
  • the range of the circuit reduces the withstand voltage requirements and size of the circuit.
  • the initialization operation voltage V F is applied to the initialization operation line FL, and the initialization control voltage V FC is applied to the initialization control line FCL to turn on the third transistor T3, so that the initialization circuit is turned on, and the initialization operation voltage V F
  • the initialization circuit 54 and the plurality of bit lines BL are transferred to the second electrode 12 of the resistive switching device 10 of the selected at least one row of memory cells.
  • the first electrode 11 of the resistive switching device is grounded through the corresponding source line SL through the turned-on switching device 20, so a positive voltage difference V F is introduced at both ends of the resistive switching device, and the resistive switching device is softly broken down.
  • the initial high-impedance state is changed to the low-impedance state, so that at least one row of selected memory cells is simultaneously initialized (Forming).
  • the third transistor T3 is a P-type transistor.
  • the initialization operation voltage V F is applied to the initialization operation line FL
  • the initialization control voltage V FC is applied to the initialization control line FCL
  • the initialization operation voltage V F is higher than the initialization control voltage V FC , so that the third transistor T3 is turned on, and the initialization circuit 54 is turned on.
  • the initialization operation voltage V F is between 2V and 6V.
  • the initialization control voltage V FC of the pulse time (T F) in the range of 1 microsecond to 10 milliseconds.
  • FIG. 4 is a schematic waveform diagram of a process of simultaneous initialization operation of different memory cells in the initialization operation stage of the operation method provided by the embodiment of the disclosure.
  • FIG. 4 schematically shows the voltage and current waveforms of the resistive switching devices in three memory cells (R1, R2, R3) located in the same row but in different columns during the initialization operation.
  • the resistance value of the resistive switching device 10 in the selected memory cell is very high, the conduction current is very small, and the current flowing through the corresponding third transistor T3 is also very small.
  • the third transistor T3 Working in the linear region, the voltage difference between the first pole and the second pole of the third transistor T3 is very small, the initialization operation voltage V F can be regarded as all applied to the resistive switching device 10;
  • the resistance value of the resistance switching device 10 becomes lower, the conduction current increases, and the current flowing through the third transistor T3 also increases; when the current increases to the saturation of the third transistor T3
  • the current (I DS, Sat ) the third transistor T3 enters the saturation region, the voltage difference between the first pole and the second pole of the third transistor T3 increases, and the conduction current remains unchanged, and is transmitted to the resistive switching device 10
  • the voltage on the upper side also drops and eventually stops at the lowest threshold voltage (V Form, TH ) of the initialization operation.
  • the lowest threshold voltage is also the lowest transition voltage of the resistive switching device.
  • the resistance value of the resistive switching device is reduced; when the external voltage is lower than the minimum threshold voltage, the resistance value of the resistive switching device remains unchanged.
  • the lowest threshold voltage is an inherent property of the resistive switching device, for example, it is related to the material, process, and structure of the resistive switching device. After the above-mentioned initialization operation, the resistance value of the resistive switching device 10 is the ratio of the lowest threshold voltage to the saturation current V Form,TH / IDS,Sat .
  • the operating method provided by the embodiments of the present disclosure can limit the voltage and the maximum conduction current applied to the resistive switching device 10 in the selected memory cell, that is, limit the passage of the resistive switching device.
  • the resistance value after the initialization operation Therefore, although multiple memory cells located in one or more rows that are selected for initialization at the same time require different resistance values due to differences in structure, material, process, etc., they ultimately reach the same resistance value or Similar, the consistency and reliability of the storage unit have been significantly improved; compared to the operation one by one, the initialization operation time is greatly shortened.
  • the resistance switching time of memory cells R1, R2, R3 located in the same row but in different columns is increased (postponed) sequentially, but the resistance switching device 10 finally reaches the same resistance value V Form,TH / I DS, Sat , have consistency.
  • the saturation current IDS,Sat of the third transistor T3 can be set to set the resistance value of the resistive switching device after the initialization operation.
  • the initialization operation will have a great impact on the reliability of the subsequent Set/Reset operation. If the resistance value of the resistive switching device is too high after the initialization operation, the reliability of the subsequent Set operation will become worse; on the contrary, if the resistance after the initialization operation is The resistance value of the variable device is too low, and the reliability of the subsequent Reset operation deteriorates.
  • the above operation method can finely control the resistance value of the resistive switching device in the memory cell after the initialization operation, so that the resistance value of the resistive switching device after the initialization operation is in a proper range, thereby improving subsequent Set and Reset.
  • the reliability of the rewrite operation For example, the resistance value is located between the maximum resistance (corresponding to the high resistance state) and the minimum resistance (corresponding to the low resistance state) in the write operation after the initialization operation of the resistive switching device.
  • the resistive memory array and its operation method proposed by the embodiments of the present disclosure can realize one or more rows without sacrificing the consistency and reliability of the memory cells.
  • the storage unit performs the initialization operation at the same time, which significantly shortens the time of the initialization operation, improves the efficiency of the initialization test operation, and reduces the cost of the initialization test.
  • the memory array is subject to the voltage stress of the initialization operation to shorten the time, and the switching devices of the memory cell can be designed with low voltage MOSFET transistors with a withstand voltage below 3V, which greatly reduces the area and manufacturing cost of the memory array. .
  • the operation method further includes a programming operation stage and an erasing operation stage.
  • the programming operation stage the resistive switching device in the selected memory cell is applied with a forward voltage to realize the programming operation of the selected memory cell;
  • a reverse voltage is applied to the resistive switching device in the selected memory cell to realize the erasing operation of the selected memory cell.
  • the resistance of the resistive switching device changes from high to low after the programming operation, and changes from low to high after the erase operation.
  • the selected memory cell is a memory cell to be programmed in the programming operation stage, for example, one or more memory cells in a row.
  • the bit line voltage is applied to the second electrode (positive electrode) of the resistive switching device of the selected memory cell through the block selection tube and the bit line, and the resistance of the selected memory cell through the source line and the switching device is applied.
  • the first electrode (negative electrode) of the variable device is applied with a source line voltage.
  • the lower voltage of the bit line voltage and the source line voltage can be set as the ground voltage, that is, the corresponding signal line (bit line or source line) can be controlled to be grounded; accordingly, the higher The voltage (program operation voltage or erase operation voltage) is designed to be a positive voltage.
  • the bit line voltage is the programming operation voltage
  • the source line voltage is the erasing operation voltage
  • multiple initialization circuits are turned off, and the block selection circuit is turned on; at least one block selection circuit 53 and at least one bit line BL apply a positive programming operation voltage V Set to the selected memory cell, and The source line SL corresponding to the selected memory cell is controlled to be grounded, so that a forward voltage is applied to the resistive switching device to perform a programming operation on the memory cell.
  • the second transistor T2 is of an N-type
  • a positive block selection voltage V BS is applied to the block selection line of the selected resistive memory array
  • the program operation voltage V Set is applied to at least one global bit line GBL to reduce the corresponding at least A block selection circuit is turned on, and the programming operation voltage V Set is transferred to the corresponding bit line BL and applied to the second electrode 12 of the resistive switching device of the selected memory cell.
  • the word line voltage V WL is applied to the control terminal of the switching device 20 (first transistor T1) in a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), and the source line voltage is applied to the selected The source line SL corresponding to the memory cell.
  • the first transistor T1 is an N-type transistor
  • the word line voltage V WL is a positive voltage
  • the source line SL is grounded, so that the switching device in the selected memory cell in the row of memory cells is turned on, and the resistive switching device The first electrode 11 is grounded.
  • the magnitude of the programming operation voltage V Set is between 1.2V and 3V, and the pulse time is between 1 nanosecond and 10 microseconds.
  • the operation method further includes: in the erasing operation phase, multiple initialization circuits are turned off, and the block selection circuit is turned on; applying a positive erase operation voltage V RST to the selected memory cell through the source line SL, and selecting at least one block
  • the circuit 53 controls the bit line BL corresponding to the selected memory cell to be grounded, thereby applying a reverse voltage to the resistive switching device to perform an erase operation on the memory cell.
  • the second transistor T2 is of an N-type, a positive block selection voltage V BS is applied to a block selection line of the resistive random access memory array, and at least one global bit line GBL is grounded to turn on the corresponding at least one block selection circuit , And ground the second electrode 12 of the resistive switching device of the selected memory cell.
  • the positive word line voltage V WL is applied to the control terminal of the switching device 20 (first transistor T1) in a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), and the erase operation
  • the voltage V RST is applied to at least one source line SL to turn on the switching device of the selected memory cell, and the erase operation voltage V RST is transferred to the first electrode 11 of the resistive switching device of the selected memory cell.
  • the magnitude of the erase operation voltage V RST is between 1.2V and 3V, and the pulse time is between 1 nanosecond and 10 microseconds.
  • the operation method also includes a read operation phase. For example, during the read operation stage, multiple initialization circuits are turned off, and at least one block selection circuit (corresponding to the selected memory cell) is turned on, thereby performing a read operation on the selected memory cell.
  • the selected storage unit is the storage unit to be read.
  • the second transistor T2 is an N-type transistor, a positive block selection voltage V BS is applied to a block selection line BSL of a selected resistive memory array, and a read operation voltage V Read is applied to at least one block selection line BSL of the resistive random access memory array.
  • the global bit line GBL (corresponding to the selected memory cell), so that the at least one block selection circuit is turned on, and the read operation voltage V Read is transferred to the first resistive switching device of the selected memory cell through the corresponding bit line BL.
  • the positive word line voltage V WL is applied to the control terminal of the switching device 20 (first transistor T1) of a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), and the multiple source lines SL Grounding, so that the switching device in the selected memory cell in the row of memory cells is turned on, and the first electrode 11 of the resistive switching device is grounded.
  • a positive V Read voltage difference is introduced across the electrodes of the resistive switching device of the selected memory cell, and a conduction read current (I Read ) is generated.
  • the resistance value of the resistance switching device is high, and the reading current is small; the resistance value is low, and the reading current is large.
  • the reading operation of the selected memory cell can be completed by detecting the reading current through the peripheral reading control circuit.
  • the read operation voltage V Read is between 0.1V and 1.2V
  • the pulse time (T Set ) is between 1 nanosecond and 10 microseconds.
  • At least one embodiment of the present disclosure also provides an operating method for operating the resistive random access memory array 50 described above.
  • the operation method includes performing the above-mentioned initialization operations on the resistive random access memory array multiple times during the initialization operation stage.
  • the number of initialization operation steps is between 2 and 100, or more.
  • the performance of the resistive switching device and the switching device in each memory cell are different.
  • the lowest threshold voltage (V Form, TH ) of each resistive switching device is different, and the saturation current (I DS, Sat ) of each switching device under the same voltage condition is different, so the final resistance value of the resistive switching device after the initial operation Different, there is a resistance distribution.
  • the resistance value of the entire row (one or more rows) of memory cells can be changed.
  • the resistance value of the device is successively reduced, and finally reaches the required target value.
  • the resistance value of the resistive switching device obtained by this method has better accuracy and consistency.
  • the resistance value distribution of the resistive switching device becomes narrower and the average value is lower.
  • the standard deviation of the resistance value distribution of the plurality of resistive switching devices is sequentially reduced, and the weighted average value of the resistance values is sequentially reduced.
  • the initialization operation voltage V F sequentially decreases with the time sequence of the initialization operation.
  • the saturation current increase effect caused by factors such as the short channel effect of the third transistor T3 can be alleviated, so that the standard deviation of the resistance value distribution of the resistive switching device after the initializing operation is reduced, thereby The resistance value distribution is narrower and more uniform.
  • V F- V FC increases sequentially with the time sequence of the initialization operation.
  • initialization operation time T F are sequentially initializing operation decreases with time sequence.
  • the initialization operation time of the multi-step initialization operation is sequentially reduced as the initialization operation progresses. Can save the power consumption of the circuit. For example, the time for the first step of the initialization operation can be set to the longest.
  • the operation method includes: turning off the plurality of block selection circuits, and performing a first initialization operation and a second initialization operation on the selected at least one row of memory cells through the plurality of initialization circuits and the plurality of bit lines.
  • the first initialization operation includes: applying a first initialization operation voltage V F 1 to the selected at least one row of memory cells through the plurality of initialization circuits and the plurality of bit lines;
  • the second initialization operation includes: The plurality of initialization circuits and the plurality of bit lines apply the second initialization operation voltage V F 2 to the selected at least one row of memory cells.
  • the first initialization operation precedes the second initialization operation.
  • the first initialization operation voltage V F 1 is different from the second initialization operation voltage V F 2.
  • the first initialization operation voltage and the second initialization operation voltage are both configured to be applied to the second electrode 12 (positive electrode) of the resistive switching device of the memory cell to make the resistive switching device forward bias.
  • the first initialization operation further includes: applying a positive word line voltage V WL through the selected word line WL (corresponding to connecting one or more rows of selected memory cells) and controlling the multiple source lines SL to be grounded, thereby making the selected row Or, the switching device 20 (the first transistor T1) in the memory cell 30 of the plurality of rows is turned on.
  • the second initialization operation further includes: applying a positive word line voltage V WL through the selected word line WL (corresponding to connecting one or more rows of selected memory cells) and controlling the multiple source lines SL to be grounded, thereby making the selected row Or, the switching device 20 (the first transistor T1) in the memory cell 30 of the plurality of rows is turned on.
  • the first initialization operation further includes: applying a first initialization control voltage V FC 1 to the control terminals of the plurality of initialization circuits to turn on the plurality of initialization circuits;
  • the second initialization operation further includes: The initialization control circuit applies a second initialization control voltage V FC 2 to turn on the plurality of initialization circuits.
  • the first initialization operation voltage V F 1 is greater than the second initialization operation voltage V F 2.
  • the saturation current increase effect caused by factors such as the short channel effect of the third transistor T3 can be alleviated, so that the standard deviation of the resistance value distribution of the resistive switching device after the initializing operation is reduced, thereby The resistance value distribution is narrower and more uniform.
  • is smaller than the difference between the second initialization operation voltage and the second initialization control voltage
  • the time of the first initialization operation is greater than the time of the second initialization operation.
  • may also be the difference between the second initialization operation voltage and the second initialization control voltage
  • the embodiments of the present disclosure do not limit the type of the third transistor T3.
  • the third transistor T3 may be P-type or N-type, and an appropriate initialization operation voltage and initialization control voltage are selected according to the corresponding transistor type to enable the initialization circuit to turn on.
  • the third transistor T3 is a P-type transistor, the first initialization control voltage V FC 1 is less than the first initialization operation voltage V F 1 to turn on the plurality of initialization circuits, and the second initialization control voltage V F 2 is less than the first initialization operation voltage V F 1. 2.
  • Initializing the operating voltage V FC 2 to turn on the plurality of initialization circuits.
  • the initialization control voltage V FC is less than the initialization operation voltage V F.
  • setting the third transistor T3 to P type can reduce the circuit The withstand voltage requirements.
  • the operation method further includes: after the second initialization operation, performing a third initialization operation on the selected at least one row of memory cells through the plurality of initialization circuits and the plurality of bit lines.
  • the third initialization operation includes: applying a third initialization operation voltage V F 3 to the selected at least one row of memory cells through the plurality of initialization circuits and the plurality of bit lines.
  • the magnitudes of the first initialization operation voltage V F 1, the second initialization operation voltage V F 2, and the third initialization operation voltage V F 3 decrease in order.
  • the third initialization operation further includes: applying a third initialization control voltage V FC 3 to the plurality of initialization control circuits to turn on the plurality of initialization circuits.
  • the first initializing operation voltage V F 1, the second initializing operating voltage V F 2, the third initializing operating voltage V F 3, the first initializing control voltage V FC 1, the second initializing control voltage V FC 2, the third The size of the initialization control voltage V FC 3 is between 2V and 6V.
  • the operation time of the first initialization operation, the second initialization operation, and the third initialization operation are sequentially reduced.
  • FIG. 5 shows a flowchart of a method for operating a resistive memory array provided by at least one embodiment of the present disclosure.
  • FIG. 5 shows an example of performing three initialization operations, but the embodiment of the present disclosure does not limit the number of initialization operation steps.
  • the operation method includes steps S1-S4.
  • Step S1 Turn off multiple block selection circuits.
  • applying the block selection voltage V BS to the block selection circuit 53 through the block selection line BSL turns the block selection circuit 53 off.
  • the second transistor T2 is an N-type transistor, and the block selection line BSL is grounded, that is, the block selection voltage V BS is zero.
  • the block selection circuit By setting the block selection circuit off to separate the transmission of the initialization circuit and the initialization operation voltage from the transmission of other control circuits and operation voltages, the range of the circuit involved in the initialization operation voltage is reduced, and the withstand voltage of the circuit is reduced. Requirements and dimensions.
  • the first transistor T1 is an N-type transistor, and the word line voltage V WL is applied through the selected word line WL (corresponding to the memory cells selected in one or more rows), and the multiple source lines SL are grounded, so that the one row or The switching device 20 (the first transistor T1) in the multiple rows of memory cells 30 is turned on, that is, the one or more rows of memory cells are selected.
  • the first electrode 21 of the switching device 20 is grounded.
  • Step S2 Perform a first initialization operation on the selected at least one row of memory cells through a plurality of initialization circuits and a plurality of bit lines.
  • the first initialization operation includes respectively applying a first initialization operation voltage V F 1 to the initialization operation line FL, and applying a second initialization control voltage V FC 2 to the initialization control line FCL so that the initialization circuit is turned on and the initialization operation voltage is applied.
  • V F 1 is transferred to the second electrode 22 of the switching device.
  • the third transistor T3 is a P-type transistor.
  • the first initialization operation voltage V F is greater than the first initialization control voltage V FC , so that the third transistor T3 is turned on, and the initialization circuit 54 Turn on.
  • the first initializing operation voltage V F 1 is between 2V and 6V.
  • the first initialization control voltage V FC 1 pulse time (T F) in the range of 1 microsecond to 10 milliseconds.
  • the plurality of resistive switching devices have a first resistance distribution and a first average resistance value (for example, a weighted average value) after the first initialization operation.
  • the standard deviation of the first resistance distribution is lower than the standard deviation of the initial resistance distribution, and the first average resistance is lower than the initial average resistance.
  • Step S3 Perform a second initialization operation on the selected at least one row of memory cells through a plurality of initialization circuits and a plurality of bit lines.
  • the second initialization operation includes: respectively applying the initialization operation voltage V F 2 to the initialization operation line FL, and the initialization control voltage V FC 2 to the initialization control line FCL so that the initialization circuit is turned on and the initialization operation voltage V F is applied. 2 is transferred to the second electrode 22 of the switching device. There is a positive voltage difference V F 2 at both ends of the resistive switching device 20, and its resistance value drops from the first resistance value to the second resistance value.
  • the third transistor T3 is a P-type transistor.
  • the second initializing operation voltage V F 2 is greater than the second initializing control voltage V FC 2, so that the third transistor T3 is turned on.
  • the circuit 54 is turned on.
  • the second initializing operation voltage V F 2 is between 2V and 6V.
  • the pulse time of the second initialization control voltage V FC 2 is in the range of 1 microsecond to 10 milliseconds.
  • the plurality of resistive switching devices have a second resistance distribution and a second average resistance value (for example, a weighted average value) after the second initialization operation.
  • the standard deviation of the second resistance distribution is smaller than the standard deviation of the first resistance distribution, that is, the resistance distribution is more convergent after the second initialization operation.
  • the second average resistance value is less than the first average resistance value.
  • Step S4 Perform a third initialization operation on the selected at least one row of memory cells through a plurality of initialization circuits and a plurality of bit lines.
  • the third initialization operation includes: respectively applying the initialization operation voltage V F 3 to the initialization operation line FL, and the initialization control voltage V FC 3 to the initialization control line FCL so that the initialization circuit is turned on and the initialization operation voltage V F is applied. 3 is transferred to the second electrode 22 of the switching device. There is a positive voltage difference V F 3 between the two ends of the resistive switching device 20, and the resistance value thereof drops from the second resistance value to the third resistance value.
  • the third transistor T3 is a P-type transistor.
  • the third initialization operation voltage V F 3 is greater than the third initialization control voltage V FC 3, so that the third transistor T3 is turned on, and the initialization The circuit 54 is turned on.
  • the third initializing operation voltage V F 3 is between 2V and 6V.
  • the pulse time of the third initialization control voltage V FC 3 is in the range of 1 microsecond to 10 milliseconds.
  • the plurality of resistive switching devices have a third resistance distribution and a third average resistance value (for example, a weighted average value) after the third initialization operation.
  • the standard deviation of the third resistance distribution is smaller than the standard deviation of the second resistance distribution, that is, the resistance distribution is more convergent after the third initialization operation.
  • the third average resistance value is less than the second average resistance value.
  • the magnitudes of the first initialization operation voltage V F 1, the second initialization operation voltage V F 2, and the third initialization operation voltage V F 3 decrease in order.
  • At least one embodiment of the present disclosure also provides a resistive random access memory circuit.
  • the resistive random access memory circuit includes the above-mentioned resistive random access memory array 50.
  • FIG. 6 is a schematic structural diagram of a resistive random access memory circuit 60 provided by at least one embodiment of the present disclosure.
  • the resistive random access memory circuit 60 further includes an initialization control circuit 61 configured to be electrically connected to the plurality of initialization circuits 54 to provide the initialization operation voltage V F and the initialization control voltage V FC .
  • the resistive random access memory circuit 60 further includes a column selection circuit 62 configured to provide the resistive random access memory array 50 with the read and write operation voltage.
  • the reading and writing operation voltage includes a programming operation voltage V Set , an erasing operation voltage V RST and a reading operation voltage V Read .
  • the program operation voltage V Set and the read operation voltage V Read are provided to the memory resistive array through the bit line BL, and the erase operation voltage V RST is provided to the memory resistive array through the source line SL.
  • the embodiment of the present disclosure does not limit this.
  • the program operation voltage V Set , the erase operation voltage V RST, and the read operation voltage V Read may all be provided to the memory resistive variable array through the bit line BL.
  • the column selection circuit 62 is electrically connected to a plurality of global bit lines GBL.
  • the resistive random access memory circuit 60 further includes a programming control circuit 63, an erasing control circuit 64 and a reading control circuit 65.
  • the programming control circuit 63 is connected to the column selection circuit 62 and is configured to provide the programming operation voltage V Set to the resistive memory array 60 through the column selection circuit 62.
  • the programming control circuit 63 applies the programming operation voltage V Set to the selected memory cell through the column selection circuit 62 and at least one bit line BL, thereby applying a forward voltage to the resistive switching device to the memory cell.
  • the unit is programmed.
  • the erasing control circuit 64 is connected to the column selection circuit 62 and is configured to provide the erasing operation voltage V RST to the resistive memory array 60 through the column selection circuit 62. For example, in the erasing operation stage, the erasing control circuit 64 applies an erasing operation voltage V RST to the selected memory cell through the column selection circuit 62 and at least one source line SL to apply a reverse voltage to the resistive switching device. Perform an erase operation on the memory cell.
  • the read control circuit 65 is connected to the column selection circuit 62 and is configured to provide a read operation voltage V Read to the resistive memory array 60 through the column selection circuit 62.
  • the read control circuit 65 applies the read operation voltage V Read to the selected memory cell through the column selection circuit 62 and at least one bit line BL to apply a forward voltage to the resistive switching device. Perform a read operation.
  • the resistive random access memory circuit 60 further includes a block selection control circuit 66 and a word line control circuit 67.
  • the block selection control circuit 66 is configured to be connected to the block selection line BSL to provide the block selection voltage V BS to the resistive random access memory array 50.
  • the word line control circuit 67 is configured to provide the word line voltage V WL to the resistive memory array 50.
  • the word line control circuit 67 is electrically connected to a plurality of word lines WL.
  • the embodiments of the present disclosure also provide a resistive random access memory array, and the second ends of the switching devices of the memory cells of each memory cell row are electrically connected to each other.
  • FIG. 7A is a schematic diagram of a resistive memory array 70 provided by at least another embodiment of the present disclosure.
  • the resistive memory array 70 includes a plurality of memory cells 30, a plurality of bit lines BL, a plurality of word lines WL, and a plurality of block selection circuits 53.
  • the plurality of memory cells 30 are arranged into n memory cell rows and m memory cell columns (m and n are greater than or equal to 2) along the first direction D1 and the second direction D2, and each memory cell 30 includes a resistive switching device 10 and a switch The device 20; the resistive switching device 10 includes a first electrode 11 and a second electrode 12, the switching device 20 includes a control terminal 21, a first terminal 22, and a second terminal 23; the first electrode 11 of the resistive switching device 10 and the The first terminal 22 of the switching device 20 is electrically connected.
  • the second ends 23 of the switching devices 20 in the memory cells 30 of each memory cell row along the first direction D1 are electrically connected to each other.
  • the plurality of bit lines BL extend along the second direction D2 and are connected to the plurality of columns of memory cells 30 in a one-to-one correspondence. Each of the plurality of bit lines BL is connected to the second row of the resistive switching device 10 in the corresponding column of memory cells 30.
  • the electrode 12 is electrically connected.
  • the plurality of word lines WL extend along the first direction D1 and are connected to the plurality of rows of memory cells 30 in a one-to-one correspondence. Each of the plurality of word lines WL is connected to the switching device 20 of the memory cell in the corresponding row of memory cells 30.
  • the control terminal 21 is electrically connected.
  • the plurality of block selection circuits 53 are electrically connected to a plurality of bit lines BL in a one-to-one correspondence.
  • Each block selection circuit 53 includes a control terminal 530, a first terminal 531, and a second terminal 532.
  • the control terminal 530 of the block selection circuit 53 is configured To receive the block selection voltage V BS
  • the first terminal 531 of the block selection circuit 53 is configured to receive read and write operation voltages
  • the second terminal 532 of the block selection circuit 53 is electrically connected to the bit line BL corresponding to the block selection circuit 53.
  • the block selection circuit is configured to, in response to the block selection voltage V BS , write the read and write operation voltage to the correspondingly connected bit line BL.
  • the reading and writing operation voltage includes a programming operation voltage V Set , an erasing operation voltage V RST and a reading operation voltage V Read .
  • the second terminals 23 of the switching devices 20 in each row of memory cells 30 are directly and electrically connected to each other at the same potential, and it is not necessary to provide a second end 23 for matching a row of memory cells in the second direction D2.
  • the potential of the second terminal 23 of each switching device in the source line is selected. This arrangement helps to reduce the density of the traces along the second direction, simplify the manufacturing process and improve the yield.
  • the resistive memory array may further include a plurality of source lines SL (SL ⁇ 0>-SL ⁇ n/2-1>), and the plurality of source lines SL extend along the first direction D1, That is, it is parallel to the plurality of word lines WL.
  • the multiple source lines SL are correspondingly connected to multiple memory cell rows, and the second ends of the switching devices of the memory cells of each memory cell row are electrically connected to each other through a corresponding source line SL.
  • the multiple source lines SL are connected to the multiple memory cell rows in a one-to-one correspondence.
  • the second end 23 of the switching device 20 of the memory cell 30 of each memory cell row is electrically connected to a corresponding source line SL, and is electrically connected to each other through the source line SL.
  • the source lines SL may be insulated from each other, or may be electrically connected to each other.
  • the embodiment of the present disclosure does not limit this.
  • every two adjacent rows of memory cells share one source line SL.
  • the second ends of the switching devices of every two adjacent rows of memory cells are electrically connected to the same source line SL. In this way, the trace density can be reduced, and the process cost can be reduced.
  • the resistive memory array 60 further includes a global source line GSL, and the second ends of the switching devices in each memory cell row are electrically connected to the global source line GSL, that is, ,
  • the global source line electrically connects the second ends of the multiple switching devices in the resistive memory array 60 to each other.
  • the global source line GSL is used to connect the second ends of the multiple switching devices to a peripheral circuit (such as the source line control circuit in FIG. 8) to provide source line voltages to the multiple memory cells.
  • the global source line GSL can also be directly grounded.
  • the global source line GSL extends along the second direction D2.
  • the number of the global source lines GSL is two, and the two global source lines GSL are respectively located on opposite sides of a memory cell array formed by a plurality of memory cells 30 in the first direction D1.
  • the multiple source lines SL are electrically connected to two global source GSL lines located on both sides.
  • the second ends 23 of the multiple switching devices 20 located in the same memory cell row are connected to the surrounding global source line GSL through a corresponding source line SL.
  • the global source line GSL is grounded, thereby grounding the second end 23 of the switching device 20 of the switching devices in the plurality of memory cells 30.
  • the resistive memory array 70 further includes a plurality of initialization circuits 54 which are respectively electrically connected to the plurality of bit lines in a one-to-one correspondence.
  • Each initialization circuit includes a control terminal, a first terminal, and a second terminal.
  • the control terminal of the initialization circuit is configured to receive an initialization control voltage
  • the first terminal of the initialization circuit is configured to receive an initialization operation voltage.
  • the second end is electrically connected to a bit line corresponding to the initialization circuit, and the initialization circuit is configured to write the initialization operation voltage to the corresponding bit line in response to the initialization control voltage.
  • the main difference between the resistive random access memory array 70 provided in this embodiment and the resistive random access memory array 50 in the foregoing embodiment described with reference to FIG. 3 is that the source lines are arranged in a different manner.
  • resistive random access memory Description of array 50. I won't repeat them here.
  • the embodiment of the present disclosure also provides an operating method for operating the resistive random access memory array 70 described above.
  • the operation method includes: applying a word line voltage through the plurality of word lines to select a row of memory cells, and applying a source line voltage to a second end of a switching device of the selected row of memory cells so that the switching device is turned on and all
  • the source line voltage is transferred to the first electrode of the resistive switching device of the selected row of memory cells, and the resistive switching device of at least one of the selected row of memory cells is transmitted through at least one of the plurality of bit lines
  • the second electrode applies a read-write operation voltage or an initialization operation voltage.
  • the read and write operation voltage includes at least one of a program operation voltage, an erase operation voltage, and a read operation voltage.
  • the potential of the first electrode 11 directly connected to the resistive switching device and the switching device 20 can be used as a reference potential for various operations. For example, during initialization operation, programming operation, erasing operation, and reading operation, the corresponding initialization operation voltage, programming operation voltage, and erasing operation voltage are respectively applied to the second electrode 12 of the resistive switching device 10 of the selected memory cell through the bit line. And read the operating voltage.
  • the source line voltage is the ground voltage.
  • a positive voltage can be applied to the bit line to perform initialization, programming, and reading operations, and a negative voltage can be applied to erase. This helps to reduce the voltage amplitude requirements, thereby reducing the circuit's withstand voltage requirements.
  • the operation method includes, for example, an initialization operation phase, a programming operation phase, an erasing operation phase, and a reading operation phase.
  • the first transistor T1 and the second transistor T2 are both N-type transistors; the third transistor T3 is a P-type transistor.
  • the embodiments of the present disclosure do not limit the types of the first to third transistors. When the types of the transistors are changed, the magnitude relationship between the signals is adjusted accordingly to make the circuit achieve the same function.
  • the word line voltage V WL is applied to the selected word line WL (corresponding to the selected memory cell connected to one or more rows), and the global source line GSL is controlled to be grounded, thereby storing the selected one or more rows
  • the switching device 20 (first transistor T1) of the cell 30 is turned on.
  • applying the block selection voltage V BS to the block selection circuit 53 through the block selection line BSL turns the block selection circuit 53 off.
  • the control block selection line BSL is grounded so that the second transistor T2 is turned off.
  • the block selection circuit is turned off to separate the transmission of the initialization circuit and the initialization operation voltage from the transmission of other control circuits and the operation voltage, thereby reducing the amount involved in the initialization operation voltage.
  • the range of the circuit reduces the withstand voltage requirements and size of the circuit.
  • the initialization operation voltage V F is applied to the initialization operation line FL
  • the initialization control voltage V FC is applied to the initialization control line FCL so that the third transistor T3 is turned on and the initialization circuit is turned on.
  • the third transistor T3 is a P-type transistor.
  • the initialization operation voltage V F is applied to the initialization operation line FL
  • the initialization control voltage V FC is applied to the initialization control line FCL
  • the initialization operation voltage V F is higher than the initialization control voltage V FC , so that the third transistor T3 is turned on, and the initialization circuit 54 is turned on.
  • the initialization operation voltage V F is between 2V and 6V.
  • the initialization control voltage V FC of the pulse time (T F) in the range of 1 microsecond to 10 milliseconds.
  • the initializing operation voltage V F is applied to the second electrode 12 of the resistive switching device 10 of the selected at least one row of memory cells through the initializing circuit 54 and a plurality of bit lines BL; the first electrode 11 of the resistive switching device passes through the The switch device 20 that is turned on is grounded, so a voltage difference V F is introduced at both ends of the resistive switching device.
  • the resistive switching device is broken down to change from an initial high-resistance state to a low-resistance state, thereby changing at least one row of selected memory cells
  • the initialization (Forming) operation is carried out.
  • multiple initialization circuits are turned off, and the block selection circuit is turned on; at least one block selection circuit 53 and at least one bit line BL apply a positive programming operation voltage V Set to the selected memory cell, and control the global source line
  • the GSL is grounded, so that a forward voltage is applied to the resistive switching device to perform a programming operation on the memory cell.
  • the positive word line voltage V WL is applied to the control terminal of the switching device 20 (first transistor T1) in a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), so that the row of memory cells
  • the switching device in the selected memory cell in is turned on, and the first electrode 11 of the resistive switching device is grounded.
  • the magnitude of the programming operation voltage V Set is between 1.2V and 3V, and the pulse time is between 1 nanosecond and 10 microseconds.
  • multiple initialization circuits are turned off, and the block selection circuit is turned on; at least one block selection circuit 53 and at least one bit line BL apply a negative erase operation voltage V RST to the selected memory cell, and control the global The source line GSL is grounded, so that a reverse voltage is applied to the resistive switching device to perform an erase operation on the memory cell.
  • a positive block selection voltage V BS to the block selection line of the selected resistive random access memory array
  • the erase operation voltage V RST to at least one global bit line GBL to turn on the corresponding at least one block selection circuit
  • the negative erase operation voltage V RST is transferred to the corresponding bit line BL and applied to the second electrode 12 of the resistive switching device of the selected memory cell.
  • the positive word line voltage V WL is applied to the control terminal of the switching device 20 in a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), so that the selected memory cell in the row of memory cells
  • the switching device in is turned on, and the first electrode 11 of the resistive switching device is grounded.
  • the magnitude of the erase operation voltage V RST is between -1.2V and -3V, and the pulse time is between 1 nanosecond and 10 microseconds.
  • the operation method also includes a read operation phase. For example, during the read operation stage, multiple initialization circuits are turned off, and at least one block selection circuit (corresponding to the selected memory cell) is turned on, thereby performing a read operation on the selected memory cell.
  • a positive block selection voltage V BS is applied to a block selection line of a selected resistive memory array, and a read operation voltage V Read is applied to at least one global bit line GBL (corresponding to the selected memory Cell), so that the at least one block selection circuit is turned on, and the read operation voltage V Read is transferred to the second electrode 12 of the resistive switching device of the selected memory cell through the corresponding bit line BL.
  • a positive word line voltage V WL is applied to the control terminal of the switching device 20 (first transistor T1) of a row of memory cells 30 through the selected word line WL (corresponding to the selected memory cell), and the global source line GSL is grounded Therefore, the switching device in the selected memory cell in the row of memory cells is turned on, and the first electrode 11 of the resistive switching device is grounded.
  • a positive V Read voltage difference is introduced across the electrodes of the resistive switching device of the selected memory cell, and a conduction read current (IRead) is generated.
  • the resistance value of the resistance switching device is high, and the reading current is small; the resistance value is low, and the reading current is large.
  • the reading operation of the selected memory cell can be completed by detecting the reading current through the peripheral reading control circuit.
  • the read operation voltage V Read is between 0.1V and 1.2V, and the pulse time is between 1 nanosecond and 10 microseconds.
  • the operation method may include a multi-step initialization operation.
  • the operation method provided by the embodiment shown in FIG. 5 is also applicable to the resistive random access memory array 70, which will not be repeated here.
  • the embodiment of the present disclosure also provides a resistive random access memory circuit 80, which includes the above-mentioned resistive random access memory circuit 70.
  • FIG. 8 is a schematic structural diagram of a resistive random access memory circuit 80 provided by at least one embodiment of the present disclosure. As shown in FIG. 8, the resistive random access memory circuit 80 further includes a source line control circuit 81 configured to be electrically connected to the second end of the switching device of the memory cell of one or more memory cell rows to provide a source Line voltage.
  • a source line control circuit 81 configured to be electrically connected to the second end of the switching device of the memory cell of one or more memory cell rows to provide a source Line voltage.
  • the source line control circuit 81 may be connected to a plurality of source lines SL to respectively provide source line voltages for a plurality of memory cell rows.
  • the source line voltages received by the memory cell row may be the same or different.
  • the source line control circuit 81 can also be electrically connected to the global source line GSL to provide a source line voltage to the resistive memory array 70.
  • the global source line GSL may be directly grounded, and in this case, the source line control circuit 81 may also be omitted.
  • the resistive random access memory circuit 80 further includes an initialization control circuit 82 configured to be electrically connected to the plurality of initialization circuits 54 to provide the initialization operation voltage VF and the initialization control voltage V FC .
  • the resistive random access memory circuit 80 further includes a column selection circuit 83 configured to be connected to a plurality of block selection circuits 53 to provide read and write operation voltages to the resistive random access memory array 70.
  • the reading and writing operation voltage includes a programming operation voltage V Set , an erasing operation voltage V RST and a reading operation voltage V Read .
  • the column selection circuit 83 is electrically connected to a plurality of global bit lines GBL.
  • the resistive random access memory circuit 80 further includes a programming and erasing control circuit 84 and a reading control circuit 85.
  • the program and erase control circuit 84 is connected to the column selection circuit 83 and is configured to provide the program operation voltage V Set and the erase operation voltage V RST to the resistive memory array 70 through the column selection circuit 83.
  • the program and erase control circuit 84 applies a positive program operation voltage V Set to the selected memory cell through the column selection circuit 83 and at least one bit line BL, thereby applying a positive direction to the resistive switching device.
  • V Set a positive program operation voltage
  • the voltage is used to program the memory cell.
  • the program and erasing control circuit 84 applies a negative erasing operation voltage V RST to the selected memory cell through the column selection circuit 83 and at least one bit line BL, thereby applying a negative erase operation voltage V RST to the resistive switching device
  • the reverse voltage is used to erase the memory cell.
  • the programming control circuit and the erasing control circuit can be integrated into the same circuit module.
  • the program and erase control circuit 84 includes a positive voltage generating circuit and a negative voltage generating circuit to generate a positive program operation voltage during the program operation phase and a negative erase operation voltage during the erase operation phase, respectively.
  • the read control circuit 85 is connected to the column selection circuit 83 and is configured to provide the read operation voltage V Read to the resistive memory array 70 through the column selection circuit 83.
  • the read control circuit 85 applies the read operation voltage V Read to the selected memory cell through the column selection circuit 83 and at least one bit line BL, thereby applying a forward voltage to the resistive switching device. Perform a read operation on the memory cell.
  • the resistive random access memory circuit 80 further includes a block selection control circuit 86 and a word line control circuit 87.
  • the block selection control circuit 86 is configured to be connected to the block selection line BSL to provide the block selection voltage V BS to the resistive random access memory array 70.
  • the word line control circuit 87 is configured to provide the word line voltage V WL to the resistive memory array 70.
  • the word line control circuit 87 is electrically connected to a plurality of word lines WL.
  • At least one embodiment of the present disclosure also provides an electronic device that includes the resistive random access memory circuit of any of the above embodiments.
  • the electronic device may be a storage device, a hard disk, a mobile device, a mobile phone, a notebook computer, or a desktop. Computer, etc.

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Abstract

Procédé de fonctionnement pour un réseau de stockage résistif (50). Le réseau de stockage résistif (50) comprend une pluralité d'unités de stockage (30), une pluralité de lignes de bits (BL), une pluralité de lignes de mots (WL), une pluralité de circuits de sélection de blocs (53), et une pluralité de circuits d'initialisation (54). Chaque unité de stockage (30) comprend un dispositif résistif (10) et un dispositif de commutation (20). La pluralité d'unités de stockage (30) est agencée sous la forme d'une pluralité de rangées d'unités de stockage et d'une pluralité de colonnes d'unités de stockage le long d'une première direction (D1) et d'une seconde direction (D2). La pluralité de BL est connectée à la pluralité de colonnes d'unités de stockage selon une correspondance biunivoque. Le procédé de fonctionnement fait appel aux étapes suivantes : la mise hors tension de la pluralité de circuits de sélection de blocs (53), et la réalisation d'une première opération d'initialisation et d'une seconde opération d'initialisation sur l'unité de stockage sélectionnée (30) dans au moins une rangée d'unités de stockage au moyen de la pluralité de circuits d'initialisation (54) et de la pluralité de BL. La valeur de résistance du dispositif résistif obtenue par le procédé de fonctionnement présente une meilleure précision et une meilleure cohérence.
PCT/CN2020/141479 2019-12-31 2020-12-30 Procédé de fonctionnement pour réseau de stockage résistif WO2021136395A1 (fr)

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CN111179991B (zh) * 2019-12-31 2022-06-03 清华大学 阻变存储阵列及其操作方法、阻变存储器电路
CN111091858B (zh) * 2019-12-31 2021-11-09 清华大学 阻变存储阵列的操作方法
CN112017715B (zh) * 2020-08-24 2022-12-06 厦门半导体工业技术研发有限公司 阻变存储器及其保护电路
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