WO2021115042A1 - 一种半导体器件及其制作方法 - Google Patents

一种半导体器件及其制作方法 Download PDF

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Publication number
WO2021115042A1
WO2021115042A1 PCT/CN2020/129374 CN2020129374W WO2021115042A1 WO 2021115042 A1 WO2021115042 A1 WO 2021115042A1 CN 2020129374 W CN2020129374 W CN 2020129374W WO 2021115042 A1 WO2021115042 A1 WO 2021115042A1
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WIPO (PCT)
Prior art keywords
word line
conductive structure
line conductive
contact portion
line contact
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PCT/CN2020/129374
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English (en)
French (fr)
Inventor
吴秉桓
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201911257093.5A external-priority patent/CN112951825A/zh
Priority claimed from CN201922203603.2U external-priority patent/CN211017077U/zh
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20898273.6A priority Critical patent/EP3971975A4/en
Priority to US17/420,125 priority patent/US20220157830A1/en
Publication of WO2021115042A1 publication Critical patent/WO2021115042A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • the present invention relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method of the semiconductor device.
  • a method for manufacturing a semiconductor device including:
  • the substrate including a memory cell array area
  • word line conductive material in the word line groove to form a word line conductive film
  • the word line conductive film that is not covered by the photoresist is etched to a target height to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact is Greater than the thickness of the word line conductive structure not covered by the photoresist;
  • the photoresist is removed.
  • the word line contact portion is located at the end of the word line conductive structure.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0.
  • the method further includes:
  • the first insulating dielectric layer is patterned, and a word line contact hole is formed on the word line contact portion.
  • the substrate further includes a peripheral circuit area
  • the peripheral circuit area includes a transistor active area
  • a second insulating dielectric layer is formed on the surface of the active area
  • the second insulating dielectric is patterned Layer, forming an active area contact hole on the source area/drain area of the active area.
  • the height difference between the active area contact hole and the word line contact hole is greater than or equal to 0 and less than 20% of the height of the active area contact hole.
  • the word line contact hole and the active area contact hole are formed by the same process.
  • the first insulating dielectric layer and the second insulating dielectric layer are formed by the same process.
  • the semiconductor device is a dynamic random access memory.
  • the above manufacturing method includes: obtaining a substrate, the substrate including a memory cell array area; forming spaced word line trenches in the memory cell array area; and filling word line conductive material in the word line trenches , Forming a word line conductive film; forming a photoresist on the surface of the substrate, the photoresist covering the word line conductive film at the word line contact portion and exposing the word line conductive film outside the word line contact portion;
  • the photoresist is a barrier layer, and the word line conductive film that is not covered by the photoresist is etched to a target depth to obtain a word line conductive structure, so that the thickness of the word line conductive structure of the word line contact portion is greater than that of the word line conductive film.
  • the thickness of the word line conductive structure covered by the photoresist is formed on the surface of the substrate.
  • the photoresist covers the word line conductive film at the word line contact portion and exposes the word line conductive film outside the word line contact portion.
  • the word line conductive film that is not covered by the photoresist is etched to a target height, so that the thickness of the word line conductive structure in the word line contact portion of the formed word line conductive structure is greater than that of the word line conductive structure not covered by the photoresist Compared with the thickness of the word line conductive structure in the word line contact part of the word line conductive structure equal to the thickness of the word line conductive structure not covered by the photoresist, the opening of the word line contact hole in the word line contact part is reduced.
  • the depth of the window position reduces the process time in the process of forming the contact hole, reduces the excessive erosion of the sidewall of the contact hole with a shallower opening depth in the contact hole process, and avoids the short circuit of the device caused by the abnormal contact hole abnormal.
  • a semiconductor device including:
  • a word line conductive structure includes a word line conductive structure in a word line contact portion and a word line conductive structure outside the word line contact portion;
  • the thickness of the word line conductive structure of the word line contact portion is greater than the thickness of the word line conductive structure outside the word line contact portion.
  • the word line contact portion is located at the end of the word line conductive structure.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.0.
  • the device further includes:
  • a peripheral circuit area includes a transistor active area, and the active area has a source area/drain area;
  • An insulating dielectric layer where the insulating dielectric layer is located on the surface of the word line conductive structure and the active area;
  • a word line contact structure located on the word line contact portion and in contact with the word line contact portion;
  • An active area contact structure located on the transistor active area and in contact with the source area/drain area of the transistor active area.
  • the height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than 20% of the height of the active area contact structure.
  • the active area contact structure and the word line contact structure are formed at the same time.
  • the semiconductor device is a dynamic random access memory.
  • the above semiconductor device includes a substrate on which a memory cell array region is formed, and the memory cell array region is formed with word line trenches arranged at intervals; a word line conductive structure, the word line conductive structure including word line contacts The conductive structure of the word line in the part and the conductive structure of the word line outside the word line contact part; wherein the thickness of the word line conductive structure of the word line contact part is greater than the thickness of the word line conductive structure outside the word line contact part.
  • the thickness of the word line conductive structure with the word line contact portion formed on the surface of the device substrate of the present application is greater than the thickness of the word line conductive structure other than the word line contact portion, and the difference between the word line conductive structure and the word line contact portion in the word line conductive structure Compared with a device whose thickness of the word line conductive structure is equal to the thickness of the word line conductive structure outside the word line contact part, the depth of the opening position of the word line contact hole is reduced, and the process time in the process of forming the contact hole is reduced, and the process time is reduced. The excessive erosion of the sidewall of the contact hole with a shallow opening depth of the contact hole in the contact hole process is avoided, and the short circuit abnormality of the device caused by the abnormal contact hole is avoided.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor device in an embodiment
  • 2a is a flowchart of forming a word line contact hole in an embodiment
  • 2b is a flow chart of forming contact holes in the active area in an embodiment
  • Figure 3a is a cross-sectional view of a semiconductor device in an embodiment
  • 3b is a cross-sectional view of the semiconductor device after the word line conductive film is formed in an embodiment
  • 3c is a cross-sectional view of the semiconductor device after forming an insulating dielectric layer in an embodiment
  • FIG. 4a is a cross-sectional view of the word line contact part in the vertical direction of the word line conductive film after the word line conductive film is formed in an embodiment
  • FIG. 4b is a cross-sectional view corresponding to FIG. 4a after the photoresist is formed in an embodiment
  • FIG. 4c is a cross-sectional view corresponding to FIG. 4b after the insulating dielectric layer is formed in an embodiment
  • FIG. 5a is a cross-sectional view of the area outside the word line contact portion in the vertical direction of the word line conductive film after the word line conductive film is formed in an embodiment
  • FIG. 5b is a cross-sectional view corresponding to FIG. 5a after the word line conductive structure is formed in an embodiment
  • FIG. 5c is a cross-sectional view corresponding to FIG. 5b after the insulating dielectric layer is formed in an embodiment.
  • first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
  • Spatial relationship terms such as “under”, “below”, “below”, “below”, “above”, “above”, etc., in It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if the device in the drawing is turned over, then elements or features described as “below” or “below” or “under” other elements will be oriented “on” the other elements or features. Therefore, the exemplary terms “below” and “below” can include both an orientation of above and below. The device can be otherwise oriented (rotated by 90 degrees or other orientation) and the spatial descriptors used here are interpreted accordingly.
  • the embodiments of the invention are described here with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, changes from the shown shape due to, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle usually has rounded or curved features and/or an implanted concentration gradient at its edges, rather than a binary change from an implanted area to a non-implanted area. Likewise, the buried region formed by the implantation can result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.
  • the deeper word line contact hole (Word line Contact, WL Contact) stays above the word line conductive structure and has not yet completed the opening of the window.
  • the transistor active area contact hole will be etched to the point Inside the source area, a spike effect (spiking) occurs.
  • a method for manufacturing a semiconductor device including:
  • the substrate 102 includes a memory cell array region, and the substrate may be at least silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (SSiGeOI), silicon germanium-on-insulator (SiGeOI) ) And germanium on insulator (GeOI) and other materials.
  • SOI silicon-on-insulator
  • SSOI silicon-on-insulator
  • SSiGeOI silicon-germanium-on-insulator
  • SiGeOI silicon germanium-on-insulator
  • GeOI germanium on insulator
  • Word line trenches 104 arranged at intervals are formed in the memory cell array area.
  • a plurality of mutually independent word line trenches are formed in the memory cell array area.
  • the word line trenches extend in a first direction and are arranged at intervals in a second direction. The first direction and the second direction intersect.
  • the word line trench is formed by dry etching. In another embodiment, the word line trench is formed by wet etching.
  • the word line trench is formed by two processes.
  • a word line conductive material is filled in the word line trench 104 to form a word line conductive film 108.
  • it before forming the word line conductive film 108, it further includes forming an insulating layer 110 on the inner wall of the word line trench 104, and the insulating layer 110 may be a silicon dioxide film layer.
  • the word line conductive material in the word line trench 104 before filling the word line conductive material in the word line trench 104, it further includes forming a first metal layer on the inner wall of the word line trench.
  • the first metal layer may be titanium/nitride for adhesion and barrier. Titanium metal layer.
  • the word line conductive material is formed by a plasma chemical vapor deposition process. In one embodiment, the word line conductive material is formed by a physical vapor deposition process. In one embodiment, the word line conductive material is a metal conductive material, such as a metal tungsten material, a metal tungsten composite material, a metal aluminum material, and the like.
  • a word line conductive film 108 is formed in the word line trench 104.
  • the excess word line conductive material on the surface of the substrate is removed by chemical mechanical polishing. In another embodiment, the excess word line conductive material on the surface of the substrate is removed by etching, such as wet etching, dry etching, and the like.
  • a photoresist 112 is formed on the surface of the substrate 102, that is, a photoresist with a photolithographic pattern is formed on the surface of the substrate.
  • the photoresist 112 covers the word line groove 115 of the word line contact portion 114, that is, the word line contact portion.
  • the photoresist is coated on the surface of the substrate, and then the photoresist is exposed and developed to expose the word line conductive film outside the word line contact part (that is, the array area (array area) of the device is developed), and the photoresist is not exposed.
  • the photoresist covers the word line conductive film at the word line contact part, and plays a role of protecting the word line conductive film at the word line contact part.
  • the word line conductive film that is not covered by the photoresist is etched to a target height to obtain the word line conductive structure 117, that is, the word line conductive film 108 is aligned with the photoresist 112 as a barrier layer
  • the word line conductive structure 117 is obtained, so that the thickness of the word line conductive structure of the word line contact portion 114 is greater than the thickness of the word line conductive structure not covered by the photoresist 112.
  • etching the word line conductive film not covered by the photoresist to a target height refers to etching the word line conductive film not covered by the photoresist until the remaining word line conductive film is lower than the surface of the substrate Below 5 nanometers, as long as the remaining word line conductive film can be realized to avoid short circuits between the word line and the bit line and other contact windows and other structures.
  • the word line conductive structure 117 is located on the shallow trench isolation oxide layer 121.
  • the word line contact 114 is located at the end of the word line conductive structure 117.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is greater than or equal to 1.5 and less than or equal to 4.0.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure not covered by the photoresist is set as required, such as 1.7, 1.9, 2.0, 2.2, 2.5 , 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, etc.
  • step S112 the method further includes:
  • a first insulating dielectric layer is formed on the surface of the word line conductive structure 117.
  • a first insulating dielectric layer film is formed on the surface of the substrate.
  • physical vapor deposition or chemical vapor deposition may be used on the surface of the substrate.
  • a first insulating medium layer film is formed; then, the excess first insulating medium layer film on the surface of the substrate is removed by etching or chemical mechanical polishing to form the first insulating medium layer.
  • the first insulating dielectric layer is a silicon oxide insulating layer.
  • the first insulating dielectric layer is patterned, and a word line contact hole 119 is formed on the word line contact portion 114.
  • the substrate further includes a peripheral circuit area
  • the peripheral circuit area includes a transistor active area
  • the manufacturing method of the semiconductor device further includes:
  • a second insulating dielectric layer is formed on the surface of the active area of the transistor.
  • the second insulating dielectric layer and the first insulating dielectric layer are formed by the same process.
  • the second insulating dielectric layer is patterned to form an active area contact hole 120 on the source/drain area 106 of the active area.
  • the height difference between the active area contact hole 120 and the word line contact hole 119 is greater than or equal to 0 and less than 20% of the height of the active area contact hole.
  • the active area The height difference between the contact hole and the word line contact hole 119 may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, etc. of the height of the active area contact hole.
  • the word line contact hole 119 and the active area contact hole 120 are formed by the same process.
  • the semiconductor device is a dynamic random access memory.
  • the above manufacturing method includes: obtaining a substrate, the substrate including a memory cell array area; forming spaced word line trenches in the memory cell array area; and filling word line conductive material in the word line trenches , Forming a word line conductive film; forming a photoresist on the surface of the substrate, the photoresist covering the word line conductive film at the word line contact portion and exposing the word line conductive film outside the word line contact portion;
  • the photoresist is a barrier layer.
  • the word line conductive film that is not covered by the photoresist is etched to a target depth to obtain a word line conductive structure, so that the thickness of the word line conductive structure at the word line contact portion is greater than that of the word line conductive film.
  • the thickness of the word line conductive structure covered by the photoresist is formed on the surface of the substrate.
  • the photoresist covers the word line conductive film at the word line contact portion and exposes the word line conductive film outside the word line contact portion.
  • the word line conductive film that is not covered by the photoresist is etched to a target height, so that the thickness of the word line conductive structure in the word line contact portion of the formed word line conductive structure is greater than that of the word line conductive structure not covered by the photoresist Compared with the thickness of the word line conductive structure in the word line contact part of the word line conductive structure equal to the thickness of the word line conductive structure not covered by the photoresist, the opening of the word line contact hole in the word line contact part is reduced.
  • the depth of the window position reduces the process time in the process of forming the contact hole, reduces the excessive erosion of the sidewall of the contact hole with a shallower opening depth in the contact hole process, and avoids the short circuit of the device caused by the abnormal contact hole abnormal.
  • a semiconductor device including:
  • the substrate 102 has a memory cell array region formed on the substrate 102, and the memory cell array region is formed with word line trenches 104 arranged at intervals. A plurality of mutually independent word line trenches are formed in the memory cell array area. The word line trenches extend in a first direction and are arranged at intervals in a second direction. The first direction and the second direction intersect.
  • the substrate may be at least silicon, silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (SSiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. One of the materials.
  • the word line conductive structure 117 includes the word line conductive structure of the word line contact portion 114 and the word line conductive structure outside the word line contact portion 114.
  • the word line contact 114 is located at the end of the word line conductive structure 117.
  • the word line conductive structure 117 is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, and the like.
  • the thickness of the word line conductive structure of the word line contact portion 114 is greater than the thickness of the word line conductive structure outside the word line contact portion 114.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is greater than or equal to 1.5 and less than or equal to 4.0.
  • the ratio of the thickness of the word line conductive structure of the word line contact portion to the thickness of the word line conductive structure outside the word line contact portion is set as needed, such as 1.7, 1.9, 2.0, 2.2, 2.5 , 2.7, 2.9, 3.0, 3.3, 3.5, 3.7, 3.9, etc.
  • the device further includes:
  • the word line contact hole 119 is formed on the word line contact portion 114 and the bottom of the word line contact hole 119 is in contact with the upper surface of the word line contact portion 114.
  • the active area contact hole 120 is formed on the transistor active area and the bottom of the active area contact hole 120 and the upper surface of the source/drain area 106 of the transistor active area contact.
  • the device further includes:
  • a peripheral circuit area includes a transistor active area, and the active area has a source area/drain area 106;
  • the insulating dielectric layer 118 is located on the surface of the word line conductive structure and the active area.
  • the insulating dielectric layer 118 includes a first insulating dielectric layer on the surface of the word line conductive structure 117 and a second insulating dielectric layer on the surface of the active region of the transistor.
  • the word line contact structure is located on the word line contact portion 114 and is in contact with the word line contact portion 114.
  • the word line contact structure is located in the word line contact hole 119 formed on the word line contact portion 114, and the word line contact structure is a conductive structure for leading out the word line conductive structure 117.
  • the word line contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, and the like.
  • the active region contact hole is located on the transistor active region and is in contact with the source region/drain region 106 of the transistor active region.
  • the active area contact structure is located in the active area contact hole 120 formed on the source area/drain area 106.
  • the active area contact structure is a conductive structure for leading out the source area/drain area 106 of the transistor.
  • the active area contact structure is a metal conductive structure, such as a metal tungsten conductive structure, a metal tungsten composite conductive structure, a metal aluminum conductive structure, and the like.
  • the height difference between the active area contact structure and the word line contact structure is greater than or equal to 0 and less than 20% of the height of the active area contact structure.
  • the height difference between the active area contact structure and the word line contact structure may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, etc. of the height of the active area contact structure.
  • the height difference between the active area contact hole 120 and the word line contact hole 119 is greater than or equal to 0 and less than 20% of the height of the active area contact hole.
  • the active area The height difference between the contact hole and the word line contact hole 119 may be 5%, 7%, 9%, 10%, 13%, 15%, 17%, 19%, etc. of the height of the active area contact hole.
  • the device further includes a first metal layer located in the word line trench, an upper surface of the first metal layer and a lower surface of the word line conductive structure
  • the contact for example, the first metal layer may be a titanium/titanium nitride metal layer for adhesion and barrier.
  • the semiconductor device is a dynamic random access memory.
  • the above semiconductor device includes a substrate on which a memory cell array region is formed, and the memory cell array region is formed with word line trenches arranged at intervals; a word line conductive structure, the word line conductive structure including word line contacts The conductive structure of the word line in the part and the conductive structure of the word line outside the word line contact part; wherein the thickness of the word line conductive structure of the word line contact part is greater than the thickness of the word line conductive structure outside the word line contact part.
  • the thickness of the word line conductive structure with the word line contact portion formed on the surface of the device substrate of the present application is greater than the thickness of the word line conductive structure other than the word line contact portion, and the difference between the word line conductive structure and the word line contact portion in the word line conductive structure Compared with the device whose thickness of the word line conductive structure is equal to the thickness of the word line conductive structure outside the word line contact part, the depth of the opening position of the word line contact hole is reduced, and the process time in the process of forming the contact hole is reduced. The excessive erosion of the sidewall of the contact hole with a shallow opening depth of the contact hole in the contact hole process is avoided, and the short circuit abnormality of the device caused by the abnormal contact hole is avoided.

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Abstract

一种半导体器件及其制作方法。包括：获取包括存储单元阵列区的衬底（102）；形成字线沟槽；在字线沟槽内形成字线导电薄膜；在衬底表面形成光刻胶，光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜，使得字线接触部的字线导电结构（117）的厚度大于未被光刻胶覆盖的字线导电结构（117）的厚度。通过在衬底表面形成光刻胶，使得字线接触部的字线导电结构（117）的厚度大于未被光刻胶覆盖的字线导电结构（117）的厚度，降低了字线接触结构中字线接触孔（119）的开窗位置深度，减少了形成字线接触孔（119）工艺制程中的工艺时间，降低了字线接触孔（119）工艺制程中对开窗深度较浅的有源区接触孔（120）的侧壁的过度侵蚀，避免了有源区接触孔（120）异常引起的器件短路异常。

Description

一种半导体器件及其制作方法 技术领域
本发明涉及半导体技术领域，特别是涉及一种半导体器件及一种半导体器件的制作方法。
背景技术
动态随机存储器在制作接触窗结构时，由于不同的接触窗结构对应的接触孔深度不同，使用同一工艺制程制备不同接触窗结构的接触孔就会出现制程工艺开窗深度不足的问题，例如有源区接触孔已经停在有源区表面时，位置较深的字线接触孔停留在字线导电结构上方还未完成开窗，继续刻蚀字线接触孔则会导致有源区接触孔蚀刻到有源区内部，同时接触孔的侧壁也会出现扩孔的问题，容易引起器件的特征尺寸变大或侧壁刻蚀引起的器件短路异常。
发明内容
基于此，有必要针对上述问题，提供一种新的半导体器件的制作方法及一种新的半导体器件。
一种半导体器件的制作方法,包括：
获取衬底，所述衬底包括存储单元阵列区；
在所述存储单元阵列区形成间隔排布的字线沟槽；
在所述字线沟槽内填充字线导电材料，形成字线导电薄膜；
在所述衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜；
以所述光刻胶为阻挡层，将未被所述光刻胶覆盖的的字线导电薄膜蚀刻至目标高度后得到字线导电结构，使得所述字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度；
去除所述光刻胶。
在其中一个实施例中，所述字线接触部位于所述字线导电结构的末端。
在其中一个实施例中，所述字线接触部的字线导电结构的厚度与未被所述光刻胶覆盖的字线导电结构的厚度的比值大于等于1.5且小于等于4.0。
在其中一个实施例中，所述去除所述光刻胶后，还包括：
在所述衬底表面形成第一绝缘介质层；
图形化所述第一绝缘介质层，在所述字线接触部上形成字线接触孔。
在其中一个实施例中，所述衬底还包括周边电路区，所述周边电路区包括晶体管有源区，所述有源区表面形成有第二绝缘介质层，图形化所述第二绝缘介质层，在所述有源区的源极区/漏极区上形成有源区接触孔。
在其中一个实施例中，所述有源区接触孔与所述字线接触孔之间的高度差大于等于0且小于有源区接触孔高度的百分之二十。
在其中一个实施例中，所述字线接触孔和所述有源区接触孔是通过同一工艺制程形成的。
在其中一个实施例中，所述第一绝缘介质层和所述第二绝缘介质层是通过同一工艺制程形成的。
在其中一个实施例中，所述半导体器件为动态随机存储器。
上述制作方法，包括：获取衬底，所述衬底包括存储单元阵列区；在所述存储单元阵列区形成间隔排布的字线沟槽；在所述字线沟槽内填充字线导电材料，形成字线导电薄膜；在所述衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜；以所述光刻胶为阻挡层，将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标深度后得到字线导电结构，使得所述字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度。本申请通过在衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜，在以光刻胶为阻挡层将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标高度，使得形成的字线导电结构中字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度，与字线导电结构中字线接触部的字线导电结构的厚度等于未被所述光刻胶覆盖的字线导电结构的厚度相比，降低了字线接触部中字线接触孔的开窗位置深度，减少了形成接触孔工艺制程中的工艺时间，降低了 接触孔工艺制程中对接触孔开窗深度较浅的接触孔的侧壁的过度侵蚀，避免了接触孔异常引起的器件短路异常。
一种半导体器件，包括：
衬底，所述衬底上形成有存储单元阵列区，所述存储单元阵列区形成有间隔排布的字线沟槽；
字线导电结构，所述字线导电结构包括字线接触部的字线导电结构和字线接触部之外的字线导电结构；
其中，所述字线接触部的字线导电结构的厚度大于所述字线接触部之外的字线导电结构的厚度。
在其中一个实施例中，所述字线接触部位于所述字线导电结构的末端。
在其中一个实施例中，所述字线接触部的字线导电结构的厚度与字线接触部之外的字线导电结构的厚度的比值大于等于1.5且小于等于4.0。
在其中一个实施例中，所述器件还包括：
周边电路区，所述周边电路区包括晶体管有源区，所述有源区具有源极区/漏极区；
绝缘介质层，所述绝缘介质层位于所述字线导电结构和所述有源区表面；
字线接触结构，所述字线接触结构位于所述字线接触部上且与所述字线接触部接触；
有源区接触结构，所述有源区接触结构位于所述晶体管有源区上且与所述晶体管有源区的源极区/漏极区接触。
在其中一个实施例中，所述有源区接触结构与所述字线接触结构之间的高度差大于等于0且小于有源区接触结构高度的百分之二十。
在其中一个实施例中，所述有源区接触结构与所述字线接触结构是同时形成的。
在其中一个实施例中，所述半导体器件为动态随机存储器。
上述半导体器件，包括衬底，所述衬底上形成有存储单元阵列区，所述存储单元阵列区形成有间隔排布的字线沟槽；字线导电结构，字线导电结构包括字线接触部的字线导电结构和字线接触部之外的字线导电结构；其中，字线接 触部的字线导电结构的厚度大于字线接触部之外的字线导电结构的厚度。本申请的器件衬底表面形成有字线接触部的字线导电结构的厚度大于字线接触部之外的字线导电结构的厚度的字线导电结构，与字线导电结构中字线接触部的字线导电结构的厚度等于字线接触部之外的字线导电结构的厚度的器件相比，降低了字线接触孔的开窗位置深度，减少了形成接触孔工艺制程中的工艺时间，降低了接触孔工艺制程中对接触孔开窗深度较浅的接触孔的侧壁的过度侵蚀，避免了接触孔异常引起的器件短路异常。
附图说明
图1为一实施例中半导体器件制作方法的流程图；
图2a为一实施例中形成字线接触孔的流程图；
图2b为一实施例中形成有源区接触孔的流程图；
图3a为一实施例中半导体器件的剖视图；
图3b为一实施例中形成字线导电薄膜后半导体器件的剖视图；
图3c为一实施例中形成绝缘介质层后半导体器件的剖视图；
图4a为一实施例中形成字线导电薄膜后字线接触部在字线导电薄膜垂直方向的剖视图；
图4b为一实施例中形成光刻胶后图4a对应的剖视图；
图4c为一实施例中形成绝缘介质层后图4b对应的剖视图；
图5a为一实施例中形成字线导电薄膜后字线接触部之外的区域在字线导电薄膜垂直方向的剖视图；
图5b为一实施例中形成字线导电结构后图5a对应的剖视图；
图5c为一实施例中形成绝缘介质层后图5b对应的剖视图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本 发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存 在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
典型的动态随机存储器在制作连接字线、位线、晶体管有源区的源极区/漏极区、晶体管栅极区这几种结构的接触窗结构时，由于不同的接触窗结构对应的接触孔要开窗到不同的目标深度上，使用同一工艺制程制备接触孔时就会出现一种接触孔已经达到对应的目标深度，而其他的接触孔还未完成开窗，此时继续开窗，接触孔深度增加的同时也会持续对接触孔的侧壁进行扩孔，容易引起器件特征尺寸变大或侧蚀器件短路异常，例如晶体管有源区接触孔(Active Area contact,AA Contact)已经停在有源区表面，较深的字线接触孔(Word line Contact,WL Contact)停留在字线导电结构上方还未完成开窗，继续刻蚀时晶体管有源区接触孔就会刻蚀到有源区内部，产生尖刺效应(spiking)。
如图1、图3a、图3b、图3c、图4a-4c、图5a-5c所示，在一个实施例中，提供一种半导体器件的制作方法,包括：
S102，获取衬底。
衬底102包括存储单元阵列区，所述衬底可以至少为硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(SSiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等材料中的一种。
S104，形成字线沟槽。
在所述存储单元阵列区形成间隔排布的字线沟槽104。所述存储单元阵列区中形成有多个相互独立的字线沟槽，所述字线沟槽沿第一方向延伸、沿第二方向间隔排布，所述第一方向和所述第二方向相交。
在一个实施例中，所述字线沟槽是通过干法刻蚀形成的。在另一个实施例中，所述字线沟槽是通过湿法刻蚀形成的。
在一个实施例中，所述字线沟槽是通过两种工艺制程形成的。
S106，形成字线导电薄膜。
在字线沟槽104内填充字线导电材料，形成字线导电薄膜108。在一个实施例中，形成字线导电薄膜108之前还包括在字线沟槽104内壁形成绝缘层110，绝缘层110可以为二氧化硅薄膜层。
在一个实施例中，在字线沟槽104内填充字线导电材料之前还包括在字线沟槽内壁形成第一金属层，例如第一金属层可以为起粘连和阻挡作用的钛/氮化钛金属层。
在一个实施例中，字线导电材料是通过等离子体化学气相淀积工艺形成的。在一个实施例中，字线导电材料是通过物理气相淀积工艺形成的。在一个实施例中，字线导电材料为金属导电材料，例如金属钨材料、金属钨的复合物材料、金属铝材料等。
在一个实施例中，去除衬底表面多余的字线导电材料后，在字线沟槽104内形成字线导电薄膜108。
在一个实施例中，通过化学机械研磨的方式去除衬底表面多余的字线导电材料。在另一个实施例，通过刻蚀的方式去除衬底表面多余的字线导电材料，例如湿法刻蚀、干法刻蚀等。
S108，形成光刻胶。
在衬底102表面形成光刻胶112，即在衬底表面形成带有光刻图形的光刻胶，光刻胶112覆盖字线接触部114的字线沟槽115即字线接触部的字线导电薄膜，且露出字线接触部114之外的字线沟槽116即字线接触部之外的字线导电薄膜。
具体为，在衬底表面涂覆光刻胶，然后对光刻胶进行曝光显影后露出字线接触部之外的字线导电薄膜(即将器件的阵列区(array区)显影开)，未曝光的光刻胶覆盖在字线接触部的字线导电薄膜，起到保护字线接触部的字线导电薄膜的作用。
S110，形成字线导电结构。
以光刻胶112为阻挡层，将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标高度后得到字线导电结构117，即以光刻胶112为阻挡层对字线导电薄膜108进行减薄后得到字线导电结构117，使得字线接触部114的字线导电结构的厚度大于未被光刻胶112覆盖的字线导电结构的厚度。其中，将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标高度是指将将未被所述光刻胶覆盖的字线导电薄膜蚀刻到剩余的字线导电薄膜低于衬底表面5纳米以下，只要能实现剩余的字线导电薄膜达到避免字线与位线及其他接触窗等结构产生短路的目的即可。
S112，去除光刻胶。
去除衬底表面的光刻胶。
在一个实施例中，字线导电结构117位于浅槽隔离氧化层121上。
在一个实施例中，字线接触部114位于字线导电结构117的末端。
在一个实施例中，所述字线接触部的字线导电结构的厚度与未被所述光刻胶覆盖的字线导电结构的厚度的比值大于等于1.5且小于等于4.0。实际工艺制程中，根据需要设置字线接触部的字线导电结构的厚度与未被所述光刻胶覆盖的字线导电结构的厚度的比值的数值，例如1.7，1.9，2.0，2.2，2.5，2.7，2.9，3.0，3.3，3.5，3.7，3.9等。
如图2a所示，在一个实施例中，步骤S112之后还包括：
S202，形成第一绝缘介质层。
在所述字线导电结构117表面形成第一绝缘介质层。
在一个实施例中，去除字线导电结构上的光刻胶后，在衬底表面形成一层第一绝缘介质层薄膜，例如可以通过物理气相淀积或化学气相淀积的方式在衬底表面形成第一绝缘介质层薄膜；然后通过刻蚀或化学机械研磨的方式去除衬底表面多余的第一绝缘介质层薄膜后形成第一绝缘介质层。
在一个实施例中，第一绝缘介质层为氧化硅绝缘层。
S204，形成字线接触孔。
如图3a所示，对第一绝缘介质层进行图形化，在字线接触部114上形成字线接触孔119。
如图2b所示，在一个实施例中，所述衬底还包括周边电路区，所述周边电 路区包括晶体管有源区，所述半导体器件的制作方法还包括：
S201，形成第二绝缘介质层。
在晶体管有源区表面形成第二绝缘介质层。
在一个实施例中，第二绝缘介质层和第一绝缘介质层是通过同一工艺制程形成的。
S203，形成有源区接触孔。
图形化所述第二绝缘介质层，在有源区的源极区/漏极区106上形成有源区接触孔120。
在一个实施例中，有源区接触孔120与字线接触孔119之间的高度差大于等于0且小于有源区接触孔高度的百分之二十，在实际工艺制程中，有源区接触孔与字线接触孔119之间的高度差可以为有源区接触孔高度的5％、7％、9％、10％、13％、15％、17％、19％等。
在一个实施例中，字线接触孔119和有源区接触孔120是通过同一工艺制程形成的。
在一个实施例中，所述半导体器件为动态随机存储器。
上述制作方法，包括：获取衬底，所述衬底包括存储单元阵列区；在所述存储单元阵列区形成间隔排布的字线沟槽；在所述字线沟槽内填充字线导电材料，形成字线导电薄膜；在所述衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜；以所述光刻胶为阻挡层，将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标深度后得到字线导电结构，使得所述字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度。本申请通过在衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜，在以光刻胶为阻挡层将未被所述光刻胶覆盖的字线导电薄膜蚀刻至目标高度，使得形成的字线导电结构中字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度，与字线导电结构中字线接触部的字线导电结构的厚度等于未被所述光刻胶覆盖的字线导电结构的厚度相比，降低了字线接触部中字线接触孔的开窗位置深度，减少了形成接触孔工艺制程中的工艺时间，降低了 接触孔工艺制程中对接触孔开窗深度较浅的接触孔的侧壁的过度侵蚀，避免了接触孔异常引起的器件短路异常。
如图3a、图3b、图3c所示，在一实施例中，提供一种半导体器件，包括：
衬底102，衬底102上形成有存储单元阵列区，所述存储单元阵列区形成有间隔排布的字线沟槽104。所述存储单元阵列区中形成有多个相互独立的字线沟槽，所述字线沟槽沿第一方向延伸、沿第二方向间隔排布，所述第一方向和所述第二方向相交。所述衬底可以至少为硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(SSiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等材料中的一种。
字线导电结构117，字线导电结构117包括字线接触部114的字线导电结构和字线接触部114之外的字线导电结构。
在一个实施例中，所述字线接触部114位于字线导电结构117的末端。
在一个实施例中，字线导电结构117为金属导电结构，例如金属钨导电结构、金属钨的复合物导电结构、金属铝导电结构等。
其中，字线接触部114的字线导电结构的厚度大于字线接触部114之外的字线导电结构的厚度。
在一个实施例中，所述字线接触部的字线导电结构的厚度与字线接触部之外的字线导电结构的厚度的比值大于等于1.5且小于等于4.0。实际半导体器件设计过程中，根据需要设置字线接触部的字线导电结构的厚度与字线接触部之外的字线导电结构的厚度的比值的数值，例如1.7，1.9，2.0，2.2，2.5，2.7，2.9，3.0，3.3，3.5，3.7，3.9等。
在一个实施例中，所述器件还包括：
字线接触孔119，字线接触孔119形成于字线接触部114上且字线接触孔119的底部与字线接触部114上表面接触。
有源区接触孔120，有源区接触孔120形成于所述晶体管有源区上且有源区接触孔120的底部与所述晶体管有源区的源极区/漏极区106的上表面接触。
在一个实施例中，所述器件还包括：
周边电路区，所述周边电路区包括晶体管有源区，所述有源区具有源极区/ 漏极区106；
绝缘介质层118，所述绝缘介质层118位于所述字线导电结构和所述有源区表面。
在一个实施例中，绝缘介质层118包括位于字线导电结构117表面的第一绝缘介质层和位于晶体管有源区表面的第二绝缘介质层。
字线接触结构，所述字线接触结构位于字线接触部114上且与字线接触部114接触。
字线接触结构位于字线接触部114上形成的字线接触孔119中，字线接触结构为导电结构，用于引出字线导电结构117。
在一个实施例中，字线接触结构为金属导电结构，例如金属钨导电结构、金属钨的复合物导电结构、金属铝导电结构等。
有源区接触结构，所述有源区接触孔位于所述晶体管有源区上且与所述晶体管有源区的源极区/漏极区106接触。
有源区接触结构位于源极区/漏极区106上形成的有源区接触孔120中，有源区接触结构为导电结构，用于引出晶体管的源极区/漏极区106。
在一个实施例中，有源区接触结构为金属导电结构，例如金属钨导电结构、金属钨的复合物导电结构、金属铝导电结构等。
在其中一个实施例中，所述有源区接触结构与所述字线接触结构之间的高度差大于等于0且小于有源区接触结构高度的百分之二十，在实际半导体器件中，有源区接触结构与字线接触结构之间的高度差可以为有源区接触结构高度的5％、7％、9％、10％、13％、15％、17％、19％等。
在一个实施例中，有源区接触孔120与字线接触孔119之间的高度差大于等于0且小于有源区接触孔高度的百分之二十，在实际半导体器件中，有源区接触孔与字线接触孔119之间的高度差可以为有源区接触孔高度的5％、7％、9％、10％、13％、15％、17％、19％等。
在一个实施例中，所述器件还包括第一金属层，所述第一金属层位于所述字线沟槽中，所述第一金属层的上表面与所述字线导电结构的下表面接触，例如第一金属层可以为起粘连和阻挡作用的钛/氮化钛金属层。
在一个实施例中，所述半导体器件为动态随机存储器。
上述半导体器件，包括衬底，所述衬底上形成有存储单元阵列区，所述存储单元阵列区形成有间隔排布的字线沟槽；字线导电结构，字线导电结构包括字线接触部的字线导电结构和字线接触部之外的字线导电结构；其中，字线接触部的字线导电结构的厚度大于字线接触部之外的字线导电结构的厚度。本申请的器件衬底表面形成有字线接触部的字线导电结构的厚度大于字线接触部之外的字线导电结构的厚度的字线导电结构，与字线导电结构中字线接触部的字线导电结构的厚度等于字线接触部之外的字线导电结构的厚度的器件相比，降低了字线接触孔的开窗位置深度，减少了形成接触孔工艺制程中的工艺时间，降低了接触孔工艺制程中对接触孔开窗深度较浅的接触孔的侧壁的过度侵蚀，避免了接触孔异常引起的器件短路异常。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种半导体器件的制作方法,包括：
    获取衬底，所述衬底包括存储单元阵列区；
    在所述存储单元阵列区形成间隔排布的字线沟槽；
    在所述字线沟槽内填充字线导电材料，形成字线导电薄膜；
    在所述衬底表面形成光刻胶，所述光刻胶覆盖字线接触部的字线导电薄膜且露出字线接触部之外的字线导电薄膜；
    以所述光刻胶为阻挡层，将未被所述光刻胶覆盖的所述字线导电薄膜蚀刻至目标高度后得到字线导电结构，使得所述字线接触部的字线导电结构的厚度大于未被所述光刻胶覆盖的字线导电结构的厚度；
    去除所述光刻胶。
  2. 根据权利要求1所述的方法，其特征在于，所述字线接触部位于所述字线导电结构的末端。
  3. 根据权利要求1所述的方法，其特征在于，所述去除所述光刻胶后，还包括：
    在所述衬底表面形成第一绝缘介质层；
    图形化所述第一绝缘介质层，在所述字线接触部上形成字线接触孔。
  4. 根据权利要求3所述的方法，其特征在于，所述衬底还包括周边电路区，所述周边电路区包括晶体管有源区，所述方法还包括：
    在所述有源区表面形成第二绝缘介质层；
    图形化所述第二绝缘介质层，在所述有源区的源极区/漏极区上形成有源区接触孔。
  5. 根据权利要求4所述的方法，其特征在于，所述字线接触孔和所述有源区接触孔是通过同一工艺制程形成的。
  6. 根据权利要求4所述的方法，其特征在于，所述第一绝缘介质层和所述第二绝缘介质层是通过同一工艺制程形成的。
  7. 一种半导体器件，包括：
    衬底，所述衬底上形成有存储单元阵列区，所述存储单元阵列区形成有间隔排布的字线沟槽；
    字线导电结构，所述字线导电结构包括字线接触部的字线导电结构和字线接触部之外的字线导电结构；
    其中，字线接触部的字线导电结构的厚度大于所述字线接触部之外的字线导电结构的厚度。
  8. 根据权利要求7所述的器件，其特征在于，所述字线接触部位于所述字线导电结构的末端。
  9. 根据权利要求7所述的器件，其特征在于，所述字线接触部的字线导电结构的厚度与所述字线接触部之外的字线导电结构的厚度的比值大于等于1.5且小于等于4.0。
  10. 根据权利要求7所述的器件，其特征在于，所述器件还包括：
    周边电路区，所述周边电路区包括晶体管有源区，所述有源区具有源极区/漏极区；
    绝缘介质层，所述绝缘介质层位于所述字线导电结构和所述有源区表面；
    字线接触结构，所述字线接触结构形成于所述字线接触部上且与所述字线接触部接触；
    有源区接触结构，所述有源区接触结构形成于所述晶体管有源区上且与所述晶体管有源区的源极区/漏极区接触。
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