TW201440146A - 半導體記憶體製程 - Google Patents

半導體記憶體製程 Download PDF

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TW201440146A
TW201440146A TW102112769A TW102112769A TW201440146A TW 201440146 A TW201440146 A TW 201440146A TW 102112769 A TW102112769 A TW 102112769A TW 102112769 A TW102112769 A TW 102112769A TW 201440146 A TW201440146 A TW 201440146A
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oxide layer
polysilicon
semiconductor memory
polysilicon layer
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TWI497609B (zh
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Yaw-Wen Hu
Ron-Fu Chu
Tzung-Han Lee
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Inotera Memories Inc
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Abstract

一種半導體記憶體製程，首先於基板中定義主動區域，形成氧化層，對氧化層進行表面處理，於氧化層上沈積第一多晶矽層、緩衝層及硬遮罩層。接著製作凹入式存取元件，包括在記憶體陣列區內的硬遮罩層中形成開口，進行乾蝕刻製程，蝕刻緩衝層、第一多晶矽層、氧化層及半導體基板，形成溝槽，接著於溝槽表面形成閘極氧化層，填入金屬閘極，填滿介電層，去除硬遮罩層及緩衝層。再製作週邊電路區內的平面式電晶體元件，包括在第一多晶矽層上沈積第二多晶矽層，然後將第一、第二多晶矽層蝕刻成閘極結構。

Description

半導體記憶體製程
本發明係有關於半導體製程，特別是有關於一種改良的半導體記憶體製程方法。
在製造記憶體的過程中，已知記憶體週邊電路區內，部分的電晶體的閘極氧化層破裂現象，會造成製程良率下降以及記憶體元件的可靠度問題。申請人相信記憶體週邊電路區內電晶體的閘極氧化層破裂，其主要原因很可能是製程過程中的應力使多晶矽重新長晶所致。
申請人於是提出一種改良的半導體記憶體製程方法發明，可以有效避免記憶體製程過程中週邊電路區內的閘極氧化層破裂現象。
為達上述目的，本發明提供一種半導體記憶體製程，包含有：提供一半導體基板，具有一記憶體陣列區以及一週邊電路區；於該半導體基板中定義出複數個主動區域；於該主動區域上形成一氧化層，其中該氧化層係作為該週邊電路區內的閘極氧化層；對該氧化層進行一表面處理步驟；於該氧化層上沈積一第一多晶矽層、一緩衝層及一硬遮罩層；進行該記憶體陣列區的凹入式存取元件的製作，包括以微影及蝕刻製程在該記憶體陣列區內的該硬遮罩層中形成一開口；進行一乾蝕刻製程，經由該開口向下蝕刻該緩衝層、該第一多晶矽層、該氧化層以及該半導體基板，形成一溝槽；再於該溝槽的表面形成一閘極氧化層，填入金屬閘極，並填滿介電層；去除該硬遮罩層及該緩衝層；以及進行該週邊電路區內的平面式電晶體元件的製作，包括在該週邊電路區內的該第一多晶矽層上沈積一第二多晶矽層，然後利用微影 及蝕刻製程，將該第一多晶矽層及該第二多晶矽層蝕刻成一閘極結構。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
10‧‧‧半導體基板
11‧‧‧溝渠絕緣結構
12‧‧‧離子井
14‧‧‧主動區域
16‧‧‧氧化層
18‧‧‧第一多晶矽層
20‧‧‧緩衝層
22‧‧‧硬遮罩層
26‧‧‧RAD溝槽
32‧‧‧閘極氧化層
34‧‧‧金屬閘極
36‧‧‧介電層
38‧‧‧第二多晶矽層
40‧‧‧閘極結構
42‧‧‧汲極/源極摻雜區
101‧‧‧記憶體陣列區
102‧‧‧週邊區
110‧‧‧絕緣溝槽
220‧‧‧開口
第1圖至第6圖為依據本發明實施例所繪示的半導體記憶體製程方法的剖面示意圖。
在下文中，將參照附圖說明本發明實施細節，該些附圖中之內容構成說明書一部份，並以可實行該實施例之特例描述方式繪示。下文實施例已揭露足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，本發明中亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
請參閱第1圖至第6圖，其為依據本發明實施例所繪示的半導體記憶體製程方法的剖面示意圖。首先，如第1圖所示，提供一半導體基板10，例如，矽基板。半導體基板10區分有記憶體陣列區101以及週邊電路區或簡稱週邊區102。根據本發明實施例，在記憶體陣列區101內將形成高密度排列的凹入式存取元件(recessed access device,RAD)及電容，而在週邊區102內將至少形成複數個平面式電晶體元件。
接著，進行主動區域的定義，包括以微影及蝕刻製程在半導體基板10表面蝕刻出絕緣溝槽110，並隨後在絕緣溝槽110內填入溝渠填充材料，例如，旋塗介電材(spin on dielectric,SOD)等，形成溝渠絕緣結構11。在平坦化之後，即完成主動區域14的定義。接下來，進行離子佈植製程，在半導體 基板10中形成離子井12，可以是P型井或N型井。
然後，進行氧化製程，在主動區域14上形成氧化層16。其中在週邊區102內氧化層16作為平面式電晶體元件的閘極氧化層。視製程需要及元件設計，週邊區102內的氧化層16可以有不同厚度，例如低壓元件可以有較薄的厚度，而高壓元件則有較厚的厚度。
根據本發明實施例，在完成氧化層16之後，可以選擇進行一表面處理步驟，使氧化層16的表面接觸純水，例如，利用潤濕(rinse)或噴灑(spray)等方式，使氧化層16與水接觸，藉以改變其表面的懸鍵(dangling bond)狀態，減少可能的弱點(weak point)。此步驟可以避免後續多晶矽在受應力下順著該弱點重新長晶，造成氧化層16破裂。上述表面處理步驟可以另包括一旋乾(spin dry)步驟，使接觸過水的氧化層16表面乾燥。
如第2圖所示，接著依序在半導體基板10上沈積一第一多晶矽層18、一緩衝層20以及一硬遮罩層22。根據本發明實施例，第一多晶矽層18可以是未摻雜(undoped)多晶矽層。緩衝層20可以包括氮化矽氧(silicon oxynitride)、矽氧層、氧化鋁等等。硬遮罩層22可以是氮化矽。
如第3圖所示，接著以微影及蝕刻製程在記憶體陣列區101內的硬遮罩層22中形成定義上述凹入式存取元件位置的開口220，然後繼續進行一乾蝕刻製程，經由開口220，利用硬遮罩層22作為蝕刻抵擋層，向下蝕刻緩衝層20、第一多晶矽層18、氧化層16以及半導體基板10，如此形成一RAD溝槽26。
如第4圖所示，接著於記憶體陣列區101內進行上述凹入式存取元件的製作，包括在RAD溝槽26的表面形成閘極氧化層32，再形成金屬閘極34，然後將RAD溝槽26填滿介電層36，如此即完成記憶體陣列區101內凹入式存取元件的製作。隨後，可以繼續將硬遮罩層22及緩衝層20去除。根據本發明實施例，可以選擇繼續將記憶體陣列區101內的第一多晶矽層18去除。但是，記憶體陣列區101內的第一多晶矽層18也可以不被去除。
如第5圖及第6圖所示，接著進行週邊區102內的平面式電晶體元件的製作，包括在週邊區102內的第一多晶矽層18上沈積一第二多晶矽層38，然後利用微影及蝕刻製程，將第一多晶矽層18及第二多晶矽層38蝕刻成一閘極結構40。最後，利用離子佈植製程，於閘極結構40兩側的半導體基板10中形成汲極/源極摻雜區42。
根據本發明實施例，形成汲極/源極摻雜區42之前，可以在閘極結構40側壁形成一側壁子(圖未示)。
根據本發明實施例，在沈積上述第二多晶矽層38之前，可以先進行一清洗製程，去除形成在第一多晶矽層18表面的原生氧化(native oxide)層。
根據本發明實施例，上述第二多晶矽層38為未摻雜多晶矽層，且在沈積上述第二多晶矽層38之後，可以蝕刻掉部分厚度的第二多晶矽層38，例如使得最後的第二多晶矽層38的厚度約為300埃左右，以維持記憶體陣列區的平坦度。
根據本發明實施例，上述第一多晶矽層18及第二多晶矽層38可以在後續步驟進行N型或P型摻雜。
根據本發明實施例，在沈積第二多晶矽層38，還可以選擇繼續沈積一導電層(圖未示)，例如鎢、氮化鈦、鈦、矽化鎢等。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體基板
11‧‧‧溝渠絕緣結構
12‧‧‧離子井
14‧‧‧主動區域
16‧‧‧氧化層
18‧‧‧第一多晶矽層
20‧‧‧緩衝層
22‧‧‧硬遮罩層
26‧‧‧RAD溝槽
101‧‧‧記憶體陣列區
102‧‧‧週邊區
110‧‧‧絕緣溝槽
220‧‧‧開口

Claims (7)

  1. 一種半導體記憶體製程，包含有：提供一半導體基板，具有一記憶體陣列區以及一週邊電路區；於該半導體基板中定義出複數個主動區域；於該主動區域上形成一氧化層，其中該氧化層係作為該週邊電路區內的閘極氧化層；對該氧化層進行一表面處理步驟；於該氧化層上沈積一第一多晶矽層、一緩衝層及一硬遮罩層；進行該記憶體陣列區的凹入式存取元件的製作，包括以微影及蝕刻製程在該記憶體陣列區內的該硬遮罩層中形成一開口；進行一乾蝕刻製程，經由該開口向下蝕刻該緩衝層、該第一多晶矽層、該氧化層以及該半導體基板，形成一溝槽；再於該溝槽的表面形成一閘極氧化層，填入金屬閘極，並填滿介電層；去除該硬遮罩層及該緩衝層；以及進行該週邊電路區內的平面式電晶體元件的製作，包括在該週邊電路區內的該第一多晶矽層上沈積一第二多晶矽層，然後利用微影及蝕刻製程，將該第一多晶矽層及該第二多晶矽層蝕刻成一閘極結構。
  2. 如申請專利範圍第1項所述之半導體記憶體製程，其中該表面處理步驟包含有使該氧化層的表面接觸純水。
  3. 如申請專利範圍第2項所述之半導體記憶體製程，其中該表面處理步驟還包含有一旋乾步驟。
  4. 如申請專利範圍第1項所述之半導體記憶體製程，其中該第一多晶矽層是一未摻雜多晶矽層。
  5. 如申請專利範圍第1項所述之半導體記憶體製程，其中該緩衝層包含有氮化矽氧、矽氧層或氧化鋁。
  6. 如申請專利範圍第1項所述之半導體記憶體製程，其中該硬遮罩層包含有氮化矽。
  7. 如申請專利範圍第1項所述之半導體記憶體製程，其中該第二多晶矽層是一未摻雜多晶矽層。
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