WO2021114471A1 - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021114471A1
WO2021114471A1 PCT/CN2020/074876 CN2020074876W WO2021114471A1 WO 2021114471 A1 WO2021114471 A1 WO 2021114471A1 CN 2020074876 W CN2020074876 W CN 2020074876W WO 2021114471 A1 WO2021114471 A1 WO 2021114471A1
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layer
insulating layer
gate
disposed
organic
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PCT/CN2020/074876
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English (en)
French (fr)
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彭浩
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武汉华星光电半导体显示技术有限公司
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Priority to US16/651,701 priority Critical patent/US11271057B2/en
Publication of WO2021114471A1 publication Critical patent/WO2021114471A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display panel.
  • Organic light-emitting display device (full English name: Organic Light-Emitting Diode, OLED for short) is also known as organic electro-laser display device and organic light-emitting semiconductor.
  • the working principle of OLED is: when the power is supplied to the appropriate voltage, the positive electrode holes and the negative electrode charges will be combined in the light-emitting layer, and under the action of the Coulomb force, they will recombine with a certain probability to form excitons in the excited state (electron-hole Yes), and this excited state is unstable in a normal environment.
  • the excitons of the excited state recombine and transfer energy to the luminescent material, making it transition from the ground state energy level to the excited state, and the excited state energy is through the radiative relaxation process It produces photons, releases light energy, and produces light. According to its different formulas, it produces three primary colors of red, green and blue RGB, which constitute the basic colors.
  • OLED has the advantages of low voltage demand, high power saving efficiency, fast response, light weight, thin thickness, simple structure, low cost, wide viewing angle, almost infinitely high contrast, low power consumption, and extremely high response speed. It has become today's One of the most important display technologies.
  • the flexible display panel needs to be bent multiple times during use, cracks are likely to occur due to stress during the bending process.
  • the existing organic film layer has a better stress release effect than the inorganic film layer, the hole is dug in the blank area of the trace, and the hole is filled with the organic film layer to achieve the effect of stress relief. Since the organic film layer in the digging structure needs to be retained, if the organic film layer in other areas is removed, it will cause a large gap in the filled digging area. The subsequent metal layer covering is prone to breakage, so that a large area is organic. The film layer remains in the laminated structure.
  • the organic film layer greatly increases the depth of the via hole at the position of the via trace connection, resulting in incomplete morphology of the trace via metal deposition, which makes the via metal connection easily broken, causing the Panel to be in the signal
  • the transmission is affected and the screen display is abnormal. Therefore, it is necessary to find a new type of display panel to solve the above-mentioned problems.
  • An object of the present invention is to provide an array substrate, a preparation method thereof, and a display panel, which can solve the problem that the organic film layer existing in the existing display panel greatly increases the depth of the via hole, resulting in insufficient appearance of the hindered metal deposition of the trace via hole Integrity, making the via metal connection easy to break, causing the Panel to be affected in signal transmission, and the screen display is abnormal.
  • an embodiment of the present invention provides an array substrate, which defines a display area and a bending area.
  • the array substrate includes: a substrate, a barrier layer, an insulating layer, a conductive layer, and an interlayer insulating layer.
  • the barrier layer is disposed on the substrate; the insulating layer is disposed on the blocking layer; the conductive layer is disposed in the insulating layer at intervals; the interlayer insulating layer is disposed on the conductive layer
  • the surface of the interlayer insulating layer of the display area away from the substrate is recessed downward until the barrier layer forms a groove, and the groove is filled with an organic material to form an organic layer; the organic layer is away from the surface of the substrate It is flush with the surface of the interlayer insulating layer away from the substrate.
  • the array substrate further includes: a buffer layer, an active layer, a source and drain layer, and a flat layer.
  • the buffer layer is arranged between the barrier layer and the insulating layer, wherein the organic layer penetrates the buffer layer; the active layer is arranged between the buffer layer and the insulating layer;
  • the source-drain layer is disposed on the interlayer insulating layer; the source-drain layer is connected to the active layer through via holes; the flat layer is disposed on the source-drain layer.
  • the insulating layer includes a first gate insulating layer and a second gate insulating layer; the conductive layer includes a first gate layer and a second gate layer.
  • the first gate insulating layer is disposed on the barrier layer; the first gate layer is disposed on the first gate insulating layer; the second gate insulating layer is disposed on the first On the gate layer; the second gate layer is arranged on the second gate insulating layer, and the interlayer insulating layer is arranged on the second gate layer.
  • Another embodiment of the present invention also provides a method for preparing the array substrate of the present invention, which includes the following steps: a barrier layer preparation step, defining the array substrate to be prepared into a display area and a bending area, and providing A substrate, a barrier layer is prepared on the substrate; an insulating layer preparation step, the insulating layer is prepared on the barrier layer; a conductive layer preparation step, the conductive layer is arranged in the insulating layer at intervals; interlayer insulation
  • the layer preparation step is to prepare the interlayer insulating layer on the conductive layer; the interlayer insulating layer of the display area away from the surface of the substrate is recessed downward until the barrier layer forms a groove; the organic layer preparation step, Filling the groove with an organic material to form an organic layer; wherein the surface of the organic layer away from the substrate is flush with the surface of the interlayer insulating layer away from the substrate.
  • the preparation method of the array substrate further includes: a buffer layer preparation step, a buffer layer is prepared between the barrier layer and the insulating layer, and the organic layer penetrates the buffer layer; an active layer preparation step , An active layer is prepared between the buffer layer and the insulating layer; the source-drain layer preparation step is to prepare a source-drain layer on the interlayer insulating layer, and the source-drain layer is connected through a via hole On the active layer; a flat layer preparation step, a flat layer is prepared on the source and drain layers.
  • the insulating layer preparation step includes a first gate insulating layer preparation step and a second gate insulating layer preparation step;
  • the conductive layer preparation step includes a first gate layer preparation step and a second gate layer preparation step step.
  • the first gate insulating layer preparation step is to prepare a first gate insulating layer on the barrier layer;
  • the first gate layer preparation step is to prepare a first gate layer on the first gate insulating layer;
  • a second gate insulating layer preparation step, a second gate insulating layer is prepared on the first gate layer;
  • a second gate layer preparation step a second gate layer is prepared on the second gate insulating layer;
  • the interlayer insulating layer is prepared on the second gate layer.
  • the step of preparing the organic layer includes: coating and filling organic material on the interlayer insulating layer and in the groove, and partially removing the organic material at the groove by using a halftone mask process to form an organic layer.
  • the step of preparing the organic layer further includes: using an exposure process to remove the organic material on the interlayer insulating layer, and finally reach the surface of the organic layer away from the substrate and the interlayer insulating layer away from the interlayer insulating layer.
  • the surface of the substrate is flush.
  • the transmittance of the halftone mask process ranges from 20-45%.
  • Another embodiment of the present invention also provides a display panel, which includes the array substrate related to the present invention.
  • the invention relates to an array substrate, a preparation method thereof, and a display panel.
  • the surface of the interlayer insulating layer in the display area away from the substrate is recessed downward until the barrier layer forms a groove, and the groove is filled with an organic material to form an organic layer. Therefore, the stress generated when the array substrate is bent multiple times can be relieved.
  • the present invention partially removes the organic material at the grooves through the halftone mask process, exposes other areas of the display area and completely removes the bending.
  • the organic material of the organic photoresist layer in the area is retained, so that the surface of the organic layer away from the substrate is flush with the surface of the interlayer insulating layer away from the substrate, and finally reaches the upper source and drain layer without interruption.
  • the morphology of the via metal deposits is not complete, making the via metal connections easy to disconnect, causing the Panel to be affected in signal transmission, and the screen display is abnormal.
  • FIG. 1 is a schematic diagram of the structure of the display panel of the present invention.
  • Fig. 2 is a flow chart of the preparation steps of the array substrate of the present invention.
  • Fig. 3 is a schematic diagram of the preparation structure of the array substrate of the present invention.
  • the first gate layer 7.
  • the component can be directly placed on the other component; there may also be an intermediate component on which the component is placed , And the intermediate component is placed on another component.
  • a component is described as “installed to” or “connected to” another component, both can be understood as directly “installed” or “connected”, or a component is “installed to” or “connected to” through an intermediate component Another component.
  • a display panel 100 is defined with a display area 101 and a bending area 102.
  • the display panel 100 includes an array substrate.
  • the array substrate includes: a substrate 1, a barrier layer 2, a buffer layer 3, an active layer 4, a first gate insulating layer 5, a first gate layer 6, a second gate insulating layer 7, and a second gate Layer 8, interlayer insulating layer 9, source and drain layer 10, and flat layer 11.
  • the display panel 100 further includes an anode 12, a pixel defining layer 13, a light emitting layer 14 and a cathode 15.
  • the substrate 1 may include a first substrate, an intermediate layer and a second substrate.
  • the constituent materials of the first substrate and the second substrate can be polyimide, and the first substrate and the second substrate made thereby have good flexibility.
  • the composition material of the intermediate layer can be SiO2, SiNx, or a laminated structure of SiO2 and SiNx.
  • the intermediate layer thus prepared has good water and oxygen blocking performance, and can also improve the first substrate and the second substrate. The trustworthiness between the two substrates.
  • the barrier layer 2 is disposed on the substrate 1 and mainly functions as a water and oxygen barrier.
  • the buffer layer 3 is disposed on the barrier layer 2 and mainly serves as a buffer and protection.
  • the active layer 4 is disposed on the buffer layer 3 of the display area 101.
  • the active layer 4 includes a main body 41 and two side parts 42.
  • excimer laser crystallization technology is mainly used to achieve polysiliconization of the active layer 4, and then the active layer 4 is patterned through a PR mask to form the main body 41 and the two side portions 42
  • the two side portions 42 of the multi-active layer 4 of a PR photomask are subjected to ion doping treatment to form a P-type semiconductor.
  • the first gate insulating layer 5 is disposed on the active layer 4; the first gate layer 6 is disposed on the first gate insulating layer 5; the second The gate insulating layer 7 is disposed on the first gate layer 6; the second gate layer 8 is disposed on the second gate insulating layer 7; wherein the interlayer insulating layer 9 is disposed on the On the second gate layer 8; the source-drain layer 10 is disposed on the interlayer insulating layer 9; the source-drain layer 10 is connected to the active layer 4 through a via hole, specifically, The source-drain layer 10 is connected to the two side portions 42 of the active layer 4 through via holes; the flat layer 11 is disposed on the source-drain layer 10.
  • the anodes 12 are arranged on the flat layer 11 at intervals; the pixel definition layer 13 is arranged on the flat layer 11 between adjacent anodes 12; the light-emitting layer 14 is arranged on the anode 13; the cathode 15 is arranged on the light-emitting layer 14.
  • the interlayer insulating layer 9 of the display area 101 of the present embodiment is recessed downward from the surface of the substrate 1 away from the substrate 1 until the barrier layer 2 forms a groove 20, and the groove 20 is filled with organic
  • the material forms the organic layer 16. Therefore, the organic layer composed of organic materials can release the stress generated when the array substrate is bent multiple times.
  • the organic layer 16 is only formed at the recess 20, which removes the organic material in other areas of the display area 101, avoiding increasing the depth of the trace vias in the source and drain layer 10, resulting in obstruction of the via metal deposition.
  • the morphology is not complete, making the via metal connection easily broken, causing the Panel to be affected in signal transmission, and the screen display is abnormal.
  • the surface of the organic layer 16 away from the substrate 1 is flush with the surface of the interlayer insulating layer 9 away from the substrate 1. In this way, it is possible to avoid a gap between the organic layer 16 and the interlayer insulating layer 9 at the groove 20, thereby avoiding the subsequent wiring disconnection and affecting the screen display.
  • this embodiment provides a method for preparing the array substrate involved in the present invention, which includes the following steps: Step S1, a barrier layer 2 preparation step, defining the array substrate to be prepared In the display area 101 and the bending area 102, a substrate 1 is provided, and a barrier layer 2 is prepared on the substrate 1; step S2, a buffer layer 3 preparation step, a buffer layer 3 is prepared on the barrier layer 2; step S3, there is The source layer 4 preparation step, the active layer 4 is prepared on the buffer layer 3; step S4, the first gate insulating layer 5 preparation step, the first gate insulating layer 5 is prepared on the active layer 4; step S5, a step of preparing the first gate layer 6, preparing the first gate layer 6 on the first gate insulating layer 5; step S6, a step of preparing the second gate insulating layer 7, in the first gate insulating layer A second gate insulating layer 7 is prepared on the layer 6; step S7, a second gate layer 8 preparation step, a second gate layer 8 is prepared on
  • the preparation step of the organic layer 16 includes: coating and filling organic material on the interlayer insulating layer 9 and in the groove, and then exposing and removing it by using a mask.
  • the mask includes a first area 17 corresponding to the groove 20, a second area 18 and a third area 19 corresponding to the organic photoresist layer 21 in the bending area 102.
  • the first region 17 adopts a halftone mask process to partially remove the organic material at the groove 20 to form the organic layer 16.
  • the third area 19 adopts an exposure process to completely remove the organic material on the interlayer insulating layer 9.
  • the retention of the organic material in the non-groove 20 will lead to the deepening of the depth of the trace vias, resulting in insufficient morphology of the hindered metal deposition of the trace vias, which makes the via metal connections prone to disconnection, causing the Panel to suffer from signal transmission. Affected, the screen display is abnormal.
  • the organic material at the groove 20 is retained to form the organic layer 16, which can release the pressure generated when the array substrate is bent multiple times.
  • the second region 18 adopts a common mask process to retain the organic material in the organic photoresist layer 21 here.
  • the half-mask process at the groove and the mask process used in the preparation of the organic photoresist layer 21 in the bending area 102 are performed at the same time, so bending is achieved without increasing the number of masks.
  • the transmittance range of the halftone mask process is 20-45%, so that the surface of the organic layer 16 away from the substrate 1 and the surface of the interlayer insulating layer 9 away from the substrate 1 can be finally achieved.
  • the surface is flush. In this way, the gap between the organic layer 16 and the interlayer insulating layer 9 at the groove can be avoided, thereby avoiding the subsequent wiring breakage and affecting the screen display.
  • the organic material can be filled in the groove by evaporation or deposition.

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Abstract

本发明涉及一种阵列基板及其制备方法、显示面板。一方面，本发明通过在显示区设置有机层。由此可以释放阵列基板在多次弯折时产生的应力。另一方面，本发明在不增加新的掩膜板数量的前提下，通过半色调掩膜工艺对凹槽处的有机材料进行部分去除，对显示区的其他区域进行曝光完全去除，对弯折区的有机光阻层的有机材料进行保留，以致所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐，最终达到上层源漏极层设置时无断差。

Description

一种阵列基板及其制备方法、显示面板
本申请要求于2019年12月11日提交中国专利局、申请号为201911266283.3、发明名称为“一种阵列基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示面板。
 背景技术
有机发光显示装置(英文全称：Organic Light-Emitting Diode, 简称OLED)又称为有机电激光显示装置、有机发光半导体。OLED的工作原理是：当电力供应至适当电压时，正极空穴与阴极电荷就会在发光层中结合，在库伦力的作用下以一定几率复合形成处于激发态的激子（电子-空穴对），而此激发态在通常的环境中是不稳定的，激发态的激子复合并将能量传递给发光材料，使其从基态能级跃迁为激发态，激发态能量通过辐射驰豫过程产生光子，释放出光能，产生光亮，依其配方不同产生红、绿和蓝RGB三基色，构成基本色彩。
OLED具有电压需求低、省电效率高、反应快、重量轻、厚度薄，构造简单，成本低、广视角、几乎无穷高的对比度、较低耗电、极高反应速度等优点，已经成为当今最重要的显示技术之一。
 技术问题
由于柔性显示面板在使用过程中需进行多次弯折，弯折过程中由于应力作用容易产生裂纹。同时由于现有的有机膜层对比无机膜层有更好的应力释放的作用，因此通过在走线空白区域进行挖孔，对挖孔部分进行有机膜层填充，以达到应力释放的作用。由于需保留挖孔结构中有机膜层填充，若对其他区域有机膜层进行去除，将导致填充挖孔区域产生较大的断差在后续金属层覆盖中易发生断线，故使得大面积有机膜层保留在叠层结构中。由此会导致在过孔走线连接位置，由于有机膜层极大增加过孔深度，导致走线过孔金属沉积受阻形貌不够完整，使得过孔金属连接易出现断线,导致Panel在信号传输受到影响，画面显示异常。因此，需要寻找一种新型的显示面板以解决上述问题。
 技术解决方案
本发明的一个目的是提供一种阵列基板及其制备方法、显示面板，其能够解决现有显示面板中存在的有机膜层极大增加过孔深度，导致走线过孔金属沉积受阻形貌不够完整，使得过孔金属连接易出现断线,导致Panel在信号传输受到影响，画面显示异常。
为了解决上述问题，本发明的一个实施方式提供了一种阵列基板，其定义有显示区和弯折区。所述阵列基板包括：基板、阻挡层、绝缘层、导电层以及层间绝缘层。其中所述阻挡层设置于所述基板上；所述绝缘层设置于所述阻挡层上；所述导电层间隔设置于所述绝缘层中；所述层间绝缘层设置于所述导电层上；所述显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽，所述凹槽内填充有机材料形成有机层；所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
进一步的，其中所述阵列基板还包括：缓冲层、有源层、源漏极层以及平坦层。其中所述缓冲层设置于所述阻挡层与所述绝缘层之间，其中所述有机层贯穿所述缓冲层；所述有源层设置于所述缓冲层与所述绝缘层之间；所述源漏极层设置于所述层间绝缘层上；所述源漏极层通过过孔连接于所述有源层上；所述平坦层设置于所述源漏极层上。
进一步的，其中绝缘层包括第一栅极绝缘层和第二栅极绝缘层；所述导电层包括第一栅极层和第二栅极层。其中所述第一栅极绝缘层设置于所述阻挡层上；所述第一栅极层设置于所述第一栅极绝缘层上；所述第二栅极绝缘层设置于所述第一栅极层上；所述第二栅极层设置于所述第二栅极绝缘层上，所述层间绝缘层设置于所述第二栅极层上。
本发明的另一个实施方式还提供了一种制备本发明所涉及的阵列基板的制备方法，其中包括以下步骤：阻挡层制备步骤，将待制备的阵列基板定义出显示区和弯折区，提供一基板，在所述基板上制备阻挡层；绝缘层制备步骤，在所述阻挡层上制备所述绝缘层；导电层制备步骤，在所述绝缘层中间隔设置所述导电层；层间绝缘层制备步骤，在所述导电层上制备所述层间绝缘层；所述显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽；有机层制备步骤，在所述凹槽内填充有机材料形成有机层；其中所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
进一步的，其中所述阵列基板的制备方法还包括：缓冲层制备步骤，在所述阻挡层与所述绝缘层之间制备缓冲层，所述有机层贯穿所述缓冲层；有源层制备步骤，在所述缓冲层与所述绝缘层之间制备有源层；源漏极层制备步骤，在所述层间绝缘层上制备源漏极层，并且所述源漏极层通过过孔连接于所述有源层上；平坦层制备步骤，在所述源漏极层上制备平坦层。
进一步的，其中所述绝缘层制备步骤包括第一栅极绝缘层制备步骤和第二栅极绝缘层制备步骤；所述导电层制备步骤包括第一栅极层制备步骤和第二栅极层制备步骤。其中第一栅极绝缘层制备步骤，在所述阻挡层上制备第一栅极绝缘层；第一栅极层制备步骤，在所述第一栅极绝缘层上制备第一栅极层；第二栅极绝缘层制备步骤，在所述第一栅极层上制备第二栅极绝缘层；第二栅极层制备步骤，在所述第二栅极绝缘层上制备第二栅极层；其中所述层间绝缘层制备于所述第二栅极层上。
进一步的，其中所述有机层制备步骤包括：在所述层间绝缘层上以及凹槽内涂覆填充有机材料，采用半色调掩膜工艺对凹槽处的有机材料进行部分去除形成有机层。
进一步的，其中所述有机层制备步骤还包括：采用曝光工艺将层间绝缘层上的有机材料进行去除，最终达到所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
进一步的，其中所述半色调掩膜工艺的透过率范围为20-45%。
本发明的另一个实施方式还提供了一种显示面板，其包括本发明所涉及的阵列基板。
 有益效果
本发明涉及一种阵列基板及其制备方法、显示面板。一方面，本发明通过在显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽，所述凹槽内填充有机材料形成有机层。由此可以释放阵列基板在多次弯折时产生的应力。另一方面，本发明在不增加新的掩膜板数量的前提下，通过半色调掩膜工艺对凹槽处的有机材料进行部分去除，对显示区的其他区域进行曝光完全去除，对弯折区的有机光阻层的有机材料进行保留，以致所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐，最终达到上层源漏极层设置时无断差，避免其增加过孔深度，导致走线过孔金属沉积受阻形貌不够完整，使得过孔金属连接易出现断线,导致Panel在信号传输受到影响，画面显示异常。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明显示面板的结构示意图。
图2是本发明阵列基板的制备步骤流程图。
图3是本发明阵列基板的制备结构示意图。
图中部件标识如下：
100、显示面板                   101、显示区
102、弯折区                     1、基板
2、阻挡层                       3、缓冲层
4、有源层                       5、第一栅极绝缘层
6、第一栅极层                   7、第二栅极绝缘层
8、第二栅极层                   9、层间绝缘层
10、源漏极层                    11、平坦层
12、阳极                        13、像素定义层
14、发光层                      15、阴极
41、主体部                      42、侧部
16、有机层                      17、第一区域
18、第二区域                    19、第三区域
20、凹槽                        21、有机光阻层
 本发明的实施方式
以下结合说明书附图详细说明本发明的优选实施例，以向本领域中的技术人员完整介绍本发明的技术内容，以举例证明本发明可以实施，使得本发明公开的技术内容更加清楚，使得本领域的技术人员更容易理解如何实施本发明。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例，下文实施例的说明并非用来限制本发明的范围。
本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是附图中的方向，本文所使用的方向用语是用来解释和说明本发明，而不是用来限定本发明的保护范围。
在附图中，结构相同的部件以相同数字标号表示，各处结构或功能相似的组件以相似数字标号表示。此外，为了便于理解和描述，附图所示的每一组件的尺寸和厚度是任意示出的 ，本发明并没有限定每个组件的尺寸和厚度。
当某些组件，被描述为“在”另一组件“上”时，所述组件可以直接置于所述另一组件上；也可以存在一中间组件，所述组件置于所述中间组件上，且所述中间组件置于另一组件上。当一个组件被描述为“安装至”或“连接至”另一组件时，二者可以理解为直接“安装”或“连接”，或者一个组件通过一中间组件“安装至”或“连接至”另一个组件。
实施例1
如图1所示，一种显示面板100，其定义有显示区101和弯折区102。所述显示面板100包括阵列基板。其中所述阵列基板包括：基板1、阻挡层2、缓冲层3、有源层4、第一栅极绝缘层5、第一栅极层6、第二栅极绝缘层7、第二栅极层8、层间绝缘层9、源漏极层10以及平坦层11。其中所述显示面板100还包括：阳极12、像素定义层13、发光层14以及阴极15。
其中所述基板1可以包括第一衬底、中间层以及第二衬底。其中所述第一衬底与所述第二衬底的组成材料可以选择聚酰亚胺，由此制成的所述第一衬底与所述第二衬底柔韧性好。其中所述中间层的组成材料可以是SiO2也可以是SiNx，还可以是SiO2与SiNx的叠层结构，由此制备的所述中间层阻水氧性能好，还可以提高第一衬底与第二衬底之间的信耐性。
如图1所示，其中所述阻挡层2设置于所述基板1上，主要是起阻水氧作用。
如图1所示，所述缓冲层3设置于所述阻挡层2上，主要是充当缓冲及保护作用。
如图1所示，其中所述有源层4设置于所述显示区101的缓冲层3上。所述有源层4包括主体部41和两个侧部42。具体的，本实施例中主要是利用准分子激光晶化技术实现有源层4的多晶硅化，然后通过PR光罩对有源层4进行图案化处理，形成主体部41和两个侧部42，最后通过一道PR光罩多有源层4的两个侧部42进行离子掺杂处理形成P型半导体。
如图1所示，所述第一栅极绝缘层5设置于所述有源层4上；所述第一栅极层6设置于所述第一栅极绝缘层5上；所述第二栅极绝缘层7设置于所述第一栅极层6上；所述第二栅极层8设置于所述第二栅极绝缘层7上；其中所述层间绝缘层9设置于所述第二栅极层8上；所述源漏极层10设置于所述层间绝缘层9上；所述源漏极层10通过过孔连接于所述有源层4上，具体的，所述源漏极层10通过过孔连接于所述有源层4的两个侧部42上；所述平坦层11设置于所述源漏极层10上。
如图1所示，其中所述阳极12相互间隔设置于所述平坦层11上；所述像素定义层13设置于相邻所述阳极12之间的所述平坦层11上；所述发光层14设置于所述阳极13上；所述阴极15设置于所述发光层14上。
如图1所示，本实施例的所述显示区101的层间绝缘层9远离所述基板1的表面向下凹陷直至所述阻挡层2形成凹槽20，所述凹槽20内填充有机材料形成有机层16。由此可以通过有机材料组成的有机层释放阵列基板在多次弯折时产生的应力。并且本实施例中所述有机层16只形成于凹槽20处，去除了显示区101的其他区域的有机材料，避免增加源漏极层10走线过孔处深度，导致过孔金属沉积受阻形貌不够完整，使得过孔金属连接易出现断线,导致Panel在信号传输受到影响，画面显示异常等现象。
如图1所示，所述有机层16远离所述基板1的表面与所述层间绝缘层9远离所述基板1的表面平齐。由此可以避免凹槽20处有机层16与层间绝缘层9存在断差，从而避免导致后续走线发生断线，影响画面显示。
实施例2
如图1、图2所示，本实施方式提供了一种制备本发明所涉及的阵列基板的制备方法，其中包括以下步骤：步骤S1，阻挡层2制备步骤，将待制备的阵列基板定义出显示区101和弯折区102，提供一基板1，在所述基板1上制备阻挡层2；步骤S2，缓冲层3制备步骤，在所述阻挡层2上制备缓冲层3；步骤S3，有源层4制备步骤，在所述缓冲层3上制备有源层4；步骤S4，第一栅极绝缘层5制备步骤，在所述有源层4上制备第一栅极绝缘层5；步骤S5，第一栅极层6制备步骤，在所述第一栅极绝缘层5上制备第一栅极层6；步骤S6，第二栅极绝缘层7制备步骤，在所述第一栅极层6上制备第二栅极绝缘层7；步骤S7，第二栅极层8制备步骤，在所述第二栅极绝缘层7上制备第二栅极层8；步骤S8，层间绝缘层9制备步骤，在所述第二栅极层8上制备所述层间绝缘层9；所述显示区101的层间绝缘层9远离所述基板1的表面向下凹陷直至所述阻挡层2形成凹槽20；步骤S9，有机层16制备步骤，在所述凹槽20内填充有机材料形成有机层16；其中所述有机层16远离所述基板1的表面与所述层间绝缘层9远离所述基板1的表面平齐；步骤S10，源漏极层10制备步骤，在所述层间绝缘层9上制备源漏极层10，并且所述源漏极层10通过过孔连接于所述有源层4上；步骤S11，平坦层11制备步骤，在所述源漏极层10上制备平坦层11。
如图3所示，其中所述有机层16制备步骤包括：在所述层间绝缘层9上以及凹槽内涂覆填充有机材料，后采用掩膜板对其进行曝光去除。其中所述掩膜板包括对应于凹槽20处的第一区域17、对应于弯折区102中的有机光阻层21的第二区域18以及第三区域19。其中第一区域17采用半色调掩膜工艺对凹槽20处的有机材料进行部分去除形成有机层16。其中第三区域19采用曝光工艺将层间绝缘层9上的有机材料进行完全去除。以此避免在非凹槽20处的有机材料保留导致走线过孔深度加深，导致走线过孔金属沉积受阻形貌不够完整，使得过孔金属连接易出现断线,导致Panel在信号传输受到影响，画面显示异常。同时保留了凹槽20处的有机材料形成有机层16，可以释放阵列基板多次弯折时产生的压力。其中所述第二区域18采用普通的掩膜工艺，保留此处的有机光阻层21中的有机材料。其中所述凹槽处的半掩膜板工艺与弯折区102中的有机光阻层21制备时采用的掩膜板工艺同时进行，因此在不增加掩膜板数量的情况下实现了弯折区102的有机光阻层21的制备，以及凹槽20处的有机材料的部分去除和非凹槽处的有机材料的完全去除。
其中所述半色调掩膜工艺的透过率范围为20-45%，以此可以最终达到所述有机层16远离所述基板1的表面与所述层间绝缘层9远离所述基板1的表面平齐。以此可以避免凹槽处有机层16与层间绝缘层9存在断差，从而避免导致后续走线发生断线，影响画面显示。
其中所述有机材料可以通过蒸镀或沉积的方式填充于所述凹槽内。
以上对本发明所提供的阵列基板及其制备方法、显示面板进行了详细介绍。应理解，本文所述的示例性实施方式应仅被认为是描述性的，用于帮助理解本发明的方法及其核心思想，而并不用于限制本发明。在每个示例性实施方式中对特征或方面的描述通常应被视作适用于其他示例性实施例中的类似特征或方面。尽管参考示例性实施例描述了本发明，但可建议所属领域的技术人员进行各种变化和更改。本发明意图涵盖所附权利要求书的范围内的这些变化和更改，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (12)

  1. 一种阵列基板，其定义有显示区和弯折区，其中包括：
    基板；
    阻挡层，所述阻挡层设置于所述基板上；
    绝缘层，所述绝缘层设置于所述阻挡层上；
    导电层，所述导电层间隔设置于所述绝缘层中；
    层间绝缘层，所述层间绝缘层设置于所述导电层上；
    所述显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽，所述凹槽内填充有机材料形成有机层；
    所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
  2. 根据权利要求1所述的阵列基板，其中还包括：
    缓冲层，所述缓冲层设置于所述阻挡层与所述绝缘层之间，其中所述有机层贯穿所述缓冲层；
    有源层，所述有源层设置于所述缓冲层与所述绝缘层之间；
    源漏极层，所述源漏极层设置于所述层间绝缘层上；所述源漏极层通过过孔连接于所述有源层上；以及
    平坦层，所述平坦层设置于所述源漏极层上。
  3. 根据权利要求1所述的阵列基板，其中所述绝缘层包括第一栅极绝缘层和第二栅极绝缘层；所述导电层包括第一栅极层和第二栅极层；
    所述第一栅极绝缘层设置于所述阻挡层上；所述第一栅极层设置于所述第一栅极绝缘层上；所述第二栅极绝缘层设置于所述第一栅极层上；所述第二栅极层设置于所述第二栅极绝缘层上，所述层间绝缘层设置于所述第二栅极层上。
  4. 一种制备权利要求1所述的阵列基板的制备方法，其中包括以下步骤：
    阻挡层制备步骤，将待制备的阵列基板定义出显示区和弯折区，提供一基板，在所述基板上制备阻挡层；
    绝缘层制备步骤，在所述阻挡层上制备所述绝缘层；
    导电层制备步骤，在所述绝缘层中间隔设置所述导电层；
    层间绝缘层制备步骤，在所述导电层上制备所述层间绝缘层；所述显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽；
    有机层制备步骤，在所述凹槽内填充有机材料形成有机层；
    其中所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
  5. 根据权利要求4所述的阵列基板的制备方法，其中还包括：
    缓冲层制备步骤，在所述阻挡层与所述绝缘层之间制备缓冲层，所述有机层贯穿所述缓冲层；
    有源层制备步骤，在所述缓冲层与所述绝缘层之间制备有源层；
    源漏极层制备步骤，在所述层间绝缘层上制备源漏极层，并且所述源漏极层通过过孔连接于所述有源层上；
    平坦层制备步骤，在所述源漏极层上制备平坦层。
  6. 根据权利要求4所述的阵列基板的制备方法，其中所述绝缘层制备步骤包括第一栅极绝缘层制备步骤和第二栅极绝缘层制备步骤；所述导电层制备步骤包括第一栅极层制备步骤和第二栅极层制备步骤；
    第一栅极绝缘层制备步骤，在所述阻挡层上制备第一栅极绝缘层；
    第一栅极层制备步骤，在所述第一栅极绝缘层上制备第一栅极层；
    第二栅极绝缘层制备步骤，在所述第一栅极层上制备第二栅极绝缘层；
    第二栅极层制备步骤，在所述第二栅极绝缘层上制备第二栅极层；
    其中所述层间绝缘层制备于所述第二栅极层上。
  7. 根据权利要求4所述的阵列基板的制备方法，其中所述有机层制备步骤包括：在所述层间绝缘层上以及凹槽内涂覆填充有机材料，采用半色调掩膜工艺对凹槽处的有机材料进行部分去除形成有机层。
  8. 根据权利要求7所述的阵列基板的制备方法，其中所述有机层制备步骤还包括：采用曝光工艺将层间绝缘层上的有机材料进行去除，最终达到所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
  9. 根据权利要求7所述的阵列基板的制备方法，其中所述半色调掩膜工艺的透过率范围为20-45%。
  10. 一种显示面板，其中包括权利要求1所述的阵列基板，所述阵列基板定义有显示区和弯折区，所述阵列基板包括：
    基板；
    阻挡层，所述阻挡层设置于所述基板上；
    绝缘层，所述绝缘层设置于所述阻挡层上；
    导电层，所述导电层间隔设置于所述绝缘层中；
    层间绝缘层，所述层间绝缘层设置于所述导电层上；
    所述显示区的层间绝缘层远离所述基板的表面向下凹陷直至所述阻挡层形成凹槽，所述凹槽内填充有机材料形成有机层；
    所述有机层远离所述基板的表面与所述层间绝缘层远离所述基板的表面平齐。
  11. 根据权利要求10所述的显示面板，所述阵列基板还包括：
    缓冲层，所述缓冲层设置于所述阻挡层与所述绝缘层之间，其中所述有机层贯穿所述缓冲层；
    有源层，所述有源层设置于所述缓冲层与所述绝缘层之间；
    源漏极层，所述源漏极层设置于所述层间绝缘层上；所述源漏极层通过过孔连接于所述有源层上；以及
    平坦层，所述平坦层设置于所述源漏极层上。
  12. 根据权利要求10所述的显示面板，其中所述绝缘层包括第一栅极绝缘层和第二栅极绝缘层；所述导电层包括第一栅极层和第二栅极层；
    所述第一栅极绝缘层设置于所述阻挡层上；所述第一栅极层设置于所述第一栅极绝缘层上；所述第二栅极绝缘层设置于所述第一栅极层上；所述第二栅极层设置于所述第二栅极绝缘层上，所述层间绝缘层设置于所述第二栅极层上。
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