WO2021110872A1 - Tape for electrical circuits with rose-gold contact pads and method for manufacturing such a tape - Google Patents
Tape for electrical circuits with rose-gold contact pads and method for manufacturing such a tape Download PDFInfo
- Publication number
- WO2021110872A1 WO2021110872A1 PCT/EP2020/084537 EP2020084537W WO2021110872A1 WO 2021110872 A1 WO2021110872 A1 WO 2021110872A1 EP 2020084537 W EP2020084537 W EP 2020084537W WO 2021110872 A1 WO2021110872 A1 WO 2021110872A1
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- Prior art keywords
- layer
- gold
- copper
- copper alloy
- tape
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/02—Local etching
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/56—Electroplating: Baths therefor from solutions of alloys
- C25D3/62—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of gold
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
- C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/54—Electroplating of non-metallic surfaces
- C25D5/56—Electroplating of non-metallic surfaces of plastics
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/627—Electroplating characterised by the visual appearance of the layers, e.g. colour, brightness or mat appearance
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07718—Constructional details, e.g. mounting of circuits in the carrier the record carrier being manufactured in a continuous process, e.g. using endless rolls
Definitions
- the invention relates to electrical circuits with contact pads.
- electrical circuits are used for manufacturing modules for smart-cards, such modules comprising electrical contact pads designed to be connected to the connector of a smart-card reader (Such smart-cards are for example used for banking applications and identification documents).
- Connector modules for smart-cards comprise a dielectric substrate supporting electrical contact pads (see for example the document W02019051712A1).
- the electrical contact pads are etched in a conductive layer supported by a flexible dielectric substrate (e.g. by photolithography and etching technologies)
- the electrical contact pads are cut out in a conductive layer prior to be co-laminated on a flexible dielectric substrate (e.g. by a lead-frame technology).
- contacts pads supported by a dielectric substate are produced as a flexible tape.
- this kind of flexible tapes with electrical circuits can be used for manufacturing the electrical contacts of connectors for memory keys or disks, etc.
- the electrical circuits produced in connection with the field of the invention are of particular interest when they are intended to be at least partially visible during their everyday use.
- An aim of the invention is to obtain electrical circuits comprising conductive tracks or pads, having a Rose-Gold color, visible on the finished product, while retaining, in particular during many connection and disconnection cycles, electrical and mechanical properties suitable for their use as contacts intended to be electrically connected with a connector.
- FIG. 1 schematically shows in perspective a smart card comprising an example of a module with an electrical circuit manufactured from a tape according to the invention
- FIG. 2 schematically shows a top view of a portion of a tape according to the invention
- FIG. 3 shows schematically in section, an example of stacked layers as can be obtained with the method according to the invention
- FIG. 4a] to [Fig. 4k] schematically represent steps of an example of implementation of the method according to the invention. Detailed Description
- a smart card 1 comprises for example a module 2 with a connector 3.
- the module 2 is generally made in the form of a separate element cut out from a tape. This element is inserted into a cavity formed in the card 1 .
- This element comprises a generally flexible substrate 4 (see FIG. 2) of PET, glass-epoxy, etc. on which is made the connector 3, to which is subsequently connected a chip (not shown).
- Fig. 2 illustrates an example of an electrical circuit portion.
- This electrical circuit portion is a printed circuit 5, with six connectors 3.
- Each connector 3 comprises eight electrical contact pads 6 (a connector 3 is essentially a module 2 without a chip, without the connections between the chip and the contact pads 6, and without an encapsulation resin for protecting the chip and the connections).
- the contact pads 6 are cutout (e.g. punched or etched) from an electrically conductive sheet 10.
- Figure 3 A schematic cross-section of an example of a multilayer structure forming a tape for manufacturing the connector 3 is shown in Figure 3.
- This multilayer structure comprises the substrate 4, an adhesive layer 9, the electrically conductive sheet 10 (made of copper or of a copper alloy for example), and a stack of more or less numerous layers A, B, and / or C, as well as a gold-copper layer 13.
- the electrically conductive sheet 10 has an internal face 18 facing the dielectric substrate 4 and an external face 19 opposite this internal face 18. More particularly, the electrically conductive sheet 10 has an internal face 18 attached to (e.g. glued with an adhesive layer or laminated) the dielectric substrate 4 The internal face 18 appears at the bottom of blind holes 14. Blind holes 14 are intended to establish an electrical connection with a chip (for example connected with a wire bonding technique) possibly housed in a cavity 15.
- the external face 19 corresponds to the contact surfaces intended to establish an electrical connection with another connector.
- the layers deposited A, B, C on the internal 18 and external 19 faces are not necessarily of the same type and of the same thickness.
- the presence of a shiny layer underneath (underneath not necessarily meaning directly below, in contact, with the gold-copper alloy layer 13) the gold-copper alloy layer 13 results in an upper surface with a brighter appearance and a more intense pink color.
- This shiny underlayer can be obtained for example by electroplating copper and/or nickel and/or a nickel alloy on the electrically conductive sheet 10, which may already be made of copper or a copper alloy.
- the shiny appearance can be obtained by polishing and/or electropolishing processes carried out on at least one underlying layer chosen from the list comprising copper, nickel, nickel alloy and copper-tin alloy.
- the electrically conductive sheet 10 is a copper sheet.
- An electroplated layer A of copper is deposited on at least a portion of the free surface of the copper sheet (the other surface being attached to the dielectric substrate).
- This electroplated layer A of copper allows reducing the roughness of the surface of the pads in the finished product (that is the free surface of the layer of copper-gold alloy). For example, this roughness is equal or close to 0.45 ⁇ 0.15 micrometers (Rz measurement). Without the electrodeposited lectroplated layer A of copper, the roughness of the top surface is equal or close to 0.90 ⁇ 0.20 micrometers (Rz measurement).
- a shiny layer deposited underneath the layer of copper-gold alloy divides by 2, as an average, the roughness of the free surface of the layer of copper-gold alloy. This allows obtaining a semi-bright finishing on the pad surface, instead of a matt finishing without underlying shiny layer (underlying not meaning directly below, in contact, with the gold-copper alloy layer 13).
- the gold layer C is optional. When deposited, the gold layer C is in the form of a "flash", that is to say electrodeposited with a thickness between 0 nanometers and 15 nanometers.
- a thin gold layer C is advantageously deposited onto the internal face 18, in the blind holes 14, prior to the deposition of the gold-copper alloy layer 13 so as to-increase the pull strength of wires bonded onto this internal face 18.
- Figures 4a to 4k schematically illustrate the steps of an example of method for manufacturing a tape as shown in Fig. 2.
- steps which can be carried out through a reel-to-reel process, include:
- the dielectric substrate is made of epoxy-glass, or polyimide, or PET, etc.;
- this electrodeposition can be carried out in one or more steps to form a stack of layers as described above in connection with Figure 3; for example, this stack comprises a nickel layer 11 and a gold layer 12 (FIG. 4j); for instance, a nickel layerl 1 is deposited with a thickness of 2 micrometers on the external face 19 and with a thickness of 5 micrometers on the internal face 18; and a gold layer 12 is deposited with a thickness of less than 15 nanometers on the external face 19 and with a thickness of 0.3 micrometers on the internal face 18;
- the copper-gold layer 13 is deposited with a thickness of 0.1 micrometers or more, on the external face 19; for instance the copper content in the layer 13 of gold-copper alloy is less than 40% Wt (by weight), preferentially it is less than, or equal to, 35% Wt more preferentially it is less than, or equal to, 30% Wt, for example it is between 10 and 20% Wt.
- the internal face 18 can be protected, for example by selective masking, during at least the deposition of the copper-gold layer 13 (that is to say, the face intended not to be visible on the finished product in not covered by the copper-gold layer 13). Only a layer of gold 12 and / or a layer 11 of nickel and / or of another alloy cover the internal face 18 in the blind holes 14. Therefore, the packaging process remains unchanged for connecting the chip compared to standard processes.
- the electrodeposition of the gold-copper layer 13 to form a Rose-Gold surface layer is to be carried out by a specific deposition of a two components alloy, with plating baths of electrolyte containing: o
- a cyanide complex of gold for instance the cyanide complex of gold is KAU(CN)2 or KAu(CN) .
- o A cyanide complex of copper for instance the cyanide complex of copper is K3Cu(CN)4.
- the gold concentration in the plating bath is comprised between 0.6 and 1.0 gram per liter and the copper concentration in the plating bath is comprised between 0.6 and 0.8 gram per liter.
- the bath has a pH comprised between 11 and 13.
- the temperature of the bath is controlled between 50 and 60°C.
- the current density and the speed of the tape in the plating baths are adjusted as a function of the available lengths of the plating cells in order to obtain the targeted thicknesses, knowing that the cathodic yield is of the order of 5 to 15 mg / minute.
- the electro-deposition bath during the copper-gold alloy deposition, does not comprise any other metallic compound (based on zinc, nickel, silver, or other).
- Colors of gold are usually calibrated according to the Swiss standard"1-5N", which ranges from specific pale yellow to pink gold alloys.
- the process disclosed above makes it possible to obtain a pink color outside of this range, i.e. a color which would be 5N++ (i.e. a more intense pink color).
- the whole surface of the contact pads 6 is Rose-Gold colored.
- using mask and/or etching techniques make possible to color only a portion for this surface (e.g. for logos).
- the pink color obtained with the process according to the invention for a layer structure corresponding to the second line of the table above has the following colorimetric parameters:
- the visual aspect of the gold-copper layer 13 after the climatic tests mentioned in the table above can be improved with a top surface protection.
- a top surface protection can be obtained through the immersion of the metallic surface into a solution containing a thiol compound (1-dodecanethiol for example).
- a lead-frame technology can be implemented for manufacturing a tape. Then, the gold-copper layer 13 can be plated on a conductive layer 10, prior or after the co-lamination of the conductive layer 10 with the dielectric substrate 4.
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- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Electrochemistry (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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Abstract
A tape for manufacturing an electrical circuit with electrical contact pads, comprising: - a flexible dielectric substrate (4), - a copper foil (10) covering at least partially the dielectric substrate (4), the copper foil (10) having an internal face (18) facing the dielectric substrate (4), and an external face (19) opposite the internal face (18), - an intermediate layer comprising at least a nickel-based layer covering at least partially the external face (19) of the copper foil (10), A gold-copper alloy layer (13) is deposited on the intermediate layer. A method for manufacturing an electrical circuit, comprising providing a tape with conductive pads, and plating pads with a layer of gold-copper alloy electro-deposited from an electro-deposition solution.
Description
Tape for electrical circuits with Rose-Gold contact pads and method for manufacturing such a tape
Technical domain The invention relates to electrical circuits with contact pads. For example, such electrical circuits are used for manufacturing modules for smart-cards, such modules comprising electrical contact pads designed to be connected to the connector of a smart-card reader (Such smart-cards are for example used for banking applications and identification documents). State of the art
Connector modules for smart-cards comprise a dielectric substrate supporting electrical contact pads (see for example the document W02019051712A1). The electrical contact pads are etched in a conductive layer supported by a flexible dielectric substrate (e.g. by photolithography and etching technologies) Alternatively, the electrical contact pads are cut out in a conductive layer prior to be co-laminated on a flexible dielectric substrate (e.g. by a lead-frame technology). In both cases, contacts pads supported by a dielectric substate are produced as a flexible tape. More generally, this kind of flexible tapes with electrical circuits can be used for manufacturing the electrical contacts of connectors for memory keys or disks, etc. Thus, the electrical circuits produced in connection with the field of the invention are of particular interest when they are intended to be at least partially visible during their everyday use.
The invention is illustrated below in using the example of electrical circuits intended to form contacts of smart-card connectors, but this example should not be understood as being restrictive, since in general, the deposition process described below can be applied to any type of metallic conductive support.
In the smart-card domain, card manufacturers wish to match the color of card bodies with the color of the card modules. For example, for aesthetic and/or customization purposes, it would be suitable to have electrical contact pads having a so-called “Rose Gold” color (i.e. pink-gold color) on the visible face of the module. However, producing the electrical contact pads with a new color must not call into question
their quality, for example, in terms of electrical contact resistance, resistance to climatic tests, resistance to corrosion, resistance to weariness, etc. The colored contacts must meet the requirements of the standards and specifications in force for the intended application. An aim of the invention is to obtain electrical circuits comprising conductive tracks or pads, having a Rose-Gold color, visible on the finished product, while retaining, in particular during many connection and disconnection cycles, electrical and mechanical properties suitable for their use as contacts intended to be electrically connected with a connector.
Summary of the invention
This aim is at least partially achieved with a tape according to claim 1 and a method according to claim 12. Other features, that shall be considered independently of one another or in combination of one or more others, of this tape and of this method are presented in the dependent claims.
In order to provide the electric contact pads with a “Rose Gold” color, compatible with demanding specifications in terms of electrical contact resistance, resistance to climatic tests, resistance to corrosion, resistance to weariness, etc., they are covered with at least one metallic layer composed of a gold-copper alloy with a specific copper concentration and a particular thickness, deposited with the help of an electrodeposition process.
Brief description of the drawings
Other characteristics, purposes and advantages of the above-mentioned tape and method will appear on reading the detailed description which follows, and with reference to the appended drawings, given by way of non-limiting examples and in which:
[Fig. 1] schematically shows in perspective a smart card comprising an example of a module with an electrical circuit manufactured from a tape according to the invention; [Fig. 2] schematically shows a top view of a portion of a tape according to the invention;
[Fig. 3] shows schematically in section, an example of stacked layers as can be obtained with the method according to the invention;
[Fig. 4a] to [Fig. 4k] schematically represent steps of an example of implementation of the method according to the invention. Detailed Description
An example of disclosure of an electrical circuit manufactured from a tape according to the invention is described below. This example is taken in the field of the smart card, but the person skilled in the art will be able, without involving inventiveness, to transpose this example to other applications of electrical circuits. In particular, the invention is particularly advantageous in all cases where the use of pink colored conductive contacts or tracks can bring aesthetic added value (e.g. for connectors of SD memory cards or for connectors of USB keys).
As illustrated in Fig. 1 , a smart card 1 comprises for example a module 2 with a connector 3. The module 2 is generally made in the form of a separate element cut out from a tape. This element is inserted into a cavity formed in the card 1 . This element comprises a generally flexible substrate 4 (see FIG. 2) of PET, glass-epoxy, etc. on which is made the connector 3, to which is subsequently connected a chip (not shown).
Fig. 2 illustrates an example of an electrical circuit portion. This electrical circuit portion is a printed circuit 5, with six connectors 3. Each connector 3 comprises eight electrical contact pads 6 (a connector 3 is essentially a module 2 without a chip, without the connections between the chip and the contact pads 6, and without an encapsulation resin for protecting the chip and the connections). The contact pads 6 are cutout (e.g. punched or etched) from an electrically conductive sheet 10. A schematic cross-section of an example of a multilayer structure forming a tape for manufacturing the connector 3 is shown in Figure 3. This multilayer structure comprises the substrate 4, an adhesive layer 9, the electrically conductive sheet 10 (made of copper or of a copper alloy for example), and a stack of more or less numerous layers A, B, and / or C, as well as a gold-copper layer 13. The electrically conductive sheet 10 has an internal face 18 facing the dielectric substrate 4 and an external face 19 opposite this internal face 18. More particularly,
the electrically conductive sheet 10 has an internal face 18 attached to (e.g. glued with an adhesive layer or laminated) the dielectric substrate 4 The internal face 18 appears at the bottom of blind holes 14. Blind holes 14 are intended to establish an electrical connection with a chip (for example connected with a wire bonding technique) possibly housed in a cavity 15. The external face 19 corresponds to the contact surfaces intended to establish an electrical connection with another connector. The layers deposited A, B, C on the internal 18 and external 19 faces are not necessarily of the same type and of the same thickness.
The presence of a shiny layer underneath (underneath not necessarily meaning directly below, in contact, with the gold-copper alloy layer 13) the gold-copper alloy layer 13 results in an upper surface with a brighter appearance and a more intense pink color. This shiny underlayer can be obtained for example by electroplating copper and/or nickel and/or a nickel alloy on the electrically conductive sheet 10, which may already be made of copper or a copper alloy. Alternatively, the shiny appearance can be obtained by polishing and/or electropolishing processes carried out on at least one underlying layer chosen from the list comprising copper, nickel, nickel alloy and copper-tin alloy. For example, with a process according to the sixth line of the above table, the electrically conductive sheet 10 is a copper sheet. An electroplated layer A of copper
is deposited on at least a portion of the free surface of the copper sheet (the other surface being attached to the dielectric substrate). This electroplated layer A of copper allows reducing the roughness of the surface of the pads in the finished product (that is the free surface of the layer of copper-gold alloy). For example, this roughness is equal or close to 0.45 ± 0.15 micrometers (Rz measurement). Without the electrodeposited lectroplated layer A of copper, the roughness of the top surface is equal or close to 0.90 ± 0.20 micrometers (Rz measurement).
A shiny layer deposited underneath the layer of copper-gold alloy divides by 2, as an average, the roughness of the free surface of the layer of copper-gold alloy. This allows obtaining a semi-bright finishing on the pad surface, instead of a matt finishing without underlying shiny layer (underlying not meaning directly below, in contact, with the gold-copper alloy layer 13).
The gold layer C is optional. When deposited, the gold layer C is in the form of a "flash", that is to say electrodeposited with a thickness between 0 nanometers and 15 nanometers.
When it is not envisaged to carry out a selective masking of the internal face 18, in particular when depositing the gold-copper alloy layer 13, a thin gold layer C is advantageously deposited onto the internal face 18, in the blind holes 14, prior to the deposition of the gold-copper alloy layer 13 so as to-increase the pull strength of wires bonded onto this internal face 18.
Figures 4a to 4k schematically illustrate the steps of an example of method for manufacturing a tape as shown in Fig. 2.
These steps, which can be carried out through a reel-to-reel process, include:
- providing a dielectric substrate 4 (Fig. 4a), for instance the dielectric substrate is made of epoxy-glass, or polyimide, or PET, etc.;
- coating a face of the substrate 4 with an adhesive layer 9 (FIG. 4b);
- punching the substrate 4 with the adhesive layer 9 so as to make holes 14 and possibly a cavity 15 in which a chip can be accommodated at a later stage (FIG. 4c);
- Co-laminating the substrate 4 provided with the adhesive layer 9 with a sheet of electrically conductive material 10 (such as a copper sheet for example), heating
the complex thus obtained to achieve a thermal crosslinking of the adhesive layer 9, and deoxidizing the complex thus obtained (Fig. 4d); holes 14 are now blind holes 14;
- laminating a dry photosensitive film 16 (Fig. 4e) on the external face 19 of the electrically conductive sheet 10;
- exposing the photosensitive film 16 through a mask (Fig. 4f),
- developing photosensitive film 16 (Fig. 4g);
- etching of the electrically conductive sheet 10 in the areas not protected by the photosensitive film 16, to define conductive tracks and / or contact pads 6 (FIG. 4h),
- removing the photosensitive film 16 (Fig. 4i);
- electrodepositing conductive layers over at least some of the tracks and / or of some of the contact pads 6 obtained after etching the electrically conductive sheet 10; this electrodeposition can be carried out in one or more steps to form a stack of layers as described above in connection with Figure 3; for example, this stack comprises a nickel layer 11 and a gold layer 12 (FIG. 4j); for instance, a nickel layerl 1 is deposited with a thickness of 2 micrometers on the external face 19 and with a thickness of 5 micrometers on the internal face 18; and a gold layer 12 is deposited with a thickness of less than 15 nanometers on the external face 19 and with a thickness of 0.3 micrometers on the internal face 18;
- electrodepositing a gold-copper layer 13 to form a surface layer having a gold-pink color (FIG. 4k); for instance, the copper-gold layer 13 is deposited with a thickness of 0.1 micrometers or more, on the external face 19; for instance the copper content in the layer 13 of gold-copper alloy is less than 40% Wt (by weight), preferentially it is less than, or equal to, 35% Wt more preferentially it is less than, or equal to, 30% Wt, for example it is between 10 and 20% Wt.
The internal face 18 can be protected, for example by selective masking, during at least the deposition of the copper-gold layer 13 (that is to say, the face intended not to be visible on the finished product in not covered by the copper-gold layer 13). Only a layer of gold 12 and / or a layer 11 of nickel and / or of another alloy cover the internal face 18 in the blind holes 14. Therefore, the packaging process remains unchanged for connecting the chip compared to standard processes.
The electrodeposition of the gold-copper layer 13 to form a Rose-Gold surface layer is to be carried out by a specific deposition of a two components alloy, with plating baths of electrolyte containing: o A cyanide complex of gold, for instance the cyanide complex of gold is KAU(CN)2 or KAu(CN) . o A cyanide complex of copper, for instance the cyanide complex of copper is K3Cu(CN)4.
For example, the gold concentration in the plating bath is comprised between 0.6 and 1.0 gram per liter and the copper concentration in the plating bath is comprised between 0.6 and 0.8 gram per liter. The bath has a pH comprised between 11 and 13. The temperature of the bath is controlled between 50 and 60°C. The current density and the speed of the tape in the plating baths are adjusted as a function of the available lengths of the plating cells in order to obtain the targeted thicknesses, knowing that the cathodic yield is of the order of 5 to 15 mg / minute. Advantageously, the electro-deposition bath, during the copper-gold alloy deposition, does not comprise any other metallic compound (based on zinc, nickel, silver, or other).
Colors of gold are usually calibrated according to the Swiss standard"1-5N", which ranges from specific pale yellow to pink gold alloys. The process disclosed above makes it possible to obtain a pink color outside of this range, i.e. a color which would be 5N++ (i.e. a more intense pink color). The whole surface of the contact pads 6 is Rose-Gold colored. Alternatively, using mask and/or etching techniques make possible to color only a portion for this surface (e.g. for logos).
For example, the pink color obtained with the process according to the invention for a layer structure corresponding to the second line of the table above (Copper sheet 10/ Nickel/Nickel alloy/gold (flash)/copper-gold alloy), has the following colorimetric parameters:
- L* = 63±1 ,
- a*= 7.1 ±0.3, and
- b*= 6.9±0.3.
Further, the visual aspect of the gold-copper layer 13 after the climatic tests mentioned in the table above can be improved with a top surface protection. For
instance, such protection can be obtained through the immersion of the metallic surface into a solution containing a thiol compound (1-dodecanethiol for example). Alternatively to the method described above, a lead-frame technology can be implemented for manufacturing a tape. Then, the gold-copper layer 13 can be plated on a conductive layer 10, prior or after the co-lamination of the conductive layer 10 with the dielectric substrate 4.
Claims
1. A tape for manufacturing an electrical circuit (5) with electrical contact pads (6), comprising:
- a flexible dielectric substrate (4), - a copper foil (10) covering at least partially the dielectric substrate (4) and comprising electrical contact pads (6) cutout in the copper foil (10), the copper foil (10) having an internal face (18) attached to the dielectric substrate (4), and an external face (19) opposite the internal face (18),
- an intermediate layer comprising at least a nickel-based layer (11) covering at least partially the external face (19) of the copper foil (10), characterized in that a gold-copper alloy layer (13) is deposited on the intermediate layer, and in that the intermediate layer comprises a thin gold layer (12) having a thickness less or equal to 15 nanometers, and covering at least partially the nickel- based layer (11), the gold-copper alloy layer (13) being deposited on top of this thin gold layer (12), the copper content in the gold-copper alloy layer (13) being greater than 10% Wt.
2. A tape according to claim 1 , wherein the copper content in the gold-copper alloy layer (13) is less than 40% Wt.
3. A tape according to claim 2, wherein the copper content in the gold-copper alloy layer (13) is less than 30% Wt.
4. A tape according to claim 3, wherein the copper content in the gold-copper alloy layer (13) is less than 20% Wt.
5. A tape according to any one of the preceding claims, wherein the layer of gold- copper alloy layer (13) has a thickness greater or equal to 0.1 micrometer.
6. A tape according to any one of the preceding claims, comprising blind holes (14) formed by the copper foil (10) at least partially covering holes made through the
dielectric substrate (4), these blind holes (14) having a bottom surface, corresponding to the internal face (18) of the copper foil (10), this bottom surface being not covered by a gold-copper alloy layer (13).
7. A tape according to any one of claims 1 to 5, comprising blind holes (14) formed by the copper foil (10) at least partially covering holes made through the dielectric substrate (4), these blind holes (14) having a bottom surface, corresponding to the internal face (18) of the copper foil (10), this bottom surface being covered by several layers comprising at least a thin gold layer and a gold-copper alloy layer (13), the gold-copper alloy layer (13) being deposited on the thin gold layer, the thin gold layer having a thickness less or equal to 15 nanometers.
8. A tape according to any one of the preceding claims, wherein the gold-copper alloy layer (13) is at least partially covered by a protection layer comprising a thiol compound.
9. A tape according to any one of the preceding claims, comprising a shiny layer underneath the gold-copper alloy layer (13).
10. A tape according to claim 9, wherein the shiny layer is an electroplated layer of a metal selected in the list consisting of copper, nickel and nickel alloy.
11. A tape according to claim 9, wherein the shiny layer is the copper foil (10) that is polished or electropolished.
12. A method for manufacturing an electrical circuit (5), comprising
- providing a tape comprising a flexible dielectric substrate (4) supporting electrically conductive pads (6), and
- plating the pads (6) with an intermediate layer comprising at least a nickel-based layer (11),
characterized in that it further comprises electro-depositing on the intermediate layer, from an electro-deposition solution, a layer (13) of gold-copper alloy, the intermediate layer comprising a thin gold layer (12) having a thickness less or equal to 15 nanometers, and covering at least partially the nickel-based layer (11), the gold-copper alloy layer (13) being deposited on top of this thin gold layer (12), and the copper content in the gold-copper alloy layer (13) being greater than 10% Wt.
13. A method according to claim 12, wherein said electro-deposition solution comprises a gold cyanide complex and a copper cyanide complex.
14. A method according to claim 12, wherein said electro-deposition solution does not comprise a cyanide compound.
15. A method according to claim 12 to 14, comprising electroplating a shiny layer made of a metal selected in the list consisting of copper, nickel and nickel alloy, underneath the gold-copper alloy layer (13).
16. A method according to claim 12 to 14, comprising polishing or electropolishing the copper foil from which are made the electrically conductive pads (6), prior to the electro-deposition of the gold-copper alloy (13).
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202080083794.6A CN114746583A (en) | 2019-12-03 | 2020-12-03 | Strip for circuit with rose gold contact pads and method for manufacturing the strip |
KR1020227022250A KR20220110247A (en) | 2019-12-03 | 2020-12-03 | Tapes for electrical circuits having rose gold contact pads and methods of making such tapes |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP19315157 | 2019-12-03 | ||
EP19315157.8 | 2019-12-03 | ||
EP20168312.5A EP3892759B1 (en) | 2020-04-06 | 2020-04-06 | Tape for electrical circuits with rose-gold contact pads and method for manufacturing such a tape |
EP20168312.5 | 2020-04-06 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021110872A1 true WO2021110872A1 (en) | 2021-06-10 |
Family
ID=73642909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2020/084537 WO2021110872A1 (en) | 2019-12-03 | 2020-12-03 | Tape for electrical circuits with rose-gold contact pads and method for manufacturing such a tape |
Country Status (3)
Country | Link |
---|---|
KR (1) | KR20220110247A (en) |
CN (1) | CN114746583A (en) |
WO (1) | WO2021110872A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023146165A1 (en) * | 2022-01-26 | 2023-08-03 | 엘지이노텍 주식회사 | Smart ic substrate, smart ic module, and ic card comprising same |
Citations (3)
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WO2014064278A1 (en) * | 2012-10-26 | 2014-05-01 | Linxens Holding | Electric circuit, electronic module for a chip card formed on the electric circuit, and method for the production of such an electric circuit |
DE102013109400A1 (en) * | 2013-08-29 | 2015-03-05 | Harting Kgaa | Contact element with gold coating |
WO2019051712A1 (en) | 2017-09-14 | 2019-03-21 | Apply Card Technology Limited | Methods of manufacturing ic card circuit board substrates and ic cards |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2011117023A (en) * | 2009-12-01 | 2011-06-16 | Seiko Epson Corp | Method of manufacturing ornament, ornament and clock |
JP5467930B2 (en) * | 2010-05-19 | 2014-04-09 | Jx日鉱日石金属株式会社 | Copper clad laminate |
FR3003722A1 (en) * | 2013-03-19 | 2014-09-26 | Linxens Holding | METHOD FOR MANUFACTURING A FLEXIBLE PRINTED CIRCUIT, FLEXIBLE PRINTED CIRCUIT OBTAINED BY THIS METHOD AND CHIP CARD MODULE COMPRISING SUCH A FLEXIBLE PRINTED CIRCUIT |
FR3034614A1 (en) * | 2015-04-03 | 2016-10-07 | Linxens Holding | METHOD FOR MANUFACTURING A FLEXIBLE CIRCUIT, FLEXIBLE CIRCUIT OBTAINED BY THIS METHOD AND CHIP CARD COMPRISING SUCH A FLEXIBLE CIRCUIT |
-
2020
- 2020-12-03 KR KR1020227022250A patent/KR20220110247A/en unknown
- 2020-12-03 WO PCT/EP2020/084537 patent/WO2021110872A1/en active Application Filing
- 2020-12-03 CN CN202080083794.6A patent/CN114746583A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014064278A1 (en) * | 2012-10-26 | 2014-05-01 | Linxens Holding | Electric circuit, electronic module for a chip card formed on the electric circuit, and method for the production of such an electric circuit |
DE102013109400A1 (en) * | 2013-08-29 | 2015-03-05 | Harting Kgaa | Contact element with gold coating |
WO2019051712A1 (en) | 2017-09-14 | 2019-03-21 | Apply Card Technology Limited | Methods of manufacturing ic card circuit board substrates and ic cards |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2023146165A1 (en) * | 2022-01-26 | 2023-08-03 | 엘지이노텍 주식회사 | Smart ic substrate, smart ic module, and ic card comprising same |
Also Published As
Publication number | Publication date |
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KR20220110247A (en) | 2022-08-05 |
CN114746583A (en) | 2022-07-12 |
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