WO2021116048A1 - Circuit for a chip card module - Google Patents

Circuit for a chip card module Download PDF

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Publication number
WO2021116048A1
WO2021116048A1 PCT/EP2020/084955 EP2020084955W WO2021116048A1 WO 2021116048 A1 WO2021116048 A1 WO 2021116048A1 EP 2020084955 W EP2020084955 W EP 2020084955W WO 2021116048 A1 WO2021116048 A1 WO 2021116048A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
insulating substrate
conductive
electrical wires
silver
Prior art date
Application number
PCT/EP2020/084955
Other languages
French (fr)
Inventor
Ghim Koon GUN
Yean-wei YEAP
Gang Fan
Original Assignee
Linxens Holding
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Linxens Holding filed Critical Linxens Holding
Priority to KR2020227000039U priority Critical patent/KR20220002152U/en
Publication of WO2021116048A1 publication Critical patent/WO2021116048A1/en

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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772—Physical layout of the record carrier
    • G06K19/07722—Physical layout of the record carrier the record carrier being multilayered, e.g. laminated sheets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
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    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
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    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • Chip cards also called smart cards.
  • Chip cards are well known to the public, for which they have multiple uses: payment cards, SIM cards for cell phones, transport cards, identity cards, etc.
  • Chip cards comprise transmission means for transmitting data from the chip to a card reader (reading) or from the card reader to the card (writing). These transmission means may be “with contact”, “contactless” or else with a dual interface where they combine the two preceding means. Dual-interface chip cards are called “dual” if the "contact” and “contactless” modes are managed by a single chip or “hybrid” if the "contact” and “contactless” modes are managed by two, physically separate, chips.
  • Chip cards are generally composed of a rigid support made of a plastic material of PVC, PVC/ABS, PET or polycarbonate type forming the body of the card, in which a separately produced electronic module is incorporated.
  • the electronic module comprises a generally flexible printed circuit board that is equipped with an electronic chip (integrated circuit) and contact pads that are electrically connected to the chip and flush with the electronic module, on the support surface, for a connection by electrical contact with a card reader.
  • Dual-interface chip cards furthermore comprise at least one antenna for transmitting data between the chip and a radiofrequency system that allows contactless reading/writing of data.
  • the antenna may be manufactured separately on an inlay which is incorporated in the rigid support.
  • the antenna In dual-interface chip cards, it has often been proposed to connect the antenna to conductive pads or lands implemented on the side that is opposite that comprising the contacts designed to be connected to a card reader. Stated otherwise, the electronic module to be inserted into a card is called a "double-sided" circuit board, with one conductive side with the contacts to be connected to a card reader and one conductive side with the conductive pads or lands to be connected to the antenna, these two conductive sides each being respectively positioned on one side of an insulating substrate.
  • One aim of the invention disclosed below is to provide modules for smart cards that are more cost-effective to produce.
  • a circuit for a chip card module in which a multilayer structure comprises an insulating substrate and at least a first conductive layer.
  • the insulating substrate has a first and a second sides and the first conductive layer is supported by one of the first and the second sides of the insulating substrate.
  • Said first conductive layer is intended to be electrically connected to an electronic chip with electrical wires.
  • the electrical wires are - bonded to the first conductive layer with a wire-bonding technique.
  • the first conductive layer is a copper-based layer having a Vicker hardness greater than or equal to 100 VHN (where “VHN” means Vicker Hardeness Number),
  • This circuit may have one or several of the following features, considered either independently of one another, or in combination of one or several others of these features: the first conductive layer has a bonding surface, onto which electrical wires are intended to be connected, with a roughness greater than or equal to 0.8 micrometres; the circuit comprises an electronic chip and silver-based electrical wires connected to both the electronic chip and the first conductive layer, the silver-based electrical wires being wire-bonded to the first conductive layer; the silver-based electrical wires are made of a silver alloy; and preferably, the main components of the electrical wires are 88% silver and 9% gold; the silver-based electrical wires are made of a silver alloy with a gold coating (i.e. an external gold layer); the multilayer structure comprises a copper-clad structure;
  • the multilayer structure comprises the first conductive layer, the insulating substrate and a layer of adhesive material between the first conductive layer and the insulating substrate;
  • the circuit comprises through-holes punched in the insulating substrate and the first conductive layer, a second conductive layer laminated on a side of the insulating substrate opposite to the side of the insulating substrate supporting the first conductive layer and silver-based electrical wires connecting the electronic chip and the first conductive layer, the electrical wires being wire-bonded to the first conductive layer;
  • a second conductive layer is supported by a side of the insulating substrate opposite to the side of the insulating substrate supporting the first conductive layer;
  • first conductive pads are formed in the first conductive layer and second conductive pads are formed in the second conductive layer, silver-based electrical wires being connected to both an electronic chip and at least the first conductive pads, the electrical wires being wire-bonded at least to the first conductive pads (and possibly to the chip), and the second conductive pads being adapted to establish an electrical connection with a
  • FIG. 1 is a diagrammatic perspective representation of a chip card accommodating a module comprising a portion of flexible circuit according to the invention
  • FIG. 1 is a diagrammatic representation of a cross-section through a chip card module comprising a flexible circuit according to an embodiment of the invention
  • FIG. 3 is a diagrammatic representation of a cross-section through a portion of a tape for flexible circuit according to another embodiment of the invention.
  • FIG. 4 is a diagrammatic representation of a cross-section through a portion of a tape for flexible circuit according to the embodiment shown in figure 2.
  • the invention may be used for making a chip card 1 (of bank card or another type).
  • This card 1 comprises a cavity 2, for example milled into the body of the card 1.
  • a chip card module 3 is accommodated in the cavity 2.
  • this chip card module 3 comprises an electrically insulating substrate 4 that is advantageously flexible.
  • the substrate 4 has a first 5 and a second 6 sides.
  • a first 7 and a second 8 conductive layers are respectively supported by the first 5 and a second 6 sides.
  • first conductive pads 9 electrically isolated from one another are made in the first conductive layer 7.
  • These first conductive pads 9 are designed to be connected to an antenna accommodated in the card body.
  • the first conductive pads 9 may be etched in the first conductive layer 7 with well-known photolithography and etching techniques. Alternatively, the first conductive pads 9 may be stamped in the first conductive layer 7 prior to its lamination onto the insulating substrate 4 according to a well-known leadframe technology.
  • second conductive pads 10 i.e. contacts to be connected to a card reader
  • the second conductive pads 10 may be etched in the second conductive layer 8 with well-known photolithography and etching techniques.
  • the second conductive pads 10 may be stamped in the second conductive layer 10 prior to its lamination onto the insulating substrate 4 according to a well-known leadframe technology.
  • the insulating substrate 4 has a cavity 11 within which an electronic chip 12 is accommodated. Blind holes 16 are also made in the substrate 4. This cavity 11 is optional. In an alternative embodiment the chip 12 is glued onto the insulating substrate 4.
  • Electrical wires 13 are connected to both the chip 12 and the first 7 and second 8 conductive pads.
  • circuit for the chip card module 3 is manufactured, with a reel to reel process as follows:
  • an insulating substrate 4 is provided;
  • the insulating substrate 4 is made, for example, of a plastic material (polyimide, PET, PEN, PVC, etc.) or of a composite material (glass-epoxy); its thickness ranges for example from 50 to 100 micrometres;
  • the first 5 and second 6 sides of the insulating substrate 4 are coated with an adhesive layer 14, 15 to 30 pm thick, for example;
  • a first conductive layer 7 is laminated onto the adhesive layer 14 laying on the first side 5 of the insulating substrate 4;
  • the multi-layered structure comprising the insulating substrate 4, the adhesive layers 14 and the first conductive layer 7 is punched through its whole thickness, in order to form the optional chip cavity 11 and through-holes 15;
  • a second conductive layer 8 is laminated onto the adhesive layer 14 laying on the second side 6 of the substrate; the through-holes 15 covered by the second conductive layer 8 form blind holes 16;
  • first 9 and second 10 conductive pads are formed respectively in the first 7 and second 8 conductive layers (If not already formed by leadframe technology prior to the lamination of the first 7 and/or second 8 conductive layers onto the insulating substrate 4); the surface of the first conductive pads 9 (on the bonding face) and of the second conductive pads 10 (both on the contact face and on the bonding face) is covered with one or several electrodeposited layers of conductive materials (for example, nickel-gold, or nickel-gold-palladium, or nickel-palladium); this results in a circuit as schematically illustrated in figure 3;
  • an electronic chip 12 is attached onto the insulating substrate 4 or in the optional chip cavity 11 ;
  • - electrical wires 13 are connected to the chip 12; some of these electrical wires 13 are connected to the second conductive pads 10 at the bottom of the blind holes 16 and others are connected to the first conductive pads 9;
  • a glob top 17 is formed with a resin over the wire connections to the chip 12 and to first 9 and second 10 conductive pads; an UV or thermal treatment is performed so as to harden the resin;
  • the tape with the electrical circuits formed according to the previous steps is cut into pieces so as to form single modules 3 (similar to the module 3 schematically illustrated in figure 2) that can be incorporated and fixed in a module cavity 2 milled in the body of a card 1.
  • the circuit for the chip card module 3 is manufactured, with a reel to reel process as follows:
  • this clad structure 18 comprising an insulating substrate 4 and a first conductive layer 7 on a first side 5 of the insulating substrate 4;
  • the insulating substrate 4 is made, for example, of a plastic material (polyimide, PET, PEN, PVC, etc.) or of a composite material (glass-epoxy); its thickness ranges for example from 50 to 100 micrometres;
  • the clad structure 18 comprising the insulating substrate 4, the adhesive layer 14 and the first conductive layer 7 is punched through its whole thickness, in order to form the optional chip cavity 11 and through-holes 15; [0037] - a second conductive layer 8 is laminated onto the adhesive layer 14 laying on the second side 6 of the insulating substrate 4; the through-holes 15 covered by the second conductive layer 8 form blind holes 16;
  • first 9 and second 10 conductive pads are formed respectively in the first 7 and second 8 conductive layers (If not already formed by leadframe technology prior to the lamination of the second conductive layer 8 onto the substrate); the surface of the first conductive pads 9 (on the bonding face) and of the second conductive pads 10 (both on the contact face and on the bonding face) is covered with one or several electrodeposited layers of conductive materials (for example, nickel-gold, or nickel-gold-palladium, or nickel-palladium); this results in a circuit as schematically illustrated in figure 4;
  • conductive materials for example, nickel-gold, or nickel-gold-palladium, or nickel-palladium
  • an electronic chip 12 is attached onto the insulating substrate 4 or in the optional chip cavity 11 ;
  • - electrical wires 13 are connected to the chip 12; some of these electrical wires 13 are connected to the second conductive pads 10 at the bottom of the blind holes 16 and others are connected to the first conductive pads 9;
  • a glob top 17 is formed with a resin over the wire connections to the chip 12 and to first 9 and second 10 conductive pads; an UV or thermal treatment is performed so as to harden the resin;
  • the tape with the electrical circuits formed according to the previous steps is cut into pieces so as to form single modules 3 (similar to the module 3 schematically illustrated in figure 2) that can be incorporated and fixed in a module cavity 2 milled in the body of a card 1.
  • the circuit may have one or several of the following features, considered either independently of one another, or in combination of one or several others of these features: the first conductive layer 7 is made of a copper foil or a copper alloy foil having a Vicker hardness greater than or equal to 100 VHN; the first conductive layer 7 has a thickness ranging, for example, from 18 to 38 micrometres; the first conductive layer 7 is advantageously coated with at least an electrodeposited nickel layer or an electrodeposited nickel alloy layer 3 to 8 pm thick, for example; a dry or wet surface treatment is performed on the copper surface onto which electrical wires are intended to be connected (prior to the possible electro-deposition of nickel or nickel alloy), in order to achieve a surface roughness greater than or equal to 0.8 micrometres, this dry or wet treatment including sandblasting, pumice, jetscrubbing; the second conductive layer 8 is made for example of a copper foil or a copper alloy layer 15 to 40 pm thick; the electrical wires
  • Steps of the above-mentioned methods may be carried out by one and the same manufacturer or by different manufacturers.
  • the bare circuit (without the electronic chip 12, the electrical wires 13 and the glob top 17) may be manufactured by a first manufacturer, the electronic chip 12 may be attached and connected by a second manufacturer, while the module 3 may be incorporated in a card body by a third manufacturer.
  • the claimed circuit for a chip card module is suitable for connecting the electronic chip 12 to first 7 and second 8 conductive pads, even if, for example at the first manufacturer, the circuit does not comprise any electronic chip 12.
  • Vicker Hardness values mentioned in the present description, as well as in the claims, are the values of first 7 and/or second 8 conductive layer(s) in the finished circuit or module 3.
  • annealing and/or curing steps may change the Vicker hardness.
  • a copper layer having a Vicker hardness of 114 VHN prior to lamination onto the insulating substrate 4 may have a Vicker hardness of 100 VHN, after a curing of the multilayer structure comprising the insulating substrate 4, the adhesive layer 14 and the first conductive layer 8, at a temperature greater than or equal to 100°C.
  • the first conductive layer made 7 of a copper layer having a Vicker hardness at least equal to 100 VHN it is possible to obtain a pull-out vertical force in the range of 7 to 9.5 gf (gram force) and a pull-out horizontal force in a range of 4 to 5.5 gf.
  • one of the advantages of the implementation of the first conductive layer made of a copper layer having a Vicker hardness at least equal to 100 VHN is that it is possible to wire-bond wires which have lower softness and ductility properties than gold wires. More particularly, it allows the use of silver-based wires (either wires made of a silver alloy or wires made of a silver alloy coated with gold or wires made of silver alloy coated with another conductive material) onto it while achieving good performances in terms pull strength and conductivity. As a consequence of the use of silver-based wires, the circuit allows cost savings compared to the use of gold wires (for example the silver-based wires may be 75% cheaper than gold wires).
  • Another advantage is that the wedge bond strength is higher, while the wire bonding process is robust and stable.
  • Another advantage is that the wire bonding productivity is improved compared to processes using additional bumps between the wire and the conductive pads (for example, the invention may increase the productivity by 15% or more compared to processes using additional bumps).
  • the second conductive layer 8 is also a copper-based layer having a Vicker hardness greater than or equal to 100 VHN.

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Abstract

A circuit for a chip card module (3) comprising a multilayer structure. This multilayer structure comprises an insulating substrate (4) and a first conductive layer (7) supported by one side of the insulating substrate (4). The first conductive layer (7) is intended to be electrically connected to an electronic chip (12), with electrical wires (13) wire- bonded to the first conductive layer (7). The first conductive layer (7) is a copper-based layer having a Vicker hardness greater than or equal to 100 VHN.

Description

CIRCUIT FOR A CHIP CARD MODULE
Technical field
[001] This disclosure relates to the field of chip cards (also called smart cards). Chip cards are well known to the public, for which they have multiple uses: payment cards, SIM cards for cell phones, transport cards, identity cards, etc.
Background art
[002] Chip cards comprise transmission means for transmitting data from the chip to a card reader (reading) or from the card reader to the card (writing). These transmission means may be "with contact", "contactless" or else with a dual interface where they combine the two preceding means. Dual-interface chip cards are called "dual" if the "contact" and "contactless" modes are managed by a single chip or "hybrid" if the "contact" and "contactless" modes are managed by two, physically separate, chips.
[003] Chip cards are generally composed of a rigid support made of a plastic material of PVC, PVC/ABS, PET or polycarbonate type forming the body of the card, in which a separately produced electronic module is incorporated. The electronic module comprises a generally flexible printed circuit board that is equipped with an electronic chip (integrated circuit) and contact pads that are electrically connected to the chip and flush with the electronic module, on the support surface, for a connection by electrical contact with a card reader. Dual-interface chip cards furthermore comprise at least one antenna for transmitting data between the chip and a radiofrequency system that allows contactless reading/writing of data. The antenna may be manufactured separately on an inlay which is incorporated in the rigid support.
[004] In dual-interface chip cards, it has often been proposed to connect the antenna to conductive pads or lands implemented on the side that is opposite that comprising the contacts designed to be connected to a card reader. Stated otherwise, the electronic module to be inserted into a card is called a "double-sided" circuit board, with one conductive side with the contacts to be connected to a card reader and one conductive side with the conductive pads or lands to be connected to the antenna, these two conductive sides each being respectively positioned on one side of an insulating substrate.
[005] Techniques commonly used for connecting the electronic chip to the contacts to be connected to a card reader are well known as “wire-bonding” techniques. With such techniques, gold wires are attached to the contact pads with either thermo-compression soldering or ultra sonic welding. Good effects are achieved in terms of conductivity and pull-strength with gold wires wire-bonded on a copper layer coated with electrodeposited layers of nickel and gold, or nickel, gold and palladium, or nickel and palladium. Summary of the invention
[006] One aim of the invention disclosed below is to provide modules for smart cards that are more cost-effective to produce.
[007] To this end, a circuit for a chip card module is presented in which a multilayer structure comprises an insulating substrate and at least a first conductive layer. The insulating substrate has a first and a second sides and the first conductive layer is supported by one of the first and the second sides of the insulating substrate. Said first conductive layer is intended to be electrically connected to an electronic chip with electrical wires. The electrical wires are - bonded to the first conductive layer with a wire-bonding technique. Further, the first conductive layer is a copper-based layer having a Vicker hardness greater than or equal to 100 VHN (where “VHN” means Vicker Hardeness Number),
[008] Indeed, good effects are achieved with the wire-bonding techniques of the prior art because of the softness and ductility properties of gold wires. But, when silver-based wires are used the results are not as satisfying. Yet, for cost saving reason it is interesting to use silver- based wires.
[009] Thanks to a copper-based layer having a Vicker hardness greater than or equal to 100 VHN it becomes possible to wire-bond silver-based wires onto it while achieving good performances in terms of pull strength and conductivity.
[0010] This circuit may have one or several of the following features, considered either independently of one another, or in combination of one or several others of these features: the first conductive layer has a bonding surface, onto which electrical wires are intended to be connected, with a roughness greater than or equal to 0.8 micrometres; the circuit comprises an electronic chip and silver-based electrical wires connected to both the electronic chip and the first conductive layer, the silver-based electrical wires being wire-bonded to the first conductive layer; the silver-based electrical wires are made of a silver alloy; and preferably, the main components of the electrical wires are 88% silver and 9% gold; the silver-based electrical wires are made of a silver alloy with a gold coating (i.e. an external gold layer); the multilayer structure comprises a copper-clad structure;
- the multilayer structure comprises the first conductive layer, the insulating substrate and a layer of adhesive material between the first conductive layer and the insulating substrate; the circuit comprises through-holes punched in the insulating substrate and the first conductive layer, a second conductive layer laminated on a side of the insulating substrate opposite to the side of the insulating substrate supporting the first conductive layer and silver-based electrical wires connecting the electronic chip and the first conductive layer, the electrical wires being wire-bonded to the first conductive layer; a second conductive layer is supported by a side of the insulating substrate opposite to the side of the insulating substrate supporting the first conductive layer; first conductive pads are formed in the first conductive layer and second conductive pads are formed in the second conductive layer, silver-based electrical wires being connected to both an electronic chip and at least the first conductive pads, the electrical wires being wire-bonded at least to the first conductive pads (and possibly to the chip), and the second conductive pads being adapted to establish an electrical connection with a chip card reader; the first conductive layer has a thickness ranging from 18 to 38 micrometres.
Description of figures
[0011] Other features and advantages of the invention will become apparent upon reading the detailed description and the appended drawings in which:
[0012] - figure 1 is a diagrammatic perspective representation of a chip card accommodating a module comprising a portion of flexible circuit according to the invention;
[0013] - figure 2 is a diagrammatic representation of a cross-section through a chip card module comprising a flexible circuit according to an embodiment of the invention;
[0014] - figure 3 is a diagrammatic representation of a cross-section through a portion of a tape for flexible circuit according to another embodiment of the invention; and [0015] - figure 4 is a diagrammatic representation of a cross-section through a portion of a tape for flexible circuit according to the embodiment shown in figure 2.
Detailed description
[0016] As illustrated in Fig. 1, the invention may be used for making a chip card 1 (of bank card or another type). This card 1 comprises a cavity 2, for example milled into the body of the card 1. A chip card module 3 is accommodated in the cavity 2.
[0017] As illustrated in Fig. 2, this chip card module 3 comprises an electrically insulating substrate 4 that is advantageously flexible. The substrate 4 has a first 5 and a second 6 sides. [0018] In an embodiment example, a first 7 and a second 8 conductive layers are respectively supported by the first 5 and a second 6 sides. On the first side 5, called the back side or bonding face, first conductive pads 9 electrically isolated from one another are made in the first conductive layer 7. These first conductive pads 9 are designed to be connected to an antenna accommodated in the card body. The first conductive pads 9 may be etched in the first conductive layer 7 with well-known photolithography and etching techniques. Alternatively, the first conductive pads 9 may be stamped in the first conductive layer 7 prior to its lamination onto the insulating substrate 4 according to a well-known leadframe technology.
[0019] On the opposite side, the second side 6 of the insulating substrate 4, called the front side or contact face, second conductive pads 10 (i.e. contacts to be connected to a card reader) that are electrically isolated from one another are made in a second conductive layer 8. The second conductive pads 10 may be etched in the second conductive layer 8 with well-known photolithography and etching techniques. Alternatively, the second conductive pads 10 may be stamped in the second conductive layer 10 prior to its lamination onto the insulating substrate 4 according to a well-known leadframe technology.
[0020] The insulating substrate 4 has a cavity 11 within which an electronic chip 12 is accommodated. Blind holes 16 are also made in the substrate 4. This cavity 11 is optional. In an alternative embodiment the chip 12 is glued onto the insulating substrate 4.
[0021] Electrical wires 13 are connected to both the chip 12 and the first 7 and second 8 conductive pads.
[0022] Two examples of method for manufacturing an electrical circuit for a chip card module are disclosed below. According to a first example of manufacturing method, the circuit for the chip card module 3 is manufactured, with a reel to reel process as follows:
[0023] - an insulating substrate 4 is provided; the insulating substrate 4 is made, for example, of a plastic material (polyimide, PET, PEN, PVC, etc.) or of a composite material (glass-epoxy); its thickness ranges for example from 50 to 100 micrometres;
[0024] - the first 5 and second 6 sides of the insulating substrate 4 are coated with an adhesive layer 14, 15 to 30 pm thick, for example;
[0025] - a first conductive layer 7 is laminated onto the adhesive layer 14 laying on the first side 5 of the insulating substrate 4;
[0026] - the multi-layered structure comprising the insulating substrate 4, the adhesive layers 14 and the first conductive layer 7 is punched through its whole thickness, in order to form the optional chip cavity 11 and through-holes 15; [0027] - a second conductive layer 8 is laminated onto the adhesive layer 14 laying on the second side 6 of the substrate; the through-holes 15 covered by the second conductive layer 8 form blind holes 16;
[0028] - first 9 and second 10 conductive pads are formed respectively in the first 7 and second 8 conductive layers (If not already formed by leadframe technology prior to the lamination of the first 7 and/or second 8 conductive layers onto the insulating substrate 4); the surface of the first conductive pads 9 (on the bonding face) and of the second conductive pads 10 (both on the contact face and on the bonding face) is covered with one or several electrodeposited layers of conductive materials (for example, nickel-gold, or nickel-gold-palladium, or nickel-palladium); this results in a circuit as schematically illustrated in figure 3;
[0029] - an electronic chip 12 is attached onto the insulating substrate 4 or in the optional chip cavity 11 ;
[0030] - electrical wires 13 are connected to the chip 12; some of these electrical wires 13 are connected to the second conductive pads 10 at the bottom of the blind holes 16 and others are connected to the first conductive pads 9;
[0031] - a glob top 17 is formed with a resin over the wire connections to the chip 12 and to first 9 and second 10 conductive pads; an UV or thermal treatment is performed so as to harden the resin;
[0032] - the tape with the electrical circuits formed according to the previous steps is cut into pieces so as to form single modules 3 (similar to the module 3 schematically illustrated in figure 2) that can be incorporated and fixed in a module cavity 2 milled in the body of a card 1.
[0033] According to a second example of manufacturing method, the circuit for the chip card module 3 is manufactured, with a reel to reel process as follows:
[0034] - a clad structure 18 is provided, this clad structure 18 comprising an insulating substrate 4 and a first conductive layer 7 on a first side 5 of the insulating substrate 4; the insulating substrate 4 is made, for example, of a plastic material (polyimide, PET, PEN, PVC, etc.) or of a composite material (glass-epoxy); its thickness ranges for example from 50 to 100 micrometres;
[0035] - - the second side 6 of the insulating substrate 4 is coated with an adhesive layer 14, 15 to 30 pm thick, for example;
[0036] the clad structure 18 comprising the insulating substrate 4, the adhesive layer 14 and the first conductive layer 7 is punched through its whole thickness, in order to form the optional chip cavity 11 and through-holes 15; [0037] - a second conductive layer 8 is laminated onto the adhesive layer 14 laying on the second side 6 of the insulating substrate 4; the through-holes 15 covered by the second conductive layer 8 form blind holes 16;
[0038] - first 9 and second 10 conductive pads are formed respectively in the first 7 and second 8 conductive layers (If not already formed by leadframe technology prior to the lamination of the second conductive layer 8 onto the substrate); the surface of the first conductive pads 9 (on the bonding face) and of the second conductive pads 10 (both on the contact face and on the bonding face) is covered with one or several electrodeposited layers of conductive materials (for example, nickel-gold, or nickel-gold-palladium, or nickel-palladium); this results in a circuit as schematically illustrated in figure 4;
[0039] - an electronic chip 12 is attached onto the insulating substrate 4 or in the optional chip cavity 11 ;
[0040] - electrical wires 13 are connected to the chip 12; some of these electrical wires 13 are connected to the second conductive pads 10 at the bottom of the blind holes 16 and others are connected to the first conductive pads 9;
[0041] - a glob top 17 is formed with a resin over the wire connections to the chip 12 and to first 9 and second 10 conductive pads; an UV or thermal treatment is performed so as to harden the resin;
[0042] - the tape with the electrical circuits formed according to the previous steps is cut into pieces so as to form single modules 3 (similar to the module 3 schematically illustrated in figure 2) that can be incorporated and fixed in a module cavity 2 milled in the body of a card 1.
[0043] In both embodiments illustrated in Figs. 3 and 4, the circuit may have one or several of the following features, considered either independently of one another, or in combination of one or several others of these features: the first conductive layer 7 is made of a copper foil or a copper alloy foil having a Vicker hardness greater than or equal to 100 VHN; the first conductive layer 7 has a thickness ranging, for example, from 18 to 38 micrometres; the first conductive layer 7 is advantageously coated with at least an electrodeposited nickel layer or an electrodeposited nickel alloy layer 3 to 8 pm thick, for example; a dry or wet surface treatment is performed on the copper surface onto which electrical wires are intended to be connected (prior to the possible electro-deposition of nickel or nickel alloy), in order to achieve a surface roughness greater than or equal to 0.8 micrometres, this dry or wet treatment including sandblasting, pumice, jetscrubbing; the second conductive layer 8 is made for example of a copper foil or a copper alloy layer 15 to 40 pm thick; the electrical wires 13 are made of a silver alloy, with or without gold coating; their diameter is in a range from 18 to 25 micrometres; the electrical wires 13 are wire- bonded to the first 7 and second 8 conductive layers (that is they are connected to the first 7 and second 8 conductive layers either with ultra-sonic welding or thermo compression soldering).
[0044] Steps of the above-mentioned methods may be carried out by one and the same manufacturer or by different manufacturers. For example, the bare circuit (without the electronic chip 12, the electrical wires 13 and the glob top 17) may be manufactured by a first manufacturer, the electronic chip 12 may be attached and connected by a second manufacturer, while the module 3 may be incorporated in a card body by a third manufacturer. However, it shall be understood that, in any case, the claimed circuit for a chip card module is suitable for connecting the electronic chip 12 to first 7 and second 8 conductive pads, even if, for example at the first manufacturer, the circuit does not comprise any electronic chip 12.
[0045] One can notice that the Vicker Hardness values mentioned in the present description, as well as in the claims, are the values of first 7 and/or second 8 conductive layer(s) in the finished circuit or module 3. Indeed, annealing and/or curing steps may change the Vicker hardness. For example, a copper layer having a Vicker hardness of 114 VHN prior to lamination onto the insulating substrate 4 may have a Vicker hardness of 100 VHN, after a curing of the multilayer structure comprising the insulating substrate 4, the adhesive layer 14 and the first conductive layer 8, at a temperature greater than or equal to 100°C.
[0046] Thanks to the implementation of the first conductive layer made 7 of a copper layer having a Vicker hardness at least equal to 100 VHN, it is possible to obtain a pull-out vertical force in the range of 7 to 9.5 gf (gram force) and a pull-out horizontal force in a range of 4 to 5.5 gf.
[0047] As already mentioned, one of the advantages of the implementation of the first conductive layer made of a copper layer having a Vicker hardness at least equal to 100 VHN, is that it is possible to wire-bond wires which have lower softness and ductility properties than gold wires. More particularly, it allows the use of silver-based wires (either wires made of a silver alloy or wires made of a silver alloy coated with gold or wires made of silver alloy coated with another conductive material) onto it while achieving good performances in terms pull strength and conductivity. As a consequence of the use of silver-based wires, the circuit allows cost savings compared to the use of gold wires (for example the silver-based wires may be 75% cheaper than gold wires).
[0048] Another advantage is that the wedge bond strength is higher, while the wire bonding process is robust and stable. [0049] Another advantage, is that the wire bonding productivity is improved compared to processes using additional bumps between the wire and the conductive pads (for example, the invention may increase the productivity by 15% or more compared to processes using additional bumps).
[0050] In an alternative embodiment, the second conductive layer 8 is also a copper-based layer having a Vicker hardness greater than or equal to 100 VHN.

Claims

1. A circuit for a chip card module (3), characterised in that, the circuit comprises a multilayer structure comprising an insulating substrate (4) having a first (5) and a second (6) sides, and a first conductive layer (7) supported by one of the first (5) and the second (6) sides of the insulating substrate (4); wherein said first conductive layer (7) is intended to be electrically connected to an electronic chip (12), with electrical wires (13) wire-bonded to the first conductive layer
(7), the first conductive layer (7) is a copper-based layer having a Vicker hardness greater than or equal to 100 VHN.
2. A circuit according to claim 1 , wherein the first conductive layer has a bonding surface onto which electrical wires (13) are intended to be connected with a roughness greater than or equal to 0.8 micrometres.
3. A circuit according to claim 1 or 2, comprising an electronic chip (12) and silver-based electrical wires (13) connected to both the electronic chip (12) and the first conductive layer (7), the silver-based electrical wires (13) being wire-bonded to the first conductive layer (7).
4. A circuit according to claim 3, wherein the silver-based electrical wires (13) are made a silver alloy.
5. A circuit according to claim 3 or 4, wherein the silver-based electrical wires (13) are made a silver alloy with an external gold layer.
6. A circuit according to any preceding claims, wherein the multilayer structure comprises a copper-clad structure (18).
7. A circuit according to any preceding claims, comprising through-holes (15) punched in the insulating substrate (4) and the first conductive layer (7), and a second conductive layer (8) laminated on a side (6) of the insulating substrate (4) opposite to the side of the insulating substrate (4) supporting the first conductive layer (7).
8. A circuit according to one of claims 1 to 6, comprising a second conductive layer (8) is supported by a side (6) of the insulating substrate (4) opposite to the side (5) of the insulating substrate (4) supporting the first conductive layer (7).
9. A circuit according to claim 8, wherein the first conductive pads (9) are formed in the first conductive layer (7) and second conductive pads (10) are formed in the second conductive layer (8), silver-based electrical wires (13) being connected to both an electronic chip (12) and at least the first conductive pads (9), the silver-based electrical wires (13) being wire-bonded to the first conductive pads (9), and the second conductive pads (10) being adapted to establish a connection by electrical contact with a chip card reader.
10. A circuit according to any preceding claims, wherein the first conductive layer (7) has a thickness ranging from 18 to 38 micrometres.
PCT/EP2020/084955 2019-12-10 2020-12-07 Circuit for a chip card module WO2021116048A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2020227000039U KR20220002152U (en) 2019-12-10 2020-12-07 Circuit for chip card module

Applications Claiming Priority (2)

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CN201922202646.9 2019-12-10
CN201922202646.9U CN211787168U (en) 2019-12-10 2019-12-10 Circuit for chip card module

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WO2021116048A1 true WO2021116048A1 (en) 2021-06-17

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463871A2 (en) * 1990-06-29 1992-01-02 Gec Avery Limited Integrated circuit token
JP2001274202A (en) * 2000-03-24 2001-10-05 Hitachi Cable Ltd Tab tape and bga structure
EP2887779A1 (en) * 2013-12-20 2015-06-24 ATOTECH Deutschland GmbH Silver wire bonding on printed circuit boards and IC-substrates
US20160330841A1 (en) * 2014-01-06 2016-11-10 Gemalto Sa Electronic module, method for manufacturing same and electronic device comprising a module of said type
US20190279942A1 (en) * 2018-03-12 2019-09-12 Stmicroelectronics International N.V. Lead frame surface finishing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0463871A2 (en) * 1990-06-29 1992-01-02 Gec Avery Limited Integrated circuit token
JP2001274202A (en) * 2000-03-24 2001-10-05 Hitachi Cable Ltd Tab tape and bga structure
EP2887779A1 (en) * 2013-12-20 2015-06-24 ATOTECH Deutschland GmbH Silver wire bonding on printed circuit boards and IC-substrates
US20160330841A1 (en) * 2014-01-06 2016-11-10 Gemalto Sa Electronic module, method for manufacturing same and electronic device comprising a module of said type
US20190279942A1 (en) * 2018-03-12 2019-09-12 Stmicroelectronics International N.V. Lead frame surface finishing

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CN211787168U (en) 2020-10-27

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