JPH0618220B2 - Chip on board - Google Patents

Chip on board

Info

Publication number
JPH0618220B2
JPH0618220B2 JP63020086A JP2008688A JPH0618220B2 JP H0618220 B2 JPH0618220 B2 JP H0618220B2 JP 63020086 A JP63020086 A JP 63020086A JP 2008688 A JP2008688 A JP 2008688A JP H0618220 B2 JPH0618220 B2 JP H0618220B2
Authority
JP
Japan
Prior art keywords
chip
board
solder resist
conductor circuit
nickel plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63020086A
Other languages
Japanese (ja)
Other versions
JPH01194428A (en
Inventor
貞久 古橋
耕士 鵜飼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP63020086A priority Critical patent/JPH0618220B2/en
Publication of JPH01194428A publication Critical patent/JPH01194428A/en
Publication of JPH0618220B2 publication Critical patent/JPH0618220B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/244Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Landscapes

  • Chemically Coating (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はベアチップ半導体素子を搭載し、金、アルミニ
ウム、銅等の材質のボンディングワイヤーによりワイヤ
ーボンディング実装を行うためのチップオンボードに関
するものである。
Description: TECHNICAL FIELD The present invention relates to a chip-on-board for mounting a bare chip semiconductor element and performing wire bonding mounting with a bonding wire made of a material such as gold, aluminum or copper. .

(従来の技術) 一般に、ベアチップ半導体素子をワイヤーボンディング
実装する金属ワイヤーとして、金ワイヤーがある。金は
高価であることは勿論であるが、ワイヤーボンディング
の安定性、信頼性の上で他のアルミニウム、銅より優れ
ているため、金ワイヤーがボンディングワイヤーの主流
となっている。この金ワイヤーによりワイヤーボンディ
ングを行う場合のチップオンボード用金メッキとしては
99.99%以上の純度が要求され、導体回路を形成す
る銅が金に拡散するのを防止するために、金の下地には
ニッケルメッキ層が形成されるのが一般的であり、ま
た、ワイヤーボンディング時の硬度を持たせるためにも
ニッケルメッキ層が形成される。
(Prior Art) Generally, there is a gold wire as a metal wire for mounting a bare chip semiconductor element by wire bonding. Gold is, of course, expensive, but gold wire is the mainstream of bonding wire because it is superior to other aluminum and copper in stability and reliability of wire bonding. A purity of 99.99% or higher is required as the gold plating for chip on board when wire bonding is performed with this gold wire, and in order to prevent the copper forming the conductor circuit from diffusing into gold, the gold base is In general, a nickel plating layer is formed, and a nickel plating layer is also formed in order to provide hardness during wire bonding.

ところで、これらのニッケル、金のメッキ法として一般
には電解メッキ法が用いられるが、特に電解ニッケルメ
ッキの場合にあっては、第2図〜第4図に示すように、
イカリ肩(80)や金ボール(90)等の異常な形状に析出し易
く、また、導体回路(20)の配線形状によって電解ニッケ
ルメッキ層(82)の厚みのバラツキが大きく導体間に段差
が発生し、それに起因してボンディングワイヤーが外れ
る等の障害が起き易くなっている。
By the way, an electrolytic plating method is generally used as the plating method for these nickel and gold. In particular, in the case of electrolytic nickel plating, as shown in FIGS.
It is likely to be deposited in abnormal shapes such as squid shoulders (80) and gold balls (90), and the thickness of the electrolytic nickel plating layer (82) varies greatly due to the wiring shape of the conductor circuit (20), resulting in a step between conductors. Occurrence occurs, and as a result, problems such as disconnection of the bonding wire are likely to occur.

これらの電解ニッケルメッキ層(82)のメッキ厚のバラツ
キ等の問題を解決するためには、ニッケルメッキを無電
解メッキ法で行えば好結果が得られそうであるが、一般
的な方法即ち、所望の導体回路(20)を形成し、ソルダー
レジスト(30)を施したのち無電解ニッケルメッキ、金メ
ッキを行う場合にあっては、以下のような問題がある。
つまり、 導体回路(20)としての銅の上に無電解ニッケルメッキ
(32)を行うためには、先ず、前処理として銅表面をパラ
ジウム等により触媒作用のある表面とする必要がある
が、この触媒工程において一般には数10%の塩酸浴が
使用されるため、前記ソルダーレジスト(30)が浮き上が
り、剥がれ不良となってしまう。
In order to solve problems such as variations in the plating thickness of these electrolytic nickel plating layers (82), good results are likely to be obtained by performing electroless plating of nickel, but a general method, namely, When the desired conductor circuit (20) is formed, the solder resist (30) is applied, and then electroless nickel plating and gold plating are performed, there are the following problems.
That is, electroless nickel plating on copper as the conductor circuit (20)
In order to carry out (32), first, it is necessary to make the copper surface a catalytic surface by using palladium or the like as a pretreatment. However, in this catalytic step, a tens of% hydrochloric acid bath is generally used. The solder resist (30) floats up, resulting in defective peeling.

年々高信頼性の要求を受けつつあるチップオンボード
(100)にあっては、前記の一般的な方法、即ち、所望の
導体回路(20)を形成し、ソルダーレジスト(30)を施した
後、無電解ニッケルメッキ(32)、金メッキ(81)を行う場
合には、ソルダーレジスト(30)の下地が銅であるため、
腐食、銅マイグレーションに対する注意が特に必要とな
る。
Chip-on-board, which is receiving high reliability every year
In (100), the general method described above, that is, after forming the desired conductor circuit (20) and applying a solder resist (30), electroless nickel plating (32), gold plating (81) When performing, because the base of the solder resist (30) is copper,
Special attention should be paid to corrosion and copper migration.

また、従来のチップオンボード(100)にあっては、高
密度配線の要求からスルーホール銅メッキは薄く形成し
てあり、ワイヤーボンディング等の加熱時の基板の厚み
方向への寸法変化に対してのスルーホールの強度を得る
ために、ニッケルメッキ層(82)で補強を行っていたが、
第4図に示すように、チップオンボード(100)用ソルダ
ーレジスト(30)は、様々な用途の要求の中でスルーホー
ル(60)部にソルダーレジスト(30)を形成する場合が多
く、従ってスルーホール(60)にはニッケルメッキ(82)が
施されず強度不足の心配があり、また銅メッキ厚付けに
より強度を保持しようとした場合には、導体回路(20)形
成時のエッチング精度が悪くなり高密度配線の妨げとな
る。
Further, in the conventional chip-on-board (100), the through-hole copper plating is thinly formed due to the requirement of high-density wiring, so that the dimensional change in the thickness direction of the substrate during heating such as wire bonding may occur. In order to obtain the strength of the through hole of, the nickel plating layer (82) was used for reinforcement,
As shown in FIG. 4, the solder resist (30) for the chip-on-board (100) often forms the solder resist (30) in the through hole (60) in order to meet various application requirements. There is a concern that the through hole (60) will not be nickel plated (82) and its strength may be insufficient.If it is attempted to maintain the strength by thickening the copper plating, the etching accuracy when forming the conductor circuit (20) will be poor. It deteriorates and hinders high-density wiring.

さらに、導体回路(20)の全面にニッケルメッキ(82)及
び金メッキ(81)を施した後、ソルダーレジスト(30)を適
宜形成する場合にあっては、本来、金が不要な導体回路
(20)の部分にも金メッキ(81)が施されることになり、大
幅なコストアップとなる。
Furthermore, in the case where the solder resist (30) is appropriately formed after the nickel plating (82) and the gold plating (81) are applied to the entire surface of the conductor circuit (20), the conductor circuit which originally does not require gold is used.
Gold plating (81) will also be applied to the part (20), resulting in a significant cost increase.

そこで、本発明者等はこの種のチップオンボードにおけ
る従来技術の不充分さを解決すべく鋭意研究してきた結
果、導体回路の全面に無電解ニッケルメッキ(32)を施
し、その後無電解ニッケルメッキ(32)の表面上の必要箇
所にソルダーレジスト(30)を公知の方法により形成し、
適宜金メッキを施すことが良い結果を招来することを新
規に知見し、本発明を完成したのである。
Therefore, as a result of intensive research conducted by the present inventors to solve the deficiency of the prior art in this type of chip-on-board, electroless nickel plating (32) is applied to the entire surface of the conductor circuit, and then electroless nickel plating is performed. (32) forms a solder resist (30) at a required location on the surface by a known method,
The present invention has been completed by newly discovering that appropriate gold plating gives good results.

(発明が解決しようとする課題) 本発明は以上のような経緯に基ずいてなされたもので、
その解決しようとする問題点は、特に金ワイヤー(40)に
よりワイヤーボンディング実装を行う際のチップオンボ
ード(100)用ニッケルメッキ層に起因するワイヤーボン
ディング性の悪さ、及びチップオンボード(100)自体の
信頼性の低さである。
(Problems to be Solved by the Invention) The present invention has been made based on the above circumstances,
The problem to be solved is a poor wire bonding property due to the nickel-plated layer for the chip-on-board (100) when performing wire bonding mounting with the gold wire (40), and the chip-on-board (100) itself. Is unreliable.

そして、本発明の目的とするところは、ワイヤーボンデ
ィング性がよいことは勿論、ソルダーレジスト(30)剥が
れ不良や導体回路の腐食、銅マイグレーションの心配が
不要であり、しかもスルーホール(60)部にソルダーレジ
スト(30)を形成した場合にあってもスルーホール(60)の
信頼性が高く、さらに、従来から採用されている機械・
設備をもそのまま使用して製造することができる安価で
高信頼性のチップオンボードを提供することにある。
And the purpose of the present invention is, of course, that the wire bonding property is good, there is no need to worry about solder resist (30) peeling failure, conductor circuit corrosion, copper migration, and moreover, through holes (60) Even if the solder resist (30) is formed, the reliability of the through hole (60) is high.
It is to provide an inexpensive and highly reliable chip-on-board that can be manufactured by using the equipment as it is.

(課題を解決するための手段) 以上の問題点を解決するために本発明が採った手段を実
施例に対応する第1図を参照して説明すると、「導体回
路(20)が形成されてベアチップ半導体素子(50)等が搭載
実装されるチップオンボード(100)において、前記導体
回路(20)の全面には無電解ニッケルメッキ(32)が形成さ
れ、さらに無電解ニッケルメッキ(32)の表面上に必要箇
所にソルダーレジスト(30)が形成されていることを特徴
とするチップオンボード(100)」である。
(Means for Solving the Problems) The means adopted by the present invention for solving the above problems will be described with reference to FIG. 1 corresponding to the embodiment, in which “a conductor circuit (20) is formed. In the chip-on-board (100) on which the bare chip semiconductor element (50) and the like are mounted and mounted, the electroless nickel plating (32) is formed on the entire surface of the conductor circuit (20), and the electroless nickel plating (32) The chip-on-board (100) is characterized in that a solder resist (30) is formed on the surface at a required position.

この構成を図面に示した具体例に従ってさらに詳しく説
明すると、第1図には本発明に係るチップオンボード(1
00)の縦断面図が示してある。このチップオンボード(10
0)は導体回路(20)が形成され、導体回路(20)の全面に無
電解ニッケルメッキ層(32)が設けてある。そして、無電
解ニッケルメッキ(32)の表面上の必要箇所にソルダーレ
ジスト(30)が形成してあり、また適宜金メッキ(31)が施
してある。ここで金メッキ層(31)は、ベアチップ半導体
素子(50)等を搭載もしくはワイヤーボンディング等の接
続を行う端子(24)部にのみ施してあり、これらの部分
は、ソルダーレジスト(30)を形成しない部分であること
は勿論である。そして、無電解ニッケルメッキ層(32)
は、前記部品を搭載もしくは接続を行う端子(24)部は勿
論、ソルダーレジスト(30)を形成したスルーホール(60)
を含む導体回路(20)の全面上に形成されている。
This configuration will be described in more detail with reference to the specific examples shown in the drawings. FIG. 1 shows the chip-on-board (1
00) is shown in vertical section. This chip on board (10
In 0), the conductor circuit (20) is formed, and the electroless nickel plating layer (32) is provided on the entire surface of the conductor circuit (20). Then, a solder resist (30) is formed on a required portion of the surface of the electroless nickel plating (32), and a gold plating (31) is appropriately applied. Here, the gold plating layer (31) is applied only to the terminal (24) portion for mounting the bare chip semiconductor element (50) or the like or for connection such as wire bonding, and these portions do not form the solder resist (30). Of course, it is a part. And electroless nickel plating layer (32)
Is a through hole (60) in which a solder resist (30) is formed, as well as a terminal (24) part for mounting or connecting the above components.
Is formed on the entire surface of the conductor circuit (20) including.

なお、このように形成したチップオンボード(100)に対
してはベアチップ半導体素子(50)等を搭載し、ボンディ
ングワイヤー(40)等により接続を行い、しかるのち必要
箇所を図面中に点線で示したように適宜樹脂封止(70)を
行うのである。
Note that the chip-on-board (100) thus formed is mounted with a bare chip semiconductor element (50) or the like, and is connected by a bonding wire (40) or the like, and then necessary parts are shown by dotted lines in the drawing. As described above, the resin sealing (70) is appropriately performed.

(発明の作用) 本発明は、以上のような手段を採ることによって以下の
ような作用がある。
(Operation of the Invention) The present invention has the following effects by adopting the above means.

すなわち、まず無電解ニッケルメッキ(32)の表面上の必
要箇所に導体回路(20)を形成し、導体回路(20)の全面に
無電解ニッケルメッキ(32)を施し、しかる後所望のソル
ダーレジスト(30)を公知の方法により形成し適宜金メッ
キを施した場合にあっては、ソルダーレジスト(30)を形
成する前工程で無電解ニッケルメッキ(32)が施されるわ
けであり、当然ソルダーレジスト(30)が触媒工程におけ
る数10%の塩酸に曝されることがない。従って、ソル
ダーレジスト(30)が塩酸により浮き上がり、剥がれ不良
となることはないのである。この場合のソルダーレジス
ト(30)の種類としては、特に耐薬品性の優れたものであ
る必要はなく、一般の耐金メッキ浴用のものの使用が可
能である。そして、本発明のニッケルのメッキ方法をニ
ッケルリン浴による無電解メッキ法に限定し、その生成
したニッケルが非晶質の析出状態であって、他のメッキ
と異なる安定な薄い、しかも酸化が進行しない酸化皮膜
のもつ性質であることを利用することによって、導体回
路の全面に無電解ニッケルメッキ(32)を施し、いかる後
ソルダーレジスト(30)を形成し適宜金メッキ(31)を施し
た場合にあっても、ソルダーレジスト(30)剥がれや金剥
がれが発生しないものとすることもできる。
That is, first, a conductor circuit (20) is formed at a required position on the surface of the electroless nickel plating (32), the electroless nickel plating (32) is applied to the entire surface of the conductor circuit (20), and then a desired solder resist is formed. When (30) is formed by a known method and is appropriately plated with gold, electroless nickel plating (32) is performed in the step before forming the solder resist (30), and naturally the solder resist is used. (30) is not exposed to several 10% hydrochloric acid in the catalytic step. Therefore, the solder resist (30) is not lifted by the hydrochloric acid and is not peeled off. In this case, the type of the solder resist (30) does not need to be particularly excellent in chemical resistance, and a general resist for gold plating bath can be used. Then, the nickel plating method of the present invention is limited to the electroless plating method using a nickel phosphorus bath, and the produced nickel is in an amorphous deposition state, which is stable and thin unlike other plating, and oxidation progresses. By utilizing the property of the oxide film that does not exist, electroless nickel plating (32) is applied to the entire surface of the conductor circuit, and after the solder resist (30) is formed, gold plating (31) is appropriately applied. Even if there is, peeling of the solder resist (30) or peeling of gold may not occur.

また、導体回路(20)のソルダーレジスト(30)の下地部の
ほか、ソルダーレジスト(30)で覆われたスルーホール(6
0)部においても全面無電解ニッケルメッキ(32)層が施さ
れているため、導体回路(20)である銅の腐食、銅マイグ
レーションの心配が不要であり、スルーホール(60)部の
信頼性も高いものとなっている。
In addition to the base of the solder resist (30) of the conductor circuit (20), the through hole (6) covered with the solder resist (30)
Since the electroless nickel plating (32) layer is applied to the entire surface (0), there is no need to worry about copper corrosion or copper migration, which is the conductor circuit (20), and the reliability of the through hole (60) is high. Is also high.

さらに、ニッケルのメッキ方法は無電解メッキ法である
ので、導体回路の配線形状によるニッケルメッキの厚み
のバラツキが小さく、異常な形状に析出し難く、そのた
めワイヤーボンディング性が良いことは勿論である。
Further, since the nickel plating method is an electroless plating method, variations in the thickness of the nickel plating due to the wiring shape of the conductor circuit are small, and it is difficult for the nickel plating to deposit in an abnormal shape. Therefore, it goes without saying that the wire bonding property is good.

(実施例) 次に、本発明に係るチップオンボード(100)を、図面に
示した実施例に従って詳細に説明する。
(Example) Next, a chip on board (100) according to the present invention will be described in detail according to an example shown in the drawings.

第1図は、本発明にの実施例に係るチップオンボード(1
00)の縦断面図が示してあり、このチップオンボード(10
0)の導体回路(20)は公知の方法により、ベアチップ半導
体素子(50)を搭載するダイパット部(23)、ボンディング
ワイヤー(40)によりベアチップ半導体素子(50)とワイヤ
ーボンディング接続を行うボンディング端子(24)部、そ
して電気的な回路としての導体回路(20)及びスルーホー
ル(60)が接続、あるいは独立したものとして適宜形成し
てある。そしてソルダーレジスト(30)、無電解ニッケル
メッキ(32)及び金メッキ(31)は以下の工程順で形成され
ている。即ち、先ず、前記導体回路(20)の全面に無電
解ニッケルメッキ(32)を施す。次に、ソルダーレジス
ト(30)を公知の方法で無電解ニッケルメッキ(32)の表面
上の必要箇所に箇所に形成する。そして金メッキ層(3
1)を適宜施すのである。
FIG. 1 shows a chip on board (1 according to an embodiment of the present invention.
00) is shown in vertical section, and this chip on board (10
The conductor circuit (20) of (0) is a known method, a die pad part (23) for mounting the bare chip semiconductor element (50), and a bonding terminal (23) for performing wire bonding connection with the bare chip semiconductor element (50) by a bonding wire (40). The portion 24) and the conductor circuit (20) as an electric circuit and the through hole (60) are appropriately formed as connected or independent. The solder resist (30), the electroless nickel plating (32) and the gold plating (31) are formed in the following process order. That is, first, electroless nickel plating (32) is applied to the entire surface of the conductor circuit (20). Next, the solder resist (30) is formed on the surface of the electroless nickel plating (32) at a necessary place by a known method. And the gold plating layer (3
1) is applied appropriately.

従って、金メッキ層(31)は前記ソルダーレジスト(30)を
形成していない部分のみとなり、また無電解ニッケルメ
ッキ層(32)は、金メッキ層(31)の下地導体回路(20)上に
施されていることは勿論、ソルダーレジスト(30)の下地
導体回路(20)上及びスルーホール(60)上にも施されたも
のとなっている。
Therefore, the gold plating layer (31) is only a portion where the solder resist (30) is not formed, and the electroless nickel plating layer (32) is applied on the underlying conductor circuit (20) of the gold plating layer (31). Of course, it is also applied on the underlying conductor circuit (20) and the through hole (60) of the solder resist (30).

なお、このように形成したチップオンボード(100)に対
してはベアチップ半導体素子(50)等を搭載し、ボンディ
ングワイヤー(40)等により接続を行い、しかるのち必要
箇所を図面中に点線で示したように適宜樹脂封止(70)を
行う。
Note that the chip-on-board (100) thus formed is mounted with a bare chip semiconductor element (50) or the like, and is connected by a bonding wire (40) or the like, and then necessary parts are shown by dotted lines in the drawing. As described above, the resin sealing (70) is appropriately performed.

(発明の効果) 以上詳述したように、本発明は、上記実施例にて例示し
た如く、「導体回路が形成されてベアチップ半導体素子
等が搭載実装されるチップオンボードにおいて、前記導
体回路の全面には無電解ニッケルメッキが形成され、さ
らに無電解ニッケルメッキ(32)の表面上の必要箇所にソ
ルダーレジストが形成されていることを特徴とするチッ
プオンボード」にその構成上の特徴があり、これによ
り、ワイヤーボンディング性がよいことは勿論、ソルダ
ーレジスト(30)剥がれ不良や導体回路(20)の腐食、銅マ
イグレーションの心配が不要であり、しかもスルーホー
ル(60)部にソルダーレジスト(30)を形成した場合であっ
てもスルーホール(60)の信頼性が高く、さらに、従来か
ら採用されている機械・設備をもそのまま使用して製造
することができる安価で、高信頼性のチップオンボード
を提供することができる。
(Effects of the Invention) As described in detail above, the present invention, as exemplified in the above-described embodiment, "in a chip on board in which a conductor circuit is formed and a bare chip semiconductor element or the like is mounted and mounted, "Electronic nickel plating is formed on the entire surface, and solder resist is formed on necessary parts on the surface of the electroless nickel plating (32)." As a result, there is no need to worry about wire resisting properties, solder resist (30) peeling defects, corrosion of conductor circuit (20), and copper migration. ) Is formed, the through hole (60) is highly reliable, and it is possible to manufacture using the machinery and equipment that have been conventionally adopted as they are. It is possible to provide an inexpensive, highly reliable chip-on-board.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例に係るチップオンボードの縦断
面図である。 なお、第2図及び第3図はそれぞれ従来のチップオンボ
ードの問題点であるイカリ肩、金ボールを説明するため
の縦断面図であり、第4図は従来のチップオンボードで
あってソルダーレジストを形成したスルーホール部にニ
ッケル層がないことを説明するための縦断面図である。 符号の説明 20……導体回路、30……ソルダーレジスト、31……金メ
ッキ層、32……無電解ニッケルメッキ層、40……ボンデ
ィングワイヤー、50……ベアチップ半導体素子、60……
スルーホール、70……樹脂封止、80……イカリ肩、90…
…金ボール、100……チップオンボード。
FIG. 1 is a vertical sectional view of a chip on board according to an embodiment of the present invention. 2 and 3 are vertical cross-sectional views for explaining the problem of the conventional chip-on-board, that is, the squid shoulder and the gold ball, and FIG. 4 is the conventional chip-on-board and the solder. It is a longitudinal cross-sectional view for explaining that there is no nickel layer in a through hole portion where a resist is formed. Explanation of symbols 20 …… Conductor circuit, 30 …… Solder resist, 31 …… Gold plating layer, 32 …… Electroless nickel plating layer, 40 …… Bonding wire, 50 …… Bare chip semiconductor element, 60 ……
Through hole, 70 ... Resin sealing, 80 ... Squid shoulder, 90 ...
… Gold balls, 100… Chip on board.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】導体回路が形成されてベアチップ半導体素
子等が搭載実装されるチップオンボードにおいて、 前記導体回路の全面には無電解ニッケルメッキが形成さ
れ、さらに、該無電解ニッケルメッキの表面上の必要箇
所にソルダーレジストが形成されていることを特徴とす
るチップオンボード。
1. In a chip-on-board on which a conductor circuit is formed and a bare chip semiconductor element or the like is mounted and mounted, electroless nickel plating is formed on the entire surface of the conductor circuit, and further, on the surface of the electroless nickel plating. A chip-on-board, characterized in that a solder resist is formed in the required areas of.
JP63020086A 1988-01-29 1988-01-29 Chip on board Expired - Lifetime JPH0618220B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63020086A JPH0618220B2 (en) 1988-01-29 1988-01-29 Chip on board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63020086A JPH0618220B2 (en) 1988-01-29 1988-01-29 Chip on board

Publications (2)

Publication Number Publication Date
JPH01194428A JPH01194428A (en) 1989-08-04
JPH0618220B2 true JPH0618220B2 (en) 1994-03-09

Family

ID=12017295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63020086A Expired - Lifetime JPH0618220B2 (en) 1988-01-29 1988-01-29 Chip on board

Country Status (1)

Country Link
JP (1) JPH0618220B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810201Y2 (en) * 1990-03-27 1996-03-27 日本電気株式会社 Package for semiconductor device
JP3389357B2 (en) * 1994-11-29 2003-03-24 新光電気工業株式会社 Substrate for mounting semiconductor chips

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0770816B2 (en) * 1986-11-19 1995-07-31 ソニー株式会社 Circuit board manufacturing method

Also Published As

Publication number Publication date
JPH01194428A (en) 1989-08-04

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