JPH0770816B2 - Circuit board manufacturing method - Google Patents

Circuit board manufacturing method

Info

Publication number
JPH0770816B2
JPH0770816B2 JP27631486A JP27631486A JPH0770816B2 JP H0770816 B2 JPH0770816 B2 JP H0770816B2 JP 27631486 A JP27631486 A JP 27631486A JP 27631486 A JP27631486 A JP 27631486A JP H0770816 B2 JPH0770816 B2 JP H0770816B2
Authority
JP
Japan
Prior art keywords
layer
plating
circuit board
resist
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP27631486A
Other languages
Japanese (ja)
Other versions
JPS63128788A (en
Inventor
三輝也 小林
英徳 林田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WORLD METAL CO., LTD.
Sony Corp
Original Assignee
WORLD METAL CO., LTD.
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WORLD METAL CO., LTD., Sony Corp filed Critical WORLD METAL CO., LTD.
Priority to JP27631486A priority Critical patent/JPH0770816B2/en
Publication of JPS63128788A publication Critical patent/JPS63128788A/en
Publication of JPH0770816B2 publication Critical patent/JPH0770816B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば半導体装置の製造の際使用する回路基
板の製法に関する。The present invention relates to a method for manufacturing a circuit board used for manufacturing a semiconductor device, for example.

〔発明の概要〕[Outline of Invention]

本発明は、回路基板の製法であり、無電解Auメッキを施
す前に下層のNi層の外周部がレジストで被覆されるよう
にレジスト層を形成しておくことにより、メッキ中にお
けるCuパターンの侵食を防止することができるようにし
たものである。The present invention is a method of manufacturing a circuit board, by forming a resist layer so that the outer peripheral portion of the lower Ni layer is covered with a resist before performing electroless Au plating, thereby forming a Cu pattern during plating. It is designed to prevent erosion.

〔従来の技術〕[Conventional technology]

従来、プリント基板や銅厚膜基板にAuのワイヤボンディ
ングを行うために、電気メッキ用のリードを引き回し、
メッキ部以外をレジストで覆った後、NiとAuを順に電気
メッキしていた。しかし、この方法による場合、メッキ
用リードを形成しなければならず、パターンの微細化と
超高密度実装化に対応できないという問題点があった。
また、ボンディングパッド部のみにNiとAuの電気メッキ
を施すと、チップ部品を実装するためのランドにおいて
Cuパターンが露出するため、半田ぬれ性が劣化したり、
保存期間が短くなるという問題点が生じていた。そこ
で、このような問題点を解決するために、近年無電解の
NiとAuのメッキによるボンディングパッドの形成が提案
されている。Conventionally, in order to perform Au wire bonding on a printed circuit board or a copper thick film substrate, a lead for electroplating is laid out,
After covering the parts other than the plated part with a resist, Ni and Au were sequentially electroplated. However, according to this method, it is necessary to form a lead for plating, and there is a problem that it is not possible to cope with the miniaturization of the pattern and the ultra-high-density mounting.
In addition, if Ni and Au are electroplated only on the bonding pad section, the land for mounting chip components
Since the Cu pattern is exposed, solder wettability deteriorates,
There has been a problem that the storage period is shortened. Therefore, in order to solve such problems, in recent years electroless
It has been proposed to form bonding pads by plating Ni and Au.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

第２図に示すように、上述した無電解メッキによるボン
ディングパッド(1)の形成は、絶縁基板(2)上にCuパター
ン(3)を形成した後、開口部(4)を有するレジスト層(5)
を形成し、この開口部(4)にNi層(6)とAu層(7)を順に形
成することにより行っている。しかし、従来の製法によ
る場合、特にAuの無電解メッキの際、高温且つ高アルカ
リのメッキ液を使用するため、メッキ液がレジスト(5)
とNi層(6)の境界面を通ってCuを侵食することにより、C
uパターン(3)の欠損が生じ、実用化できなくなるという
問題が起きていた。As shown in FIG. 2, the formation of the bonding pad (1) by the electroless plating described above is performed by forming the Cu pattern (3) on the insulating substrate (2) and then forming the resist layer ((4)) having the opening (4). Five)
Is formed, and the Ni layer (6) and the Au layer (7) are sequentially formed in the opening (4). However, in the case of the conventional manufacturing method, since the high-temperature and high-alkali plating solution is used especially for the electroless plating of Au, the plating solution is the resist (5).
C by eroding Cu through the interface between the Cu and Ni layers (6)
There was a problem that the u pattern (3) was lost and could not be put to practical use.

本発明は、上記問題点を解決することができる回路基板
の製法を提供するものである。The present invention provides a method for manufacturing a circuit board that can solve the above problems.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る回路基板の製法においては、絶縁基板（1
1）上に形成されたCuパターン（12）上に開口部（14）
を有する永久レジスト層（15）を形成する工程と、開口
部（14）におけるCuパターン（12）上に無電解Niメッキ
を施してNi層（16）を形成する工程と、このNi層（16）
の外周部（18）がレジストで被覆されるようにメッキ用
のレジスト層（19）を形成する工程と、レジスト層（1
9）が形成されていないNi層（16）上の開口部（20）に
無電解Auメッキを施してAu層（21）を形成する工程と、
レジスト層（19）を除去してボンディングパッド（22）
を形成する工程を有する。In the method for manufacturing a circuit board according to the present invention, the insulating substrate (1
1) Opening (14) on the Cu pattern (12) formed on it
And a step of forming a permanent resist layer (15) having a layer, a step of forming an Ni layer (16) by electroless Ni plating on the Cu pattern (12) in the opening (14), and this Ni layer (16). )
A step of forming a resist layer (19) for plating so that the outer peripheral part (18) of the resist layer (18) is covered with the resist;
9) a step of forming an Au layer (21) by electroless Au plating on the opening (20) on the Ni layer (16) in which the Au layer (21) is not formed,
The resist layer (19) is removed and the bonding pad (22)
To form a.

上記製法において、レジスト（19）で被覆すべきNi層
（16）の外周部（18）の大きさは、無電解Auメッキの
際、高温と高アルカリのメッキ液によるCuパターン（1
2）の侵食を防ぐことができる大きさとする。In the above-mentioned manufacturing method, the size of the outer peripheral portion (18) of the Ni layer (16) to be covered with the resist (19) is such that the Cu pattern (1
It should be large enough to prevent the erosion of 2).

〔作用〕[Action]

本発明によれば、無電解Auメッキを行う際において、Ni
層（16）の外周部（18）に及んでメッキ用のレジスト層
（19）が形成されているため、この部分におけるレジス
トによって高温且つ高アルカリのメッキ液が永久レジス
ト層（15）とNi層（16）との境界面からCuパターン（1
2）に侵入するのを阻止することができる。According to the present invention, when performing electroless Au plating, Ni
Since the resist layer (19) for plating is formed so as to extend to the outer peripheral part (18) of the layer (16), the resist in this part allows the high-temperature and highly alkaline plating solution to be a permanent resist layer (15) and a Ni layer. From the interface with (16) Cu pattern (1
2) can be prevented from entering.

〔実施例〕〔Example〕

図面を参照して本発明の１実施例を説明する。 An embodiment of the present invention will be described with reference to the drawings.

先ず第１図Ａに示すように、絶縁基板（11）上にCuパタ
ーン（12）を形成した後、このCuパターン（12）上にチ
ップランドを形成すべき開口部（13）及びボンディング
パッドを形成すべき開口部（14）を除いて永久レジスト
層（15）を形成する。First, as shown in FIG. 1A, after forming a Cu pattern (12) on an insulating substrate (11), an opening (13) for forming a chip land and a bonding pad are formed on this Cu pattern (12). A permanent resist layer (15) is formed except for the opening (14) to be formed.

次に第１図Ｂに示すように、開口部（13），（14）にお
けるCuパターン（12）上に中性液中で無電解メッキを施
して厚さ0.1〜10μのNi層（16）を形成する。（17）は
チップ部品を実装するための半田付性の良いチップラン
ドである。Next, as shown in FIG. 1B, electroless plating is performed in a neutral solution on the Cu pattern (12) in the openings (13) and (14) to form a Ni layer (16) having a thickness of 0.1 to 10 μm. To form. (17) is a chip land with good solderability for mounting chip parts.

次に第１図Ｃに示すように、ボンディングパッドを形成
すべき開口部（14）において、Ni層（16）の外周部（1
8）もレジストで被覆されるようにその他の開口部（1
3）上と永久レジスト層（15）上にメッキ用のレジスト
層（19）を形成する。（20）は、このレジスト層（19）
によって形成されたNi層（16）上の開口部である。Next, as shown in FIG. 1C, in the opening (14) where the bonding pad is to be formed, the outer peripheral portion (1) of the Ni layer (16) is formed.
8) Other openings (1 to be covered with resist)
3) A resist layer (19) for plating is formed on and on the permanent resist layer (15). (20) This resist layer (19)
Is an opening on the Ni layer (16) formed by.

次に第１図Ｄに示すように、下記組成より成るメッキ液
を使用してこの開口部（20）に無電解Auメッキを施し、
厚さ0.1〜２μのAu層（21）を形成する。Next, as shown in FIG. 1D, electroless Au plating is applied to the opening (20) using a plating solution having the following composition,
An Au layer (21) having a thickness of 0.1 to 2 μ is formed.

〈メッキ液の組成〉 メッキ液の温度は、75〜80℃である。<Composition of plating solution> The temperature of the plating solution is 75-80 ° C.

次に第１図Ｅに示すように、レジスト層（19）を除去す
ることにより、ボンディングパッド（22）を形成し、本
実施例に係る回路基板（23）を作製する。Next, as shown in FIG. 1E, the resist layer (19) is removed to form a bonding pad (22), and a circuit board (23) according to this embodiment is manufactured.

〔発明の効果〕〔The invention's effect〕

本発明によれば、無電解メッキでボンディングパッドを
形成する際、特にAu層を形成するためのメッキ液による
Cuパターンの侵食を防止することができる。これによ
り、半導体装置の微細化に対応することが可能になる。
また、チップランドの半田付性を良好にすることがで
き、更に回路基板の保存期間を延ばすこともできる。従
って、本発明によれば超高密度ダイレクトボンディング
用の回路基板が得られる。According to the present invention, when a bonding pad is formed by electroless plating, a plating solution for forming an Au layer is used.
Erosion of Cu pattern can be prevented. As a result, it becomes possible to cope with the miniaturization of the semiconductor device.
In addition, the solderability of the chip land can be improved, and the storage period of the circuit board can be extended. Therefore, according to the present invention, a circuit board for ultra-high density direct bonding can be obtained.

【図面の簡単な説明】[Brief description of drawings]

第１図は実施例の工程図、第２図は従来例の断面図であ
る。 （11）は絶縁基板、（12）はCuパターン、（14）は開口
部、（15）は永久レジスト層、（16）はNi層、（18）は
外周部、（19）はレジスト層、（20）は開口部、（21）
はAu層、（22）はボンディングパッド、（23）は回路基
板である。FIG. 1 is a process drawing of the embodiment, and FIG. 2 is a sectional view of a conventional example. (11) is an insulating substrate, (12) is a Cu pattern, (14) is an opening, (15) is a permanent resist layer, (16) is a Ni layer, (18) is an outer peripheral portion, (19) is a resist layer, (20) is the opening, (21)
Is an Au layer, (22) is a bonding pad, and (23) is a circuit board.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】絶縁基板上に形成されたCuパターン上に開
口部を有する永久レジスト層を形成する工程と、 上記開口部における上記Cuパターン上に無電解Niメッキ
を施してNi層を形成する工程と、 上記Ni層の外周部がレジストで被覆されるようにレジス
ト層を形成する工程と、 上記レジスト層が形成されていない上記Ni層上の開口部
に無電解Auメッキを施してAu層を形成する工程と、 上記レジスト層を除去してボンディングパッドを形成す
る工程 を有する回路基板の製法。1. A step of forming a permanent resist layer having an opening on a Cu pattern formed on an insulating substrate, and electroless Ni plating on the Cu pattern in the opening to form a Ni layer. A step of forming a resist layer so that the outer peripheral portion of the Ni layer is covered with a resist, and an electroless Au plating is applied to the opening on the Ni layer where the resist layer is not formed to form an Au layer. And a step of forming the bonding pad by removing the resist layer.
JP27631486A 1986-11-19 1986-11-19 Circuit board manufacturing method Expired - Fee Related JPH0770816B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27631486A JPH0770816B2 (en) 1986-11-19 1986-11-19 Circuit board manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27631486A JPH0770816B2 (en) 1986-11-19 1986-11-19 Circuit board manufacturing method

Publications (2)

Publication Number Publication Date
JPS63128788A JPS63128788A (en) 1988-06-01
JPH0770816B2 true JPH0770816B2 (en) 1995-07-31

Family

ID=17567726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27631486A Expired - Fee Related JPH0770816B2 (en) 1986-11-19 1986-11-19 Circuit board manufacturing method

Country Status (1)

Country Link
JP (1) JPH0770816B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618220B2 (en) * 1988-01-29 1994-03-09 イビデン株式会社 Chip on board
JPH0271590A (en) * 1988-09-06 1990-03-12 Mitsubishi Electric Corp Substrate for hybrid ic
JPH03173144A (en) * 1989-11-30 1991-07-26 Nippon Micron Kk Board for bonding and electroless gold plating for bonding
US5235139A (en) * 1990-09-12 1993-08-10 Macdermid, Incorprated Method for fabricating printed circuits
JP2008118162A (en) * 2008-01-29 2008-05-22 Ibiden Co Ltd Printed wiring board

Also Published As

Publication number Publication date
JPS63128788A (en) 1988-06-01

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