WO2021102633A1 - 阵列基板、控光面板和显示装置 - Google Patents

阵列基板、控光面板和显示装置 Download PDF

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Publication number
WO2021102633A1
WO2021102633A1 PCT/CN2019/120635 CN2019120635W WO2021102633A1 WO 2021102633 A1 WO2021102633 A1 WO 2021102633A1 CN 2019120635 W CN2019120635 W CN 2019120635W WO 2021102633 A1 WO2021102633 A1 WO 2021102633A1
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WIPO (PCT)
Prior art keywords
signal line
wiring portion
line
width
array substrate
Prior art date
Application number
PCT/CN2019/120635
Other languages
English (en)
French (fr)
Inventor
张瑞锋
高锦成
姜涛
张冠永
Original Assignee
京东方科技集团股份有限公司
合肥京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 合肥京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/120635 priority Critical patent/WO2021102633A1/zh
Priority to US16/977,319 priority patent/US11892735B2/en
Priority to CN201980002573.9A priority patent/CN113179654B/zh
Publication of WO2021102633A1 publication Critical patent/WO2021102633A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1347—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells
    • G02F1/13471—Arrangement of liquid crystal layers or cells in which the final condition of one light beam is achieved by the addition of the effects of two or more layers or cells in which all the liquid crystal cells or layers remain transparent, e.g. FLC, ECB, DAP, HAN, TN, STN, SBE-LC cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a light control panel, and a display device.
  • the liquid crystal display device includes a backlight module (backlight unit) and a liquid crystal panel.
  • the backlight module is arranged on the non-display side of the liquid crystal panel to provide a light source for the display operation of the display panel.
  • the liquid crystal panel includes a polarizer, an array substrate, a counter substrate, and a layer of liquid crystal molecules filled between the two substrates.
  • the liquid crystal display device deflects the liquid crystal molecules in the liquid crystal molecule layer by forming an electric field between the array substrate and the opposite substrate, and the deflected liquid crystal molecules cooperate with the polarizer to form a liquid crystal light valve. Since the liquid crystal molecular layer itself does not emit light, it is necessary to use a backlight module to realize the display function. With the continuous development of display technology, users have put forward higher and higher requirements for the contrast, brightness uniformity, and reliability of the display device.
  • At least one embodiment of the present disclosure provides an array substrate including: a first signal line for sub-pixel rows extending in a first direction as a whole, and a second signal line for sub-pixel rows extending in a whole along the first direction.
  • the second signal line of the sub-pixel column extending in the direction.
  • the first signal line includes a plurality of broken line structures directly connected in sequence, and each of the plurality of broken line structures includes a first wiring portion, a second wiring portion, and a third wiring portion that are directly connected in sequence;
  • the extension direction of the first wiring portion and the extension direction of the third wiring portion both intersect the first direction and the second direction, and the second wiring portion extends along the first direction;
  • a center line of the first wiring portion extending along the extending direction of the first wiring portion and a center line of the second wiring portion extending along the extending direction of the second wiring portion intersect to form a first included angle;
  • the second wiring portion includes a first side and a second side opposite to each other in the second direction, the first side is located inside the first included angle and the second side is located at the The outer side of the first included angle;
  • the side of the first wiring part close to the second signal line intersects the first side at the first position of the first side, and the third wiring part
  • the edge close to the second signal line intersects the first edge at the second position of
  • the third position and the fourth position are both located between the first position and the second position.
  • the second signal line includes a first line segment; the first line segment is the second signal line located between the first wiring and the second signal line.
  • the portion between the two wires; and the first wire segment and the third wire portion are inclined in the same direction with respect to the second direction.
  • the third position is located between a first midpoint and the first position, and the first midpoint is an edge of the first side located at the first position.
  • the first signal line is a gate line; the inclination angle of the third wiring part with respect to the second direction is greater than that of the first line segment with respect to the The inclination angle of the second direction is three times and less than four times the inclination angle of the first line segment with respect to the second direction; the second signal line is a data line and the width of the first wiring part is greater than the The second signal line has twice the width of the second signal line and is less than three times the width of the second signal line, or the second signal line is a common electrode line and the width of the first wiring portion is greater than that of the second signal line Three times the width and less than four times the width of the second signal line; and the width of the first trace portion is less than the length of the second side and greater than the first side at the first position and The length of the line segment between the second positions.
  • the third position coincides with the first position.
  • the width of the first wiring portion is equal to the width of the third wiring portion; the width of the second wiring portion is greater than the width of the first wiring portion
  • the width of the part is less than twice the width of the first wiring part.
  • the third position is located between the first midpoint and the second position; the first midpoint is the edge of the first side located in the first The midpoint of the line segment between the position and the second position; and the side of the orthographic projection of the second signal line on the electrode layer where the first signal line is close to the first wiring part and the The orthographic projection of the intersection of the second side on the first side is located on the side of the first midpoint away from the third position.
  • the first signal line is a gate line; the inclination angle of the third wiring part with respect to the second direction is greater than that of the first line segment with respect to the The inclination angle of the second direction is three times and less than four times the inclination angle of the first line segment with respect to the second direction; the second signal line is a data line and the width of the first wiring part is greater than the The second signal line has twice the width of the second signal line and is less than three times the width of the second signal line, or the second signal line is a common electrode line and the width of the first wiring portion is greater than that of the second signal line Three times the width and less than four times the width of the second signal line; the width of the first trace portion is greater than the length of the second side; and the width of the second trace portion is greater than that of the first The width of the wiring portion is twice and less than three times the width of the first wiring portion.
  • the third position is located at a first midpoint, and the first midpoint is between the first position and the second position of the first side.
  • the midpoint of the line segment between.
  • the width of the second wiring portion is greater than the width of the first wiring portion and the width of the third wiring portion; and the first wiring The width of the part is equal to the width of the third wiring part.
  • the fourth position coincides with the second position.
  • the slope angle of at least one of the first signal line and the second signal line is between 40 degrees and 60 degrees.
  • At least one embodiment of the present disclosure further provides a light control panel, which includes: a counter substrate, a liquid crystal layer, and any array substrate provided in at least one embodiment of the present disclosure.
  • the array substrate and the counter substrate are arranged oppositely, and the liquid crystal layer is sandwiched between the array substrate and the counter substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes: a display panel, a backlight unit, and any light control panel provided in at least one embodiment of the present disclosure.
  • the display panel, the light control panel, and the backlight unit are stacked, the display panel is located on the light exit side of the light control panel, and the backlight unit is located on the side of the light control panel away from the display panel .
  • 1A is a schematic cross-sectional view of a liquid crystal display device
  • FIG. 1B shows a schematic plan view of the light control panel and the display panel of the liquid crystal display device shown in FIG. 1A;
  • FIG. 2A shows a schematic plan view of a display panel of the liquid crystal display device shown in FIG. 1A;
  • FIG. 2B shows a schematic plan view of the array substrate of the light control panel of the liquid crystal display device shown in FIG. 1A;
  • 3A is a schematic plan view of the light control pixel unit of the array substrate shown in FIG. 2B;
  • FIG. 3B is an enlarged view of the part of the gate line located in the first region of the array substrate shown in FIG. 2B;
  • 3C is an enlarged view of a portion of a gate line located in a second area of the array substrate shown in FIG. 2B;
  • 3D shows a schematic diagram of a short circuit caused by electrostatic breakdown in the overlapping area between the data line and the gate line;
  • 3E shows a schematic diagram of a short circuit caused by electrostatic breakdown in the overlapping area between the common electrode line and the gate line of the data line;
  • 4A is a schematic plan view of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4B is a schematic plan view of the light control pixel unit of the array substrate shown in FIG. 4A;
  • 5A is a schematic diagram of an example of a portion of the first signal line located in the first area of the array substrate shown in FIG. 4A;
  • 5B is a schematic diagram of an example of a portion of the first signal line located in the second area of the array substrate shown in FIG. 4A;
  • 5C is another schematic diagram of the example of the part of the first signal line shown in FIG. 5A;
  • 5D is another schematic diagram of the example of the part of the first signal line shown in FIG. 5B;
  • 6A is a schematic diagram of an overlapping triangle between the first signal line and the second signal line;
  • 6B is a schematic diagram of an overlapping triangle between the first signal line and the third signal line;
  • FIG. 7A is a simplified schematic diagram of the overlapping triangle between the first signal line and the second signal line shown in FIG. 6A when the second signal line has no alignment error with respect to the first signal line;
  • 7B is an equivalent schematic diagram of the overlapping triangle between the first signal line and the second signal line shown in FIG. 6A when the second signal line has no alignment error with respect to the first signal line;
  • FIG. 7C is a case where the second signal line has a horizontal alignment error with respect to the first signal line but does not have a vertical alignment error, the equivalent of the overlapping triangle between the first signal line and the offset second signal line Effective schematic diagram;
  • FIG. 7D is an equivalent schematic diagram of the overlapping triangle between the first signal line and the offset second signal line when the second signal line has a horizontal alignment error and a vertical alignment error relative to the first signal line ;
  • 8A is a simplified schematic diagram of the overlapping triangle between the first signal line and the third signal line shown in FIG. 6B when the third signal line has no alignment error with respect to the first signal line;
  • 8B is an equivalent schematic diagram of the overlapping triangle between the first signal line and the third signal line shown in FIG. 6B when the third signal line has no alignment error with respect to the first signal line;
  • FIG. 8C is a case where the third signal line has a horizontal alignment error with respect to the first signal line but does not have a vertical alignment error, the equivalent of the overlapping triangle between the first signal line and the shifted third signal line Effective schematic diagram;
  • FIG. 8D is an equivalent schematic diagram of the overlapping triangle between the first signal line and the offset third signal line when the third signal line has a horizontal alignment error and a vertical alignment error relative to the first signal line ;
  • FIG. 9A is a schematic diagram of another example of the portion of the first signal line located in the first region of the array substrate shown in FIG. 4A;
  • 9B is a schematic diagram of another example of the portion of the first signal line located in the second area of the array substrate shown in FIG. 4A;
  • FIG. 9C is another schematic diagram of an example of the part of the first signal line shown in FIG. 9A;
  • FIG. 9D is another schematic diagram of the example of the part of the first signal line shown in FIG. 9B;
  • 10A is another simplified schematic diagram of the overlapping triangle between the first signal line and the second signal line shown in FIG. 6A;
  • 10B is another simplified schematic diagram of the overlapping triangle between the first signal line and the third signal line shown in FIG. 6B;
  • FIG. 11A is a schematic diagram of still another example of the portion of the first signal line located in the first area of the array substrate shown in FIG. 4A; FIG.
  • FIG. 11B is a schematic diagram of another example of the portion of the first signal line located in the second area of the array substrate shown in FIG. 4A; FIG.
  • 11C is a schematic diagram of still another example of the portion of the first signal line located in the first region of the array substrate shown in FIG. 4A;
  • 11D is a schematic diagram of still another example of the portion of the first signal line located in the second area of the array substrate shown in FIG. 4A;
  • 12A is a schematic cross-sectional view of the signal line when the slope angle of the signal line is small;
  • 12B is a schematic diagram of undercutting caused by etching deviation when the slope angle of the signal line is relatively large;
  • FIG. 13 is a schematic cross-sectional view of a light control panel provided by at least one embodiment of the present disclosure.
  • FIG. 14 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure.
  • 15A is a schematic plan view of the display panel of the display device shown in FIG. 14;
  • FIG. 15B is a schematic plan view of the display device shown in FIG. 14.
  • the inventors of the present disclosure have noticed in their research that the display panels of ordinary liquid crystal display devices (for example, liquid crystal display devices based on advanced super-dimensional field conversion technology with a single liquid crystal cell) usually have a dark state light leakage problem, which makes the liquid crystal display The contrast of the display screen of the device is low.
  • the inventor of the present disclosure has noticed in research that a liquid crystal display device with dual liquid crystal cells (that is, a liquid crystal display device based on the dual liquid crystal cell area brightness adjustment technology) can be used to improve the contrast of the display screen.
  • a liquid crystal display device with dual liquid crystal cells that is, a liquid crystal display device based on the dual liquid crystal cell area brightness adjustment technology
  • FIG. 1A shows a schematic cross-sectional view of a liquid crystal display device 500.
  • the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502, and a display panel 501 that are sequentially arranged in the third direction D3.
  • the light control panel 502 is configured to adjust the intensity of light emitted by the backlight unit 503 and incident on the display panel 501.
  • the light emitted from the light control panel 502 is white light, that is, the light control panel 502 does not have a color adjustment function.
  • FIG. 1B shows a schematic plan view of the light control panel 502 and the display panel 501 of the liquid crystal display device 500 shown in FIG. 1A;
  • FIG. 2A shows a schematic plan view of the display panel 501 of the liquid crystal display device 500 shown in FIG. 1A;
  • 2B shows a schematic plan view of the array substrate of the light control panel 502 of the liquid crystal display device 500 shown in FIG. 1A.
  • the display panel 501 includes a plurality of first signal lines 541 extending in a first direction D1 and a plurality of second signal lines 542 extending in a second direction D2; a plurality of first signal lines 541 It intersects the plurality of second signal lines 542 to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 530 arranged in an array; each display pixel unit 530 includes a first display sub-pixel unit
  • the pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 are, for example, red display sub-pixels, respectively Unit, green display sub-pixel unit and blue display sub-pixel unit.
  • first direction D1, the second direction D2, and the third direction D3 intersect each other (for example, perpendicular to each other).
  • first signal line 541 is a gate line of the display panel 501
  • second signal line 542 is a data line of the display panel 501.
  • the light control panel 502 includes an array substrate (see FIG. 2B), a liquid crystal layer (not shown in the figure) and a counter substrate (not shown in the figure) which are sequentially arranged in the third direction D3.
  • the array substrate of the light control panel 502 includes a plurality of gate lines 510 respectively extending along the first direction D1 and a plurality of data lines 520 respectively extending along the second direction D2; The intersection of 510 and the plurality of data lines 520 defines a plurality of light-controlling pixel units 530.
  • the light control panel 502 further includes a plurality of common electrode lines 560 extending along the second direction D2, respectively.
  • the plurality of data lines 520 and the plurality of common electrode lines 560 are alternately arranged in the first direction D1.
  • the light control panel 502 includes a plurality of light control units (not shown in the figure) arranged in an array.
  • a plurality of light control pixel units 530 of the array substrate are respectively arranged in corresponding light control units.
  • the light control unit further includes a portion of the liquid crystal layer that overlaps the light control pixel unit in the third direction D3 and a portion of the opposite substrate.
  • the light control panel 502 can adjust the transmittance of each light control unit of the light control panel based on the data signal received by the data line 520. Therefore, the light control unit of the light control panel 502 can be used to control the incident light to the light control unit corresponding to the light control panel.
  • the display panel 501 of the unit displays the intensity of light on the sub-pixel unit, so the light control panel 502 can be used to provide the display panel 501 with adjusted backlight. For example, by providing the light control panel 502 in the display device 500, the transmittance of the light control unit corresponding to the region where the brightness of the display screen of the liquid crystal display device is low (for example, the brightness is zero) is low (for example, the transmittance The rate is equal to or close to zero).
  • a liquid crystal display device with dual liquid crystal cells that is, with The display device of the light control panel can improve the contrast of the displayed picture. For example, by providing the light control panel 502 in the display device 500, the contrast of the liquid crystal display device 500 can be increased from 1,000 to more than 40,000.
  • the inventor of the present disclosure has noticed in research that the appearance of the array substrate of the light control panel 502 of the liquid crystal display device 500 shown in FIG. 1 (for example, during the production process and/or use process) is caused by electrostatic discharge.
  • the possibility of failure is high, thereby reducing the yield and reliability of the liquid crystal display device 500.
  • the inventors of the present disclosure have noticed in the research (for example, by counting the positions of defects caused by electrostatic discharge in multiple array substrates) that the defects (for example, short circuits) caused by electrostatic discharge are at the overlap of the data line 520 and the gate line 510.
  • the area and the overlapping area of the common electrode line 560 and the gate line 510 are more likely to appear. Exemplary descriptions are given below in conjunction with FIGS. 1A-1B, 2A-2B, and 3A-3C.
  • each gate line 510 of the light control panel 502 includes a plurality of first fold line structures 515 directly connected in sequence, and each of the plurality of first fold line structures 515 includes a first line directly connected in sequence.
  • each data line 520 of the light control panel 502 includes a plurality of second fold line structures 521 directly connected in sequence, and each of the plurality of second fold line structures 521 includes a fifth line directly connected in sequence.
  • the wire portion 522 and the sixth wire portion 523 As shown in FIGS.
  • each common electrode line 560 of the light control panel 502 includes a plurality of third fold line structures 561 directly connected in sequence, and each of the plurality of third fold line structures 561 includes a seventh fold line structure directly connected in sequence.
  • FIG. 3A is a schematic plan view of the light control pixel unit 530 of the array substrate shown in FIG. 2B;
  • FIG. 3B is an enlarged view of a part of the gate line 510 located in the first region RE1 of the array substrate shown in FIG. 2B; The enlarged view of the portion of the gate line 510 in the second region RE2 of the array substrate shown in FIG. 2B.
  • the data line 520 and the gate line 510 overlap each other in a direction perpendicular to the array substrate, and have a first overlap area 581 (for example, an overlap triangle); the common electrode line 560 and the gate line 510 overlap each other in a direction perpendicular to the array substrate, and have a second overlap area 583 (for example, an overlap triangle).
  • first overlap area 581 for example, an overlap triangle
  • second overlap area 583 for example, an overlap triangle
  • FIG. 3D shows a schematic diagram of a short circuit caused by electrostatic breakdown in a portion 585 of the overlap region between the data line 520 and the gate line 510.
  • FIG. 3E shows a schematic diagram of a short circuit caused by electrostatic breakdown in a portion 586 of the overlap region between the data line common electrode line 560 and the gate line 510.
  • the yield and reliability of the array substrate and the light control panel and the liquid crystal display device including the array substrate are reduced. Therefore, there is an urgent need for an array substrate that can reduce the possibility of defects caused by electrostatic discharge.
  • At least one embodiment of the present disclosure provides an array substrate, a light control panel, and a display device.
  • the array substrate includes first signal lines for sub-pixel rows extending in a first direction as a whole, and second signal lines for sub-pixel columns extending in a second direction intersecting the first direction as a whole.
  • the first signal line includes a plurality of broken line structures directly connected in sequence, each of the plurality of broken line structures includes a first wiring portion, a second wiring portion, and a third wiring portion that are directly connected in sequence; the first wiring portion The extension direction of the third wiring part and the extension direction of the third wiring part intersect the first direction and the second direction, the second wiring part extends along the first direction; the first wiring part extends along the extension direction of the first wiring part The middle line and the middle line of the second wiring part extending along the extending direction of the second wiring part intersect to form a first included angle; the second wiring part includes a first side and a second side facing each other in the second direction.
  • One side is located on the inner side of the first included angle and the second side is located on the outer side of the first included angle; the side of the first wiring part close to the second signal line intersects the first side at the first position of the first side, and the third The side of the wiring part close to the second signal line intersects the first side at the second position of the first side; the orthographic projection of the second signal line on the electrode layer where the first signal line is located is close to the first wiring part The side at the third position of the first side intersects the first side, and the side of the orthographic projection of the second signal line on the electrode layer where the first signal line is located close to the third trace is at the fourth position of the first side.
  • the first side intersects; and the length of the line segment of the first side between the first position and the second position is greater than the length of the line segment of the first side between the third position and the fourth position.
  • the array substrate, the light control panel, and the display device can reduce the possibility of defects (for example, short-circuit defects) caused by electrostatic discharge.
  • FIG. 4A is a schematic plan view of an array substrate 100 provided by at least one embodiment of the present disclosure.
  • the array substrate 100 includes a first signal line 110 for sub-pixel rows extending in a first direction D1 as a whole, and sub-pixel rows 110 for extending in a second direction D2 intersecting the first direction D1 as a whole.
  • the first direction D1 and the second direction D2 cross each other (for example, perpendicular to each other).
  • the array substrate 100 includes a plurality of first signal lines 110 and a plurality of second signal lines 130; the plurality of first signal lines 110 and the plurality of second signal lines 130 cross and form an array arrangement A number of light-controlling pixel units 134.
  • 4B is a schematic plan view of the light control pixel unit 134 of the array substrate 100 shown in FIG. 4A.
  • the light-controlling pixel units 134 located in the same row form sub-pixel rows extending in the first direction D1 as a whole, and the array substrate 100 includes multiple rows of sub-pixel rows arranged in the second direction D2;
  • the columns of light-controlling pixel units 134 form sub-pixel columns extending in the second direction D2 as a whole, and the array substrate 100 includes multiple sub-pixel columns arranged in the first direction D1.
  • a plurality of first signal lines 110 correspond to a plurality of rows of sub-pixel rows one-to-one, and a plurality of first signal lines 110 are configured to drive corresponding sub-pixel rows; a plurality of second signal lines 130 There is a one-to-one correspondence with multiple sub-pixel columns, and the multiple second signal lines 130 are configured to drive the corresponding sub-pixel columns.
  • the first signal line 110 and the second signal line 130 are electrically connected to different signal sources.
  • the first signal line 110 is a gate line and is electrically connected to the gate driving circuit of the display device including the array substrate 100
  • the second signal line 130 is a data line and is connected to the data driving circuit of the display device including the array substrate 100 Electric connection.
  • each of the plurality of first signal lines 110 as a whole extends along the first direction D1; each of the plurality of second signal lines 130 as a whole extends along the second direction D2.
  • the entire extension of each of the plurality of first signal lines 110 along the first direction D1 only defines the overall extension direction of the first signal line 110, and does not indicate the individual wiring portions included in the first signal line 110 Are parallel to the first direction D1; each of the plurality of second signal lines 130 extending in the second direction D2 as a whole only defines the overall extension direction of the second signal line 130, and does not mean that each of the second signal lines 130 includes The wiring parts are all parallel to the second direction D2.
  • the first signal line 110 (for example, each of the plurality of first signal lines 110) includes a plurality of broken line structures 111 (first broken line structure) directly connected in sequence, and each of the plurality of broken line structures 111 Including the first wiring portion 112, the second wiring portion 113, the third wiring portion 114 and the fourth wiring portion 115 directly connected in sequence; the extension direction of the first wiring portion 112 and the third wiring portion 114
  • the extension directions of both intersect the first direction D1 and the second direction D2, and the second wiring portion 113 and the fourth wiring portion 115 respectively extend along the first direction D1.
  • the fourth routing portion 115 of each of the plurality of folding line structures 111 (the fourth routing portion 115 is away from each of the plurality of folding line structures 111 One end of the first wiring portion 112) and the first wiring portion 112 of another broken line structure 111 located on the right side of each of the plurality of broken line structures 111 (the first wiring portion 112 is far from the other broken line structure One end of the fourth wiring portion 115 of 111) is directly connected.
  • first wiring portion 112, the second wiring portion 113, the third wiring portion 114, and the fourth wiring portion 115 are all straight line segments, but at least one embodiment of the present disclosure is not limited thereto.
  • at least one of the first wiring portion 112, the second wiring portion 113, the third wiring portion 114, and the fourth wiring portion 115 is a curved line segment.
  • the second signal line 130 (for example, each of the plurality of second signal lines 130) includes a plurality of second broken line structures 131 directly connected in sequence, and each of the plurality of second broken line structures 131 It includes a first line segment 132 and a second line segment 133 directly connected in sequence; the extension direction of the first line segment 132 and the extension direction of the second line segment 133 both intersect the first direction D1 and the second direction D2.
  • the second signal line 130 for example, each of the plurality of second signal lines 130
  • each of the plurality of second broken line structures 131 It includes a first line segment 132 and a second line segment 133 directly connected in sequence; the extension direction of the first line segment 132 and the extension direction of the second line segment 133 both intersect the first direction D1 and the second direction D2.
  • the second line segment 133 of each of the plurality of second fold line structures 131 (for example, the second line segment 133 is far away from the second fold line structure 131)
  • One end of the second line segment 133 of the other second broken line structure 131) is directly connected.
  • the first line segment 132 and the second line segment 133 are both straight line segments
  • the array substrate 100 further includes a plurality of third signal lines 140, and each of the plurality of third signal lines 140 is entirely along the second direction D2.
  • the third signal line 140 (for example, each of the plurality of third signal lines 140) includes a plurality of third fold line structures 141 directly connected in sequence, and each of the plurality of third fold line structures 141 includes a third fold line structure directly connected in sequence.
  • the line segment 142 and the fourth line segment 143; the extension direction of the third line segment 142 and the extension direction of the fourth line segment 143 both intersect the first direction D1 and the second direction D2. For example, as shown in FIG.
  • the fourth line segment 143 of each of the plurality of third fold line structures 141 and the fourth line segment 143 located below each of the plurality of third fold line structures 141 The third line segment 142 of the other third broken line structure 141 on the side is directly connected.
  • the third signal line 140 is a common electrode line and is configured to receive a common voltage.
  • the third line segment 142 and the fourth line segment 143 are both straight line segments,
  • FIG. 5A is a schematic diagram of an example of the portion of the first signal line 110 located in the first region RE1 of the array substrate 100 shown in FIG. 4A.
  • the center line 151 of the first wiring portion 112 extending along the extending direction of the first wiring portion 112 intersects the center line 152 of the second wiring portion 113 extending along the extending direction of the second wiring portion 113
  • a first included angle ⁇ 1 is formed;
  • the second wiring portion 113 includes a first side 121 and a second side 122 opposite to each other in the second direction D2, the first side 121 is located inside the first included angle ⁇ 1, and the second side 122 is located outside the first included angle ⁇ 1.
  • the side of the first wiring portion 112 close to the second signal line 130 (for example, the first line segment 132 of the second signal line 130) is at the first position P1 of the first side 121 and the first side 121 intersect, the side of the third wiring portion 114 close to the second signal line 130 (for example, the first line segment 132 of the second signal line 130) intersects the first side 121 at the second position P2 of the first side 121;
  • the side close to the first wiring portion 112 of the orthographic projection of the second signal line 130 on the electrode layer where the first signal line 110 is located intersects the first side 121 at the third position P3 of the first side 121, and the second signal line 130
  • the side close to the third wiring portion 114 of the orthographic projection on the electrode layer where the first signal line 110 is located intersects the first side 121 at the fourth position P4 of the first side 121.
  • the length of the line segment of the first side 121 between the first position P1 and the second position P2 is greater than the length of the line segment of the first side 121 between the third position P3 and the fourth position P4.
  • the first side 121 can be increased.
  • the possibility that the third position P3 and the fourth position P4 are located between the first position P1 and the second position P2 can reduce the possibility that the second signal line 130 overlaps with the third trace portion 114 of the first signal line 110 Therefore, it is possible to reduce the possibility of forming an overlapping triangle (such as the overlapping triangle shown in FIG. 3B) between the second signal line 130 and the first signal line 110, and to reduce the defects caused by electrostatic discharge (such as poor short circuit). ) Possibility.
  • the third position P3 and the fourth position P4 are both located between the first position P1 and the second position P2. It should be noted that the third position P3 and the fourth position P4 are both located between the first position P1 and the second position P2, including the third position P3 overlapping the first position P1, and the fourth position P4 overlapping the second position P2. happening.
  • the third position P3 and the fourth position P4 both located between the first position P1 and the second position P2
  • the overlapping triangles shown and the possibility of defects (e.g., short-circuit defects) caused by electrostatic discharge are reduced.
  • the third position P3 and the fourth position P4 are not limited to being located between the first position P1 and the second position P2.
  • the fourth position P4 is located on the side of the second position P2 away from the first position P1, and the area of the overlapping triangle formed between the second signal line 130 and the first signal line 110 is smaller than that shown in FIG. 3B
  • it is also possible to reduce the possibility of defects due to electrostatic discharge for example, short-circuit defects between the second signal line 130 and the first signal line 110).
  • the first line segment 132 is the part of the second signal line 130 between the first line and the second line; the first line segment 132 and the third line portion 114 They are inclined in the same direction with respect to the second direction D2.
  • the first line segment 132 and the third wiring portion 114 are both inclined toward the right side of the second direction D2.
  • FIG. 5B is a schematic diagram of an example of the portion of the first signal line 110 located in the second region RE2 of the array substrate 100 shown in FIG. 4A.
  • the center line 153 of the third wiring portion 114 extending along the extending direction of the third wiring portion 114 intersects the center line 154 of the fourth wiring portion 115 extending along the extending direction of the fourth wiring portion 115
  • a second included angle ⁇ 2 is formed;
  • the fourth wiring portion 115 includes a third side 123 and a fourth side 124 opposite to each other in the second direction D2, and the third side 123 is located inside the second included angle ⁇ 2 and the fourth side 124 is located outside the second included angle ⁇ 2.
  • the side of the third wiring portion 114 close to the third signal line 140 (for example, the third line segment 142 of the third signal line 140) is at the fifth position P5 of the third side 123 and the third side 123 Intersect, the side of the first wiring portion 112 close to the third signal line 140 (for example, the third line segment 142 of the third signal line 140) intersects the third side 123 at the sixth position P6 of the third side 123;
  • the side close to the third wiring portion 114 of the orthographic projection of the signal line 140 on the electrode layer where the first signal line 110 is located intersects the third side 123 at the seventh position P7 of the third side 123, and the third signal line 140 is at the third side 123.
  • the side of the orthographic projection on the electrode layer where the signal line 110 is located close to the first wiring portion 112 intersects the third side 123 at the eighth position P8 of the third side 123.
  • the length of the line segment of the third side 123 between the fifth position P5 and the sixth position P6 is greater than the length of the line segment of the third side 123 between the seventh position P7 and the eighth position P8.
  • the first side 123 can be increased.
  • the seventh position P7 and the eighth position P8 are both located between the fifth position P5 and the sixth position P6, so the possibility that the third signal line 140 overlaps with the first wiring portion 112 of the first signal line 110 can be reduced Therefore, it is possible to reduce the possibility of overlapping triangles (for example, the overlapping triangles shown in FIG. 3C) formed between the third signal line 140 and the first signal line 110, and to reduce defects caused by electrostatic discharge (for example, Poor short circuit).
  • overlapping triangles for example, the overlapping triangles shown in FIG. 3C
  • the seventh position P7 and the eighth position P8 are both located between the fifth position P5 and the sixth position P6. It should be noted that the seventh position P7 and the eighth position P8 are both located between the fifth position P5 and the sixth position P6, including the seventh position P7 and the fifth position P5 overlapping, and the eighth position P8 and the sixth position P6 overlapping.
  • the seventh position P7 and the eighth position P8 both located between the fifth position P5 and the sixth position P6, it is possible to avoid the formation of an overlapping triangle between the third signal line 140 and the first signal line 110 (e.g., FIG. The overlapping triangles shown in 3C) and the possibility of defects due to electrostatic discharge (for example, short-circuit defects between the third signal line 140 and the first signal line 110) are reduced.
  • the third position P3 is located between the first midpoint M1 and the first position P1, and the seventh position P7 is located between the second midpoint M2 and the fifth position P5;
  • the first midpoint M1 is The midpoint of the line segment between the first position P1 and the second position P2 of the first side 121
  • the second midpoint M2 is the midpoint of the line segment of the third side 123 between the fifth position P5 and the sixth position P6 point.
  • FIG. 5C is another schematic diagram of the example of the part of the first signal line 110 shown in FIG. 5A
  • FIG. 5D is another schematic diagram of the example of the part of the first signal line 110 shown in FIG. 5B.
  • the inclination angle ⁇ 1 of the third trace portion 114 relative to the second direction D2 is greater than three times the inclination angle ⁇ 2 of the first line segment 132 relative to the second direction D2 and is smaller than the first line
  • the inclination angle ⁇ 2 of the section 132 relative to the second direction D2 is four times;
  • the inclination angle ⁇ 3 of the first trace portion 112 relative to the second direction D2 is greater than three times the inclination angle ⁇ 4 of the third line segment 142 relative to the second direction D2 and is smaller than the Four times the inclination angle ⁇ 4 of the three-line segment 142 with respect to the second direction D2 (the inclination angles ⁇ 1- ⁇ 4 are acute angles and positive values);
  • the length L1 of the line segment of the first side 121 between the first position P1 and the second position P2 is greater than the length L3 of the line segment of the third side 123 between the fifth position P5 and the sixth position P6.
  • the length L2 of the second side 122 is greater than the length L4 of the fourth side 124.
  • the inclination angle ⁇ 1 of the third trace portion 114 relative to the second direction D2 is equal to the inclination angle ⁇ 3 of the first trace portion 112 relative to the second direction D2; the inclination angle ⁇ 2 of the first line segment 132 relative to the second direction D2 is equal to the first line segment 132 relative to the second direction D2.
  • the width Lg2 of the second wiring portion 113 is greater than the width Lg1 of the first wiring portion 112 and less than twice the width Lg1 of the first wiring portion 112; the width Lg4 of the fourth wiring portion 115 is greater than that of the second wiring
  • the width of the portion 113 is Lg2.
  • the width of the wiring part refers to the width of the wiring part in a direction perpendicular to the extension direction of the wiring part.
  • the width of the second wiring portion 113 refers to the width of the second wiring portion 113 in the second direction D2
  • the width of the fourth wiring portion 115 refers to the width of the fourth wiring portion 115 in the second direction D2. width.
  • FIG. 6A is a schematic diagram of the overlapping triangle between the first signal line 110 (for example, the third wiring portion 114 of the first signal line 110) and the second signal line 130;
  • FIG. 6B is the first signal line 110 and the third signal line 110 A schematic diagram of the overlapping triangles between the signal lines 140.
  • Ld 8 microns
  • Lc 6 microns
  • L1b 5 microns
  • L2b 18 microns
  • L3b 5 microns
  • L4b 17 microns.
  • the overlapping triangle between the first signal line 110 and the second signal line 130 refers to the formation of the orthographic projection of the second signal line 130 on the electrode layer where the first signal line 110 is located and the first signal line 110.
  • Overlapping triangle; the overlapping triangle between the first signal line 110 and the third signal line 140 refers to the intersection formed by the orthographic projection of the third signal line 140 on the electrode layer where the first signal line 110 is located and the first signal line 110 Stack the triangles.
  • design ideas provided by at least one embodiment of the present disclosure are not limited to eliminating the overlapping triangles in the examples of FIGS. 6A and 6B.
  • a similar design idea can be used to set L1-L4 to eliminate or reduce the overlapping triangle between the first signal line 110 and the second signal line 130 and the overlapping triangle between the first signal line 110 and the third signal line 140 .
  • the following is a design of how to eliminate or reduce the overlapping triangle between the first signal line 110 (for example, the third wiring portion 114 of the first signal line 110) and the second signal line 130 in conjunction with FIGS. 7A-7D
  • the idea that is, by shifting the third wiring portion 114 of the first signal line 110 to a side away from the second signal line 130) is exemplified.
  • FIG. 7A is a simplified schematic diagram of the overlapping triangle between the first signal line 110 and the second signal line 130 shown in FIG. 6A when the second signal line 130 has no alignment error with respect to the first signal line 110.
  • FIG. 7B is the equivalent of the overlapping triangle ⁇ ABC between the first signal line 110 and the second signal line 130 shown in FIG. 6A when the second signal line 130 has no alignment error with respect to the first signal line 110 Schematic.
  • the left boundary L of the second signal line 130 passes through the midpoint of the line segment MB (the length of which is equal to L1b), and the rectangular coordinate system
  • the origin O is located at the midpoint of the line segment MC.
  • FIG. 7C shows that the second signal line 130 has a horizontal alignment error (that is, the alignment error along the x-axis) but does not have a vertical alignment error (that is, the alignment error along the y-axis) relative to the first signal line 110. ), the equivalent schematic diagram of the overlapping triangle ⁇ A1BC1 between the first signal line 110 and the offset (relative to the second signal line shown in FIG. 6A) after the second signal line 130; FIG. 7D When the second signal line 130 has a horizontal alignment error and a vertical alignment error relative to the first signal line 110, the first signal line 110 and the offset (relative to the second signal line shown in FIG.
  • FIGS. 7B-7D when the second signal line 130 is shifted DX to the right and DY downward relative to the first signal line 110, the overlapping triangle between the first signal line 110 and the second signal line 130 The largest area. Therefore, in order to better eliminate the overlapping triangle between the first signal line 110 and the second signal line 130, the design can be based on the overlapping triangle ⁇ A2BC2 shown in FIG. 7D.
  • the second signal line 130 has an alignment error DX in the horizontal direction and an alignment error DY in the vertical direction relative to the first signal line 110 (see FIG.
  • the following is a design idea of how to eliminate or reduce the overlapping triangle between the first signal line 110 (the first wiring portion 112 of the first signal line 110) and the third signal line 140 in conjunction with FIGS. 8A-8D ( That is, the exemplary description is made by shifting the first wiring portion 112 of the first signal line 110 to a side away from the third signal line 140).
  • the design idea of eliminating or reducing the overlapping triangle between the first signal line 110 and the third signal line 140 is the same as that described in FIGS. 7A-7D.
  • the design ideas of the overlapping triangles are similar, and the repetition will not be repeated.
  • FIG. 8A is a simplified schematic diagram of the overlapping triangle between the first signal line 110 and the third signal line 140 shown in FIG. 6B when the third signal line 140 has no alignment error with respect to the first signal line 110.
  • 8B is the equivalent of the overlapping triangle ⁇ FDE between the first signal line 110 and the third signal line 140 shown in FIG. 6B when the third signal line 140 has no alignment error with respect to the first signal line 110 Schematic diagram; as shown in FIGS. 8A and 8B, assuming that there is no alignment error in the manufacturing process, the left boundary S of the third signal line 140 passes through the midpoint of the line segment QD, and the origin P of the rectangular coordinate system is located in the line segment The midpoint of QD.
  • the length of the line segment QD is equal to L3b.
  • FIG. 8C shows that the third signal line 140 has a horizontal alignment error (ie, an alignment error along the x-axis) but does not have a vertical alignment error (ie, an alignment error along the y-axis) relative to the first signal line 110.
  • FIG. 8D is In the case where the third signal line 140 has a horizontal alignment error and a vertical alignment error with respect to the first signal line 110, the first signal line 110 is offset (relative to the third signal line shown in FIG. 6B)
  • the absolute value of the maximum horizontal alignment error of the third signal line 140 relative to the first signal line 110 is DX
  • the absolute value of the maximum vertical alignment error of the third signal line 140 relative to the first signal line 110 is DY.
  • the design can be based on the overlapping triangle ⁇ F2DE2 shown in FIG. 8D.
  • One side translation, L1b, L2b, L3b, and L4b shown in FIGS. 6A and 6B can be set to 13 micrometers, 26 micrometers, 11 micrometers, and 23 micrometers, respectively, thereby eliminating or reducing the first signal line 110 and the first signal line 110.
  • the overlapping triangle between the two signal lines 130 and the overlapping triangle between the first signal line 110 and the third signal line 140 can suppress defects (short-circuit defects) caused by electrostatic discharge.
  • the fourth position P4 may coincide with the second position P2; the eighth position P8 may coincide with the sixth position P6, but the embodiment of the present disclosure is not limited thereto.
  • the fourth position P4 is close to but not coincident with the second position P2; the eighth position P8 is close to but not coincident with the sixth position P6.
  • the third position P3 is located between the first midpoint M1 and the second position P2; the seventh position P7 is located between the second midpoint M2 and the eighth position P8; the second signal line 130 (for example, The first line segment 132 of the second signal line 130) is an orthographic projection of the intersection of the side close to the first wiring portion 112 and the second side 122 on the first side 121 located at the first midpoint M1 away from the third position P3.
  • Side; the third signal line 140 (for example, the third line segment 142 of the third signal line 140) is close to the third wiring portion 114 and the intersection of the fourth side 124.
  • the orthographic projection on the third side 123 is located in the second middle
  • the point M2 is away from the side of the seventh position P7.
  • the width of the second wiring portion 113 and the width of the fourth wiring portion 115 are both greater than the width of the first wiring portion 112; the width of the first wiring portion 112 is equal to the width of the third wiring portion 114, for example.
  • An exemplary description will be given below in conjunction with FIGS. 9A-9D. It should be noted that the orthographic projection of a point on an edge refers to the intersection of a perpendicular line from the point to the edge and the edge.
  • FIG. 9A is a schematic diagram of another example of a portion of the first signal line 110 located in the first region RE1 of the array substrate 100 shown in FIG. 4A
  • FIG. 9B is a schematic diagram of another example of the portion of the first signal line 110 located in the second region RE2 of the array substrate 100 shown in FIG. 4A
  • a schematic diagram of another example of a portion of the first signal line 110 FIG. 9C is another schematic diagram of an example of a portion of the first signal line 110 shown in FIG. 9A
  • FIG. 9D is a schematic diagram of the first signal line 110 shown in FIG. 9B Another schematic diagram of part of the example.
  • the structure of the part of the first signal line 110 shown in FIG. 9A and the overlapping relationship between the first signal line 110 and the second signal line 130 are similar to those of FIG. 5A, and the structure of the part of the first signal line 110 shown in FIG.
  • the overlap relationship between the signal line 110 and the third signal line 140 is similar to that of FIG. 5B. Therefore, only the differences between FIG. 9A and FIG. 5A and the differences between FIG. 9B and FIG. 5B will be described here, and the similarities will not be repeated.
  • the inclination angle ⁇ 1 of the third trace portion 114 with respect to the second direction D2 is greater than three times the inclination angle ⁇ 2 of the first line segment 132 with respect to the second direction D2 and is smaller than the inclination angle ⁇ 2 of the first line segment 132.
  • the inclination angle ⁇ 2 in the second direction D2 is four times; the inclination angle ⁇ 3 of the first trace portion 112 relative to the second direction D2 is greater than three times the inclination angle ⁇ 4 of the third line segment 142 relative to the second direction D2 and is smaller than the third line segment 142
  • the inclination angle ⁇ 4 relative to the second direction D2 is four times (the inclination angles ⁇ 1- ⁇ 4 here are acute angles and positive values);
  • the width Lg1 of the first wiring portion 112 is greater than twice the width Ld of the second signal line 130 and Less than three times the width Ld of the second signal line 130; the width Lg1 of the first wiring portion 112 is greater than three times the width Lc of the third signal line 140 and less than four times the width Lc of the third signal line 140;
  • the width Ld of 130 is greater than the width Lc of the third signal line 140; the width Lg1 of the first wiring portion 112 is greater than the length L2 of the second
  • the width Lg2 of the second wiring portion 113 is greater than the width Lg4 of the fourth wiring portion 115.
  • the inclination angle ⁇ 1 of the third trace portion 114 relative to the second direction D2 is equal to the inclination angle ⁇ 3 of the first trace portion 112 relative to the second direction D2; the inclination angle ⁇ 2 of the first line segment 132 relative to the second direction D2 is equal to the first line segment 132 relative to the second direction D2.
  • the width Lg2b of the second wiring portion 113 shown in FIG. 7A is obtained by the following derivation.
  • the fourth position P4 may coincide with the second position P2; the eighth position P8 may coincide with the sixth position P6, but the embodiment of the present disclosure is not limited thereto.
  • the fourth position P4 is close to but not coincident with the second position P2; the eighth position P8 is close to but not coincident with the sixth position P6.
  • the third position P3 is located at the first midpoint M1; the seventh position P3 is located at the second midpoint M2.
  • the width of the second wiring portion 113 and the width of the fourth wiring portion 115 are both greater than the width of the first wiring portion 112; the width of the first wiring portion 112 is equal to the width of the third wiring portion 114, for example.
  • FIG. 11A is a schematic diagram of another example of the first signal line located in the first area of the array substrate shown in FIG. 4A;
  • FIG. 11B is the first signal line located in the second area of the array substrate shown in FIG. 4A Schematic diagram of yet another example of part.
  • the third position P3 and the fourth position P4 are both located between the first position P1 and the second position P2, and the third position P3 is located at the first midpoint M1.
  • the seventh position P7 and the eighth position P8 are both located between the fifth position P5 and the sixth position P6, and the seventh position P3 is located at the second midpoint M2.
  • the fourth position P4 is close to but not overlapped with the second position P2; as shown in FIG. 11B, the eighth position P8 and the sixth position P6 overlap, but the embodiment of the present disclosure is not limited thereto.
  • the fourth position P4 coincides with the second position P2; the eighth position P8 is close to but not coincides with the sixth position P6.
  • the design idea of shifting the third wiring portion 114 of the first signal line 110 and the design idea of increasing the width of the second wiring portion 113 can be used at the same time to reduce or eliminate the first signal line 110.
  • the overlapping triangle between the three wiring portion 114 and the second signal line 130; at the same time, the design idea of shifting the first wiring portion 112 of the first signal line 110 and the design idea of increasing the width of the fourth wiring portion 115 are used to The overlapping triangle between the first wiring portion 112 of the first signal line 110 and the second signal line 130 is reduced or eliminated; the specific design idea can be referred to the previous example, which will not be repeated here.
  • the design idea of shifting the third wiring portion 114 of the first signal line 110 and the design idea of increasing the width of the second wiring portion 113 to reduce or eliminate the third wiring portion 114 of the first signal line 110 The overlapping triangle between the second signal line 130 and the second signal line 130 can prevent the width and length of the second wiring portion 113 from increasing too much, and thus can be better compatible with the current manufacturing process.
  • the third position P3 is located between the first position P1 and the first midpoint M1; the seventh position P7 is located between the fifth position P5 and the second midpoint M2.
  • the distance between the third position P3 and the first position P1 is small; the distance between the seventh position P7 and the fifth position P5 is small.
  • FIG. 11C is a schematic diagram of yet another example of the portion of the first signal line located in the first area of the array substrate shown in FIG. 4A;
  • FIG. 11D is the first signal line located in the second area of the array substrate shown in FIG. 4A Schematic diagram of yet another example of the part.
  • the third position P3 and the fourth position P4 are both located between the first position P1 and the second position P2, and the seventh position P7 and the eighth position P8 are both located at the fifth position P5 and the sixth position. Between position P6.
  • the third position P3 coincides with the first position P1; as shown in FIG. 11B, and the seventh position P3 coincides with the fifth position P5; but the embodiment of the present disclosure is not limited thereto.
  • the third position P3 coincides with the first position P1; the seventh position P3 is close to but does not overlap with the fifth position P5; for another example, the third position P3 and the first position P1, and the seventh position P3 and the fifth position P5 are both Close but not coincident.
  • two positions are close but not overlapping means that the distance between the two positions is greater than zero and less than two micrometers (for example, less than one micrometer).
  • the fourth position P4 overlaps with the second position P2; the eighth position P8 overlaps with the sixth position P6, but the embodiment of the present disclosure is not limited thereto.
  • the fourth position P4 is close to but not coincident with the second position P2; the eighth position P8 is close to but not coincident with the sixth position P6.
  • the width of the first wiring portion 112 and the width of the third wiring portion 114 are equal; the width of the second wiring portion 113 is greater than the width of the first wiring portion 112 and less than two times the width of the first wiring portion 112. Times.
  • the overlapping triangles can be eliminated or reduced through the following design and/or manufacturing ideas; for example, the third position P3 can be located at the first position P1 and the first position P1 through the following design and/or manufacturing ideas. Between the midpoint M1 (for example, making the third position P3 coincide with the first position P1), the seventh position P7 is located between the fifth position P5 and the second midpoint M2 (for example, making the seventh position P7 and the fifth position P5 coincides).
  • the width of the first signal line 110 for example, the width of the first wiring portion 112 and the third wiring portion 114 of the first signal line 110
  • the length of the line segment of the first side 121 between the third position P3 and the fourth position P4 can be reduced by reducing the width of the second signal line 130.
  • the length of the line segment of the third side 123 between the seventh position P7 and the eighth position P8 can be reduced by reducing the width of the third signal line 140.
  • the width of the first side 121 between the first position P1 and the second position P2 can be greater than the length of the first side 121 between the third position P3 and the fourth position P4, and the first side 121
  • the length of the line segment of the three sides 123 between the fifth position P5 and the sixth position P6 is greater than the length of the line segment of the third side 123 between the seventh position P7 and the eighth position P8.
  • a third can be added.
  • defects for example, short-circuit defects
  • the line width design value of the array substrate 100 is reduced to reduce at least one of the first signal line 110, the second signal line 130, and the third signal line 140 (for example, the first signal line 110, the second signal line 130, and the third signal line).
  • the width of each of the lines 140 in this case, a new mask can be designed and used in the production process.
  • the critical dimension of the photoresist can be reduced by increasing the exposure dose of the exposure machine, so as to reduce the first signal line 110, the second signal line 130, and the third signal line 140.
  • the line width of at least one of for example, each of the first signal line 110, the second signal line 130, and the third signal line 140; in this case, the mask used in the related technology can be used without design and Use a new mask.
  • the charging rate can also be reduced by reducing at least one of the first signal line 110, the second signal line 130, and the third signal line 140 (for example, each of the first signal line 110, the second signal line 130, and the third signal line 140).
  • the design idea of eliminating or reducing overlapping triangles by the line width of root is combined with at least one of the following three design ideas to eliminate or reduce overlapping triangles.
  • the wiring portion 112 is used to increase the length of the line segment of the third side 123 between the fifth position P5 and the sixth position P6.
  • the side 123 is located at the length of the line segment between the fifth position P5 and the sixth position P6.
  • the second signal line 130 is shifted to the right in the x direction (offset away from the first position P1) and shifted downward in the y direction (toward the first side 121).
  • the direction of the second side 122 is offset
  • the area of the overlapping triangle between the second signal line 130 and the first signal line 110 increases;
  • the third signal line 140 is shifted to the right along the x direction (away from the fifth signal line)
  • the position P5 is offset
  • upward in the y direction offset toward the third side 123 toward the fourth side 124
  • the area of the overlapping triangle between the third signal line 140 and the first signal line 110 increases .
  • the preset overlapping position of the second signal line 130 and the second wiring portion 113 and the preset overlapping position of the third signal line 140 and the fourth wiring portion 115 can be changed on the array substrate.
  • the above-mentioned offset of the second signal line 130 and the third signal line 140 is realized in the final product of 100 (relative to the structure shown in FIG. 6A and FIG. 6B); in this case, a new one can be designed and used in the manufacturing process.
  • Mask plate is a new one can be designed and used in the manufacturing process.
  • the above-mentioned offset of the second signal line 130 and the third signal line 140 can be realized in the final product of the array substrate 100 by using the offset feedback function that comes with the exposure machine (relative to the offset shown in FIGS. 6A and 6B). Structure);
  • the mask used in the related technology can be used.
  • the specific method is as follows.
  • each film layer is manufactured (for example, a mask is used to pattern the film). ) Must be aligned first.
  • the mask for making the second signal line 130 and the mask for making the first signal line 110 are aligned (for example, indirect alignment).
  • alignment marks on the base substrate of the array substrate 100 can be used for alignment.
  • the absolute values of the maximum horizontal alignment error and the maximum vertical alignment error of the third signal line 140 and the second signal line 130 relative to the first signal line 110 are both 1.5 micrometers; In this case, when the second signal line 130 is offset by 1.5 micrometers to the right in the x direction and 1.5 micrometers in the y direction, the overlapping triangle between the second signal line 130 and the first signal line 110 The area is the largest; the area of the overlapping triangle between the third signal line 140 and the first signal line 110 is the largest when the third signal line 140 is offset by 1.5 micrometers to the right along the x direction and 1.5 micrometers upwards along the y direction.
  • the second signal line 130 when the second signal line 130 is offset by 1.5 micrometers to the left in the x direction and 1.5 micrometers upwards in the y direction, the area of the overlapping triangle between the second signal line 130 and the first signal line 110 is the smallest;
  • the third signal line 140 is offset by 1.5 micrometers to the left in the x direction and 1.5 micrometers downwards in the y direction, the area of the overlapping triangle between the third signal line 140 and the first signal line 110 is the smallest.
  • the second signal line 130 can be shifted by 1.5 micrometers to the left in the x direction and 1.5 micrometers upwards in the y direction, and the third signal line 140 can be shifted to the left by 1.5 micrometers in the x direction.
  • offset down by 1.5 microns in the y direction for example, the overlay feedback of the operation page of the exposure machine can be used to realize the above-mentioned offset of the second signal line 130 and the third signal line 140.
  • the overlapped area of the first signal line 110 (eg, gate line) and the second signal line 130 and the area of the first signal line 110 and the third signal line 140
  • Designing the overlapping area of the first signal line 110 can eliminate the overlapping triangle between the third trace portion 114 of the first signal line 110 and the second signal line 130 and the first signal
  • the overlapping triangles between the first wiring portion 112 of the line 110 and the third signal line 140 can reduce defects caused by electrostatic discharge (for example, the third wiring portion 114 of the first signal line 110 and the second The possibility of a short circuit between the signal lines 130 and a short circuit between the first wiring portion 112 of the first signal line 110 and the third signal line 140).
  • the above-mentioned design of the overlapping area of the first signal line 110 (for example, the gate line) and the second signal line 130 and the overlapping area of the first signal line 110 and the third signal line 140 includes the The parameters of other structures of the light control panel of the array substrate 100 (the width of the black matrix, the overlap capacitance between the traces) have little influence (for example, the influences are all within a controllable and acceptable range).
  • the design idea of eliminating overlapping triangles provided by at least one embodiment of the present disclosure is simple, and the structure of the first signal line (the structure of the gate line) obtained by using the design idea of eliminating overlapping triangles provided by at least one embodiment of the present disclosure The structure of the bend) is easy to realize.
  • the array substrate provided by at least one embodiment of the present disclosure is suitable for medium and large size (for example, larger than 60 inches; for example, 65 inches and 75 inches) of display devices with dual liquid crystal cells.
  • FIGS. 5A to 5D and the examples shown in FIGS. 9A to 9D are aimed at eliminating the overlapping triangles between the third wiring portion 114 of the first signal line 110 and the second signal line 130 and eliminating The overlapping triangle between the first wiring portion 112 of the first signal line 110 and the third signal line 140 adopts the same design idea; for example, in the example shown in FIGS. 5A-5D, the first signal is shifted.
  • the third wiring portion 114 and the first wiring portion 112 of the line 110 are used to eliminate overlapping triangles; in the example shown in FIGS.
  • the second wiring portion 113 and the second wiring portion 113 and the second wiring portion of the first signal line 110 are added
  • the width of the four trace portions 115 is used to eliminate overlapping triangles; however, the embodiments of the present disclosure are not limited to this; different design ideas can be used to eliminate the gap between the third trace portion 114 of the first signal line 110 and the second signal line 130. And eliminate the overlapping triangle between the first wiring portion 112 of the first signal line 110 and the third signal line 140; correspondingly, in the final product of the array substrate 100, the structure of the first signal line 110 , And the relative positional relationship between the first signal line 110, the second signal line 130, and the third signal line 140 will correspondingly change.
  • the overlapping triangle between the third wiring portion 114 of the first signal line 110 and the second signal line 130 can be eliminated by shifting the third wiring portion 114 of the first signal line 110, and the fourth wiring portion 114 can be added.
  • the width of the line portion 115 is used to eliminate the overlapping triangle between the first wiring portion 112 of the first signal line 110 and the third signal line 140; correspondingly, the third position P3 is located at the first midpoint M1 and the first position P1
  • the seventh position P7 is located between the second midpoint M2 and the eighth position P8, and the intersection of the side of the third signal line 140 close to the third wiring portion 114 and the fourth side 124 is on the third side 123
  • the orthographic projection is located on the side of the second midpoint M2 away from the seventh position P7.
  • the line width of at least one of the first signal line 110 and the second signal line 130 (for example, each of the first signal line 110 and the second signal line 130) and strictly control the manufacturing process of the array substrate 100.
  • the alignment deviation of the second signal line 130 relative to the first signal line 110 is used to eliminate the overlapping triangle between the third trace portion 114 of the first signal line 110 and the second signal line 130, and the first signal is shifted.
  • the first wiring portion 112 of the line 110 is used to eliminate the overlapping triangle between the first wiring portion 112 of the first signal line 110 and the third signal line 140.
  • FIGS. 5A-5D and the examples shown in FIGS. 9A-9D both eliminate the overlapping triangles between the third wiring portion 114 of the first signal line 110 and the second signal line 130 And the overlapping triangle between the first wiring portion 112 of the first signal line 110 and the third signal line 140, but the embodiment of the present disclosure is not limited thereto. In one example, only the overlapping triangle between the third trace portion 114 of the first signal line 110 and the second signal line 130 can be eliminated; in another example, only the first trace of the first signal line 110 can be eliminated. The overlapping triangle between the line portion 112 and the third signal line 140.
  • the third wiring portion 114 and the second The four-wire portion 115, the first wire portion 112, the second wire portion 113, and the third signal wire 140 are called the first wire portion, the second wire portion, the third wire portion, and the fourth wire portion, respectively. Part and the second signal line will not be repeated here.
  • the design ideas provided by at least one embodiment of the present disclosure can be used to eliminate the overlapping triangles of each fold line structure 111 (first fold line structure) of the array substrate 100; for another example, at least one embodiment of the present disclosure can be selected The provided design idea only eliminates the overlapping triangles of a part of the broken line structure 111 (the first broken line structure) of the array substrate 100.
  • each broken line structure 111 (first broken line structure) of the first signal line 110 only includes the first wiring portion 112, the second wiring portion 113, and the third wiring portion 114 that are directly connected in sequence; in this case Next, the third wiring portion 114 of each broken line structure 111 of the first signal line 110 is directly connected to the first wiring portion 112 of the broken line structure 111 adjacent to each broken line structure 111 described above.
  • each broken line structure 111 (first broken line structure) of the first signal line 110 only includes a first wiring portion 112, a third wiring portion 114, and a fourth wiring portion 115 that are directly connected in sequence.
  • the partial broken line structure 111 (first broken line structure) of the first signal line 110 includes a first wiring portion 112, a second wiring portion 113, a third wiring portion 114, a fourth wiring portion 115, and a first wiring portion 112, a second wiring portion 113, a third wiring portion 114, and a fourth wiring portion 115.
  • the remaining broken line structure 111 (first broken line structure) of the signal line 110 only includes the first wiring portion 112, the second wiring portion 113, and the third wiring portion 114 that are directly connected in sequence, or only includes the directly connected portions in sequence.
  • a plurality of second signal lines 130 for example, data lines
  • a plurality of third signal lines 140 for example, common electrode lines
  • two second signal lines 130 may be provided between every two adjacent third signal lines 140.
  • the setting of the slope angle of at least one of the first signal line 110, the second signal line 130, and the third signal line 140 will be exemplarily described below with reference to FIGS. 12A and 12B.
  • the slope angle of at least one of the first signal line 110, the second signal line 130, and the third signal line 140 (for example, each of the first signal line 110, the second signal line 130, and the third signal line 140) Located between 40 degrees and 60 degrees (for example, about 50 degrees).
  • the slope angle of at least one of the first signal line 110, the second signal line 130, and the third signal line 140 between 40 degrees and 60 degrees (for example, about 50 degrees).
  • Fig. 12A is a schematic cross-sectional view of the signal line when the slope angle of the signal line is small.
  • the slope angle of the signal line is small (for example, less than 30 degrees)
  • the Re_ESD is wider in the area where the thickness of the signal line is small.
  • FIG. 3B the position where electrostatic discharge is likely to occur is the position where the edge of the third wiring portion 114 of the first signal line 110 overlaps with the edge of the second signal line 130 (in the direction perpendicular to the array substrate 100).
  • FIG. 12B is a schematic diagram of undercut caused by etching deviation when the slope angle (designed slope angle) of the signal line is relatively large (for example, the slope angle is greater than 70 degrees).
  • the signal line can also be reduced.
  • the processing time is reduced and the process difficulty is reduced, so that the processing speed of the array substrate 100 can be increased.
  • FIG. 13 is a schematic cross-sectional view of a light control panel 10 provided by at least one embodiment of the present disclosure.
  • the light control panel 10 includes a counter substrate 201, a liquid crystal layer 202, and any array substrate 100 provided by at least one embodiment of the present disclosure; the array substrate 100 and the counter substrate 201 are arranged opposite to each other, and the liquid crystal layer 202 It is sandwiched between the array substrate 100 and the counter substrate 201.
  • the counter substrate 201 includes a black matrix unit but does not include a color filter.
  • the counter substrate 201, the liquid crystal layer 202, and the array substrate 100 are sequentially arranged in the third direction D3.
  • the third direction D3, the first direction D1, and the second direction D2 cross each other (for example, perpendicular to each other).
  • the light control panel 10 includes a plurality of light control units (not shown in the figure) arranged in an array.
  • a plurality of light control pixel units of the array substrate 100 are respectively arranged in corresponding light control units.
  • the light control unit further includes a portion of the liquid crystal layer that overlaps the light control pixel unit in the third direction D3 and a portion of the opposite substrate.
  • the light control panel 10 can adjust the transmittance of each light control unit of the light control panel 10 based on the data signal received by the data line of the array substrate 100. Therefore, the light control unit of the light control panel 10 can be used to control the light incident to the corresponding The intensity of the light on the display sub-pixel unit of the display panel of the light control unit, thus, the light control panel 10 can be used to provide the adjusted backlight to the display panel (the display panel of the display device including the light control panel).
  • the light control panel can reduce the possibility of defects (for example, short-circuit defects) caused by electrostatic discharge.
  • FIG. 14 is a schematic cross-sectional view of a display device 01 provided by at least one embodiment of the present disclosure.
  • the display device 01 includes a display panel 30, a backlight unit 20, and any light control panel 10 provided by at least one embodiment of the present disclosure, which are stacked on each other in the third direction D3.
  • the display panel 30 is located on the light exit side of the light control panel 10, and the backlight unit 20 is located on the side of the light control panel 10 away from the display panel 30.
  • the display panel 30, the light control panel 10, and the backlight unit 20 are sequentially arranged in the third direction D3.
  • the array substrate 100 of the light control panel 10 is closer to the backlight unit 20.
  • FIG. 15A is a schematic plan view of the display panel 30 of the display device 01 shown in FIG. 14.
  • the display panel 30 includes a plurality of first signal lines 305 extending in a first direction D1 and a plurality of second signal lines 306 extending in a second direction D2; a plurality of first signal lines 305 and a plurality of The second signal line 306 intersects to define a plurality of display sub-pixel units arranged in an array, and the plurality of display sub-pixel units form a plurality of display pixel units 304 arranged in an array.
  • the first signal line 305 is a gate line of the display panel 20
  • the second signal line 306 is a data line of the display panel 30.
  • each display pixel unit 304 includes a first display sub-pixel unit 3041, a second display sub-pixel unit 3042, and a third display sub-pixel unit 3043; the first display sub-pixel unit 3041, the second display sub-pixel unit
  • the unit 3042 and the third display sub-pixel unit 3043 are, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit, respectively.
  • FIG. 15B is a schematic plan view of the display device 01 shown in FIG. 14.
  • the size of each light control pixel unit 130 in the first direction D1 is equal to twice the size of each display pixel unit 304 in the first direction D1
  • each light control pixel unit 130 is The size in the second direction D2 is equal to or slightly smaller than four times the size of each display pixel unit 304 in the second direction D1.
  • the display device 01 further includes an isotropic diffusion film (not shown in the figure) disposed between the display panel 30 and the light control panel 10.
  • the isotropic diffusion film can diffuse the light emitted from the light control panel 10 in a smaller angle range, thereby blurring the pattern of the data line and further eliminating moiré, and at the same time, it will not emit light to the light control panel 10 The direction of the light has a greater impact.
  • the display device 01 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • other components of the display device 01 for example, a control device, an image data encoding/decoding device, a row scan driver, a column scan driver, a clock circuit, etc.
  • Those of ordinary skill should understand that it will not be repeated here, nor should it be used as a limitation to the present disclosure.

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Abstract

一种阵列基板、控光面板和显示装置。该阵列基板(100)包括用于整体沿第一方向(D1)延伸的子像素行的第一信号线(110)，以及用于整体沿与第一方向(D1)交叉的第二方向(D2)延伸的子像素列的第二信号线(130)。第一信号线(110)包括顺次直接相连多个折线结构(111)，多个折线结构(111)的每个包括顺次直接相连的第一走线部分(112)、第二走线部分(113)和第三走线部分(114)；第一走线部分(112)的延伸方向和第三走线部分(114)的延伸方向均与第一方向(D1)和第二方向(D2)相交，第二走线部分(113)沿第一方向(D1)延伸；第一走线部分(112)的沿第一走线部分(112)延伸方向延伸的中线(151)与第二走线部分(113)的沿第二走线部分(113)延伸方向延伸的中线(152)相交形成第一夹角(α1)；第二走线部分(113)包括在第二方向(D2)上彼此对置的第一边(121)和第二边(122)，第一边(121)位于第一夹角的内侧和第二边(122)位于第一夹角的外侧；第一走线部分(112)的靠近第二信号线(130)的边在第一边(121)的第一位置(P1)与第一边(121)相交，第三走线部分(114)的靠近第二信号线(130)的边在第一边(121)的第二位置(P2)与第一边(121)相交；第二信号线(130)的在第一信号线(110)所在电极层上的正投影的靠近第一走线部分(112)的边在第一边(121)的第三位置(P3)与第一边(121)相交，第二信号线(130)的在第一信号线(110)所在电极层上的正投影的靠近第三走线部分(114)的边在第一边(121)的第四位置(P4)与第一边(121)相交；第一边(121)的位于第一位置(P1)和第二位置(P2)之间的线段的长度大于第一边(121)的位于第三位置(P3)和第四位置(P4)之间的线段长度。例如，该阵列基板(100)可以降低因静电释放导致的不良(例如，短路不良)的可能性。

Description

阵列基板、控光面板和显示装置 技术领域
本公开的实施例涉及一种阵列基板、控光面板和显示装置。
背景技术
液晶显示装置包括背光模组(背光单元)和液晶面板，背光模组设置在液晶面板的非显示侧以为显示面板的显示操作提供光源。液晶面板包括偏光片、阵列基板、对置基板以及填充在由这两个基板之间的液晶分子层。液晶显示装置通过在阵列基板和对置基板之间的形成电场使液晶分子层中液晶分子偏转，偏转后的液晶分子配合偏光片可形成液晶光阀。由于液晶分子层本身并不发光，因此需要借助背光模组来实现显示功能。随着显示技术的不断发展，用户对显示装置的对比度、亮度均匀性、可靠性等提出了越来越高的要求。
发明内容
本公开的至少一个实施例提供了一种阵列基板，其包括：用于整体沿第一方向延伸的子像素行的第一信号线，以及用于整体沿与所述第一方向交叉的第二方向延伸的子像素列的第二信号线。所述第一信号线包括顺次直接相连多个折线结构，所述多个折线结构的每个包括顺次直接相连的第一走线部分、第二走线部分和第三走线部分；所述第一走线部分的延伸方向和所述第三走线部分的延伸方向均与所述第一方向和所述第二方向相交，所述第二走线部分沿所述第一方向延伸；所述第一走线部分的沿所述第一走线部分延伸方向延伸的中线与所述第二走线部分的沿所述第二走线部分延伸方向延伸的中线相交形成第一夹角；所述第二走线部分包括在所述第二方向上彼此对置的第一边和第二边，所述第一边位于所述第一夹角的内侧和所述第二边位于所述第一夹角的外侧；所述第一走线部分的靠近所述第二信号线的边在所述第一边的第一位置与所述第一边相交，所述第三走线部分的靠近所述第二信号线的边在所述第一边的第二位置与所述第一边相交；所述第二信号线的在 所述第一信号线所在电极层上的正投影的靠近所述第一走线部分的边在所述第一边的第三位置与所述第一边相交，所述第二信号线的在所述第一信号线所在电极层上的正投影的靠近所述第三走线部分的边在所述第一边的第四位置与所述第一边相交；以及所述第一边的位于所述第一位置和所述第二位置之间的线段的长度大于所述第一边的位于所述第三位置和所述第四位置之间的线段长度。
例如，在所述阵列基板的至少一个示例中，所述第三位置和所述第四位置均位于所述第一位置和所述第二位置之间。
例如，在所述阵列基板的至少一个示例中，所述第二信号线包括第一线段；所述第一线段为所述第二信号线的位于所述第一走线和所述第二走线之间的部分；以及所述第一线段和所述第三走线部分相对于所述第二方向朝向相同的方向倾斜。
例如，在所述阵列基板的至少一个示例中，所述第三位置位于第一中点和所述第一位置之间，所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点。
例如，在所述阵列基板的至少一个示例中，所述第一信号线为栅线；所述第三走线部分相对于所述第二方向的倾角大于所述第一线段相对于所述第二方向的倾角的三倍且小于所述第一线段相对于所述第二方向的倾角的四倍；所述第二信号线为数据线且所述第一走线部分的宽度大于所述第二信号线宽度的两倍且小于所述第二信号线宽度的三倍，或者所述第二信号线为公共电极线且所述第一走线部分的宽度大于所述第二信号线宽度的三倍且小于所述第二信号线宽度的四倍；以及所述第一走线部分的宽度小于所述第二边的长度且大于所述第一边的位于所述第一位置和所述第二位置之间的线段的长度。
例如，在所述阵列基板的至少一个示例中，所述第三位置与所述第一位置重合。
例如，在所述阵列基板的至少一个示例中，所述第一走线部分的宽度和所述第三走线部分的宽度相等；所述第二走线部分的宽度大于所述第一走线部分的宽度且小于所述第一走线部分的宽度的二倍。
例如，在所述阵列基板的至少一个示例中，所述第三位置位于第一中点 和所述第二位置之间；所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点；以及所述第二信号线在所述第一信号线所在电极层上的正投影的靠近所述第一走线部分的边与所述第二边的交点在所述第一边上的正投影位于所述第一中点远离所述第三位置的一侧。
例如，在所述阵列基板的至少一个示例中，所述第一信号线为栅线；所述第三走线部分相对于所述第二方向的倾角大于所述第一线段相对于所述第二方向的倾角的三倍且小于所述第一线段相对于所述第二方向的倾角的四倍；所述第二信号线为数据线且所述第一走线部分的宽度大于所述第二信号线宽度的两倍且小于所述第二信号线宽度的三倍，或者所述第二信号线为公共电极线且所述第一走线部分的宽度大于所述第二信号线宽度的三倍且小于所述第二信号线宽度的四倍；所述第一走线部分的宽度大于所述第二边的长度；以及所述第二走线部分的宽度大于所述第一走线部分的宽度的二倍且小于所述第一走线部分的宽度的三倍。
例如，在所述阵列基板的至少一个示例中，所述第三位置位于第一中点，所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点。
例如，在所述阵列基板的至少一个示例中，所述第二走线部分的宽度大于所述第一走线部分的宽度和所述第三走线部分的宽度；以及所述第一走线部分的宽度和所述第三走线部分的宽度相等。
例如，在所述阵列基板的至少一个示例中，所述第四位置与所述第二位置重合。
例如，在所述阵列基板的至少一个示例中，所述第一信号线和所述第二信号线的至少一根的坡度角位于40度-60度之间。
本公开的至少一个实施例还提供了一种控光面板，其包括：对置基板、液晶层，以及本公开的至少一个实施例提供的任一阵列基板。所述阵列基板和所述对置基板相对设置，所述液晶层夹置于所述阵列基板和所述对置基板之间。
本公开的至少一个实施例还提供了一种显示装置，其包括：显示面板、背光单元以及本公开的至少一个实施例提供的任一控光面板。所述显示面板、所述控光面板和所述背光单元层叠设置，所述显示面板位于所述控光面板的 出光侧，所述背光单元位于所述控光面板远离所述显示面板的一侧。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种液晶显示装置的截面示意图；
图1B示出了图1A所示的液晶显示装置的控光面板和显示面板的平面示意图；
图2A示出了图1A所示的液晶显示装置的显示面板的平面示意图；
图2B示出了图1A所示的液晶显示装置的控光面板的阵列基板的平面示意图；
图3A是图2B所示的阵列基板的控光像素单元的平面示意图；
图3B是位于图2B所示的阵列基板的第一区域的栅线的部分的放大图；
图3C是位于图2B所示的阵列基板的第二区域的栅线的部分的放大图；
图3D示出了数据线和栅线之间的交叠区域存在静电击穿导致的短路的示意图；
图3E示出了数据线公共电极线和栅线之间的交叠区域存在静电击穿导致的短路的示意图；
图4A是本公开的至少一个实施例提供的阵列基板的平面示意图；
图4B是图4A所示的阵列基板的控光像素单元的平面示意图；
图5A是位于图4A所示的阵列基板的第一区域的第一信号线的部分的一个示例的示意图；
图5B是位于图4A所示的阵列基板的第二区域的第一信号线的部分的一个示例的示意图；
图5C是图5A所示的第一信号线的部分的示例的另一个示意图；
图5D是图5B所示的第一信号线的部分的示例另一个示意图；
图6A是第一信号线和第二信号线之间的交叠三角形的示意图；
图6B是第一信号线和第三信号线之间的交叠三角形的示意图；
图7A是在第二信号线相对于第一信号线不具有对位误差情况下，图6A所示的第一信号线和第二信号线之间的交叠三角形的简化示意图；
图7B是第二信号线相对于第一信号线不具有对位误差情况下，图6A所示的第一信号线和第二信号线之间的交叠三角形的等效示意图；
图7C是第二信号线相对于第一信号线具有水平对位误差但不具有垂直对位误差的情况下，第一信号线和偏移后的第二信号线之间的交叠三角形的等效示意图；
图7D是第二信号线相对于第一信号线具有水平对位误差和垂直对位误差的情况下，第一信号线和偏移后的第二信号线之间的交叠三角形的等效示意图；
图8A是在第三信号线相对于第一信号线不具有对位误差情况下，图6B所示的第一信号线和第三信号线之间的交叠三角形的简化示意图；
图8B是第三信号线相对于第一信号线不具有对位误差情况下，图6B所示的第一信号线和第三信号线之间的交叠三角形的等效示意图；
图8C是第三信号线相对于第一信号线具有水平对位误差但不具有垂直对位误差的情况下，第一信号线和偏移后的第三信号线之间的交叠三角形的等效示意图；
图8D是第三信号线相对于第一信号线具有水平对位误差和垂直对位误差的情况下，第一信号线和偏移后的第三信号线之间的交叠三角形的等效示意图；
图9A是位于图4A所示的阵列基板的第一区域的第一信号线的部分的另一个示例的示意图；
图9B是位于图4A所示的阵列基板的第二区域的第一信号线的部分的另一个示例的示意图；
图9C是图9A所示的第一信号线的部分的示例的另一个示意图；
图9D是图9B所示的第一信号线的部分的示例另一个示意图；
图10A是图6A所示的第一信号线和第二信号线之间的交叠三角形的另一个简化示意图；
图10B是图6B所示的第一信号线和第三信号线之间的交叠三角形的另一个简化示意图；
图11A是位于图4A所示的阵列基板的第一区域的第一信号线的部分的再一个示例的示意图；
图11B是位于图4A所示的阵列基板的第二区域的第一信号线的部分的 再一个示例的示意图；
图11C是位于图4A所示的阵列基板的第一区域的第一信号线的部分的又再一个示例的示意图；
图11D是位于图4A所示的阵列基板的第二区域的第一信号线的部分的又再一个示例的示意图；
图12A是在信号线的坡度角较小的情况下信号线的截面示意图；
图12B是在信号线的坡度角较大的情况下因刻蚀偏差导致的钻蚀的示意图；
图13是本公开的至少一个实施例提供的控光面板的截面示意图；
图14是本公开的至少一个实施例提供的显示装置的截面示意图；
图15A是图14所示的显示装置的显示面板的平面示意图；以及
图15B是图14所示的显示装置的平面示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人在研究中注意到，普通的液晶显示装置(例如，具有单个液晶盒的基于高级超维场转换技术的液晶显示装置)的显示面板通常存在 暗态漏光问题，这使得液晶显示装置的显示画面的对比度较低。本公开的发明人在研究中注意到，可以采用具有双液晶盒的液晶显示装置(也即，基于双液晶盒区域亮度调节技术的液晶显示装置)来提升显示画面的对比度，下面结合图1A-图1B以及图2A-图2B进行示例性说明。
图1A示出了一种液晶显示装置500的截面示意图。如图1A所示，该液晶显示装置500包括在第三方向D3顺次设置的背光单元503、控光面板502和显示面板501。例如，控光面板502被配置为调节背光单元503发射的且入射至显示面板501上的光线的强度。例如，从控光面板502出射的光线为白光，也即，控光面板502不具有色彩调节功能。
图1B示出了图1A所示的液晶显示装置500的控光面板502和显示面板501的平面示意图；图2A示出了图1A所示的液晶显示装置500的显示面板501的平面示意图；图2B示出了图1A所示的液晶显示装置500的控光面板502的阵列基板的平面示意图。
如图1B和图2A所示，显示面板501包括多根沿第一方向D1延伸的第一信号线541以及多根沿第二方向D2延伸的第二信号线542；多根第一信号线541和多根第二信号线542相交界定多个阵列排布的显示子像素单元，多个显示子像素单元形成阵列排布的多个显示像素单元530；每个显示像素单元530包括第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533；第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533例如分别为红色显示子像素单元、绿色显示子像素单元和蓝色显示子像素单元。例如，第一方向D1、第二方向D2和第三方向D3彼此相交(例如，彼此垂直)。例如，第一信号线541为显示面板501的栅线，第二信号线542为显示面板501的数据线。
例如，控光面板502包括在第三方向D3上顺次设置的阵列基板(参加图2B)、液晶层(图中未示出)和对置基板(图中未示出)。
如图1B和图2B所示，控光面板502的阵列基板包括分别沿第一方向D1延伸的多根栅线510以及分别沿第二方向D2的延伸的多根数据线520；多根栅线510和多根数据线520相交界定多个控光像素单元530。例如，控光面板502还包括分别沿与第二方向D2的延伸的多根公共电极线560。例如，多根数据线520和多根公共电极线560在第一方向D1上交替布置。
例如，控光面板502包括阵列布置的多个控光单元(图中未示出)。例 如，阵列基板的多个控光像素单元530分别设置在对应的控光单元中。例如，控光单元还包括与控光像素单元在第三方向D3上叠置的液晶层的部分以及对置基板的部分。
例如，该控光面板502可以基于数据线520接收的数据信号来调节控光面板的各个控光单元的透射率，因此，控光面板502的控光单元可用于控制入射至对应于该控光单元的显示面板501的显示子像素单元上的光线的强度，由此控光面板502可用于向显示面板501提供调节后的背光。例如，通过在显示装置500中设置控光面板502，可以使得对应于液晶显示装置的显示画面的亮度较低(例如，亮度为零)的区域的控光单元的透射率较低(例如，透射率等于或接近于零)，此种情况下，显示面板501的可能的暗态漏光问题对显示画面的对比度的不利影响较小，由此采用具有双液晶盒的液晶显示装置(也即，具有控光面板的显示装置)可以提升显示画面的对比度。例如，通过在显示装置500中设置控光面板502，可以使得液晶显示装置500的对比度由1000提高到40000以上。
然而，本公开的发明人在研究中注意到，图1所示的液晶显示装置500的控光面板502的阵列基板出现(例如，在生产过程和/或使用过程中出现)因静电释放导致的不良的可能性较大，由此降低了液晶显示装置500的良率以及可靠性。本公开的发明人在研究中(例如，通过统计多个阵列基板存在静电释放导致的不良的位置)注意到，静电释放导致的不良(例如，短路)在数据线520和栅线510的交叠区域以及公共电极线560和栅线510的交叠区域出现的可能性较大。下面结合图1A-图1B、图2A-图2B以及图3A-图3C进行示例性说明。
如图1B和图2B所示，控光面板502的每根栅线510包括顺次直接相连多个第一折线结构515，多个第一折线结构515的每个包括顺次直接相连第一走线部分511、第二走线部分512、第三走线部分513和第四走线部分514。如图1B和图2B所示，控光面板502的每根数据线520包括顺次直接相连多个第二折线结构521，多个第二折线结构521的每个包括顺次直接相连第五走线部分522和第六走线部分523。如图1B和图2B所示，控光面板502的每根公共电极线560包括顺次直接相连多个第三折线结构561，多个第三折线结构561的每个包括顺次直接相连第七走线部分562和第八走线部分563。
图3A是图2B所示的阵列基板的控光像素单元530的平面示意图；图3B 是位于图2B所示的阵列基板的第一区域RE1的栅线510的部分的放大图；图3C是位于图2B所示的阵列基板的第二区域RE2的栅线510的部分的放大图。
例如，如图3B所示，数据线520和栅线510在垂直于阵列基板的方向上彼此交叠，且具有第一交叠区域581(例如，交叠三角形)；公共电极线560和栅线510在垂直于阵列基板的方向上彼此交叠，且具有第二交叠区域583(例如，交叠三角形)。
例如，在第一交叠区域581出现静电释放(Electro-Static discharge)时，数据线520和栅线510之间的绝缘层被击穿，数据线520和栅线510中的至少一个出现融化，并因此导致数据线520和栅线510之间短路。例如，由于第一交叠区域581的第一位置582(第一交叠区域581的锐角尖端)为交叠三角形角度最小的顶角，因此，第一位置582更容易累积静电，数据线520和栅线510之间短路更容易出现在第一交叠区域581的第一位置582。图3D示出了数据线520和栅线510之间的交叠区域的部分585存在静电击穿导致的短路的示意图。
例如，在第二交叠区域583出现静电释放时，公共电极线560和栅线510之间的绝缘层被击穿，公共电极线560和栅线510中的至少一个出现融化，并因此导致公共电极线560和栅线510之间短路。例如，由于第二交叠区域583的第二位置584更容易累积静电，因此，公共电极线560和栅线510之间短路更容易出现在第二交叠区域583的第二位置584(第二交叠区域583的尖端)。图3E示出了数据线公共电极线560和栅线510之间的交叠区域的部分586存在静电击穿导致的短路的示意图。
例如，由于数据线520和栅线510之间的短路以及公共电极线560和栅线510之间的短路降低了阵列基板以及包括该阵列基板的控光面板和液晶显示装置的良率和可靠性，由此亟需一种能够降低发生静电释放导致的不良的可能性的阵列基板。
本公开的至少一个实施例提供了一种阵列基板、控光面板和显示装置。该阵列基板包括用于整体沿第一方向延伸的子像素行的第一信号线，以及用于整体沿与第一方向交叉的第二方向延伸的子像素列的第二信号线。第一信号线包括顺次直接相连多个折线结构，多个折线结构的每个包括顺次直接相连的第一走线部分、第二走线部分和第三走线部分；第一走线部分的延伸方 向和第三走线部分的延伸方向均与第一方向和第二方向相交，第二走线部分沿第一方向延伸；第一走线部分的沿第一走线部分延伸方向延伸的中线与第二走线部分的沿第二走线部分延伸方向延伸的中线相交形成第一夹角；第二走线部分包括在第二方向上彼此对置的第一边和第二边，第一边位于第一夹角的内侧和第二边位于第一夹角的外侧；第一走线部分的靠近第二信号线的边在第一边的第一位置与第一边相交，第三走线部分的靠近第二信号线的边在第一边的第二位置与第一边相交；第二信号线的在第一信号线所在电极层上的正投影的靠近第一走线部分的边在第一边的第三位置与第一边相交，第二信号线的在第一信号线所在电极层上的正投影的靠近第三走线部分的边在第一边的第四位置与第一边相交；以及第一边的位于第一位置和第二位置之间的线段的长度大于第一边的位于第三位置和第四位置之间的线段长度。例如，该阵列基板、控光面板和显示装置可以降低因静电释放导致的不良(例如，短路不良)的可能性。
下面通过几个示例或实施例对根据本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例或实施例中不同特征可以相互组合，从而得到新的示例或实施例，这些新的示例或实施例也都属于本公开保护的范围。
图4A是本公开的至少一个实施例提供的阵列基板100的平面示意图。如图4A所示，该阵列基板100包括用于整体沿第一方向D1延伸的子像素行的第一信号线110，以及用于整体沿与第一方向D1交叉的第二方向D2延伸的子像素列的第二信号线130。第一方向D1和第二方向D2彼此交叉(例如，彼此垂直)。
例如，如图4A所示，该阵列基板100包括多根第一信号线110和多根第二信号线130；多根第一信号线110和多根第二信号线130交叉并形成阵列排布的多个控光像素单元134。图4B是图4A所示的阵列基板100的控光像素单元134的平面示意图。
例如，如图4A所示，位于同一行的控光像素单元134形成整体沿第一方向D1延伸的子像素行，阵列基板100包括在第二方向D2排布的多行子像素行；位于同一列的控光像素单元134形成整体沿第二方向D2延伸的子像素列，阵列基板100包括在第一方向D1排布的多列子像素列。
例如，如图4A所示，多根第一信号线110与多行子像素行一一对应，且 多根第一信号线110被配置为驱动对应的子像素行；多根第二信号线130与多列子像素列一一对应，且多根第二信号线130被配置为驱动对应的子像素列。例如，第一信号线110和第二信号线130与不同的信号源电连接。例如，第一信号线110是栅线且与包括该阵列基板100的显示装置的栅极驱动电路电连接；第二信号线130是数据线且与包括该阵列基板100的显示装置的数据驱动电路电连接。
例如，如图4A所示，多根第一信号线110的每根整体沿第一方向D1延伸；多根第二信号线130的每根整体沿第二方向D2延伸。需要说明的是，多根第一信号线110的每根整体沿第一方向D1延伸仅限定了第一信号线110的整体延伸方向，而并不表示第一信号线110包括的各个走线部分均平行于第一方向D1；多根第二信号线130的每根整体沿第二方向D2延伸仅限定了第二信号线130的整体延伸方向，而并不表示第二信号线130包括的各个走线部分均平行于第二方向D2。
如图4A所示，第一信号线110(例如，多根第一信号线110的每根)包括顺次直接相连多个折线结构111(第一折线结构)，多个折线结构111的每个包括顺次直接相连的第一走线部分112、第二走线部分113、第三走线部分114和第四走线部分115；第一走线部分112的延伸方向和第三走线部分114的延伸方向均与第一方向D1和第二方向D2相交，第二走线部分113和第四走线部分115分别沿第一方向D1延伸。例如，如图4A所示，除位于最右侧的折线结构111，多个折线结构111的每个的第四走线部分115(第四走线部分115的远离多个折线结构111的每个的第一走线部分112的一端)与位于该多个折线结构111的每个的右侧的另一个折线结构111的第一走线部分112(第一走线部分112的远离另一个折线结构111的第四走线部分115的一端)直接相连。
例如，第一走线部分112、第二走线部分113、第三走线部分114和第四走线部分115均为直线线段，但本公开的至少一个实施例不限于此。又例如，第一走线部分112、第二走线部分113、第三走线部分114和第四走线部分115的至少一个为曲线线段。
例如，如图4A所示，第二信号线130(例如，多根第二信号线130的每根)包括顺次直接相连多个第二折线结构131，多个第二折线结构131的每个包括顺次直接相连的第一线段132和第二线段133；第一线段132的延伸方向 和第二线段133的延伸方向均与第一方向D1和第二方向D2相交。例如，如图4A所示，除位于最上侧的第二折线结构131，多个第二折线结构131的每个的第二线段133(例如，第二线段133远离多个第二折线结构131的每个的第一线段132的一端)与位于该多个第二折线结构131的每个的上侧的另一个第二折线结构131的第一线段132(例如，第一线段132远离另一个第二折线结构131的第二线段133的一端)直接相连。例如，第一线段132和第二线段133均为直线线段，
例如，如图4A所示，阵列基板100还包括多根第三信号线140，多根第三信号线140的每根整体沿第二方向D2。第三信号线140(例如，多根第三信号线140的每根)包括顺次直接相连多个第三折线结构141，多个第三折线结构141的每个包括顺次直接相连的第三线段142和第四线段143；第三线段142的延伸方向和第四线段143的延伸方向均与第一方向D1和第二方向D2相交。例如，如图4A所示，除位于最下侧的第三折线结构141，多个第三折线结构141的每个的第四线段143与位于该多个第三折线结构141的每个的下侧的另一个第三折线结构141的第三线段142直接相连。例如，第三信号线140是公共电极线且配置为接收公共电压。例如，第三线段142和第四线段143均为直线线段，
图5A是位于图4A所示的阵列基板100的第一区域RE1的第一信号线110的部分的一个示例的示意图。如图5A所示，第一走线部分112的沿第一走线部分112的延伸方向延伸的中线151与第二走线部分113的沿第二走线部分113的延伸方向延伸的中线152相交形成第一夹角α1；第二走线部分113包括在第二方向D2上彼此对置的第一边121和第二边122，第一边121位于第一夹角α1的内侧，第二边122位于第一夹角α1的外侧。
如图5A所示，第一走线部分112的靠近第二信号线130(例如，第二信号线130的第一线段132)的边在第一边121的第一位置P1与第一边121相交，第三走线部分114的靠近第二信号线130(例如，第二信号线130的第一线段132)的边在第一边121的第二位置P2与第一边121相交；第二信号线130在第一信号线110所在电极层上的正投影的靠近第一走线部分112的边在第一边121的第三位置P3与第一边121相交，第二信号线130在第一信号线110所在电极层上的正投影的靠近第三走线部分114的边在第一边121的第四位置P4与第一边121相交。
如图5A所示，第一边121的位于第一位置P1和第二位置P2之间的线段的长度大于第一边121的位于第三位置P3和第四位置P4之间的线段长度。例如，通过使得第一边121的位于第一位置P1和第二位置P2之间的线段的长度大于第一边121的位于第三位置P3和第四位置P4之间的线段长度，可以增加第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间的可能性，因此可以降低第二信号线130与第一信号线110的第三走线部分114交叠的可能性，由此可以降低第二信号线130和第一信号线110之间形成交叠三角形(例如图3B所示的交叠三角形)的可能性以及降低因静电释放导致的不良(例如，短路不良)的可能性。
例如，如图5A所示，第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间。需要说明的是，第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间包括第三位置P3与第一位置P1重合，第四位置P4与第二位置P2重合的情况。
例如，通过使得第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间，可以避免第二信号线130和第一信号线110之间形成交叠三角形(例如图3B所示的交叠三角形)以及降低因静电释放导致的不良(例如，短路不良)的可能性。
需要说明的是，第三位置P3和第四位置P4不限于均位于第一位置P1和第二位置P2之间。例如，在第四位置P4位于第二位置P2远离第一位置P1的一侧，且第二信号线130和第一信号线110之间形成的交叠三角形的面积小于图3B所示的交叠三角形的情况下，也可能降低因静电释放导致的不良(例如，第二信号线130和第一信号线110之间短路不良)的可能性。
例如，如图4A和图5A所示，第一线段132为第二信号线130的位于第一走线和第二走线之间的部分；第一线段132和第三走线部分114相对于第二方向D2朝向相同的方向倾斜。例如，如图4A和图5A所示，第一线段132和第三走线部分114均朝向第二方向D2的右侧倾斜。
图5B是位于图4A所示的阵列基板100的第二区域RE2的第一信号线110的部分的一个示例的示意图。如图5B所示，第三走线部分114的沿第三走线部分114的延伸方向延伸的中线153与第四走线部分115的沿第四走线部分115的延伸方向延伸的中线154相交形成第二夹角α2；第四走线部分115包括在第二方向D2上彼此对置的第三边123和第四边124，第三边123位于 第二夹角α2的内侧和第四边124位于第二夹角α2的外侧。
如图5B所示，第三走线部分114的靠近第三信号线140(例如，第三信号线140的第三线段142)的边在第三边123的第五位置P5与第三边123相交，第一走线部分112的靠近第三信号线140(例如，第三信号线140的第三线段142)的边在第三边123的第六位置P6与第三边123相交；第三信号线140在第一信号线110所在电极层上的正投影的靠近第三走线部分114的边在第三边123的第七位置P7与第三边123相交，第三信号线140在第一信号线110所在电极层上的正投影的靠近第一走线部分112的边在第三边123的第八位置P8与第三边123相交。
如图5B所示，第三边123的位于第五位置P5和第六位置P6之间的线段的长度大于第三边123的位于第七位置P7和第八位置P8之间的线段长度。例如，通过使得第三边123的位于第五位置P5和第六位置P6之间的线段的长度大于第三边123的位于第七位置P7和第八位置P8之间的线段长度，可以增加第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间的可能性，因此可以降低第三信号线140与第一信号线110的第一走线部分112交叠的可能性，由此可以降低第三信号线140和第一信号线110之间形成的交叠三角形(例如，图3C所示的交叠三角形)的可能性以及降低因静电释放导致的不良(例如，短路不良)的可能性。
例如，如图5B所示，第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间。需要说明的是，第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间包括第七位置P7与第五位置P5重合，第八位置P8与第六位置P6重合。
例如，通过使得第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间，可以避免第三信号线140和第一信号线110之间形成交叠三角形(例如，图3C所示的交叠三角形)以及降低因静电释放导致的不良(例如，第三信号线140和第一信号线110之间的短路不良)的可能性。
在一个示例中，第三位置P3位于第一中点M1和第一位置P1之间，第七位置P7位于第二中点M2和第五位置P5之间；此处，第一中点M1为第一边121的位于第一位置P1和第二位置P2之间的线段的中点，第二中点M2为第三边123的位于第五位置P5和第六位置P6之间的线段的中点。下面结合图5A-图5D进行示例性说明。
图5C是图5A所示的第一信号线110的部分的示例的另一个示意图，图5D是图5B所示的第一信号线110的部分的示例另一个示意图。如图4A、图5A-图5D所示，第三走线部分114相对于第二方向D2的倾角θ1大于第一线段132相对于第二方向D2的倾角θ2的三倍且小于第一线段132相对于第二方向D2的倾角θ2的四倍；第一走线部分112相对于第二方向D2的倾角θ3大于第三线段142相对于第二方向D2的倾角θ4的三倍且小于第三线段142相对于第二方向D2的倾角θ4的四倍(此处的倾角θ1-θ4是锐角且为正值)；第一走线部分112的宽度Lg1等于第三走线部分114的宽度Lg3相等；第一走线部分112的宽度Lg1大于第二信号线130的宽度Ld的两倍且小于第二信号线130的宽度Ld的三倍；第一走线部分112的宽度Lg1大于第三信号线140宽度Lc的三倍且小于第三信号线140宽度Lc的四倍；第二信号线130的宽度Ld大于第三信号线140宽度Lc；第一走线部分112的宽度Lg1小于第二边122的长度L2且大于第一边121的位于第一位置P1和第二位置P2之间的线段的长度L1；第一走线部分112的宽度Lg1小于第四边124的长度L4且大于第三边123的位于第五位置P5和第六位置P6之间的线段的长度L3。
例如，第一边121的位于第一位置P1和第二位置P2之间的线段的长度L1大于第三边123的位于第五位置P5和第六位置P6之间的线段的长度L3。例如，第二边122的长度L2大于第四边124的长度L4。例如，第三走线部分114相对于第二方向D2的倾角θ1等于第一走线部分112相对于第二方向D2的倾角θ3；第一线段132相对于第二方向D2的倾角θ2等于第三线段142相对于第二方向D2的倾角θ4。例如，第二走线部分113的宽度Lg2大于第一走线部分112的宽度Lg1且小于第一走线部分112的宽度Lg1的二倍；第四走线部分115的宽度Lg4大于第二走线部分113的宽度Lg2。
需要说明的是，走线部分的宽度是指：走线部分在垂直于走线部分的延伸方向的宽度。例如，第二走线部分113的宽度是指第二走线部分113在第二方向D2上的宽度，第四走线部分115的宽度是指第四走线部分115在第二方向D2上的宽度。
在图5A-图5D所示的示例中，Lg1＝Lg3＝20微米，Ld＝8微米，Lc＝6微米，θ1＝θ3＝27度，θ2＝θ4＝7度；L1＝13微米，L2＝26微米，L3＝11微米，L4＝23微米。在图5A-图5D所示的示例中，例如，Lg2＝31.3微米；Lg4＝32.3微米。
下面结合图7A-图7D以及8A-图8D对如何通过重新设置图6A-图6B中 的L1b、L2b、L3b和L4b(也即，将L1b、L2b、L3b和L4b分别设置为L1、L2、L3和L4)来消除或减小图6A-图6B中第一信号线110和第二信号线130之间的交叠三角形以及第一信号线110和第三信号线140之间的交叠三角形(以获得图5A-图5D的结构)的设计思路进行示例性说明。
图6A是第一信号线110(例如，第一信号线110的第三走线部分114)和第二信号线130之间的交叠三角形的示意图；图6B是第一信号线110和第三信号线140之间的交叠三角形的示意图。在图6A和图6B的示例中，Lg1＝Lg3＝20微米，Ld＝8微米，Lc＝6微米，θ1＝θ3＝27度，θ2＝θ4＝7；L1b＝5微米、L2b＝18微米、L3b＝5微米，L4b＝17微米。
需要说明的是，第一信号线110和第二信号线130之间的交叠三角形是指第二信号线130在第一信号线110所在电极层上的正投影与第一信号线110形成的交叠三角形；第一信号线110和第三信号线140之间的交叠三角形是指第三信号线140在第一信号线110所在电极层上的正投影与第一信号线110形成的交叠三角形。
需要说明的是，本公开的至少一个实施例提供的设计思路不限于消除图6A和图6B的示例中的交叠三角形，在Lg1、Lg3、Ld、Lc以及θ1-θ4的取值变化时，可以采用类似的设计思路设置L1-L4来消除或减小第一信号线110和第二信号线130之间的交叠三角形以及第一信号线110和第三信号线140之间的交叠三角形。
下面结合图7A-图7D对如何消除或减小第一信号线110(例如，第一信号线110的第三走线部分114)和第二信号线130之间的交叠三角形的一种设计思路(也即，通过将第一信号线110的第三走线部分114向远离第二信号线130的一侧平移)进行示例性说明。
图7A是在第二信号线130相对于第一信号线110不具有对位误差情况下，图6A所示的第一信号线110和第二信号线130之间的交叠三角形的简化示意图。图7B是第二信号线130相对于第一信号线110不具有对位误差情况下，图6A所示的第一信号线110和第二信号线130之间的交叠三角形△ABC的等效示意图。如图7A和图7B所示，假设在制作过程中不存在对位误差的情况下，第二信号线130的左边界L经过线段MB(其长度等于L1b)的中点，且直角坐标系的原点O位于线段MC的中点。
图7C是第二信号线130相对于第一信号线110具有水平对位误差(也即， 沿x轴的对位误差)但不具有垂直对位误差(也即，沿y轴的对位误差)的情况下，第一信号线110和偏移后(相对于图6A所示的第二信号线偏移)的第二信号线130之间的交叠三角形△A1BC1的等效示意图；图7D是第二信号线130相对于第一信号线110具有水平对位误差和垂直对位误差的情况下，第一信号线110和偏移后(相对于图6A所示的第二信号线偏移)的第二信号线130之间的交叠三角形△A2BC2的等效示意图。例如，第二信号线130相对于第一信号线110的最大水平对位误差的绝对值为DX，第二信号线130相对于第一信号线110的最大垂直对位误差的绝对值为DY。例如，DX＝DY＝1.5微米。如图7B-7D所示，在第二信号线130相对于第一信号线110向右平移DX且向下平移DY时，第一信号线110和第二信号线130之间的交叠三角形的面积最大。因此，为了更好的消除第一信号线110和第二信号线130之间的交叠三角形，可以基于图7D所示的交叠三角形△A2BC2进行设计。
例如，可以采用以下的设计思路消除图7D所示的交叠三角形。
首先，获取图7D所示的交叠三角形△A2BC2中线段A2C2所在的直线的方程。具体方法如下。(1)获取在第二信号线130相对于第一信号线110不具有对位误差情况下(参见图7B)，交叠三角形△ABC中BC线段的长度L_BC＝L_OC-L_OB＝L_A’A-L_OB＝Ld/sin(90-θ2)-L_MB/2。(2)获取在第二信号线130相对于第一信号线110在水平方向上具有对位误差DX但不具有垂直误差的情况下(参见图7C)，交叠三角形△A1BC1中BC1线段的长度L_BC1＝L_BC+L_CC1＝L_BC+DX＝Ld/sin(90-θ2)-L_MB/2+DX；例如，L_BC1＝8/sin(83)-2.5+1.5＝7.06微米。(3)获取线段A1C1所在的直线的方程y_A1C1＝(x-L_OC1)tan(90-θ2)＝(x-L_BC1-L_OB)tan(90-θ2)＝(x-L_BC1-L_MB/2)tan(90-θ2)。(4)获取在第二信号线130相对于第一信号线110在水平方向上具有对位误差DX且在垂直方向上具有对位误差DY的情况下(参见图7F)，交叠三角形△A2BC2中线段A2C2所在的直线的方程y_A2C2＝(x--L_BC1-L_MB/2)tan(90-θ2)-DY＝(x-7.06-2.5)tan(83°)-1.5＝(x-9.56)tan(83°)-1.5。需要说明的是，L_XX表示线段XX的长度。例如，L_CC1表示线段CC1的长度。
其次，获取线段MC2的长度L_MC2＝L_MO+L_OC2＝L_MB/2+DY/tan(90-θ2)+L_BC1+L_MB/2；例如，L_MC2＝2.5+1.5/tan(83)+7.06+2.5＝12.244。
第三，基于L_MC2设定L1和L2；例如，可以使得L1＝L_MC2；又例如，还可以使得L1略大于L_MC2，以更好的消除交叠三角形；此处，L1＝13微米。例如，L2＝L2b-L1b+L1＝18-5+13＝26微米。
下面结合图8A-图8D对如何消除或减小第一信号线110(第一信号线110的第一走线部分112)和第三信号线140之间的交叠三角形的一种设计思路(也即，通过将第一信号线110的第一走线部分112向远离第三信号线140的一侧平移)进行示例性说明。消除或减小第一信号线110和第三信号线140之间的交叠三角形的设计思路与图7A-图7D所述的消除或减小第一信号线110和第二信号线130之间的交叠三角形的设计思路类似，重复之处不再赘述。
图8A是在第三信号线140相对于第一信号线110不具有对位误差情况下，图6B所示的第一信号线110和第三信号线140之间的交叠三角形的简化示意图。图8B是第三信号线140相对于第一信号线110不具有对位误差情况下，图6B所示的第一信号线110和第三信号线140之间的交叠三角形△FDE的等效示意图；如图8A和图8B所示，假设在制作过程中不存在对位误差的情况下，第三信号线140的左边界S经过线段QD的中点，且直角坐标系的原点P位于线段QD的中点。此处，线段QD的长度等于L3b。
图8C是第三信号线140相对于第一信号线110具有水平对位误差(也即，沿x轴的对位误差)但不具有垂直对位误差(也即，沿y轴的对位误差)的情况下，第一信号线110和偏移后(相对于图6B所示的第三信号线偏移)第三信号线140之间的交叠三角形△F1DE1的等效示意图；图8D是第三信号线140相对于第一信号线110具有水平对位误差和垂直对位误差的情况下，第一信号线110和偏移后(相对于图6B所示的第三信号线偏移)第三信号线140之间的交叠三角形△F2DE2的等效示意图。例如，第三信号线140相对于第一信号线110的最大水平对位误差的绝对值为DX，第三信号线140相对于第一信号线110的最大垂直对位误差的绝对值为DY。例如，DX＝DY＝1.5微米。如图8B-8D所示，在第三信号线140相对于第一信号线110向右平移DX且向上平移DY时，第一信号线110和第三信号线140之间的交叠三角形的面积最大。因此，为了更好的消除第一信号线110和第三信号线140之间的交叠三角形，可以基于图8D所示的交叠三角形△F2DE2进行设计。
例如，可以采用以下的设计思路消除图8D所示的交叠三角形。
首先，获取图8D所示的交叠三角形△F2DE 2中线段F2E2所在的直线的 方程。具体方法如下。(1)获取在第三信号线140相对于第一信号线110不具有对位误差情况下(参见图8B)，交叠三角形△FDE中DE线段的长度L_DE＝L_PE-L_PD＝L_F’F-L_PD＝Lc/sin(90-θ4)-L_QD/2。(2)获取在第三信号线140相对于第一信号线110在水平方向上具有对位误差DX但不具有垂直误差的情况下(参见图8C)，交叠三角形△F1DE1中DE1线段的长度L_DE1＝L_DE+L_EE1＝L_DE+DX＝Lc/sin(90-θ4)-L_QD/2+DX；例如，L_DE1＝6/sin(83)-2.5+1.5＝5.05微米。(3)获取线段F1E1所在的直线的方程y_F1E1＝(x-L_PE1)tan(90+θ4)＝(x-L_DE1-L_PD)tan(90+θ4)＝(x-L_DE1-L_QD/2)tan(90+θ4)。(4)使用以下的推导过程获取在第二信号线130相对于第一信号线110在水平方向上具有对位误差DX且在垂直方向上具有对位误差DY的情况下(参见图7F)，交叠三角形△F2DE2中线段F2E2所在的直线的方程y_F2E2。
y_F2E2＝(x--L_DE1-L_QD/2)tan(90+θ4)+DY
＝(x-5.05-2.5)tan(97°)+1.5＝(x-7.55)tan(97°)+1.5。
其次，使用以下的推导过程获取线段QE2的长度。
L_QE2＝L_QP+L_PE2
＝L_QD/2-DY/tan(90+θ4)+L_DE1+L_QD/2。
例如，L_QE2＝2.5-1.5/tan(97)+5.05+2.5＝10.234。
第三，基于L_QE2设定L3和L4；例如，可以使得L3＝L_QE2；又例如，还可以使得L3略大于L_QE2，以更好的消除交叠三角形；此处，L3＝11微米。最后，获取L4＝L4b-L3b+L3＝17-5+11＝23微米。
综上，通过将第一信号线110的第三走线部分114向远离第二信号线130的一侧平移以及将第一信号线110的第一走线部分112向远离第三信号线140的一侧平移，可以将图6A和图6B所示的L1b、L2b、L3b和L4b分别设置为13微米、26微米、11微米和23微米，由此可以消除或减小第一信号线110和第二信号线130之间的交叠三角形以及第一信号线110和第三信号线140之间的交叠三角形，并可以抑制静电释放导致的不良(短路不良)。
例如，在一个示例中，第四位置P4可以与第二位置P2重合；第八位置P8可以与第六位置P6重合，但本公开的实施例不限于此。例如，第四位置P4与第二位置P2接近但不重合；第八位置P8与第六位置P6接近但不重合。
在另一个示例中，第三位置P3位于第一中点M1和第二位置P2之间； 第七位置P7位于第二中点M2和第八位置P8之间；第二信号线130(例如，第二信号线130的第一线段132)靠近第一走线部分112的边与第二边122的交点在第一边121上的正投影位于第一中点M1远离第三位置P3的一侧；第三信号线140(例如，第三信号线140的第三线段142)靠近第三走线部分114的边与第四边124的交点在第三边123上的正投影位于第二中点M2远离第七位置P7的一侧。例如，第二走线部分113的宽度和第四走线部分115的宽度均大于第一走线部分112的宽度；第一走线部分112的宽度例如等于第三走线部分114的宽度。下面结合图9A-图9D进行示例性说明。需要说明的是，点在边上的正投影是指该点到该边的垂线与该边的交点。
图9A是位于图4A所示的阵列基板100的第一区域RE1的第一信号线110的部分的另一个示例的示意图，图9B是位于图4A所示的阵列基板100的第二区域RE2的第一信号线110的部分的另一个示例的示意图，图9C是图9A所示的第一信号线110的部分的示例的另一个示意图，图9D是图9B所示的第一信号线110的部分的示例另一个示意图。
图9A所示第一信号线110的部分的结构以及第一信号线110与第二信号线130的交叠关系与图5A类似，图9B所示第一信号线110的部分的结构以及第一信号线110与第三信号线140的交叠关系与图5B类似。因此，此处将仅阐述图9A与图5A的不同之处以及图9B与图5B的不同之处，相同之处不再赘述。
如图9A-图9D所示，第三走线部分114相对于第二方向D2的倾角θ1大于第一线段132相对于第二方向D2的倾角θ2的三倍且小于第一线段132相对于第二方向D2的倾角θ2的四倍；第一走线部分112相对于第二方向D2的倾角θ3大于第三线段142相对于第二方向D2的倾角θ4的三倍且小于第三线段142相对于第二方向D2的倾角θ4的四倍(此处的倾角θ1-θ4是锐角且为正值)；第一走线部分112的宽度Lg1大于第二信号线130的宽度Ld的两倍且小于第二信号线130的宽度Ld的三倍；第一走线部分112的宽度Lg1大于第三信号线140宽度Lc的三倍且小于第三信号线140宽度Lc的四倍；第二信号线130的宽度Ld大于第三信号线140宽度Lc；第一走线部分112的宽度Lg1大于第二边122的长度L2以及第四边124的长度L4；第二走线部分113的宽度Lg2大于第一走线部分112的宽度Lg1的二倍且小于第一走线部分112的宽度Lg1的三倍；第四走线部分115的宽度Lg4大于第一走线部 分112的宽度Lg1的二倍且小于第一走线部分112的宽度Lg1的三倍。
例如，第二走线部分113的宽度Lg2大于第四走线部分115的宽度Lg4。例如，第三走线部分114相对于第二方向D2的倾角θ1等于第一走线部分112相对于第二方向D2的倾角θ3；第一线段132相对于第二方向D2的倾角θ2等于第三线段142相对于第二方向D2的倾角θ4。
在图9A-图9D所示的示例中，例如，Lg1＝Lg3＝20微米，Ld＝8微米，Lc＝6微米；θ1＝θ3＝27度，θ2＝θ4＝7度；L2＝18微米，L4＝17微米；Lg2＝51微米；Lg4＝47微米。
下面结合图7A-图7D、图8A-图8D和图10A-图10B对如何通过重新设置图6A-图6B中的L1b、L2b、L3b、L4b、Lg2和Lg4(也即，将L1b、L2b、L3b、L4b、Lg2和Lg4分别设置为L1、L2、L3、L4、Lg2和Lg4)来消除或减小图6A-图6B中第一信号线110和第二信号线130之间的交叠三角形以及第一信号线110和第三信号线140之间的交叠三角形(以获得图9A-图9D的结构)的设计思路进行示例性说明。
下面结合图7A-图7D以及图10A对如何消除或减小图6A所示的第一信号线110(第一信号线110的第三走线部分114)和第二信号线130之间的交叠三角形的另一种设计思路(也即，通过增加第二走线部分113的宽度)进行示例性说明。
首先，使用线段A2C2所在直线的方程以及线段A2B所在直线的方程获取图7D所示的交叠三角形△A2BC2中A2点的坐标；线段A2C2所在直线的方程为y_A2C2＝(x--L_BC1-L_MB/2)tan(90-θ2)-DY＝(x-9.56)tan(83°)-1.5；线段A2B所在直线的方程为y_A2B＝(x-L_OB)tan(90-θ1)＝(x-2.5)tan(63)；通过联立上述两个方程可以得到A2点的坐标为(12.04,18.73)，因此，线段A2Z的长度L_A2Z＝18.73。
其次，通过以下的推导获取图7A所示的第二走线部分113的宽度Lg2b。
Lg2b＝L_OO1＝L_T1T4
＝L_T1T2×tan(90-θ1)
＝(L_OT2-L_OT1)×tan(90-θ1)
＝(L_OB+L_BT2-L_O1T4)×tan(90-θ1)
＝(L_MB/2+L_g3/sin(90-θ1)-L_2b/2)×tan(90-θ1)
＝(2.5+20/sin(63)-9)×tan(63°)
＝31.3(微米)。
然后，使得Lg2＞Lg2b+L_A2Z＝31.3+18.73＝50.03微米。例如，使得Lg2＝51微米。
下面结合图8A-图8D以及图10B对如何消除或减小图6B所示的第一信号线110(第一信号线110的第一走线部分112)和第三信号线140之间的交叠三角形的另一种设计思路(也即，通过增加第四走线部分115的宽度)进行示例性说明。
首先，使用线段F2E2所在直线的方程以及线段F2D所在直线的方程获取图7D所示的交叠三角形△F2DE2中F2点的坐标；F2E2所在直线的方程为y_F2E2＝(x--L_DE1-L_QD/2)tan(90+θ4)+DY＝(x-7.55)tan(97°)+1.5；线段F2D所在直线的方程为y_F2D＝(x-L_PD)tan(90+θ3)＝(x-2.5)tan(117°)；通过联立上述两个方程可以得到F2点的坐标为(9.396，-13.534)，因此，线段A2Z的长度L_F2Z2＝13.534。
其次，通过以下的推导获取图8A所示的第四走线部分115的宽度LG4b
Lg4b＝L_PP1＝L_G1G4
＝L_G1G2×tan(90-θ1)
＝(L_PG2-L_PG1)×tan(90-θ1)
＝(L_PQ+L_QG2-L_P1G4)×tan(90-θ1)
＝(L_QD/2+L_g3/sin(90-θ1)-L_4b/2)×tan(90-θ1)
＝(2.5+20/sin(63)-8.5)×tan(63°)
＝32.3(微米)。
然后，使得Lg4＞Lg4b+L_F2Z2＝32.3+13.534＝45.834微米。例如，使得Lg4＝47微米。
在另一个示例中，例如，第四位置P4可以与第二位置P2重合；第八位置P8可以与第六位置P6重合，但本公开的实施例不限于此。例如，第四位置P4与第二位置P2接近但不重合；第八位置P8与第六位置P6接近但不重合。
在再一个示例中，第三位置P3位于第一中点M1；第七位置P3位于第二中点M2。例如，第二走线部分113的宽度和第四走线部分115的宽度均大于第一走线部分112的宽度；第一走线部分112的宽度例如等于第三走线部分114的宽度。下面结合图11A和图11B进行示例性说明。
图11A是位于图4A所示的阵列基板的第一区域的第一信号线的部分的再一个示例的示意图；图11B是位于图4A所示的阵列基板的第二区域的第一信号线的部分的再一个示例的示意图。
如图11A所示，第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间，且第三位置P3位于第一中点M1。如图11B所示，第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间，且第七位置P3位于第二中点M2。例如，如图11A所示，第四位置P4与第二位置P2接近但不重合；如图11B所示，第八位置P8与第六位置P6重合，但本公开的实施例不限于此。例如，第四位置P4与第二位置P2重合；第八位置P8与第六位置P6接近但不重合。
在再一个示例中，可以同时利用平移第一信号线110的第三走线部分114的设计思路以及增加第二走线部分113的宽度的设计思路来减小或消除第一信号线110的第三走线部分114和第二信号线130之间的交叠三角形；同时利用平移第一信号线110的第一走线部分112的设计思路以及增加第四走线部分115的宽度的设计思路来减小或消除第一信号线110的第一走线部分112和第二信号线130之间的交叠三角形；具体设计思路可以参见先前的示例，在此不做赘述。
例如，通过利用平移第一信号线110的第三走线部分114的设计思路以及增加第二走线部分113的宽度的设计思路来减小或消除第一信号线110的第三走线部分114和第二信号线130之间的交叠三角形，可以避免第二走线部分113的宽度和长度增加过多，由此可以更好的兼容当前的制造工艺。
在又再一个示例中，第三位置P3位于第一位置P1和第一中点M1之间；第七位置P7位于第五位置P5和第二中点M2之间。例如，第三位置P3与第一位置P1的间距较小；第七位置P7与第五位置P5的间距较小。下面结合图11C和图11D进行示例性说明。
图11C是位于图4A所示的阵列基板的第一区域的第一信号线的部分的又再一个示例的示意图；图11D是位于图4A所示的阵列基板的第二区域的第一信号线的部分的又再一个示例的示意图。
如图11C和图11D所示，第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间，第七位置P7和第八位置P8均位于第五位置P5和第六位置P6之间。
例如，如图11C和图11D所示，第三位置P3与第一位置P1重合；如图11B所示，且第七位置P3与第五位置P5重合；但本公开的实施例不限于此。例如，第三位置P3与第一位置P1重合；第七位置P3与第五位置P5接近但不重合；又例如，第三位置P3与第一位置P1以及第七位置P3与第五位置P5均接近但不重合。需要说明的是，两个位置接近但不重合是指两个位置之间的间距大于零小于两微米(例如，小于一微米)。
例如，如图11C和图11D所示，第四位置P4与第二位置P2重合；第八位置P8与第六位置P6重合，但本公开的实施例不限于此。例如，第四位置P4与第二位置P2接近但不重合；第八位置P8与第六位置P6接近但不重合。
例如，第一走线部分112的宽度和第三走线部分114的宽度相等；第二走线部分113的宽度大于第一走线部分112的宽度且小于第一走线部分112的宽度的二倍。
在又再一个示例中，可以通过以下的设计和/或制作思路消除或减小交叠三角形；例如，可以通过以下的设计和/或制作思路使得第三位置P3位于第一位置P1和第一中点M1之间(例如，使得第三位置P3与第一位置P1重合)，第七位置P7位于第五位置P5和第二中点M2之间(例如，使得第七位置P7与第五位置P5重合)。
例如，可以通过减小第一信号线110的宽度(例如，第一信号线110的第一走线部分112和第三走线部分114的宽度)来增加第一边121位于第一位置P1和第二位置P2之间的线段的长度以及第三边123位于第五位置P5和第六位置P6之间的线段的长度。例如，可以通过减小第二信号线130的宽度来减小第一边121的位于第三位置P3和第四位置P4之间的线段长度。例如，可以通过减小第三信号线140的宽度来减小第三边123的位于第七位置P7和第八位置P8之间的线段长度。例如，可以通过减小第一信号线110、第二信号线130和第三信号线140的至少一个(例如，第一信号线110、第二信号线130和第三信号线140的每根)的宽度，可以使得第一边121的位于第一位置P1和第二位置P2之间的线段的长度大于第一边121的位于第三位置P3和第四位置P4之间的线段长度以及使得第三边123位于第五位置P5和第六位置P6之间的线段的长度大于第三边123的位于第七位置P7和第八位置P8之间的线段长度，此种情况下，可以增加第三位置P3和第四位置P4均位于第一位置P1和第二位置P2之间的可能性以及增加第七位置P7和第八位置P8均 位于第五位置P5和第六位置P6之间的可能性，并可以降低第二信号线130与第一信号线110的第三走线部分114交叠的可能性以及第三信号线140与第一信号线110的第一走线部分112交叠的可能性，由此可以降低第二信号线130和第一信号线110之间形成交叠三角形的可能性以及第三信号线140和第一信号线110之间形成交叠三角形的可能性，进而可以降低因静电释放导致的不良(例如，短路不良)的可能性。
例如，可以通过减小第一信号线110、第二信号线130和第三信号线140的至少一个(例如，第一信号线110、第二信号线130和第三信号线140的每根)的线宽设计值来减小阵列基板100的第一信号线110、第二信号线130和第三信号线140的至少一个(例如，第一信号线110、第二信号线130和第三信号线140的每根)的线宽；此种情况下，可以设计新的掩膜版并在制作过程中采用新的掩膜版。又例如，可以通过增加曝光机的曝光剂量来来减小光刻胶的关键尺寸(Develop Inspection Critical Dimension,DICD)，以减小第一信号线110、第二信号线130和第三信号线140的至少一个(例如，第一信号线110、第二信号线130和第三信号线140的每根)的线宽；此种情况下，可以采用相关技术中采用的掩膜版而无需设计和采用新的掩膜版。
例如，为避免第一信号线110、第二信号线130和第三信号线140的宽度(线宽)减少过多以及影响第一信号线110、第二信号线130和第三信号线140的充电率，还可以将减小第一信号线110、第二信号线130和第三信号线140的至少一个(例如，第一信号线110、第二信号线130和第三信号线140的每根)的线宽来消除或减小交叠三角形的设计思路与以下三个设计思路中的至少一个结合来消除或减小交叠三角形。(1)通过平移第一信号线110的第三走线部分114来增加第一边121位于第一位置P1和第二位置P2之间的线段的长度，通过平移第一信号线110的第一走线部分112来增加第三边123位于第五位置P5和第六位置P6之间的线段的长度。(2)通过增加第二走线部分113的宽度来增加第一边121位于第一位置P1和第二位置P2之间的线段的长度，通过增加第四走线部分115的宽度来增加第三边123位于第五位置P5和第六位置P6之间的线段的长度。(3)通过平移第二信号线130来减小第三位置P3与第一位置P1之间的间距(例如，使得第四位置P4也位于第一位置P1和第二位置P2之间)；通过平移第三信号线140来减小第七位置P7与第五位置P5之间的间距(例如，使得第八位置P8也位于第五位置P5 和第六位置P6之间)。例如，第一个和第二个设计思路可以参见先前的示例，在此不再赘述。以下具体说明第三个设计思路。
例如，由图7D和图8D所示的示例可知，在第二信号线130沿x方向向右偏移(远离第一位置P1偏移)以及沿y方向向下偏移(朝向第一边121指向第二边122的方向偏移)时，第二信号线130与第一信号线110之间的交叠三角形的面积增加；在第三信号线140沿x方向向右偏移(远离第五位置P5偏移)以及沿y方向向上偏移(朝向第三边123指向第四边124的方向偏移)时，第三信号线140与第一信号线110之间的交叠三角形的面积增加。对应地，在第二信号线130沿x方向向左偏移(朝向第一位置P1偏移)以及沿y方向向上偏移(朝向第二边122指向第一边121的方向偏移)时，第二信号线130与第一信号线110之间的交叠三角形的面积减小；在第三信号线140沿x方向向左偏移(朝向第五位置P5偏移)以及沿y方向向下偏移(朝向第四边124指向第三边123的方向偏移)时，第三信号线140与第一信号线110之间的交叠三角形的面积减小。
例如，可以在设计时，改变第二信号线130与第二走线部分113的预设的交叠位置以及第三信号线140与第四走线部分115的预设的交叠位置在阵列基板100的最终产品中实现第二信号线130和第三信号线140的上述偏移(相对于图6A和图6B所示的结构)；此种情况下，可以设计并在制作过程中采用新的掩膜版。
又例如，可以通过利用曝光机自带的偏移反馈功能在阵列基板100的最终产品中实现第二信号线130和第三信号线140的上述偏移(相对于图6A和图6B所示的结构)；此种情况下，可以采用相关技术中采用的掩膜版。具体方法如下。
在制作阵列基板100(薄膜晶体管基板)的过程中，为保证阵列基板100各膜层之间的不发生严重的错位，在制作每一层膜层(例如，使用掩膜版对薄膜进行图案化)时都要先进行对位。例如，将制作第二信号线130的掩膜版与制作第一信号线110的掩膜版进行对位(例如，间接对位)。例如，可以利用阵列基板100的衬底基板上的对位标记进行对位。
在图7D和图8D所示的示例中，第三信号线140和第二信号线130相对于第一信号线110的最大水平对位误差和最大垂直对位误差的绝对值均为1.5微米；此种情况下，在第二信号线130沿x方向向右偏移1.5微米以及沿y 方向向下偏移1.5微米时，第二信号线130与第一信号线110之间的交叠三角形的面积最大；在第三信号线140沿x方向向右偏移1.5微米以及沿y方向向上偏移1.5微米时，第三信号线140与第一信号线110之间的交叠三角形的面积最大。对应地，在第二信号线130沿x方向向左偏移1.5微米以及沿y方向向上偏移1.5微米时，第二信号线130与第一信号线110之间的交叠三角形的面积最小；在第三信号线140沿x方向向左偏移1.5微米以及沿y方向向下偏移1.5微米时，第三信号线140与第一信号线110之间的交叠三角形的面积最小。例如，可以通过严格控制对位误差来使得第二信号线130沿x方向向左偏移1.5微米以及沿y方向向上偏移1.5微米以及使得第三信号线140沿x方向向左偏移1.5微米以及沿y方向向下偏移1.5微米。例如，可以利用曝光机的操作页面的对位反馈(Overlay Feedback)来实现第二信号线130和第三信号线140的上述偏移。
例如，在本公开的至少一个实施例中，通过对第一信号线110(例如，栅线)的与第二信号线130的交叠的区域以及第一信号线110的与第三信号线140的交叠的区域进行设计(例如，相比于相关结构的重新设计)，可以消除第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形以及第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形，由此可以降低因静电释放导致的不良(例如，第一信号线110的第三走线部分114与第二信号线130之间短路不良以及第一信号线110的第一走线部分112与第三信号线140之间短路不良)的可能性。例如，上述对第一信号线110(例如，栅线)的与第二信号线130的交叠的区域以及第一信号线110的与第三信号线140的交叠的区域进行设计对包括该阵列基板100的控光面板的其它结构的参数(黑矩阵的宽度、走线之间的交叠电容)的影响较小(例如，影响均在可控以及可接受范围内)。例如，本公开的至少一个实施例提供的消除交叠三角形的设计思想简单，并且利用本公开的至少一个实施例提供的消除交叠三角形的设计思想获取的第一信号线的结构(栅线的弯折处的结构)容易实现。例如，本公开的至少一个实施例提供的阵列基板适用于中大尺寸(例如，大于60英寸；例如，65英寸和75英寸)的具有双液晶盒的显示装置中。
有以下几点需要说明。
1、尽管图5A-图5D所示的示例以及图9A-图9D所示的示例针对消除第 一信号线110的第三走线部分114与第二信号线130之间的交叠三角形以及消除第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形采用了相同的设计思路；例如，在图5A-图5D所示的示例中，采用平移第一信号线110的第三走线部分114和第一走线部分112来消除交叠三角形；在图9A-图9D所示的示例中，采用增加第一信号线110的第二走线部分113和第四走线部分115的宽度来消除交叠三角形；但本公开的实施例不限于此；可以不同的设计思路来消除第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形以及消除第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形；对应地，在阵列基板100的最终产品中，第一信号线110的结构，以及第一信号线110与第二信号线130和第三信号线140相对位置关系将对应改变。例如，可以通过平移第一信号线110的第三走线部分114来消除第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形，并采用增加第四走线部分115的宽度来消除第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形；对应地，第三位置P3位于第一中点M1和第一位置P1之间，第七位置P7位于第二中点M2和第八位置P8之间，且第三信号线140靠近第三走线部分114的边与第四边124的交点在第三边123上的正投影位于第二中点M2远离第七位置P7的一侧。又例如，可以通过减小第一信号线110和第二信号线130的至少一个(例如，第一信号线110和第二信号线130的每根)的线宽以及严格控制阵列基板100制造过程中第二信号线130相对于第一信号线110的对位偏差来消除第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形，并采用平移第一信号线110的第一走线部分112来消除第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形。
2、尽管图5A-图5D所示的示例以及图9A-图9D所示的示例均同时消除了第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形以及第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形，但本公开的实施例不限于此。在一个示例中，可以仅消除第一信号线110的第三走线部分114与第二信号线130之间的交叠三角形；在另一个示例，可以仅消除第一信号线110的第一走线部分112与第三信号线140之间的交叠三角形。例如，在仅消除第一信号线110的第一走线部分112与第三信号线140(例如，公共电极线)之间的交叠三角形的情况下，可以将第三走线部 分114、第四走线部分115、第一走线部分112、第二走线部分113和第三信号线140分别称为第一走线部分、第二走线部分、第三走线部分、第四走线部分和第二信号线，在此不再赘述。
3、例如，可以选用本公开的至少一个实施例提供的设计思路消除阵列基板100的每个折线结构111(第一折线结构)的交叠三角形；又例如，可以选用本公开的至少一个实施例提供的设计思路仅消除阵列基板100的部分折线结构111(第一折线结构)的交叠三角形。
4、尽管图5A-图5D所示的示例以及图9A-图9D所示的示例中的第一信号线110的折线结构111(第一折线结构)均包括第一走线部分112、第二走线部分113、第三走线部分114、第四走线部分115，但本公开的实施例不限于此。例如，第一信号线110的每个折线结构111(第一折线结构)仅包括顺次直接相连的第一走线部分112、第二走线部分113、第三走线部分114；此种情况下，第一信号线110的每个折线结构111的第三走线部分114和与上述每个折线结构111相邻的折线结构111的第一走线部分112直接相连。又例如，第一信号线110的每个折线结构111(第一折线结构)仅包括顺次直接相连的第一走线部分112、第三走线部分114和第四走线部分115。再例如，第一信号线110的部分折线结构111(第一折线结构)包括第一走线部分112、第二走线部分113、第三走线部分114、第四走线部分115，第一信号线110的其余的折线结构111(第一折线结构)仅包括顺次直接相连的第一走线部分112、第二走线部分113、第三走线部分114或者仅包括顺次直接相连的第一走线部分112、第三走线部分114和第四走线部分115。
5、尽管在图4A所示的阵列基板100中，多个第二信号线130(例如，数据线)和多个第三信号线140(例如，公共电极线)在第一方向D1上交替布置，但本公开的实施例不限于此。例如，每两根相邻的第三信号线140之间可以设置两根第二信号线130。
例如，下面结合图12A和图12B对第一信号线110、第二信号线130和第三信号线140的至少一根的坡度角的设置方式进行示例性的说明。
例如，第一信号线110、第二信号线130和第三信号线140的至少一根(例如，第一信号线110、第二信号线130和第三信号线140的每根)的坡度角位于40度-60度之间(例如，约为50度)。例如，通过使得第一信号线110、第二信号线130和第三信号线140的至少一根的坡度角位于40度-60度之间(例 如，约为50度)，可以提升形成在信号线之上的薄膜的台阶覆盖性(step coverage)以及进一步地降低静电释放导致的不良的可能性。具体分析如下。
图12A是在信号线的坡度角较小的情况下信号线的截面示意图。如图12A所示，在信号线的坡度角较小的情况下(例如，小于30度)，位于信号线的厚度较小的区域Re_ESD较宽。下面结合图3B中的交叠三角形进行示例性说明。如图3B所示，静电释放容易发生的位置是第一信号线110的第三走线部分114的边缘与第二信号线130的边缘交叠(在垂直于阵列基板100的方向)的位置处，也即，交叠三角形的尖端(也即，三角形中角度最小的顶点)；在信号线的坡度角较小的情况下，由于第一信号线110的第三走线部分114的边缘与第二信号线130的边缘的厚度较小的区域的宽度增加，且累积在第一信号线110的第三走线部分114的边缘与第二信号线130的边缘的静电荷不易沿走线部分导走，因此，第一信号线110的第三走线部分114的边缘与第二信号线130的边缘的容易累积静电荷的区域增加，容易累积静电荷的区域用于累积发生静电释放所需的静电荷所需的时间降低，由此，信号线的坡度角较小的情况下，第一信号线110的第三走线部分114的边缘与第二信号线130的边缘交叠位置处更容易发生静电释放的导致的不良。
图12B是在信号线的坡度角(设计的坡度角)较大(例如，坡度角大于70度)的情况下因刻蚀偏差导致的钻蚀(under cut)的示意图。
例如，通过使得第一信号线110、第二信号线130和第三信号线140的至少一根的坡度角位于40度-60度之间(例如，约为50度)，还可以降低信号线的加工时间以及降低工艺难度，由此可以提升阵列基板100的加工速度。
本公开的至少一个实施例还提供了一种控光面板10。图13是本公开的至少一个实施例提供的控光面板10的截面示意图。如图13所示，该控光面板10包括对置基板201、液晶层202以及本公开的至少一个实施例提供的任一阵列基板100；阵列基板100和对置基板201相对设置，液晶层202夹置于阵列基板100和对置基板201之间。例如，对置基板201包括黑矩阵单元但不包括彩色滤光片。例如，如图13所示，对置基板201、液晶层202和阵列基板100在第三方向D3上顺次设置。例如，第三方向D3、第一方向D1和第二方向D2彼此交叉(例如，彼此垂直)。
例如，控光面板10包括多个阵列布置的控光单元(图中未示出)。例如，阵列基板100的多个控光像素单元分别设置在对应的控光单元中。例如，控 光单元还包括与控光像素单元在第三方向D3上叠置的液晶层的部分以及对置基板的部分。
例如，控光面板10可以基于阵列基板100的数据线接收的数据信号来调节控光面板10的各个控光单元的透射率，因此，控光面板10的控光单元可用于控制入射至对应于该控光单元的显示面板的显示子像素单元上的光线的强度，由此，控光面板10可用于向显示面板(包括该控光面板的显示装置的显示面板)提供调节后的背光。
例如，该控光面板可以降低因静电释放导致的不良(例如，短路不良)的可能性。
图14是本公开的至少一个实施例提供的显示装置01的截面示意图。如图14所示，该显示装置01包括在第三方向D3上彼此叠置的显示面板30、背光单元20以及本公开的至少一个实施例提供的任一控光面板10。显示面板30位于控光面板10的出光侧，背光单元20位于控光面板10远离显示面板30的一侧。例如，如图14所示，显示面板30、控光面板10和背光单元20在第三方向D3上顺次设置。例如，相比于控光面板10的对置基板201，控光面板10的阵列基板100更靠近背光单元20。
图15A是图14所示的显示装置01的显示面板30的平面示意图。如图15A所示，显示面板30包括多根沿第一方向D1延伸的第一信号线305以及多根沿第二方向D2延伸的第二信号线306；多根第一信号线305和多根第二信号线306相交界定阵列排布的多个显示子像素单元，多个显示子像素单元形成阵列排布的多个显示像素单元304。例如，第一信号线305为显示面板20的栅线，第二信号线306为显示面板30的数据线。例如，第一信号线305和第二信号线306与不同的信号源相连。如图15A所示，每个显示像素单元304包括第一显示子像素单元3041、第二显示子像素单元3042和第三显示子像素单元3043；第一显示子像素单元3041、第二显示子像素单元3042和第三显示子像素单元3043例如分别为红色显示子像素单元、绿色显示子像素单元和蓝色显示子像素单元。
图15B是图14所示的显示装置01的平面示意图。例如，如图15B所示，每个控光像素单元130在第一方向D1上的尺寸等于每个显示像素单元304在第一方向D1上的尺寸的两倍，每个控光像素单元130在第二方向D2上的尺寸等于或略小于每个显示像素单元304在第二方向D1上的尺寸的四倍。
例如，显示装置01还包括设置于显示面板30与控光面板10之间的各向同性扩散膜(isotropic diffusion film，图中未示出)。各向同性扩散膜可以使由控光面板10出射的光在较小的角度范围内扩散，从而使数据线的图案变得模糊从而进一步消除摩尔纹，同时，不会对控光面板10出射的光的方向产生较大的影响。
例如，该显示装置01可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。需要说明的是，对于该显示装置01的其它组成部分(例如，控制装置、图像数据编码/解码装置、行扫描驱动器、列扫描驱动器、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (15)

  1. 一种阵列基板，包括：
    用于整体沿第一方向延伸的子像素行的第一信号线，以及
    用于整体沿与所述第一方向交叉的第二方向延伸的子像素列的第二信号线，
    其中，所述第一信号线包括顺次直接相连多个折线结构，所述多个折线结构的每个包括顺次直接相连的第一走线部分、第二走线部分和第三走线部分；
    所述第一走线部分的延伸方向和所述第三走线部分的延伸方向均与所述第一方向和所述第二方向相交，所述第二走线部分沿所述第一方向延伸；
    所述第一走线部分的沿所述第一走线部分延伸方向延伸的中线与所述第二走线部分的沿所述第二走线部分延伸方向延伸的中线相交形成第一夹角；
    所述第二走线部分包括在所述第二方向上彼此对置的第一边和第二边，所述第一边位于所述第一夹角的内侧和所述第二边位于所述第一夹角的外侧；
    所述第一走线部分的靠近所述第二信号线的边在所述第一边的第一位置与所述第一边相交，所述第三走线部分的靠近所述第二信号线的边在所述第一边的第二位置与所述第一边相交；
    所述第二信号线在所述第一信号线所在电极层上的正投影的靠近所述第一走线部分的边在所述第一边的第三位置与所述第一边相交，所述第二信号线在所述第一信号线所在电极层上的正投影的靠近所述第三走线部分的边在所述第一边的第四位置与所述第一边相交；以及
    所述第一边的位于所述第一位置和所述第二位置之间的线段的长度大于所述第一边的位于所述第三位置和所述第四位置之间的线段长度。
  2. 根据权利要求1所述的阵列基板，其中，所述第三位置和所述第四位置均位于所述第一位置和所述第二位置之间。
  3. 根据权利要求1或2所述的阵列基板，其中，所述第二信号线包括第一线段；
    所述第一线段为所述第二信号线的位于所述第一走线和所述第二走线之间的部分；以及
    所述第一线段和所述第三走线部分相对于所述第二方向朝向相同的方向倾斜。
  4. 根据权利要求3所述的阵列基板，其中，所述第三位置位于第一中点和所述第一位置之间，所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点。
  5. 根据权利要求4所述的阵列基板，其中，所述第一信号线为栅线；
    所述第三走线部分相对于所述第二方向的倾角大于所述第一线段相对于所述第二方向的倾角的三倍且小于所述第一线段相对于所述第二方向的倾角的四倍；
    所述第二信号线为数据线且所述第一走线部分的宽度大于所述第二信号线宽度的两倍且小于所述第二信号线宽度的三倍，或者所述第二信号线为公共电极线且所述第一走线部分的宽度大于所述第二信号线宽度的三倍且小于所述第二信号线宽度的四倍；以及
    所述第一走线部分的宽度小于所述第二边的长度且大于所述第一边的位于所述第一位置和所述第二位置之间的线段的长度。
  6. 根据权利要求3所述的阵列基板，其中，所述第三位置与所述第一位置重合。
  7. 根据权利要求4-6任一所述的阵列基板，其中，所述第一走线部分的宽度和所述第三走线部分的宽度相等；所述第二走线部分的宽度大于所述第一走线部分的宽度且小于所述第一走线部分的宽度的二倍。
  8. 根据权利要求3所述的阵列基板，其中，所述第三位置位于第一中点和所述第二位置之间；
    所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点；以及
    所述第二信号线在所述第一信号线所在电极层上的正投影的靠近所述第一走线部分的边与所述第二边的交点在所述第一边上的正投影位于所述第一中点远离所述第三位置的一侧。
  9. 根据权利要求8所述的阵列基板，其中，所述第一信号线为栅线；
    所述第三走线部分相对于所述第二方向的倾角大于所述第一线段相对于所述第二方向的倾角的三倍且小于所述第一线段相对于所述第二方向的倾角的四倍；
    所述第二信号线为数据线且所述第一走线部分的宽度大于所述第二信号线宽度的两倍且小于所述第二信号线宽度的三倍，或者所述第二信号线为公共电极线且所述第一走线部分的宽度大于所述第二信号线宽度的三倍且小于所述第二信号线宽度的四倍；
    所述第一走线部分的宽度大于所述第二边的长度；以及
    所述第二走线部分的宽度大于所述第一走线部分的宽度的二倍且小于所述第一走线部分的宽度的三倍。
  10. 根据权利要求3所述的阵列基板，其中，所述第三位置位于第一中点，所述第一中点为所述第一边的位于所述第一位置和所述第二位置之间的线段的中点。
  11. 根据权利要求8-10任一所述的阵列基板，其中，所述第二走线部分的宽度大于所述第一走线部分的宽度和所述第三走线部分的宽度；以及
    所述第一走线部分的宽度和所述第三走线部分的宽度相等。
  12. 根据权利要求1-11任一所述的阵列基板，其中，所述第四位置与所述第二位置重合。
  13. 根据权利要求1-12任一所述的阵列基板，其中，所述第一信号线和所述第二信号线的至少一根的坡度角位于40度-60度之间。
  14. 一种控光面板，包括：
    对置基板，
    液晶层，以及
    如权利要求1-13任一所述的阵列基板，
    其中，所述阵列基板和所述对置基板相对设置，所述液晶层夹置于所述阵列基板和所述对置基板之间。
  15. 一种显示装置，包括：
    显示面板，
    背光单元，以及
    如权利要求14所述的控光面板，
    其中，所述显示面板、所述控光面板和所述背光单元层叠设置，所述显示面板位于所述控光面板的出光侧，所述背光单元位于所述控光面板远离所述显示面板的一侧。
PCT/CN2019/120635 2019-11-25 2019-11-25 阵列基板、控光面板和显示装置 WO2021102633A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101802699A (zh) * 2007-11-16 2010-08-11 夏普株式会社 液晶显示装置
CN104749839A (zh) * 2013-12-30 2015-07-01 三星显示有限公司 弯曲液晶显示器
CN206523727U (zh) * 2015-11-25 2017-09-26 株式会社日本显示器 显示装置
CN108983463A (zh) * 2018-08-29 2018-12-11 京东方科技集团股份有限公司 显示面板及显示装置
US20190206296A1 (en) * 2017-12-28 2019-07-04 Lg Display Co., Ltd. Display device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108254987B (zh) * 2018-02-02 2021-03-16 厦门天马微电子有限公司 阵列基板以及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101802699A (zh) * 2007-11-16 2010-08-11 夏普株式会社 液晶显示装置
CN104749839A (zh) * 2013-12-30 2015-07-01 三星显示有限公司 弯曲液晶显示器
CN206523727U (zh) * 2015-11-25 2017-09-26 株式会社日本显示器 显示装置
US20190206296A1 (en) * 2017-12-28 2019-07-04 Lg Display Co., Ltd. Display device
CN108983463A (zh) * 2018-08-29 2018-12-11 京东方科技集团股份有限公司 显示面板及显示装置

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