WO2021036874A1 - 阵列基板、控光面板和显示装置 - Google Patents

阵列基板、控光面板和显示装置 Download PDF

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Publication number
WO2021036874A1
WO2021036874A1 PCT/CN2020/109937 CN2020109937W WO2021036874A1 WO 2021036874 A1 WO2021036874 A1 WO 2021036874A1 CN 2020109937 W CN2020109937 W CN 2020109937W WO 2021036874 A1 WO2021036874 A1 WO 2021036874A1
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WIPO (PCT)
Prior art keywords
line
array substrate
grid
fold line
line segment
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PCT/CN2020/109937
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English (en)
French (fr)
Inventor
郭远辉
高玉杰
郭威
郭坤
廖燕平
Original Assignee
京东方科技集团股份有限公司
武汉京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 武汉京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/288,188 priority Critical patent/US11460743B2/en
Publication of WO2021036874A1 publication Critical patent/WO2021036874A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133606—Direct backlight including a specially adapted diffusing, scattering or light controlling members
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133611—Direct backlight including means for improving the brightness uniformity
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the embodiments of the present disclosure relate to an array substrate, a light control panel, and a display device.
  • the liquid crystal display device includes a backlight module and a liquid crystal panel.
  • the backlight module is arranged on the non-display side of the liquid crystal panel to provide a light source for the display operation of the display panel.
  • the liquid crystal panel includes a polarizer, an array substrate, an opposite substrate, and a layer of liquid crystal molecules filled between the two substrates.
  • the liquid crystal display device rotates the liquid crystal molecules in the liquid crystal molecule layer by forming an electric field between the array substrate and the opposite substrate, and the rotated liquid crystal molecules cooperate with the polarizer to form a liquid crystal light valve. Since the liquid crystal molecular layer itself does not emit light, a backlight module is needed to realize the display function. With the continuous development of display technology, users have put forward higher and higher requirements for the contrast and brightness uniformity of the display device.
  • At least one embodiment of the present disclosure provides an array substrate.
  • the array substrate includes a plurality of gate lines respectively extending in a first direction, a plurality of data lines respectively extending in a second direction intersecting the first direction, and a plurality of light-controlling pixel units.
  • Each of the grid lines includes a plurality of grid portions arranged side by side along the first direction and sequentially connected, and each grid portion includes a grid line and an open area surrounded by the grid line.
  • the grid lines of each of the grid portions include a first fold line and a second fold line; the starting point of the first fold line and the first fold line The start points of the two fold lines meet; the end points of the first fold lines meet the end points of the second fold lines; and the vertices of the first fold lines and the second fold lines The vertices are arranged at intervals in the second direction.
  • the first fold line includes a first line segment and a second line segment that are sequentially connected, and the connection point of the first line segment and the second line segment is The vertex of the first fold line;
  • the second fold line includes a third line segment and a fourth line segment that are sequentially connected, and the connection point of the third line segment and the fourth line segment is the second fold line line
  • the absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, the third line segment and the The absolute value of the acute angle included in the first direction and the absolute value of the acute included angle between the fourth line segment and the first direction are between 38 degrees and 55 degrees.
  • the absolute value of the acute angle between the first line segment and the first direction, and the absolute value of the acute angle between the second line segment and the first direction are between 42 degrees and 48 degrees.
  • the first fold line and the second fold line are relative to the start point of the first fold line and the end point of the first fold line.
  • the connection is symmetrical.
  • the first line segment and the second line segment are symmetrical with respect to the line connecting the apex of the first fold line and the apex of the second fold line.
  • the third line segment and the fourth line segment are symmetrical with respect to the line connecting the apex of the first fold line and the apex of the second fold line.
  • each of the data lines and a grid line of a corresponding grid portion have two overlapping positions in a direction perpendicular to the array substrate, or are adjacent to each other.
  • the connection of the two grid portions overlaps in a direction perpendicular to the array substrate.
  • the array substrate further includes a common electrode line extending along the second direction.
  • the connection between the common electrode line and two adjacent grid portions overlaps in a direction perpendicular to the array substrate, or the grid line of a corresponding grid portion overlaps in a direction perpendicular to the array substrate There are two overlapping positions on the.
  • the opening area surrounded by each of the grid portions and one or two of the light control pixel units partially overlap in a direction perpendicular to the array substrate.
  • the boundary wiring of each light-controlling pixel unit is formed by the first fold-line wiring of the grid portion of the corresponding data line and the corresponding gate line; and The second fold line of the grid portion of each gate line runs through the inside of the corresponding light control pixel unit.
  • the array substrate further includes a common electrode line extending in the second direction.
  • the connection between the common electrode line and two adjacent grid portions overlaps in a direction perpendicular to the array substrate; the boundary wiring of each light control pixel unit is composed of the corresponding common electrode line and The first fold line routing of the grid portion corresponding to the grid line is formed; and the second fold line routing of the grid portion of each grid line passes through the inside of the corresponding light control pixel unit.
  • each of the light-controlling pixel units further includes a switching element and a pixel electrode; the switching element includes a gate, a source, and a drain, and the gate of the switching element Is electrically connected to the corresponding second fold line, one of the source and drain of the switching element is electrically connected to the pixel electrode; and the number of the switching element is equal to the number of the second fold line .
  • the widths of the first fold line trace and the second fold line trace are both between 9 ⁇ m and 11 ⁇ m.
  • the grid lines of each of the grid portions include a first fold line and a second fold line; the starting point of the first fold line and the first fold line The start points of the two fold lines are connected, and the end points of the first fold lines are connected with the end points of the second fold lines; the vertices of the first fold lines and the vertices of the second fold lines are connected Are arranged at intervals in the second direction; the first broken line routing includes a first line segment and a second line segment that are sequentially connected, and the connection point of the first line segment and the second line segment is the first line segment The vertex of the fold line; the second fold line includes a third line segment and a fourth line segment that are sequentially connected, and the connection point of the third line segment and the fourth line segment is the apex of the second fold line; The absolute value of the acute angle between the first line segment and the first direction, the absolute value of the acute angle between the second line segment and the first direction, and the third line segment and the first direction, and the third line segment and the first direction and the
  • At least one embodiment of the present disclosure also provides a light control panel, which includes a counter substrate, a liquid crystal layer, and an array substrate.
  • the array substrate and the counter substrate are arranged opposite to each other, the liquid crystal layer is sandwiched between the array substrate and the counter substrate;
  • the array substrate includes a plurality of gate lines respectively extending in a first direction, A plurality of data lines extending in a second direction that intersects the first direction, and a plurality of light-controlling pixel units respectively; each of the gate lines includes parallelly arranged and sequentially connected along the first direction A plurality of grid parts; and each grid part includes a grid line and an open area surrounded by the grid line.
  • At least one embodiment of the present disclosure also provides a display device, which includes a display panel, a backlight unit, and a light control panel.
  • the display panel is located on the light exit side of the light control panel
  • the backlight unit is located on the side of the light control panel away from the display panel.
  • the light control panel includes an array substrate, a counter substrate, and a liquid crystal layer; the array substrate and the counter substrate are arranged opposite to each other; the liquid crystal layer is sandwiched between the array substrate and the counter substrate;
  • the array substrate includes a plurality of gate lines respectively extending in a first direction, a plurality of data lines respectively extending in a second direction intersecting the first direction, and a plurality of light control pixel units; each of the gate lines
  • the line includes a plurality of grid parts arranged side by side in the first direction and sequentially connected; and each grid part includes a grid line and an open area surrounded by the grid line.
  • the display panel includes a plurality of display pixel units arranged in an array; the size of each grid portion in the first direction is equal to that of each display pixel Twice the size of the cell in the first direction; and the size of each grid portion in the second direction is less than or equal to the size of each display pixel cell in the second direction Twice as much.
  • the size of each light control pixel unit in the first direction is equal to twice the size of each display pixel unit in the first direction
  • the size of each of the light control pixel units in the second direction is equal to 2.5-3 times the size of each of the display pixel units in the first direction.
  • At least one embodiment of the present disclosure also provides a manufacturing method of an array substrate, which includes: forming a plurality of gate lines respectively extending in a first direction; forming a plurality of gate lines respectively extending in a second direction intersecting the first direction Multiple data lines.
  • the plurality of gate lines and the plurality of data lines intersect to define a plurality of light-controlling pixel units, each of the gate lines includes a plurality of grid portions arranged in parallel along the first direction and sequentially connected, each Each grid portion includes grid lines and an open area surrounded by the grid lines.
  • FIG. 1A shows a schematic cross-sectional view of a liquid crystal display device
  • FIG. 1B shows a schematic plan view of the light control panel and the display panel of the liquid crystal display device shown in FIG. 1A;
  • FIG. 1C shows a schematic plan view of the light control pixel unit of the light control panel shown in FIG. 1A;
  • FIG. 2A shows a schematic diagram of the gate line shielding situation of the liquid crystal display device shown in FIG. 1A at a first viewing angle
  • FIG. 2B shows a schematic diagram of the gate line shielding of the liquid crystal display device shown in FIG. 1A at a second viewing angle
  • FIG. 3 is a schematic plan view of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4 shows a schematic plan view of the gate lines of the array substrate shown in FIG. 3;
  • FIG. 5 shows a schematic plan view of switching elements and pixel electrodes of the array substrate shown in FIG. 3;
  • FIG. 6A shows a schematic plan view of another array substrate provided by at least one embodiment of the present disclosure
  • 6B shows a schematic plan view of another gate line of the array substrate provided by at least one embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional view of a light control panel provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic cross-sectional view of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 9A is a schematic plan view of the display panel of the display device shown in FIG. 8;
  • FIG. 9B is a schematic plan view of the display device shown in FIG. 8;
  • FIG. 10 is a schematic plan view of the grid portion of the display device shown in FIG. 9B.
  • FIG. 11 is a schematic plan view of a pixel unit of the display device shown in FIG. 9B.
  • the inventors of the present disclosure have noticed in their research that ordinary liquid crystal display devices (for example, liquid crystal display devices based on advanced super-dimensional field conversion technology with a single liquid crystal cell) usually have a dark state light leakage problem, which makes the display of the liquid crystal display device The contrast of the picture is low.
  • the inventor of the present disclosure has noticed in research that a liquid crystal display device with dual liquid crystal cells can be used to improve the contrast of the displayed picture. The following is an exemplary description with reference to FIG. 1.
  • FIG. 1A shows a schematic cross-sectional view of a liquid crystal display device 500.
  • the liquid crystal display device 500 includes a backlight unit 503, a light control panel 502, and a display panel 501 that are sequentially arranged (e.g., in a direction perpendicular to the liquid crystal display device 500).
  • FIG. 1B shows a schematic plan view of the light control panel 502 and the display panel 501 of the liquid crystal display device 500 shown in FIG. 1A.
  • the light control panel 502 is configured to adjust the intensity of light emitted by the backlight unit 503 and incident on the display panel 501.
  • the display panel 501 includes a plurality of first signal lines 541 extending in a first direction D1 and a plurality of second signal lines 542 extending in a second direction D2; a plurality of first signal lines 541 and a plurality of The intersection of the second signal line 542 defines a plurality of display pixel units 530 (for example, display sub-pixel units of the plurality of display pixel units 530); each display pixel unit 530 includes a first display sub-pixel unit 531 and a second display sub-pixel unit 532 and the third display sub-pixel unit 533; the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 are, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit, respectively Display sub-pixel unit.
  • each display pixel unit 530 includes a first display sub-pixel unit 531 and a second display sub-pixel unit 532 and the third display sub-pixel unit 5
  • first direction D1 and the second direction D2 cross (for example, perpendicular).
  • first signal line 541 is a gate line of the display panel 501
  • second signal line 542 is a data line of the display panel 501.
  • the light control panel 502 includes a plurality of gate lines 510 respectively extending in a first direction D1 and a plurality of data lines 521 extending in a second direction D2 intersecting the first direction D1;
  • the intersection of the line 510 and the plurality of data lines 521 defines a plurality of light-controlling pixel units 523.
  • the width of the first signal line 541 is greater than the width of the gate line 510.
  • the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 have the same size in the first direction D1.
  • the sizes of the pixel unit 532 and the third display sub-pixel unit 533 in the second direction D2 are the same as each other.
  • each gate line 510 is implemented as a broken line; each gate line 510 includes a plurality of first line segments 511 and a plurality of second line segments 512, and each gate line 510 includes a plurality of first lines
  • the segments 511 and the plurality of second line segments 512 are alternately arranged (for example, alternately arranged in the first direction D1), and adjacent first line segments 511 and second line segments 512 are connected to each other (for example, directly connected).
  • the angle (acute angle) between the first line segment 511 (or/and the second line segment 512) and the first direction D1 is about 50-70 degrees, so as to reduce the moiré problem of the liquid crystal display device 500.
  • the first line segment 511 and the second line segment 512 are both straight line segments.
  • FIG. 1C shows the light control pixel unit 523 of the light control panel 502 shown in FIG. 1A.
  • the size of the light control pixel unit 523 in the first direction D1 is L1
  • the size of the light control pixel unit 523 in the second direction D2 is L2.
  • the size L1 of the light control pixel unit 523 in the first direction D1 is equal to twice the size of the display pixel unit 530 in the first direction D1
  • the light control pixel unit 523 is in the second direction D2.
  • the size L2 above is equal to four times the size of the display pixel unit 530 in the second direction D2.
  • the inventor of the present disclosure has noticed in research that by implementing the gate line 510 as a broken line, the problem of uneven brightness of the liquid crystal display device 500 can be suppressed.
  • the problem of uneven brightness is poor black and white stripes or poor horizontal stripes ( For example, the problem of poor black and white lines under the side view angle).
  • the specific analysis is as follows. In the case where the grid line 510 is realized as a straight line, if an alignment error occurs when the light control panel 502 and the display panel 501 are attached, the orthographic projection of the grid line 510 (straight line) on the display panel 501 will be the same as that of the display panel 501.
  • the gate line 510 will block the light provided by the backlight unit 503, and make the brightness of the area corresponding to the gate line 510 of the liquid crystal display device 500 close to zero (that is, corresponding to black stripes), the liquid crystal display device
  • the area of 500 other than the gate line 510 corresponds to white stripes; in this case, the liquid crystal display device 500 has black stripes and white stripes alternately arranged in the second direction D2, that is, the liquid crystal display device 500 may have The problem of bad black and white patterns.
  • the gate line 510 is implemented as a broken line, the problem of black and white stripes or horizontal stripes of the liquid crystal display device 500 can be suppressed.
  • the inventors of the present disclosure have also noticed in their research that the liquid crystal display device 500 shown in FIGS. 1A and 1B may have at least one of the problem of color unevenness (rainbow pattern) and signal delay.
  • the liquid crystal display device 500 shown in FIGS. 1A and 1B may have a rainbow pattern problem; the rainbow pattern problem is a problem of uneven color mixing in different areas of the display device. Specifically, when the predetermined display screen of the display device is a white screen, the actual screen observed by the user has colored stripes.
  • the problem of the rainbow pattern is related to the difference in the shielding of the display sub-pixel units of different colors by the gate line 510 at different viewing angles (for example, the viewing angle of the user).
  • the rainbow pattern problem will be exemplified below in conjunction with FIG. 2A and FIG. 2B.
  • FIG. 2A shows a schematic diagram of the gate line 510 of the liquid crystal display device 500 shown in FIG.
  • FIG. 1A under a first viewing angle for example, a front viewing angle
  • FIG. 2B shows a second viewing angle different from the first viewing angle (
  • a side view angle) is a schematic diagram of the case where the gate line 510 of the liquid crystal display device 500 shown in FIG. 1A is shielded.
  • the sizes of the first display sub-pixel unit 531, the second display sub-pixel unit 532, and the third display sub-pixel unit 533 in the first direction D1 are the same; the first line segment 511 and the second The line segments 512 are all straight line segments. As shown in FIGS.
  • the line segment (for example, The length of the portion of the first line segment 511) corresponding to the first display sub-pixel unit 531 (for example, the length in the extending direction of the first line segment 511), the line segment (for example, the first line segment 511) corresponds to The length of the portion of the second display sub-pixel unit 532 and the length of the portion of the line segment (for example, the first line segment 511) corresponding to the third display sub-pixel unit 533 are the same as each other. As shown in FIG.
  • the overlapping area of the line segment (for example, the first line segment 511) and the first display sub-pixel unit 531, and the line segment (for example, the first line segment 511) and the third display sub-pixel unit 533 are all smaller than the line segment (for example, The overlapping area between the first line segment 511) and the second display sub-pixel unit 532; in this case, the display image at the first viewing angle is biased toward the color of the second display sub-pixel unit 532.
  • the part of the line segment (for example, the first line segment 511) corresponding to the second display sub-pixel unit 532 also overlaps the first signal line 541
  • the overlapping area of the line segment (for example, the first line segment 511) and the first display sub-pixel unit 531, and the line segment (for example, the first line segment 511) and the third display sub-pixel unit 533 are all smaller than the line segment (for example, The overlapping area between the first line segment 511) and the second display sub-pixel unit 532; in this case, the display image at the first viewing angle is
  • the display screen at the second viewing angle is biased toward the first display sub-pixel unit 532 (that is, biased toward the corresponding display sub-pixel unit where the line segment overlaps the first signal line 541). )s color. Since the user observes the liquid crystal display device 500 within a certain viewing angle range, the actual screen observed by the user has color stripes.
  • the part of the line segment corresponding to the display sub-pixel unit refers to two parts of the boundary between the line segment and the display sub-pixel unit (for example, a column of display sub-pixel units where the display sub-pixel unit is located) in the first direction. The part of the line segment between the intersections.
  • the liquid crystal display device 500 shown in FIGS. 1A and 1B may have a signal delay problem. This is because the angle (acute angle) between the first line segment 511 (or/and the second line segment 512) and the first direction D1 is relatively large. Therefore, the length of the first line segment 511 (or/and the second line segment 512) is longer, and therefore, the time required for the signal to be transmitted from one end of the gate line 510 to the other end of the gate line 510 is longer.
  • the embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, a light control panel, and a display device.
  • the array substrate includes a plurality of gate lines respectively extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and a plurality of light control pixel units.
  • Each grid line includes a plurality of grid portions arranged side by side along the first direction and sequentially connected, and each grid portion includes a grid line and an open area surrounded by the grid line.
  • the array substrate can improve the display effect of the display device including the array substrate.
  • the array substrate can suppress the problem of unevenness (for example, at least one of unevenness in brightness and unevenness in color) of a display screen of a display device including the array substrate.
  • FIG. 3 is a schematic plan view of an array substrate 100 provided by at least one embodiment of the present disclosure.
  • the array substrate 100 is used for a light control panel.
  • the array substrate 100 includes a plurality of gate lines 101 respectively extending in a first direction D1 and a plurality of data lines 102 respectively extending in a second direction D2 intersecting the first direction D1.
  • the first direction D1 is perpendicular to the second direction D2.
  • a plurality of gate lines 101 and a plurality of data lines 102 intersect to define a plurality of light-controlling pixel units 103, and each gate line 101 includes a plurality of grids arranged side by side along the first direction D1 and sequentially connected.
  • Each of the grid portions 110 includes a grid line 111 and an opening area 112 surrounded by the grid line 111.
  • the plurality of gate lines 101 are configured to provide scan signals (for example, light control scan signals)
  • the plurality of data lines 102 are configured to provide data signals (for example, light control data signals)
  • the above light control data signals are configured as
  • the transmittance of the light control pixel unit 103 is controlled.
  • the shapes and sizes of the plurality of mesh parts 110 included in each gate line 101 are substantially the same.
  • the data line 102 may be a straight line parallel to the second direction D2, but the embodiment of the present disclosure is not limited to this. According to actual application requirements, the data line 102 may also be implemented as a broken line, that is, , The data line 102 has a bent structure.
  • each gate line 101 by making each gate line 101 include a plurality of grid portions 110 arranged side by side along the first direction D1 and sequentially connected, the display effect of the display device 01 including the array substrate 100 can be improved.
  • each gate line 101 by making each gate line 101 include a plurality of grid portions 110 arranged side by side and sequentially connected in the first direction D1, the grid portion of the light control panel 10 (see FIG. 7) including the array substrate 100 can be reduced. (Compared to the grid size of the light control panel 10 shown in FIG. 1B). In this case, the grid size of the light control panel 10 including the array substrate 100 and the grid size of the array substrate 100 can be reduced.
  • the difference between the grid sizes of the display panel of the display device 01 can thereby suppress the moiré of the display device 01 including the array substrate 100, and improve the display of the display device 01 (see FIG. 8) including the array substrate 100 effect.
  • the grid of the light control panel 10 including the array substrate 100 shown in FIG. 3 refers to the grid formed by the adjacent grid portion 110 and the data line 102 and the grid corresponding to the grid portion 110.
  • FIG. 4 shows a schematic plan view of the gate lines 101 of the array substrate 100 shown in FIG. 3.
  • the grid lines 111 of each grid portion 110 include a first fold line 120 and a second fold line 130.
  • the start point of the first fold line 120 and the start point of the second fold line 130 meet; the end of the first fold line 120 and the end point of the second fold line 130 meet; the apex of the first fold line 120
  • the apexes of the second fold line 130 are spaced apart in the second direction D2.
  • first fold line 120 and the second fold line 130 are arranged side by side in the second direction D2, the end point of the first fold line 120 and the corresponding end point of the second fold line 130 are directly connected, and except for the first Outside the end points of the fold line 120 and the second fold line 130, the first fold line 120 and the second fold line 130 do not overlap in a direction perpendicular to the array substrate 100.
  • the start and end points of a polyline route refer to the two points that are the furthest apart in the first direction D1; for example, the polyline route is located on the first side of the two points that are the furthest apart in the first direction D1
  • the point on the left (for example, the left side) and the point on the second side (for example, the right side) are the starting point and the end point of the broken line, respectively.
  • the first fold line 120 includes a first line segment 121 and a second line segment 122 connected in sequence, the first line segment 121 and the second line segment 122 (in the same grid portion 110)
  • the connection point of the first line segment 121 and the second line segment 122) is the apex of the first fold line 120;
  • the second fold line 130 includes a third line segment 131 and a fourth line segment 134 that are sequentially connected, and the third line segment 131 and the second line segment 131 and 134 are connected in sequence.
  • the connection point of the four line segments 134 (the third line segment 131 and the fourth line segment 134 in the same grid portion 110) is the vertex of the second broken line route 130.
  • the vertex of the polyline route refers to the point of the polyline route that is farthest from the virtual line between the start point and the end point of the polyline route in the second direction D2.
  • the extension of the plurality of gate lines 101 along the first direction D1 only limits the extension direction of the gate line 101, and does not indicate the traces included in the gate line 101 (the first fold line 120 and the second fold line run).
  • Line 130) is parallel to the first direction D1.
  • the absolute value of the acute angle between the first line segment 121 and the first direction D1 the absolute value of the acute angle between the second line segment 122 and the first direction D1, and the third line segment 131
  • the absolute value of the acute angle with the first direction D1 and the absolute value of the acute angle with the fourth line segment 134 and the first direction D1 are between 38 degrees and 55 degrees (for example, 38 degrees and 50 degrees).
  • the absolute value of the acute angle between the first line segment 121 and the first direction D1 the absolute value of the acute angle between the second line segment 122 and the first direction D1
  • the acute angle between the third line segment 131 and the first direction D1 The absolute value of and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 are equal to each other.
  • the absolute value of the included angle and the absolute value of the included angle between the fourth line segment 134 and the acute angle of the first direction D1 can reduce the contrast between the gate lines 101 of the array substrate 100 and the display panel 20 of the display device 01 including the array substrate 100.
  • the difference in the occlusion of pixels can thereby suppress rainbow patterns (for example, suppress rainbow patterns in a pure-color picture, where the pure-color picture means that the colors of each sub-pixel of a display device including the array substrate are the same as each other).
  • the absolute value of the included angle and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 can also reduce the length of the first line segment 121, the second line segment 122, the third line segment 131, and the fourth line segment 134 by This can reduce the time required for the signal to pass from one end (for example, the left end) of the gate line 101 to the other end (for example, the right end) of the gate line 101, thereby reducing signal delay.
  • the absolute value of the acute angle between the first line segment 121 and the first direction D1 the absolute value of the acute angle between the second line segment 122 and the first direction D1, and the third line segment 131
  • the absolute value of the acute angle with the first direction D1 and the absolute value of the acute angle with the fourth line segment 134 and the first direction D1 are between 42 degrees and 48 degrees (for example, 43 degrees and 44 degrees).
  • the absolute value ⁇ 1 of the acute angle between the first line segment 121 and the first direction D1 the absolute value of the acute angle between the second line segment 122 and the first direction D1, and the third line segment 131 and the first direction D1
  • the absolute value of the acute angle and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 are between 42 degrees and 48 degrees (for example, 43 degrees and 44 degrees), which can be degraded (for example, not significantly degraded) In the case of black and white streaks, suppress rainbow streaks and reduce signal delay.
  • each grid line 101 include a plurality of grid portions 110 arranged side by side and sequentially connected in the first direction D1, the absolute value of the acute angle between the first line segment 121 and the first direction D1 can be reduced.
  • the absolute value of the acute angle between the second line segment 122 and the first direction D1, the absolute value of the acute angle between the third line segment 131 and the first direction D1, and the absolute value of the acute angle between the fourth line segment 134 and the first direction D1 In the case of the value, each row of display pixel units 204 in the display panel 20 of the display device 01 including the array substrate 100 is partially blocked by the gate line 101, thereby avoiding the deterioration of the black and white streak problem.
  • each grid line 101 includes a plurality of grid portions 110 arranged side by side and sequentially connected in the first direction D1, it is also possible to reduce the distance between the first line segment 121-the fourth line segment 134 and the first direction D1.
  • the number of light control pixel units 103 of the light control panel 10 is prevented from doubling. This is because when the grid line does not include the grid portion, the first line segment 121 to the fourth line segment 134
  • the decrease in the absolute value of the acute angle with the first direction D1 will result in an increase in the number of gate lines of the array substrate, thereby avoiding an increase in the load (for example, capacitive load) of the light control panel 10.
  • the first fold line 120 and the second fold line 130 are relative to the line connecting the start point of the first fold line 120 and the end point of the first fold line 120 (for example, virtual The connection) is symmetrical; in this case, the display effect of the display device 01 including the array substrate 100 can be improved.
  • the first line segment 121 and the second line segment 122 are connected to the apex of the first polyline 120 and the second polyline 130 (for example, a virtual connection) Symmetrical; the third line segment 131 and the fourth line segment 134 are symmetrical with respect to the connection (for example, virtual connection) between the apex of the first fold line 120 and the apex of the second fold line 130; in this case, it can be further
  • the display effect of the display device 01 including the array substrate 100 is improved.
  • the boundary traces of the light-controlling pixel unit 103 are formed by the corresponding data line 102 and the first folding line 120 of the grid portion 110 corresponding to the gate line 101; each gate line 101
  • the second folding line 130 of the grid portion 110 passes through the inside of the corresponding light control pixel unit 103.
  • two adjacent data lines 102 intersect the first fold line 120 of two adjacent gate lines, and the two adjacent data lines 102 are located at the two adjacent gate lines.
  • the part between the first fold line traces 120 of the line and the part of the first fold line traces 120 of the two adjacent gate lines that are located between the two adjacent data lines 102 form a light control pixel unit. Align the border of 103.
  • the array substrate includes a base substrate (not shown in the figure), and the orthographic projection of the second fold line 130 of the grid portion 110 of each gate line 101 on the base substrate is aligned with the above-mentioned second fold line 130.
  • the orthographic projection of the corresponding light-controlling pixel unit 103 on the base substrate completely covers.
  • the orthographic projection of the start point, the end point and the vertex of the second fold line 130 of the grid portion 110 of each grid line 101 on the base substrate is determined by the light control pixel unit 103 corresponding to the second fold line 130.
  • Orthographic coverage (for example, complete coverage) of the boundary trace on the base substrate.
  • each light-controlling pixel unit 103 further includes a switching element 141 and a pixel electrode 142;
  • FIG. 5 shows a schematic plan view of the switching element 141 and the pixel electrode 142 of the array substrate 100 shown in FIG. 3.
  • the switching element 141 includes a gate, a source, and a drain, and the gate of the switching element 141 is connected to the corresponding second fold line 130 (that is, passing through the light control pixel unit including the switching element 141).
  • the switching element 141 is electrically connected, one of the source and drain of the switching element 141 is electrically connected to the pixel electrode 142 (for example, electrically connected through a via), and the other of the source and drain of the switching element 141 is One is electrically connected to the data line 102.
  • the above-mentioned data line 102 electrically connected to the other of the source and drain of the switching element 141 refers to the two data lines used to form the boundary wiring of the light control pixel unit 103 including the switching element 141 and the The switching element 141 is closer to the data line.
  • the number of the switching elements 141 is equal to the number of the second broken line traces 130 (that is, the number of the mesh parts 110). For example, as shown in FIG.
  • the gate of the switching element 141 is electrically connected to the position of the second fold line 130 close to the vertex of the second fold line 130.
  • the gate line 101 and the data line 102 may be formed of a metal material (for example, copper, aluminum or aluminum alloy), and the pixel electrode 142 may be formed of a transparent conductive material, for example.
  • the transparent conductive material is indium tin oxide (ITO) or indium zinc oxide (IZO).
  • the pixel electrode 142 and the light control pixel unit 103 have substantially the same shape.
  • that the pixel electrode 142 and the light control pixel unit 103 have substantially the same shape means that the design shape of the pixel electrode 142 and the light control pixel unit 103 are the same.
  • the shape of the pixel electrode 142 and the light control pixel unit 103 are allowed. There is a certain (for example, less than 5% or 10%) deviation.
  • the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same size.
  • that the pixel electrode 142 and the light-controlling pixel unit 103 have substantially the same size refers to the difference between the size of the pixel electrode 142 and the size of the light-controlling pixel unit 103 and the difference between the size of the pixel electrode 142 and the size of the light-controlling pixel unit 103.
  • the ratio of the average value is less than 10% (for example, less than 5%).
  • each data line 102 corresponds to a grid portion 110 (that is, the grid portion 110 that overlaps the orthographic projection of each data line 102 on the grid line).
  • the grid lines have two overlapping positions in the direction perpendicular to the array substrate 100.
  • the above-mentioned overlapping positions correspond to the apex of the first fold line 120 and the apex of the second fold line 130, respectively.
  • the array substrate 100 further includes a common electrode line 104 extending along the second direction D2. The connection between the common electrode line 104 and two adjacent grid portions 110 is perpendicular to the array substrate. Overlap in the direction of 100. For example, as shown in FIGS.
  • each grid portion 110 and two light control pixel units 103 Partially overlap in the direction perpendicular to the array substrate 100.
  • a plurality of common electrode lines 104 and a plurality of data lines 102 are alternately arranged in the first direction D1. It should be noted that each data line 102 and a corresponding grid line of the grid portion 110 have two overlapping positions in the direction perpendicular to the array substrate 100, which means that each data line 102 has a corresponding grid portion 110.
  • the common electrode line 104 is configured to receive a common electrode signal.
  • the widths of the first fold line 120 and the second fold line 130 are both between 9 ⁇ m and 11 ⁇ m (for example, 10 ⁇ m).
  • the width of the gate line 101 shown in FIG. 1B is about 20 micrometers.
  • the opening of the display device 01 including the array substrate 100 can be made The rate does not decrease.
  • FIG. 6A shows a schematic plan view of another array substrate 100 provided by at least one embodiment of the present disclosure.
  • the array substrate 100 shown in FIG. 6A is similar to the array substrate 100 shown in FIG. 3; only the differences between the two are explained here. The similarities will not be repeated here.
  • the boundary traces of the light control pixel unit 103 of the array substrate 100 shown in FIG. 6A are formed by the corresponding common electrode line 104 and the first folding line 120 of the grid portion 110 corresponding to the gate line 101;
  • the second folding line 130 of the grid portion 110 passes through the inside of the corresponding light control pixel unit 103.
  • the opening area 112 surrounded by each grid portion 110 of the array substrate 100 shown in FIG. 6A and one light control pixel unit 103 at least partially overlap (for example, completely overlap) in a direction perpendicular to the array substrate 100.
  • two adjacent common electrode lines 104 intersect the first fold line 120 of two adjacent gate lines, and the two adjacent common electrode lines 104 are located at the two adjacent ones.
  • the portion between the first fold-line traces 120 of a gate line and the portion of the first fold-line traces 120 of the two adjacent gate lines that are located between the two adjacent common electrode lines 104 form a control.
  • the boundary of the optical pixel unit 103 is routed.
  • FIG. 6B shows a schematic plan view of another gate line 101 of the array substrate 100 provided by at least one embodiment of the present disclosure. As shown in FIG. 6B, the first line segment 121, the second line segment 122, the third line segment 131, and the fourth line segment 134 are all implemented as curved line segments.
  • connection between each data line 102 and two adjacent grid portions 110 overlaps in a direction perpendicular to the array substrate 100, and the common electrode line 104 is overlapped with a corresponding grid portion 110 (that is, The grid lines of the grid portion 110 that overlap with the orthographic projection of the common electrode line 104 on the grid line have two overlapping positions in the direction perpendicular to the array substrate 100.
  • the grid lines of the grid portion 110 that overlap with the orthographic projection of the common electrode line 104 on the grid line have two overlapping positions in the direction perpendicular to the array substrate 100.
  • the fact that the common electrode line 104 and the grid line of a corresponding grid part 110 have two overlapping positions in the direction perpendicular to the array substrate 100 means that the common electrode line 104 and one corresponding grid part 110 have two overlapping positions.
  • FIG. 7 is a schematic cross-sectional view of a light control panel 10 provided by at least one embodiment of the present disclosure.
  • the light control panel 10 includes a counter substrate 201, a liquid crystal layer 202, and any array substrate 100 provided by at least one embodiment of the present disclosure; the array substrate 100 and the counter substrate 201 are arranged opposite to each other, and the liquid crystal layer 202 It is sandwiched between the array substrate 100 and the counter substrate 201.
  • the counter substrate 201, the liquid crystal layer 202, and the array substrate 100 are sequentially arranged in the third direction D3.
  • the third direction D3, the first direction D1, and the second direction D2 cross each other (for example, perpendicular to each other).
  • the array substrate 100 and the counter substrate 201 at least partially overlap in a direction perpendicular to the light control panel 10 or in the third direction D3.
  • the light control panel 10 can adjust the transmittance of each light control pixel unit 103 of the light control panel 10 (not shown in FIG. 7, see FIG. 8) based on the data signal it receives, and the light control panel 10 can be used to display 20 provides adjusted backlight.
  • the light control pixel unit 103 of the light control panel is configured to control the intensity of light incident on the display sub-pixel unit (display sub-pixel unit included in the display panel 20) corresponding to the light control pixel unit 103.
  • the shape and size of the plurality of light control pixel units 103 included in the light control panel 10 are substantially the same.
  • At least one embodiment of the present disclosure also provides a display device 01.
  • the display device 01 can be implemented as a display device based on ADS (Advanced Super Dimensional Field Conversion Technology) or a display device based on IPS-ADS (that is, i-ADS, In-Plane Conversion-Advanced Super Dimensional Field Conversion Technology) technology.
  • FIG. 8 is a schematic cross-sectional view of a display device 01 provided by at least one embodiment of the present disclosure.
  • the display device 01 includes a display panel 20, a backlight unit 30, and any light control panel 10 provided by at least one embodiment of the present disclosure.
  • the display panel 20 is located on the light exit side of the light control panel 10, and the backlight unit 30 is located on the side of the light control panel 10 away from the display panel 20.
  • the display panel 20, the light control panel 10, and the backlight unit 30 are stacked in the third direction D3.
  • the display panel 20, the light control panel 10, and the backlight unit 30 are sequentially arranged in the third direction D3.
  • the array substrate 100 of the light control panel 10 is closer to the backlight unit 30.
  • the resolution of the display panel 20 is twice the resolution of the light control panel 10.
  • FIG. 9A is a schematic plan view of the display panel 20 of the display device 01 shown in FIG. 8.
  • the display panel 20 includes a plurality of first signal lines 205 extending in a first direction D1 and a plurality of second signal lines 206 extending in a second direction D2; a plurality of first signal lines 205 and a plurality of The intersection of the second signal line 206 defines a plurality of display pixel units 204 (for example, defines a plurality of display sub-pixel units).
  • the first signal line 205 is a gate line of the display panel 20
  • the second signal line 206 is a data line of the display panel 20.
  • the first signal line 205 is configured to provide a scan signal (for example, a display scan signal)
  • the second signal line 206 is configured to provide a data signal (for example, a display data signal)
  • the above-mentioned display data signal is configured to control the display sub
  • the transmittance of the pixel unit For example, the shapes and sizes of the plurality of display pixel units 204 are substantially the same.
  • each display pixel unit 204 includes a first display sub-pixel unit 2041, a second display sub-pixel unit 2042, and a third display sub-pixel unit 2043; the first display sub-pixel unit 2041, the second display sub-pixel unit
  • the unit 2042 and the third display sub-pixel unit 2043 are, for example, a red display sub-pixel unit, a green display sub-pixel unit, and a blue display sub-pixel unit, respectively.
  • FIG. 9B is a schematic plan view of the display device 01 shown in FIG. 8.
  • the size of each display pixel unit 204 in the first direction D1 is equal to the size of each display pixel unit 204 in the second direction D2.
  • the size of each display sub-pixel unit in the first direction D1 is equal to one third of the size of each display pixel unit 204 in the first direction D1.
  • the width of the first signal line 205 (the width of the first signal line 205 in the second direction or in the extending direction perpendicular to the first signal line 205) is greater than the width of the first folding line 120 (and the second The width of the fold line 130).
  • the width of the first signal line 205 (the width of the first signal line 205 in the second direction) is equal to twice the width of the first fold line 120 (and the width of the second fold line 130).
  • the width of the fold line refers to the width of the fold line in the direction perpendicular to the extension direction of the fold line.
  • FIG. 10 is a schematic plan view of the grid portion 110 of the display device 01 shown in FIG. 9B.
  • the size of the mesh portion 110 in the first direction D1 is W1
  • the size of the mesh portion 110 in the second direction D2 is W2.
  • the size W1 of the grid portion 110 in the first direction D1 is equal to twice the size of the display pixel unit 204 in the first direction D1;
  • the size W2 of the grid portion 110 in the second direction D2 is smaller than (Slightly smaller than) twice the size of the display pixel unit 204 in the second direction D2, and larger than the size of the display pixel unit 204 in the second direction D2.
  • the size W2 of the grid portion 110 in the second direction D2 may also be equal to twice the size of the display pixel unit 204 in the second direction D2. In this case, the vertex of the first fold line 120 The vertex of the second fold line 130 crosses the second direction D2.
  • the size of the mesh portion 110 in the first direction D1 refers to the two points furthest apart (for example, the vertex of the first fold line 120 and the second fold line) of the mesh portion 110 in the first direction D1.
  • the distance between the vertices of the line 130) in the first direction D1; the size of the grid portion 110 in the second direction D2 refers to the two furthest points of the grid portion 110 in the second direction D2 (for example, the first The distance between the start point and the end point of a broken line 120 in the second direction D2.
  • FIG. 11 is a schematic plan view of a pixel unit of the display device 01 shown in FIG. 9B.
  • the size of the light control pixel unit 103 in the first direction D1 is P1
  • the size of the light control pixel unit 103 in the second direction D2 is P2.
  • the size P1 of the light control pixel unit 103 in the first direction D1 is equal to twice the size of the display pixel unit 204 in the first direction D1; the light control pixel unit 103 is in the second direction D2
  • the size above is equal to 2.5 to 3 times the size of the display pixel unit 204 in the first direction D1.
  • the size of the pixel unit in the second direction D2 is equal to the distance in the second direction D2 of two parallel lines parallel to the first direction D1 connected to the vertices on both sides of the pixel unit in the second direction D2;
  • the size of the pixel unit in the second direction D2 is equal to the vertex connected to the upper side of the pixel unit in the second direction D2 and parallel to the parallel line of the first direction D1 and the vertex of the lower side of the pixel unit in the second direction D2.
  • the display device 01 further includes an isotropic diffusion film (not shown in the figure) disposed between the display panel 20 and the light control panel 10.
  • the isotropic diffusion film can diffuse the light emitted from the light control panel 10 in a smaller angle range, thereby blurring the pattern of the data line 102 to further eliminate moiré, and at the same time, it will not emit to the light control panel 10 The direction of the light has a greater impact.
  • the display device 01 may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • other components of the display device for example, the control device, the image data encoding/decoding device, the row scan driver, the column scan driver, the clock circuit, etc.
  • the display device can improve the display effect.
  • At least one embodiment of the present disclosure also provides a manufacturing method of an array substrate.
  • the manufacturing method of the array substrate includes forming a plurality of gate lines respectively extending in a first direction, a plurality of data lines extending in a second direction intersecting the first direction, and a plurality of light-controlling pixel units.
  • each grid line includes a plurality of grid portions arranged side by side in the first direction and sequentially connected, and each grid portion includes a grid line and an open area surrounded by the grid line.
  • the specific structure of the array substrate can be referred to the array substrate provided by at least one embodiment of the present disclosure, which will not be repeated here.
  • a display device including an array substrate manufactured by using the manufacturing method can improve the display effect.

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Abstract

一种阵列基板(100)、控光面板(10)和显示装置(01)。该阵列基板(100)包括分别沿第一方向(D1)延伸的多根栅线(101)，分别沿与所述第一方向(D1)相交的第二方向的延伸的多根数据线(102)以及多个控光像素单元(103)。每根所述栅线(101)包括沿所述第一方向(D1)并列布置且顺次相接的多个网格部(110)，每个网格部(110)包括网格线(111)以及由所述网格线(111)围成的开口区域。该阵列基板(100)可以提升包括该阵列基板(100)的显示装置的显示效果。

Description

阵列基板、控光面板和显示装置
对相关申请的交叉参考
本申请要求于2019年8月23日递交的中国专利申请第201910782667.4号的优先权，出于所有目的，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、控光面板和显示装置。
背景技术
液晶显示装置包括背光模组和液晶面板，背光模组设置在液晶面板的非显示侧以为显示面板的显示操作提供光源。液晶面板包括偏光片、阵列基板、对置基板以及填充在由这两个基板之间的液晶分子层。液晶显示装置通过在阵列基板和对置基板之间的形成电场使液晶分子层中液晶分子旋转，旋转后的液晶分子配合偏光片可形成液晶光阀。由于液晶分子层本身并不发光，因此需要借助背光模组来实现显示功能。随着显示技术的不断发展，用户对显示装置的对比度、亮度均匀性等提出了越来越高的要求。
发明内容
本公开的至少一个实施例提供了一种阵列基板。该阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元。每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部，每个网格部包括网格线以及由所述网格线围成的开口区域。
例如，在所述阵列基板的至少一个示例中，每个所述网格部的网格线包括第一折线走线和第二折线走线；所述第一折线走线的起点和所述第二折线走线的起点相接；所述第一折线走线的终点和所述第二折线走线的终点相接；以及所述第一折线走线的顶点和所述第二折线走线的顶点在所述第二方向上 间隔设置。
例如，在所述阵列基板的至少一个示例中，所述第一折线走线包括依次连接的第一线段和第二线段，所述第一线段和所述第二线段的连接点为所述第一折线走线的顶点；所述第二折线走线包括依次连接的第三线段和第四线段，所述第三线段和所述第四线段的连接点为所述第二折线走线的顶点；以及所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于38度-55度之间。
例如，在所述阵列基板的至少一个示例中，所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于42度-48度之间。
例如，在所述阵列基板的至少一个示例中，所述第一折线走线和所述第二折线走线相对于所述第一折线走线的起点和所述第一折线走线的终点的连线对称。
例如，在所述阵列基板的至少一个示例中，所述第一线段和所述第二线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称；以及所述第三线段和所述第四线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称。
例如，在所述阵列基板的至少一个示例中，每根所述数据线与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置，或者与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠。
例如，在所述阵列基板的至少一个示例中，所述的阵列基板还包括沿所述第二方向延伸的公共电极线。所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠，或者与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置。
例如，在所述阵列基板的至少一个示例中，每个所述网格部包围的开口区域和一个或两个所述控光像素单元在垂直于所述阵列基板的方向上部分重叠。
例如，在所述阵列基板的至少一个示例中，每个所述控光像素单元的边界走线由对应的所述数据线和对应的栅线的网格部的第一折线走线形成；以及每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部。
例如，在所述阵列基板的至少一个示例中，所述阵列基板还包括沿所述第二方向延伸的公共电极线。所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠；每个所述控光像素单元的边界走线由对应的所述公共电极线和对应所述栅线的网格部的第一折线走线形成；以及每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部。
例如，在所述阵列基板的至少一个示例中，每个所述控光像素单元还包括开关元件和像素电极；所述开关元件包括栅极、源极和漏极，所述开关元件的栅极与对应的所述第二折线走线电连接，所述开关元件的源极和漏极之一与所述像素电极电连接；以及所述开关元件的数目等于所述第二折线走线的数目。
例如，在所述阵列基板的至少一个示例中，所述第一折线走线和所述第二折线走线的宽度均位于9微米-11微米之间。
例如，在所述阵列基板的至少一个示例中，每个所述网格部的网格线包括第一折线走线和第二折线走线；所述第一折线走线的起点和所述第二折线走线的起点相接，所述第一折线走线的终点和所述第二折线走线的终点相接；所述第一折线走线的顶点和所述第二折线走线的顶点在所述第二方向上间隔设置；所述第一折线走线包括依次连接的第一线段和第二线段，所述第一线段和所述第二线段的连接点为所述第一折线走线的顶点；所述第二折线走线包括依次连接的第三线段和第四线段，所述第三线段和所述第四线段的连接点为所述第二折线走线的顶点；所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于42度-48度之间；所述第一折线走线和所述第二折线走线相对于所述第一折线走线的起点和所述第一折线走线的终点的连线对称；所述第一线段和所述第二线段相对于所述第一折线走线的顶点和所述第二折 线走线的顶点的连线对称；所述第三线段和所述第四线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称；每根所述数据线与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置；所述阵列基板还包括沿所述第二方向延伸的公共电极线，所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠；每个所述网格部包围的开口区域和两个所述控光像素单元在垂直于所述阵列基板的方向上部分重叠；所述控光像素单元的边界走线由对应的所述数据线和对应的栅线的网格部的第一折线走线形成，每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部；每个所述控光像素单元还包括开关元件和像素电极；所述开关元件包括栅极、源极和漏极，所述开关元件的栅极与对应的所述第二折线走线电连接，所述开关元件的源极和漏极之一与所述像素电极电连接，所述开关元件的数目等于所述第二折线走线的数目。
本公开的至少一个实施例还提供了一种控光面板，该控光面板包括对置基板、液晶层以及阵列基板。所述阵列基板和所述对置基板相对设置，所述液晶层夹置于所述阵列基板和所述对置基板之间；所述阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元；每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部；以及每个网格部包括网格线以及由所述网格线围成的开口区域。
本公开的至少一个实施例还提供了一种显示装置，其包括：显示面板、背光单元以及控光面板。所述显示面板位于所述控光面板的出光侧，所述背光单元位于所述控光面板远离所述显示面板的一侧。所述控光面板包括阵列基板、对置基板和液晶层；所述阵列基板和所述对置基板相对设置；所述液晶层夹置于所述阵列基板和所述对置基板之间；所述阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元；每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部；以及每个网格部包括网格线以及由所述网格线围成的开口区域。
例如，在所述显示装置的至少一个示例中，所述显示面板包括阵列排列的多个显示像素单元；每个所述网格部在所述第一方向上的尺寸等于每个所 述显示像素单元在所述第一方向上的尺寸的二倍；以及每个所述网格部在所述第二方向上的尺寸小于或等于每个所述显示像素单元在所述第二方向上的尺寸的二倍。
例如，在所述显示装置的至少一个示例中，每个所述控光像素单元在所述第一方向上的尺寸等于每个所述显示像素单元在所述第一方向上的尺寸的二倍；以及每个所述控光像素单元在所述第二方向上的尺寸等于每个所述显示像素单元在所述第一方向上的尺寸的2.5-3倍。
本公开的至少一个实施例还提供了一种阵列基板的制作方法，其包括：形成分别沿第一方向延伸的多根栅线；形成分别沿与所述第一方向相交的第二方向的延伸的多根数据线。所述多根栅线和所述多根数据线相交界定多个控光像素单元，每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部，每个网格部包括网格线以及由所述网格线围成的开口区域。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A示出了一种液晶显示装置的截面示意图；
图1B示出了图1A所示的液晶显示装置的控光面板和显示面板的平面示意图；
图1C示出了图1A所示的控光面板的控光像素单元的平面示意图；
图2A示出了在第一视角下图1A所示的液晶显示装置的栅线遮挡情况的示意图；
图2B示出了在第二视角下图1A所示的液晶显示装置的栅线遮挡情况的示意图；
图3是本公开的至少一个实施例提供的阵列基板的平面示意图；
图4示出了图3所示的阵列基板的栅线的平面示意图；
图5示出了图3所示的阵列基板的开关元件和像素电极的平面示意图；
图6A示出了本公开的至少一个实施例提供的另一种阵列基板的平面示意图；
图6B示出了本公开的至少一个实施例提供的阵列基板的另一种栅线的平面示意图；
图7是本公开的至少一个实施例提供的控光面板的截面示意图；
图8是本公开的至少一个实施例提供的显示装置的截面示意图；
图9A是图8所示的显示装置的显示面板的平面示意图；
图9B是图8所示的显示装置的平面示意图；
图10是图9B所示的显示装置的网格部的平面示意图；以及
图11是图9B所示的显示装置的像素单元的平面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人在研究中注意到，普通的液晶显示装置(例如，具有单个液晶盒的基于高级超维场转换技术的液晶显示装置)通常存在暗态漏光问题，这使得液晶显示装置的显示画面的对比度较低。本公开的发明人在研究中注意到，可以采用具有双液晶盒的液晶显示装置来提升显示画面的对比度，下面结合图1进行示例性说明。
图1A示出了一种液晶显示装置500的截面示意图。如图1A所示，该液 晶显示装置500包括顺次设置(例如，在垂直于液晶显示装置500的方向上顺次设置)的背光单元503、控光面板502和显示面板501。图1B示出了图1A所示的液晶显示装置500的控光面板502和显示面板501的平面示意图。例如，控光面板502被配置为调节背光单元503发射的且入射至显示面板501上的光线的强度。
如图1B所示，显示面板501包括多根沿第一方向D1延伸的第一信号线541以及多根沿第二方向D2延伸的第二信号线542；多根第一信号线541和多根第二信号线542相交界定多个显示像素单元530(例如，多个显示像素单元530的显示子像素单元)；每个显示像素单元530包括第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533；第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533例如分别为红色显示子像素单元、绿色显示子像素单元和蓝色显示子像素单元。例如，第一方向D1与第二方向D2交叉(例如，垂直)。例如，第一信号线541为显示面板501的栅线，第二信号线542为显示面板501的数据线。
如图1B所示，控光面板502包括分别沿第一方向D1延伸的多根栅线510以及分别沿与第一方向D1相交的第二方向D2的延伸的多根数据线521；多根栅线510和多根数据线521相交界定多个控光像素单元523。例如，如图2A所示，第一信号线541的宽度大于栅线510的宽度。例如，第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533在第一方向D1上的尺寸彼此相同，例如，第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533在第二方向D2上的尺寸彼此相同。
如图1B所示，每根栅线510实现为折线走线；每根栅线510包括多个第一线段511和多个第二线段512，每根栅线510包括的多个第一线段511和多个第二线段512交替布置(例如，在第一方向D1交替布置)，且相邻的第一线段511和第二线段512彼此相连(例如，直接相连)。如图1B所示，第一线段511(或/和第二线段512)与第一方向D1的夹角(锐角)约为50-70度，以降低液晶显示装置500的摩尔纹问题。例如，第一线段511和第二线段512均为直线线段。
图1C示出了图1A所示的控光面板502的控光像素单元523。如图1C所示，控光像素单元523在第一方向D1上的尺寸为L1，控光像素单元523 在第二方向D2上的尺寸为L2。如图1B和图1C所示，控光像素单元523在第一方向D1上的尺寸L1等于显示像素单元530在第一方向D1上的尺寸的两倍，控光像素单元523在第二方向D2上的尺寸L2等于显示像素单元530在第二方向D2上的尺寸的四倍。
本公开的发明人在研究中注意到，通过使得栅线510实现为折线走线，可以抑制液晶显示装置500的亮度不均匀问题，例如，该亮度不均匀问题为黑白纹不良或横纹不良(例如，侧视角度下的黑白纹不良)问题。具体分析如下。在栅线510实现为直线的情况下，如果在贴合控光面板502和显示面板501时出现对位误差，则栅线510(直线)在显示面板501上的正投影将与显示面板501的一行显示像素重叠，该栅线510将遮挡背光单元503提供的光线，并使得液晶显示装置500的对应于栅线510的区域的亮度接近于零(也即，对应于黑纹)，液晶显示装置500的对应于栅线510以外的区域对应于白纹；此种情况下，液晶显示装置500在第二方向D2上存在交替排布的黑纹和白纹，也即，液晶显示装置500可能存在的黑白纹不良问题。在栅线510实现为折线走线的情况下，则可抑制液晶显示装置500的黑白纹不良或横纹不良问题。
本公开的发明人在研究中还注意到，图1A和图1B所示的液晶显示装置500可能存在颜色不均匀问题(彩虹纹)问题和信号延迟问题中的至少一个。
例如，图1A和图1B所示的液晶显示装置500可能存在彩虹纹问题；彩虹纹问题是显示装置的不同区域的混色不均匀问题。具体而言，在显示装置的预定显示画面为白色画面的情况下，用户观察到的实际的画面的具有彩色条纹。彩虹纹问题与栅线510在不同视角(例如，用户的观察视角)下对不同颜色的显示子像素单元的遮挡存在差异相关。下面结合图2A和图2B对彩虹纹问题进行示例性说明。图2A示出了在第一视角(例如，正视视角)下图1A所示的液晶显示装置500的栅线510遮挡情况的示意图，图2B示出了在与第一视角不同的第二视角(例如，侧视视角)下图1A所示的液晶显示装置500的栅线510遮挡情况的示意图。为方便解释，此处假设：第一显示子像素单元531、第二显示子像素单元532和第三显示子像素单元533在第一方向D1上的尺寸彼此相同；第一线段511和第二线段512均为直线线段。如图2A和图2B所示，由于第一显示子像素单元531、第二显示子像素单元 532和第三显示子像素单元533在第一方向D1上的尺寸彼此相同，因此，线段(例如，第一线段511)的对应于第一显示子像素单元531的部分的长度(例如，在第一线段511的延伸方向上的长度)，线段(例如，第一线段511)的对应于第二显示子像素单元532的部分的长度，以及线段(例如，第一线段511)的对应于第三显示子像素单元533的部分的长度彼此相同。如图2A所示，在第一视角下，由于线段(例如，第一线段511)的对应于第二显示子像素单元532的部分还与第一信号线541交叠，因此，在第一视角下，线段(例如，第一线段511)与第一显示子像素单元531的交叠面积以及线段(例如，第一线段511)与第三显示子像素单元533均小于线段(例如，第一线段511)与第二显示子像素单元532的交叠面积；此种情况下，第一视角下的显示画面偏向于第二显示子像素单元532的颜色。基于类似的原因，如图2B所示，第二视角下的显示画面偏向于第一显示子像素单元532(也即，偏向于线段与第一信号线541交叠区域处对应的显示子像素单元)的颜色。由于用户在一定视角范围内观察液晶显示装置500，因此，用户观察到的实际的画面的具有彩色条纹。需要说明的是，线段的对应于显示子像素单元的部分是指线段的与该显示子像素单元(例如，该显示子像素单元所在的一列显示子像素单元)在第一方向的边界的两个交点之间的线段部分。
又例如，图1A和图1B所示的液晶显示装置500可能存在信号延迟问题，这是由于第一线段511(或/和第二线段512)与第一方向D1的夹角(锐角)较大，由此第一线段511(或/和第二线段512)的长度较长，因此，信号从栅线510的一端传输到栅线510的另一端所需的时间较长。
本公开的实施例提供了一种阵列基板及其制作方法、控光面板和显示装置。该阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与第一方向相交的第二方向的延伸的多根数据线以及多个控光像素单元。每根栅线包括沿第一方向并列布置且顺次相接的多个网格部，每个网格部包括网格线以及由网格线围成的开口区域。该阵列基板可以提升包括该阵列基板的显示装置的显示效果。例如，该阵列基板可以抑制包括该阵列基板的显示装置的显示画面的不均匀问题(例如，亮度不均匀和颜色不均匀的至少一种)。
下面通过几个示例和实施例对根据本公开实施例提供的阵列基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例和实 施例中不同特征可以相互组合，从而得到新的示例和实施例，这些新的示例和实施例也都属于本公开保护的范围。
图3是本公开的至少一个实施例提供的阵列基板100的平面示意图。该阵列基板100用于控光面板。如图3所示，该阵列基板100包括分别沿第一方向D1延伸的多根栅线101以及分别沿与第一方向D1相交的第二方向D2的延伸的多根数据线102。例如，第一方向D1垂直于第二方向D2。
如图3所示，多根栅线101和多根数据线102相交界定多个控光像素单元103，每根栅线101包括沿第一方向D1并列布置且顺次相接的多个网格部110，每个网格部110包括网格线111以及由网格线111围成的开口区域112。例如，多根栅线101被配置为提供扫描信号(例如，控光扫描信号)，多根数据线102被配置为提供数据信号(例如，控光数据信号)，上述控光数据信号被配置为控制控光像素单元103的透过率。例如，每根栅线101包括的多个网格部110的形状和尺寸实质上相同。
例如，如图3所示，数据线102可以是平行于第二方向D2的直线，但本公开的实施例不限于此，根据实际应用需求，数据线102也可以实现为折线走线，也即，数据线102具有弯折结构。
例如，通过使得每根栅线101包括沿第一方向D1并列布置且顺次相接的多个网格部110，可以提升包括该阵列基板100的显示装置01的显示效果。例如，通过使得每根栅线101包括沿第一方向D1并列布置且顺次相接的多个网格部110，可以降低包括该阵列基板100的控光面板10(参见图7)的网格的尺寸(相比于图1B所示的控光面板10的网格的尺寸)，此种情况下，可以降低包括阵列基板100的控光面板10的网格的尺寸以及包括该阵列基板100的显示装置01的显示面板的网格的尺寸之间的差异，由此可以抑制包括该阵列基板100的显示装置01的摩尔纹，提升包括该阵列基板100的显示装置01(参见图8)的显示效果。例如，包括图3所示的阵列基板100的控光面板10的网格是指相邻的网格部110与数据线102形成的网格以及网格部110对应的网格。
图4示出了图3所示的阵列基板100的栅线101的平面示意图。如图3和图4所示，每个网格部110的网格线111包括第一折线走线120和第二折线走线130。例如，第一折线走线120的起点和第二折线走线130的起点相 接；第一折线走线120的终点和第二折线走线130的终点相接；第一折线走线120的顶点和第二折线走线130的顶点在第二方向D2上间隔设置。例如，第一折线走线120和第二折线走线130在第二方向D2上并列布置，第一折线走线120的端点和第二折线走线130的对应端点直接相接，且除第一折线走线120和第二折线走线130的端点外，第一折线走线120和第二折线走线130在垂直与阵列基板100的方向上不重叠。
例如，折线走线的起点和终点是指该折线走线在第一方向D1相距最远的两个点；例如，折线走线在第一方向D1相距最远的两个点中位于第一侧(例如，左侧)的点和第二侧(例如，右侧)的点分别为折线走线的起点和终点。
如图3和图4所示，第一折线走线120包括依次连接的第一线段121和第二线段122，第一线段121和第二线段122(在同一个网格部110中的第一线段121和第二线段122)的连接点为第一折线走线120的顶点；第二折线走线130包括依次连接的第三线段131和第四线段134，第三线段131和第四线段134(在同一个网格部110中的第三线段131和第四线段134)的连接点为第二折线走线130的顶点。
例如，折线走线的顶点是指折线走线在第二方向D2上距离折线走线的起点和终点之间的虚拟连线最远的点。
需要说明的是，多根栅线101分别沿第一方向D1延伸仅限定了栅线101的延伸方向，而并不表示栅线101包括的走线(第一折线走线120和第二折线走线130)平行于第一方向D1。
例如，如图3和图4所示，第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值位于38度-55度(例如，38度-50度)之间。
例如，第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值彼此相等。
例如，通过降低第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向 D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值，可以降低阵列基板100的栅线101对包括该阵列基板100的显示装置01的显示面板20中不同颜色子像素的遮挡差异，由此可以抑制彩虹纹(例如，抑制纯色画面的彩虹纹，此处，纯色画面是指包括该阵列基板的显示装置的各个子像素的颜色彼此相同)。
例如，通过降低第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值，还可以降低第一线段121、第二线段122、第三线段131和第四线段134的长度，由此可以降低信号从栅线101的一端(例如，左端)传递到栅线101的另一端(例如，右端)所需的时间，由此可以降低信号延迟。
例如，如图3和图4所示，第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值位于42度-48度(例如，43度-44度)之间。
例如，通过使得第一线段121与第一方向D1的锐角夹角的绝对值α1，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值位于42度-48度(例如，43度-44度)，可以在不劣化(例如，不明显劣化)黑白纹问题的情况下抑制彩虹纹以及降低信号延迟。
例如，通过使得每根栅线101包括沿第一方向D1并列布置且顺次相接的多个网格部110，可以在降低第一线段121与第一方向D1的锐角夹角的绝对值，第二线段122与第一方向D1的锐角夹角的绝对值，第三线段131与第一方向D1的锐角夹角的绝对值以及第四线段134与第一方向D1的锐角夹角的绝对值的情况下，使得(例如，保证)包括该阵列基板100的显示装置01的显示面板20中的每行显示像素单元204均被栅线101部分遮挡，由此可以避免黑白纹问题劣化。
例如，通过使得每根栅线101包括沿第一方向D1并列布置且顺次相接的多个网格部110，还可以在降低第一线段121-第四线段134与第一方向D1的锐角夹角的绝对值的情况下，避免控光面板10的控光像素单元103的数目 加倍，这是由于在栅线不包括网格部的情况下，第一线段121-第四线段134与第一方向D1的锐角夹角的绝对值降低将导致阵列基板的栅线的数目的增多，由此可以避免控光面板10的负载(例如，电容负载)增加。
例如，如图3和图4所示，第一折线走线120和第二折线走线130相对于第一折线走线120的起点和第一折线走线120的终点的连线(例如，虚拟连线)对称；此种情况下，可以提升包括该阵列基板100的显示装置01的显示效果。
例如，如图3和图4所示，第一线段121和第二线段122相对于第一折线走线120的顶点和第二折线走线130的顶点的连线(例如，虚拟连线)对称；第三线段131和第四线段134相对于第一折线走线120的顶点和第二折线走线130的顶点的连线(例如，虚拟连线)对称；此种情况下，可以进一步地提升包括该阵列基板100的显示装置01的显示效果。
例如，如图3和图4所示，控光像素单元103的边界走线由对应的数据线102和对应栅线101的网格部110的第一折线走线120形成；每根栅线101的网格部110的第二折线走线130穿过对应的控光像素单元103的内部。如图3所示，相邻的两根数据线102与相邻的两根栅线的第一折线走线120相交，且上述相邻的两根数据线102的位于上述相邻的两根栅线的第一折线走线120之间的部分以及上述相邻的两根栅线的第一折线走线120的位于上述相邻的两根数据线102的之间的部分形成了控光像素单元103的边界走线。
例如，阵列基板包括衬底基板(图中未示出)，每根栅线101的网格部110的第二折线走线130在衬底基板上的正投影被与上述第二折线走线130对应的控光像素单元103在衬底基板上的正投影完全覆盖。例如，每根栅线101的网格部110的第二折线走线130的起点、终点和顶点在衬底基板上的正投影被与上述第二折线走线130对应的控光像素单元103的边界走线在衬底基板上的正投影覆盖(例如，完全覆盖)。
例如，每个控光像素单元103还包括开关元件141和像素电极142；图5示出了图3所示的阵列基板100的开关元件141和像素电极142的平面示意图。如图5所示，开关元件141包括栅极、源极和漏极，开关元件141的栅极与对应的第二折线走线130(也即，穿过包括该开关元件141的控光像素单元103的第二折线走线130)电连接，开关元件141的源极和漏极之一与 像素电极142电连接(例如，通过过孔电连接)，开关元件141的源极和漏极的另一个与数据线102电连接。例如，上述与开关元件141的源极和漏极的另一个电连接的数据线102是指用于形成包括该开关元件141的控光像素单元103的边界走线的两根数据线中与该开关元件141更为接近的数据线。例如，开关元件141的数目等于第二折线走线130的数目(也即，网格部110的数目)。例如，如图5所示，开关元件141的栅极与第二折线走线130的靠近第二折线走线130的顶点的位置电连接。例如，栅线101和数据线102例如可以采用金属材料(例如，铜、铝或者铝合金)形成，像素电极142例如可以采用透明导电材料形成。例如，透明导电材料为氧化铟锡(ITO)或氧化铟锌(IZO)。
例如，像素电极142与控光像素单元103具有实质上相同的形状。例如，像素电极142与控光像素单元103具有实质上相同的形状是指像素电极142与控光像素单元103的设计形状相同，在实际产品中，允许像素电极142与控光像素单元103的形状具有一定(例如，小于5％或10％)的偏差。
例如，像素电极142与控光像素单元103具有实质上相同的尺寸。例如，像素电极142与控光像素单元103具有实质上相同的尺寸是指像素电极142的尺寸与控光像素单元103的尺寸的差值与像素电极142的尺寸与控光像素单元103的尺寸的平均值的比值小于10％(例如，小于5％)。
例如，如图3和图4所示，每根数据线102与一个对应的网格部110(也即，与上述每根数据线102在栅线上的正投影重叠的网格部110)的网格线在垂直于阵列基板100的方向上具有两个重叠位置。例如，上述重叠位置分别对应于第一折线走线120的顶点和第二折线走线130的顶点。例如，如图3和图4所示，阵列基板100还包括沿第二方向D2延伸的公共电极线104，公共电极线104与相邻的两个网格部110的连接处在垂直于阵列基板100的方向上重叠。例如，如图3和图4所示，每个网格部110包围的开口区域112和两个控光像素单元103(例如，两个在第一方向D1相邻的控光像素单元103)在垂直于阵列基板100的方向上部分重叠。例如，如图3所示，多根公共电极线104和多根数据线102在第一方向D1上交替排布。需要说明的是，每根数据线102与一个对应的网格部110的网格线在垂直于阵列基板100的方向上具有两个重叠位置表示每根数据线102与一个对应的网格部110的网 格线上的两个位置在垂直于阵列基板100的方向上重叠，或者每根数据线102在栅线上的正投影与一个对应的网格部110的网格线具有两个重叠位置。例如，公共电极线104被配置为接收公共电极信号。
例如，第一折线走线120和第二折线走线130的宽度(例如，垂直折线走线的延伸方向上的宽度)均位于9微米-11微米之间(例如，10微米)。例如，图1B所示的栅线101的宽度(例如，垂直栅线的延伸方向上的宽度)约为20微米。例如，通过使得图3所示的第一折线走线120和第二折线走线130约为图1B所示的栅线510的宽度的一半，可以使得包括该阵列基板100的显示装置01的开口率不降低。
图6A示出了本公开的至少一个实施例提供的另一种阵列基板100的平面示意图，图6A所示的阵列基板100与图3所示的阵列基板100类似；此处仅阐述两者不同之处，相同之处不再赘述。
图6A所示的阵列基板100的控光像素单元103的边界走线由对应的公共电极线104和对应栅线101的网格部110的第一折线走线120形成；每根栅线101的网格部110的第二折线走线130穿过对应的控光像素单元103的内部。图6A所示的阵列基板100的每个网格部110包围的开口区域112和一个控光像素单元103在垂直于阵列基板100的方向上至少部分重叠(例如，完全重叠)。
如图6A所示，相邻的两根公共电极线104与相邻的两根栅线的第一折线走线120相交，且上述相邻的两根公共电极线104的位于上述相邻的两根栅线的第一折线走线120之间的部分以及上述相邻的两根栅线的第一折线走线120的位于上述相邻的两根公共电极线104的之间的部分形成了控光像素单元103的边界走线。
需要说明的是，第一线段121、第二线段122、第三线段131和第四线段134不限于实现为图3和图6A所示的直线线段(对应地，栅线101的网格部110不限于为菱形)，还可以实现为曲线线段。图6B示出了本公开的至少一个实施例提供的阵列基板100的另一种栅线101的平面示意图。如图6B所示，第一线段121、第二线段122、第三线段131和第四线段134均实现为曲线线段。
在一些示例中，每根数据线102与相邻的两个网格部110的连接处在垂 直于阵列基板100的方向上重叠，公共电极线104与一个对应的网格部110(也即，与上述公共电极线104在栅线上的正投影重叠的网格部110)的网格线在垂直于阵列基板100的方向上具有两个重叠位置。需要说明的是，公共电极线104与一个对应的网格部110的网格线在垂直于阵列基板100的方向上具有两个重叠位置是指公共电极线104与一个对应的网格部110的网格线的两个位置在垂直于阵列基板100的方向上重叠，或者公共电极线104在栅线上的正投影与一个对应的网格部110的网格线具有两个重叠位置。
本公开的至少一个实施例还提供了一种控光面板10。图7是本公开的至少一个实施例提供的控光面板10的截面示意图。如图7所示，该控光面板10包括对置基板201、液晶层202以及本公开的至少一个实施例提供的任一阵列基板100；阵列基板100和对置基板201相对设置，液晶层202夹置于阵列基板100和对置基板201之间。例如，如图7所示，对置基板201、液晶层202和阵列基板100在第三方向D3上顺次设置。例如，第三方向D3、第一方向D1、第二方向D2彼此交叉(例如，彼此垂直)。例如，阵列基板100和对置基板201在垂直于控光面板10的方向上或第三方向D3上在至少部分重叠。
例如，控光面板10可以基于其接收的数据信号来调节控光面板10(图7未示出，参见图8)的各个控光像素单元103的透射率，控光面板10可用于向显示面板20提供调节后的背光。例如，控光面板的控光像素单元103被配置为控制入射至对应于该控光像素单元103的显示子像素单元(显示面板20包括的显示子像素单元)上的光线的强度。例如，控光面板10包括的多个控光像素单元103的形状和尺寸实质上相同。
本公开的至少一个实施例还提供了一种显示装置01。例如。该显示显示装置01可以实现为基于ADS(高级超维场转换技术)的显示装置或者基于IPS-ADS(也即，i-ADS，平面内转换-高级超维场转换技术)技术的显示装置。
图8是本公开的至少一个实施例提供的显示装置01的截面示意图。如图8所示，该显示装置01包括显示面板20、背光单元30以及本公开的至少一个实施例提供的任一控光面板10。显示面板20位于控光面板10的出光侧，背光单元30位于控光面板10远离显示面板20的一侧。例如，如图8所示， 显示面板20、控光面板10和背光单元30在第三方向D3叠置。例如，如图8所示，显示面板20、控光面板10和背光单元30在第三方向D3上顺次设置。例如，相比于控光面板10的对置基板201，控光面板10的阵列基板100更靠近背光单元30。例如，显示面板20的分辨率为控光面板10分辨率的二倍。
图9A是图8所示的显示装置01的显示面板20的平面示意图。如图9A所示，显示面板20包括多根沿第一方向D1延伸的第一信号线205以及多根沿第二方向D2延伸的第二信号线206；多根第一信号线205和多根第二信号线206相交界定多个显示像素单元204(例如，限定多个显示子像素单元)。例如，第一信号线205为显示面板20的栅线，第二信号线206为显示面板20的数据线。例如，第一信号线205被配置为提供扫描信号(例如，显示扫描信号)，第二信号线206被配置为提供数据信号(例如，显示数据信号)，上述显示数据信号被配置为控制显示子像素单元的透过率。例如，多个显示像素单元204的形状和尺寸实质上相同。
如图9A所示，每个显示像素单元204包括第一显示子像素单元2041、第二显示子像素单元2042和第三显示子像素单元2043；第一显示子像素单元2041、第二显示子像素单元2042和第三显示子像素单元2043例如分别为红色显示子像素单元、绿色显示子像素单元和蓝色显示子像素单元。
图9B是图8所示的显示装置01的平面示意图。例如，如图9B所示，每个显示像素单元204在第一方向D1上的尺寸等于每个显示像素单元204在第二方向D2上的尺寸。如图9B所示，每个显示子像素单元在第一方向D1上的尺寸等于每个显示像素单元204在第一方向D1上的尺寸的三分之一。例如，第一信号线205的宽度(第一信号线205在第二方向上或在在垂直于第一信号线205的延伸方向上的宽度)大于第一折线走线120的宽度(和第二折线走线130的宽度)。例如，第一信号线205的宽度(第一信号线205在第二方向上的宽度)等于第一折线走线120的宽度(和第二折线走线130的宽度)的二倍。例如，折线走线的宽度是指折线走线在垂直于折线走线的延伸方向上的宽度。
图10是图9B所示的显示装置01的网格部110平面示意图。如图9B和图10所示，网格部110在第一方向D1上的尺寸为W1，网格部110在第二 方向D2上的尺寸为W2。如图9B所示，网格部110在第一方向D1上的尺寸W1等于显示像素单元204在第一方向D1上的尺寸的两倍；网格部110在第二方向D2上的尺寸W2小于(略小于)显示像素单元204在第二方向D2上的尺寸的两倍，且大于显示像素单元204在第二方向D2上的尺寸。在一些示例中，网格部110在第二方向D2上的尺寸W2还可以等于显示像素单元204在第二方向D2上的尺寸的两倍，此种情况下，第一折线走线120的顶点和第二折线走线130的顶点与第二方向D2交叉。
例如，网格部110在第一方向D1上的尺寸是指网格部110在第一方向D1上的相距最远的两个点(例如，第一折线走线120的顶点和第二折线走线130的顶点)在第一方向D1上的间距；网格部110在第二方向D2上的尺寸是指网格部110在第二方向D2上的相距最远的两个点(例如，第一折线走线120的起点和终点)在第二方向D2上的间距。
图11是图9B所示的显示装置01的像素单元的平面示意图。如图9B和图11所示，控光像素单元103在第一方向D1上的尺寸为P1，控光像素单元103在第二方向D2上的尺寸为P2。如图1B和图1C所示，控光像素单元103在第一方向D1上的尺寸P1等于显示像素单元204在第一方向D1上的尺寸的二倍；控光像素单元103在第二方向D2上的尺寸等于显示像素单元204在第一方向D1上的尺寸的2.5倍-3倍。
需要说明的是，像素单元在第二方向D2上的尺寸等于与像素单元在第二方向D2上两侧的顶点相连的两条平行于第一方向D1平行线在第二方向D2上的间距；例如，像素单元在第二方向D2上的尺寸等于与像素单元在第二方向D2的上侧的顶点相连且平行于第一方向D1平行线以及与像素单元在第二方向D2的下侧的顶点相连且平行于第一方向D1平行线在第二方向D2上的间距。
例如，显示装置01还包括设置于显示面板20与控光面板10之间的各向同性扩散膜(isotropic diffusion film，图中未示出)。各向同性扩散膜可以使由控光面板10出射的光在较小的角度范围内扩散，从而使数据线102的图案变得模糊从而进一步消除摩尔纹，同时，不会对控光面板10出射的光的方向产生较大的影响。
例如，该显示装置01可以为：手机、平板电脑、电视机、显示器、笔记 本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。需要说明的是，对于该显示装置的其它组成部分(例如，控制装置、图像数据编码/解码装置、行扫描驱动器、列扫描驱动器、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。该显示装置可以实现提升显示效果。
例如，基于同一发明构思，本公开的至少一个实施例还提供了一种阵列基板的制造方法。该阵列基板的制造方法包括：形成分别沿第一方向延伸的多根栅线，分别沿与第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元。
例如，每根栅线包括沿第一方向并列布置且顺次相接的多个网格部，每个网格部包括网格线以及由网格线围成的开口区域。例如，阵列基板的具体结构可以参见本公开的至少一个实施例提供的阵列基板，在此不再赘述。例如，包括采用了该制造方法制作的阵列基板的显示装置可以提升显示效果。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (18)

  1. 一种阵列基板，包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元，
    其中，每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部，每个网格部包括网格线以及由所述网格线围成的开口区域。
  2. 根据权利要求1所述的阵列基板，其中，每个所述网格部的网格线包括第一折线走线和第二折线走线；
    所述第一折线走线的起点和所述第二折线走线的起点相接；
    所述第一折线走线的终点和所述第二折线走线的终点相接；以及
    所述第一折线走线的顶点和所述第二折线走线的顶点在所述第二方向上间隔设置。
  3. 根据权利要求2所述的阵列基板，其中，所述第一折线走线包括依次连接的第一线段和第二线段，所述第一线段和所述第二线段的连接点为所述第一折线走线的顶点；
    所述第二折线走线包括依次连接的第三线段和第四线段，所述第三线段和所述第四线段的连接点为所述第二折线走线的顶点；以及
    所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于38度-55度之间。
  4. 根据权利要求3所述的阵列基板，其中，所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于42度-48度之间。
  5. 根据权利要求3或4所述的阵列基板，其中，所述第一折线走线和所述第二折线走线相对于所述第一折线走线的起点和所述第一折线走线的终点的连线对称。
  6. 根据权利要求3-5任一项所述的阵列基板，其中，所述第一线段和所述第二线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称；以及
    所述第三线段和所述第四线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称。
  7. 根据权利要求1-6任一所述的阵列基板，其中，每根所述数据线与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置，或者与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠。
  8. 根据权利要求7所述的阵列基板，还包括沿所述第二方向延伸的公共电极线，
    其中，所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠，或者与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置。
  9. 根据权利要求1-6任一所述的阵列基板，其中，每个所述网格部包围的开口区域和一个或两个所述控光像素单元在垂直于所述阵列基板的方向上部分重叠。
  10. 根据权利要求2-6任一所述的阵列基板，其中，每个所述控光像素单元的边界走线由对应的所述数据线和对应的栅线的网格部的第一折线走线形成；以及
    每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部。
  11. 根据权利要求2-6和10任一所述的阵列基板，还包括沿所述第二方向延伸的公共电极线，
    其中，所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠；
    每个所述控光像素单元的边界走线由对应的所述公共电极线和对应所述栅线的网格部的第一折线走线形成；以及
    每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部。
  12. 根据权利要求2-6、10和11任一所述的阵列基板，其中，每个所述控光像素单元还包括开关元件和像素电极；
    所述开关元件包括栅极、源极和漏极，
    所述开关元件的栅极与对应的所述第二折线走线电连接，所述开关元件的源极和漏极之一与所述像素电极电连接；以及
    所述开关元件的数目等于所述第二折线走线的数目。
  13. 根据权利要求2-6和10-12任一所述的阵列基板，其中，所述第一折线走线和所述第二折线走线的宽度均位于9微米-11微米之间。
  14. 根据权利要求1所述的阵列基板，其中，每个所述网格部的网格线 包括第一折线走线和第二折线走线；
    所述第一折线走线的起点和所述第二折线走线的起点相接，所述第一折线走线的终点和所述第二折线走线的终点相接；
    所述第一折线走线的顶点和所述第二折线走线的顶点在所述第二方向上间隔设置；
    所述第一折线走线包括依次连接的第一线段和第二线段，所述第一线段和所述第二线段的连接点为所述第一折线走线的顶点；
    所述第二折线走线包括依次连接的第三线段和第四线段，所述第三线段和所述第四线段的连接点为所述第二折线走线的顶点；
    所述第一线段与所述第一方向的锐角夹角的绝对值，所述第二线段与所述第一方向的锐角夹角的绝对值，所述第三线段与所述第一方向的锐角夹角的绝对值以及所述第四线段与所述第一方向的锐角夹角的绝对值位于42度-48度之间；
    所述第一折线走线和所述第二折线走线相对于所述第一折线走线的起点和所述第一折线走线的终点的连线对称；
    所述第一线段和所述第二线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称；
    所述第三线段和所述第四线段相对于所述第一折线走线的顶点和所述第二折线走线的顶点的连线对称；
    每根所述数据线与一个对应的网格部的网格线在垂直于所述阵列基板的方向上具有两个重叠位置；
    所述阵列基板还包括沿所述第二方向延伸的公共电极线，所述公共电极线与相邻的两个网格部的连接处在垂直于所述阵列基板的方向上重叠；
    每个所述网格部包围的开口区域和两个所述控光像素单元在垂直于所述阵列基板的方向上部分重叠；
    所述控光像素单元的边界走线由对应的所述数据线和对应的栅线的网格部的第一折线走线形成，每根所述栅线的网格部的第二折线走线穿过对应的所述控光像素单元的内部；
    每个所述控光像素单元还包括开关元件和像素电极；所述开关元件包括栅极、源极和漏极，所述开关元件的栅极与对应的所述第二折线走线电连接，所述开关元件的源极和漏极之一与所述像素电极电连接，所述开关元件的数目等于所述第二折线走线的数目。
  15. 一种控光面板，包括阵列基板、对置基板和液晶层，
    其中，所述阵列基板和所述对置基板相对设置；
    所述液晶层夹置于所述阵列基板和所述对置基板之间；
    所述阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元；
    每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部；以及
    每个网格部包括网格线以及由所述网格线围成的开口区域。
  16. 一种显示装置，包括：显示面板、控光面板以及背光单元，
    其中，所述显示面板位于所述控光面板的出光侧；
    所述背光单元位于所述控光面板远离所述显示面板的一侧；
    所述控光面板包括阵列基板、对置基板和液晶层；
    所述阵列基板和所述对置基板相对设置；
    所述液晶层夹置于所述阵列基板和所述对置基板之间；
    所述阵列基板包括分别沿第一方向延伸的多根栅线，分别沿与所述第一方向相交的第二方向的延伸的多根数据线，以及多个控光像素单元；
    每根所述栅线包括沿所述第一方向并列布置且顺次相接的多个网格部；以及
    每个网格部包括网格线以及由所述网格线围成的开口区域。
  17. 根据权利要求16所述的显示装置，其中，所述显示面板包括阵列排列的多个显示像素单元；
    每个所述网格部在所述第一方向上的尺寸等于每个所述显示像素单元在所述第一方向上的尺寸的二倍；以及
    每个所述网格部在所述第二方向上的尺寸小于或等于每个所述显示像素单元在所述第二方向上的尺寸的二倍。
  18. 根据权利要求16或17所述的显示装置，其中，每个所述控光像素单元在所述第一方向上的尺寸等于每个所述显示像素单元在所述第一方向上的尺寸的二倍；以及
    每个所述控光像素单元在所述第二方向上的尺寸等于每个所述显示像素单元在所述第一方向上的尺寸的2.5-3倍。
PCT/CN2020/109937 2019-08-23 2020-08-19 阵列基板、控光面板和显示装置 WO2021036874A1 (zh)

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