WO2021098546A1 - 一种碳纳米管器件及其制造方法 - Google Patents

一种碳纳米管器件及其制造方法 Download PDF

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WO2021098546A1
WO2021098546A1 PCT/CN2020/127661 CN2020127661W WO2021098546A1 WO 2021098546 A1 WO2021098546 A1 WO 2021098546A1 CN 2020127661 W CN2020127661 W CN 2020127661W WO 2021098546 A1 WO2021098546 A1 WO 2021098546A1
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carbon nanotube
layer
gate
dielectric layer
metal
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PCT/CN2020/127661
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English (en)
French (fr)
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孟令款
肖梦梦
张志勇
彭练矛
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北京元芯碳基集成电路研究院
北京华碳元芯电子科技有限责任公司
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Publication of WO2021098546A1 publication Critical patent/WO2021098546A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/464—Lateral top-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/80—Constructional details
    • H10K10/82—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

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  • the invention relates to a carbon nanotube CMOS integrated circuit process, in particular to a carbon nanotube device and a manufacturing method thereof.
  • Carbon nanotubes have the advantages of high speed and low power consumption, and are considered to be one of the best channel materials for field effect transistors in the future.
  • CNTs carbon nanotubes
  • research on the application of carbon nanotubes (CNTs) in integrated circuits has mainly focused on the following aspects, namely, exploring new devices, physical principles, preparation methods, and optimization of performance and structure.
  • this kind of ⁇ -like tri-gate device has a certain limitation in its gate control ability. If the ability of the entire carbon nanotube can be used, the performance of the carbon nanotube device will be effectively enhanced.
  • the floating carbon nanotube device is a more perfect ring-gate device because it avoids the contact between the carbon tube and the substrate material, which can effectively suppress current fluctuations.
  • the gate control capability has also been greatly enhanced, which helps to improve the performance of the device from the improvement of the device structure itself.
  • the process for preparing the gate structure of HKMG is generally divided into two processes: front gate and back gate.
  • the HKMG gate structure chip manufactured by the gate last process has the advantages of lower power consumption and less leakage, so that the high-frequency operation state is more stable, and the phenomenon of frequency reduction after a period of operation will not occur.
  • front gate process it is undoubtedly more advanced, but the manufacturing technology is complicated and the yield rate is difficult to improve. It is difficult to achieve mass production at the early stage of the technology. It also requires customer manufacturers to modify the circuit design according to their needs. More popular in the early days. Later, as the process gradually matures and overcomes the various problems of the gate last process, the post gate process has gradually replaced the front gate process as the main manufacturing process of the HKMG gate structure in recent years.
  • the first is to use photolithography exposure and etching to achieve the suspension of carbon nanotubes.
  • the disadvantage is that the photoresist and hard mask materials are difficult to remove on the surface of the carbon nanotubes, and the carbon nanotubes may be damaged during the process. The surface of the material will affect the performance of the device.
  • the second method is to process the source and drain electrodes on the substrate in advance, and then use the in-situ chemical vapor deposition method to grow the carbon nanotubes between the electrodes to achieve suspension.
  • this method avoids the effects of the above methods, the carbon nanotubes are only attached to the surface of the source and drain electrodes.
  • this method of processing the source and drain first cannot use a self-aligned process, and it is very difficult when the gate electrode is subsequently processed.
  • the present invention proposes a new manufacturing method, which can use a method compatible with the semiconductor industry to manufacture ring-gate carbon nanotube devices, which will effectively promote the application of this new device in the semiconductor industry.
  • the purpose of the present invention is to provide a carbon nanotube device in which the carbon nanotubes are completely released to form an unsupported floating channel, which is then integrated with the traditional CMOS device back gate process to form Ring-gate carbon nanotube device.
  • One aspect of the present invention provides a carbon nanotube device, including a substrate, covering a dielectric layer, a carbon nanotube layer, and a gate dielectric layer on the substrate.
  • the gate dielectric layer has a gate including sidewalls and a high-K metal gate material.
  • the pole structure is as follows:
  • the central layer of the rod-shaped ring gate is a rod-shaped carbon nanotube, an outer layer covering a gate dielectric layer and a high-K metal gate material layer, and at the same time, a metal gate threshold modulation layer and a metal gate are respectively deposited in the trenches between the sidewalls.
  • the gate barrier layer and the lead metal layer are composed of various single metals or a combination of multiple metals.
  • the substrate is selected from hard insulating materials such as silicon wafers, SOI silicon wafers, silicon oxide, silicon nitride, quartz, glass, aluminum oxide and the like, and high temperature resistant flexible insulating materials such as PET, PEN, and polyimide, and Preferably it is a silicon wafer.
  • the carbon nanotube layer can be a carbon nanotube film with a semiconductor ratio of >90%, or a grown carbon nanotube array, a carbon nanotube network film, a carbon tube self-assembled film, and the above A composite layer of any combination of the two.
  • the source and drain metal electrode layers are selected from single metals or alloys thereof such as palladium, scandium, nickel platinum alloy, titanium, cobalt, yttrium, aluminum, molybdenum, or other metals.
  • the dielectric layer is silicon oxide, silicon nitride, silicon oxynitride, or a composite material composed of any two or three of the foregoing, and may also be other insulating layer materials that are easy to remove.
  • Another aspect of the present invention provides a method for manufacturing the aforementioned carbon nanotube device, which is characterized in that it comprises the following steps:
  • S1 Provide a substrate sequentially covered with a dielectric layer, a carbon nanotube layer, and a gate dielectric layer, on which a gate structure including a dummy gate electrode and a side wall is formed, and source and drain metal electrode layers are formed on both sides of the side wall ;
  • step S2 Depositing a first interlayer dielectric layer ILD0 on the structure formed in the above step S1 to cover the entire dummy gate structure, and performing CMP planarization, stopping on the surface of the dummy gate electrode;
  • a gate dielectric layer and a high-K metal gate material layer are sequentially deposited to respectively cover the outer surface of the suspended horizontal rod-shaped carbon nanotube array to form a horizontal rod-shaped ring gate, and then the metal gates are sequentially deposited in the trenches Modulation layer, metal gate barrier layer and lead metal layer until the entire trench is filled;
  • S5 Choose a suitable CMP technology to planarize the high-K metal gate material (HKMG) after filling the film, and then adopt the subsequent process to make contact holes, hole film filling, and local and global metal interconnection layers.
  • HKMG high-K metal gate material
  • the first interlayer dielectric layer ILD0 is formed by PECVD, HDPCVD deposition of silicon oxide, fluid CVD (FCVD) deposition of silicon oxide, and spin-coated insulating dielectric SOD method.
  • step S3 a dry or wet etching technique is used to remove the dummy gate electrode.
  • step S4 wet etching or vaporization etching or other dry etching techniques are used to remove the dielectric layer under the carbon nanotube layer.
  • the dielectric layer is silicon oxide, silicon nitride, silicon oxynitride, or a composite material composed of any two or three of the foregoing, and may also be other insulating layer materials that are easy to remove.
  • Fig. 1 A three-dimensional view of the surrounding grid structure of a carbon nanotube device.
  • FIG. 1 Schematic diagram of the process flow of the nanotube device manufacturing method.
  • FIG. 3 is a schematic diagram of the structure of the dummy gate structure and the source and drain metal electrode layers formed on the semiconductor layer.
  • Figure 4 The ILD0 layer is deposited and planarized.
  • FIG. 5 is a schematic diagram of the device structure with the dummy gate electrode removed to expose the carbon nanotube layer.
  • FIG. 6 is a schematic diagram of the device structure in which the silicon oxide layer on the lower substrate of the carbon nanotube is partially removed so that the carbon nanotube is completely suspended.
  • FIG. 7 is a schematic diagram of the device structure after the HKMG gate is deposited in the trench structure.
  • FIG. 8 is a schematic diagram of the device structure after the HKMG filled film is planarized by CMP.
  • Figure 9 is a schematic diagram of the final device structure after contact hole lithography, filling and other subsequent processes.
  • Fig. 10 is a three-dimensional schematic diagram of the final carbon nanotube device.
  • the present invention proposes a carbon nanotube device structure.
  • the carbon nanotube device includes a substrate 101, covering a dielectric layer 102, a carbon nanotube layer 103, and a gate dielectric layer 104 on the substrate 101.
  • the gate dielectric layer 104 has a gate structure including sidewall spacers 108 and 108 ′ and a dummy gate electrode 107.
  • the dielectric layer 102 may be composed of silicon oxide, silicon nitride, or a composite structure of the two, or other insulating layer materials that are easy to remove, etc.
  • the gate dielectric layer 104 may be silicon oxide or silicon oxynitride.
  • the source and drain metal electrode layers 105 and 106 located on both sides of the sidewalls 108, 108' are deposited on the carbon nanotube 103, and the plane of the carbon nanotube layer 103 between 105 and 106 has a Lateral rod-shaped ring grid array.
  • the ring grid array consists of a plurality of horizontal rod-shaped ring grids 113 connected to the carbon nanotube layer 103 at both ends.
  • each horizontal rod-shaped ring grid 113 is rod-shaped carbon nanotubes 110, the outer layer is coated with a grid dielectric layer 111 and a high K
  • the metal gate material layer 112 and at the same time, materials such as a metal gate modulation layer, a metal gate barrier layer, and a lead metal layer are respectively deposited in the trenches between the sidewall spacers 107 and 108.
  • Figure 2 shows the process flow of the carbon nanotube device manufacturing method proposed by the present invention.
  • Figures 3-10 specifically show the specific steps for preparing the carbon nanotube device proposed by the present invention. Specific embodiments of the invention are described in detail.
  • a substrate 101 is provided, a silicon oxide layer 102, a carbon nanotube layer 103, and a gate oxide layer 104 are formed on the substrate 101, and a dummy gate electrode 107 and a side surface are formed thereon.
  • the gate structure of the wall 108, and then source and drain metal electrode layers 105 and 106 are formed on both sides of the side wall 107, which are located on top of 103.
  • the substrate 101 can be selected from hard insulating materials such as silicon wafers, silicon oxide, silicon nitride, quartz, glass, and aluminum oxide, and high-temperature resistant flexible insulating materials such as PET, PEN, and polyimide. In this embodiment, The substrate 101 uses a silicon wafer.
  • the carbon nanotube layer 103 is a carbon nanotube film with a semiconductor ratio of 90% to 99.9999%, which can be a grown carbon nanotube array and a carbon nanotube network, that is, a neatly arranged film, a carbon tube self-assembled film, and any other
  • the composite film of the combination of the two is a carbon nanotube film in this embodiment.
  • the source and drain electrode metal layers 105 and 106 are selected from single metals such as palladium, scandium, nickel-platinum alloy, titanium, titanium palladium, cobalt, yttrium, aluminum, etc., or other metals not listed here, depending on specific application requirements. Of course, it can also be an alloy or stack of multiple metals composed of the above single metal. In this embodiment, scandium is used as the source and drain electrode metal layers.
  • the material of the dummy gate electrode 107 can be traditional gate oxide materials such as silicon oxide, silicon oxynitride, etc., or high-K dielectric materials such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide or lanthanum aluminum oxide, with a thickness of 1 ⁇ 10nm, silicon oxide with a thickness of 5nm is used in this embodiment.
  • gate oxide materials such as silicon oxide, silicon oxynitride, etc.
  • high-K dielectric materials such as hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide or lanthanum aluminum oxide, with a thickness of 1 ⁇ 10nm, silicon oxide with a thickness of 5nm is used in this embodiment.
  • an interlayer dielectric layer (ILD0) 109 is formed on the source and drain electrode metal layers 105 and 106, the dummy gate structure 107, and the sidewall spacer 108, and chemical mechanical planarization (CMP) is performed , Stop on the surface of the dummy gate electrode 107.
  • the interlayer dielectric layer (ILD0) can be deposited by CVD methods such as SACVD, PECVD, HDPCVD or fluid CVD technology (FCVD) applied to high aspect ratio structures or other more advanced CVD technologies that may be developed in the future. Doped or undoped silicon oxide, or spin-coating method to obtain insulating medium or depositing low-k material to form.
  • Doped silicon oxide includes materials such as borosilicate glass (BSG), phosphosilicate glass (PSG), and borophosphosilicate glass (BPSG).
  • Low-k materials include, but are not limited to, organic low-k materials (for example, containing aromatic groups or Polycyclic organic polymers), inorganic low-k materials, such as amorphous carbonitride films, polycrystalline boron-nitrogen films, fluorosilicate glass, etc., and porous low-k materials (such as disilicate trioxane (SSQ)-based porous low-k Materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymer) and so on.
  • organic low-k materials for example, containing aromatic groups or Polycyclic organic polymers
  • inorganic low-k materials such as amorphous carbonitride films, polycrystalline boron-nitrogen films, fluorosilicate glass, etc.
  • step S3 dry or wet etching technology is used to remove the dummy gate electrode 107 and the gate oxide layer 104 in the trench structure until the carbon nanotube layer 103 is exposed.
  • step S3 using wet etching or vaporization etching or other suitable dry etching techniques to partially remove the dielectric layer 102 under the carbon nanotube layer 103 until the carbon nanotube layer 103 can be completely suspended to form
  • the unsupported structure forms a suspended horizontal rod-shaped array 110 with two ends connected to the carbon nanotube layer 103 respectively.
  • 102 can be made of silicon oxide, silicon nitride, silicon oxynitride, or a composite material composed of any two or three of the foregoing.
  • silicon nitride is used first, and then silicon oxide is deposited on the composite laminate form, except
  • other insulating layer materials that are easy to remove can also be used.
  • a single silicon oxide is used, which can be effectively removed by wet etching with partially diluted HF. The specific removal accuracy can be achieved by accurately controlling the dilution ratio, thereby reducing the degree of lateral corrosion.
  • a gate dielectric layer 111 and a high-K metal material layer 112 are grown and deposited sequentially on the surface of the suspended carbon nanotube layer 110 to respectively cover the surface of each suspended horizontal rod-shaped array 110 to form a ring grid Structure 113, and continue to deposit materials such as a metal gate modulation layer, a metal gate barrier layer, and a lead metal layer in the trench.
  • the structure of the dashed frame part in FIG. 7 is as shown in the enlarged view in FIG. 1.
  • the suspended horizontal rod-shaped array includes a plurality of horizontally suspended ring grid structures 113.
  • step S5 choose to use CMP technology to planarize the high-K metal material (HKMG) filling film filled in the trenches between the sidewalls, and continue to perform subsequent contact hole photolithography and film filling
  • the process specifically, depositing the second interlayer dielectric layer (ILD1) 115 on the structure obtained in step S5 can be formed by depositing silicon oxide by PECVD, SACVD, LPCVD, or HDPCVD, or spin-coating a layer of insulating dielectric SOD.
  • the material selection of ILD1 can be the same or different from that of ILD0.
  • CMP chemical mechanical polishing
  • one-step photolithography is used, that is, the source and drain contact holes and the gate lead metal contact holes are formed at one time.
  • a two-step photolithography is used to form the contact hole, that is, a photolithography pattern of the source and drain contact regions is formed first, and then two regions of the contact hole interconnection metal and the gate connection lead metal are formed. The lithography pattern, then, enters the subsequent process.
  • the carbon nanotube array film is formed globally, and then a gate dielectric layer is formed thereon to protect the channel region of the carbon nanotube array film, and then a dummy gate structure is formed thereon, thereby forming a dummy gate structure
  • it usually needs to go through a photolithography or etching process, which will undoubtedly cause damage to the carbon nanotube array film.
  • due to the gate dielectric layer in the channel region and the source region, and the channel region and the drain region it can When processing the carbon nanotube array film in the source area or the drain area, it plays a role in isolating and protecting the carbon nanotube film in the channel area, and reduces the damage to the carbon nanotube array film in the channel area by external processes. .
  • the dummy gate and the gate dielectric layer in the channel region are removed by etching or vaporization, and the dielectric layer under the carbon nanotube array film is partially removed, thereby forming a suspended carbon nanotube rod array. Since the floating carbon nanotubes in the channel region are released, the gate dielectric layer remaining between the channel region and the source region and between the channel region and the drain region can also affect the floating rod-shaped array. In order to fix and protect, it can minimize the damage to the rod-shaped carbon nanotube array in the channel area.
  • the present invention can adopt a method compatible with the semiconductor industry to manufacture a ring-gate carbon nanotube device, which will effectively promote the application of this new device in the semiconductor industry.

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Abstract

一种碳纳米管器件及其制造方法，该碳纳米管器件结构位于侧墙（108, 108 '）之间的栅电极底部位置，由多个两端分别与碳纳米管层（103）连接的横向棒状环栅（113）阵列构成，各横向棒状环栅（113）外层包覆栅介质层（111）和高K金属栅材料层（112）。同时还提出了该器件的制造方法，首先通过前栅工艺形成假栅电极结构，然后通过去除假栅电极（107）露出碳纳米管层（103），再将该层下方的电介质材料腐蚀掉，从而将碳纳米管层（103）从其上完全释放出来，形成无支撑的结构，并在悬空的棒状环栅阵列表面上生长栅介质层（111）和高K金属栅材料等，并进行后续处理工艺得到满足需要的环栅纳米线器件，从而实现了采用自对准工艺与传统CMOS器件技术相集成制备环栅碳纳米管器件的方法。

Description

一种碳纳米管器件及其制造方法
相关申请的交叉引用
本申请要求享有于2019年11月19日提交的名称为“一种碳纳米管器件及其制造方法”的中国专利申请CN 201911131392.4的优先权上述申请的全部内容通过引用并入本文中。
技术领域
本发明涉及碳纳米管CMOS集成电路工艺，特别涉及一种碳纳米管器件及其制造方法。
背景技术
碳纳米管(CNTs)具有高速、低功耗等方面的优点，被认为是未来最佳的构建场效应晶体管的沟道材料之一。在过去近20年中，碳纳米管(CNTs)在集成电路应用上的研究主要集中于如下几个方面，即探索新器件、物理原理、制备方式以及性能和结构的优化。
绝大多数的研究聚焦于平面碳纳米管器件上，即碳纳米管需要生长在衬底支撑层，如氧化硅上，作为后续的沟道材料使用。从实际效果上来说，近似于一个Ω结构的三栅器件。研究发现，这种器件在工作过程中，有较明显的回滞现象。所谓回滞现象是指输入信号周期性变化的时候，输出的非周期变化，就是非单一对应关系。对于场效应晶体管而言，器件在工作中一个很重要的因素就是电压对电流的稳定控制，而稳定性又可分为两种：长期稳定性和可重复性。而电流回滞现象是“电压-电流”调控关系不可重复性的最直接体现(瞿敏妮，《有机薄膜晶体管中电流回滞现象及其起源研究》，2014，复旦大学硕士论文)。对于许多研究指出碳纳米管下的氧化硅材料之中存在的缺陷或两者的相互作用对回滞有一定影响。消除底部氧化硅会明显地提升碳纳米管的器件性能。
另一方面，这种类Ω结构的三栅器件，栅控能力受到一定限制，如果能够将整个碳纳米管的能力都发挥出来必将有效增强碳纳米管器件的性能。
比起依赖衬底的Ω结构碳纳米管器件，悬空碳纳米管器件是一种更为完美的环栅器件，因为它避免了碳管和衬底材料的接触，由此可以有效抑制电流波动，同时栅控能力也得到了极大的增强，这从器件结构本身的改进上便有助于提升器件性能。
在CMOS工艺中，制备HKMG(金属栅极+高介电常数绝缘层(High-k)栅结构)栅极结构的工艺一般分为前栅、后栅两种工艺。采用后栅极工艺制造的HKMG栅极结构的芯片，具有功耗更低和漏电更少的优势，从而让高频运行状态更加稳定，不会出现运行一段时间后降频这种现象。相比前栅极工艺无疑更加先进，但是生产制造技术复杂、良品率较难提升，技术诞生初期很难做到大规模量产，还需要客户厂商根据需求配合修改电路设计，所以前栅极工艺在早期更受欢迎。后来，随着工艺逐渐走向成熟，克服了后栅极工艺的种种问题之后，近几年后栅极工艺逐渐取代前栅极工艺成为HKMG栅极结构的主要制造工艺。
目前，制备悬空的环栅碳纳米管器件主要有两种方法：
第一种是利用光刻曝光和刻蚀的方法实现碳纳米管悬空，缺点是光刻胶及硬掩模材料在碳纳米管表面上较难去除，在工艺过程中有可能会损伤碳纳米管的材料表面，进而会影响器件的性能。
第二种方法是预先在衬底上加工好源漏电极，然后采用原位生长的化学气相沉积法使碳纳米管生长在电极之间实现悬空。尽管这种方法避免了上述方法的影响，但是碳纳米管只是附着在源漏电极表面。同时，这种先加工源漏的方式，无法采用自对准工艺，在后续进行栅电极时，非常困难。
尽管当前已经有了将碳纳米管从衬底材料上释放出来的报道，并做出了简单的器件并进行了验证，但还没有采用能与半导体量产制造技术有效集成而制备环栅碳纳米管器件的报道。本发明提出了一种新的制造方法，可以采用能够与半导体工业兼容的方法将环栅碳纳米管器件制造出来，这将有效推动这一新型器件在半导体产业上的应用。
发明内容
本发明的目的是提供一种碳纳米管器件，在该器件结构中碳纳米管被完全释放，从而形成无支撑的悬空沟道，之后再将其与传统的CMOS器件后栅工艺相集成，形成环栅碳纳米管器件。
本发明一方面提供了一种碳纳米管器件，包括衬底，覆盖衬底上的电介质层、碳纳米管层和栅介质层，栅介质层上具有包括侧墙和高K金属栅材料的栅极结构，具体如下：
侧墙外侧具有源漏金属电极层，在所述侧墙沟槽之间的碳纳米管层所在平面具有一横向棒状环栅阵列，该阵列两端分别与源漏金属电极下的碳纳米管层连接，所述棒状环栅中心层为棒状碳纳米管、外层包覆栅介质层和高K金属栅材料层，同时在侧墙之间的沟槽中分别沉积由金属栅阈值调制层、金属栅阻挡层及引线金属层组成的各种单一金属或多种金属的组合材料。
优选地，衬底选自硅片、SOI硅片、氧化硅、氮化硅、石英、玻璃、氧化铝等硬质绝缘材料，以及PET、PEN、聚酰亚胺等耐高温柔性绝缘材料，并优选为硅片。
优选地，碳纳米管层可以是具有半导体比例>90％的碳纳米管薄膜，也可以是生长的碳纳米管阵列、碳纳米管网络状(Network)薄膜，碳管自组装薄膜，以及由上述任两者组合的复合层。
优选地，源漏金属电极层选自钯、钪、镍铂合金、钛、钴、钇、铝、钼或其他金属等的单一金属或其合金。
优选地，电介质层为氧化硅、氮化硅、氮氧化硅或由上述任意两种或三种组成的复合材料，也可以是其他易于去除的绝缘层材料。
本发明另一方面提供了一种制造上述碳纳米管器件的方法，其特征在于，包含以下步骤：
S1：提供一依次覆盖有电介质层、碳纳米管层以及栅介质层的衬底，在其上形成包括假栅电极和侧墙的栅极结构，并在侧墙两侧形成源漏金属电极层；
S2：在上述步骤S1上形成的结构上沉积第一层间介质层ILD0覆盖整个假栅结构，并进行CMP平坦化，停止在假栅电极表面；
S3：去除沟槽结构中的假栅电极和栅介质层，直到暴露出所述碳纳米管，并部分去除所述碳纳米管层下方的电介质层，直到碳纳米管能够完全悬空，形成两端分别与所述沟槽两侧的碳纳米管层侧面连接的悬空的横向棒状碳纳米管阵列；
S4：在上述沟槽结构中依次沉积栅介质层和高K金属栅材料层分别包覆悬空的横向棒状碳纳米管阵列外表面，形成横向棒状环栅，并继续在沟槽中依次沉积金属栅调制层、金属栅阻挡层及引线金属层，直到填充整个沟槽；
S5：选择合适的CMP技术进行高K金属栅材料(HKMG)填充薄膜后的平坦化，然后采取后续流程制作接触孔、孔薄膜填充以及局部和全局金属互连层。
优选地，其中所述第一层间介质层ILD0采用PECVD、HDPCVD沉积氧化硅、流动性CVD(FCVD)沉积氧化硅、旋涂的绝缘介质SOD方法形成。
优选地，步骤S3中采用干法或湿法刻蚀技术去除所述假栅电极。
优选地，步骤S4中采用湿法腐蚀或气化腐蚀或其他干法刻蚀技术去除所述碳纳米管层下的电介质层。
优选地，电介质层为氧化硅、氮化硅、氮氧化硅或由上述任意 两种或三种组成的复合材料，也可以是其他易于去除的绝缘层材料。
附图说明
通过以下参照附图对本发明的碳纳米管器件结构及其制作方法进行描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1碳纳米管器件环栅结构立体图。
图2纳米管器件制作方法流程示意图。
图3在半导体层上形成假栅结构和源漏金属电极层结构示意图。
图4沉积ILD0层并进行平坦化。
图5去除假栅电极暴露出碳纳米管层的器件结构示意图。
图6部分去除碳纳米管下衬底上的氧化硅层使碳纳米管完全悬空的器件结构示意图。
图7在沟槽结构中沉积HKMG栅极后的器件结构示意图。
图8进行HKMG填充薄膜的CMP平坦化后的器件结构示意图。
图9接触孔光刻、填充等后续工艺后的最终器件结构示意图。
图10最终碳纳米管器件立体示意图。
具体实施方式
下面将参照附图详细说明本发明的实施方式。在各附图中，相同的元件采用相同的附图标记来表示，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的半导体结构。
应当理解，在描述器件的结构时，当将一层、一个区域称为位于另一层、另一个区域“上面”或“上方”时，可以指直接位于另一层、另一个区域上面，或者在其与另一层、另一个区域之间还包含其它的层或区域。并且，如果将器件翻转，该一层、一个区域将位于另一层、另一个区域“下面”或“下方”。
如果为了描述直接位于另一层、另一个区域上面的情形，本文将 采用“A直接在B上面”或“A在B上面并与之邻接”的表述方式。在本申请中，“A直接位于B中”表示A位于B中，并且A与B直接邻接，而非A位于B中形成的掺杂区中。
本发明提出了一种碳纳米管器件结构，如图1所示，该碳纳米管器件包括衬底101，覆盖衬底101上的电介质层102、碳纳米管层103和栅介质层104，在栅介质层104上具有包括侧墙108、108’和假栅电极107的栅极结构。其中，电介质层102可以为氧化硅、氮化硅或二者的复合结构组成，也可以采用其他易于去除的绝缘层材料等，栅介质层104可以为氧化硅、氮氧化硅。经过一系列工艺步骤后，位于侧墙108，108’两侧的源漏金属电极层105和106沉积在碳纳米管103之上，在105和106之间的碳纳米管层103所在平面具有一横向棒状环栅阵列。该环栅阵列由多个两端分别与碳纳米管层103连接的横向棒状环栅113，各个横向棒状环栅113内层为棒状碳纳米管110、外层包覆栅介质层111和高K金属栅材料层112，同时在侧墙107和108之间的沟槽中分别沉积金属栅调制层、金属栅阻挡层及引线金属层等材料。
图2示出了本发明提出的碳纳米管器件制造方法工艺流程，图3-10具体示出了本发明提出的制备碳纳米管器件的具体步骤，下面根据图3-9所示的步骤对本发明的具体实施例进行详细描述。
按照步骤S1，如图3所示，提供一衬底101，在衬底101上形成氧化硅层102、碳纳米管层103以及栅氧化层104，并在其上形成包括假栅电极107和侧墙108的栅极结构，然后在侧墙107两侧形成源漏金属电极层105和106，位于103之上。其中衬底101可以选自硅片、氧化硅、氮化硅、石英、玻璃、氧化铝等硬质绝缘材料，以及PET、PEN、聚酰亚胺等耐高温柔性绝缘材料，在本实施例中衬底101采用硅片。
碳纳米管层103为具有90％-99.9999％半导体比例的碳纳米管薄 膜，可以是生长的碳纳米管阵列和碳纳米管网络状即为排列整齐的薄膜，碳管自组装薄膜，以及彼此任两者组合的复合薄膜，本实施例中为碳纳米管薄膜。
源漏电极金属层105和106选自钯、钪、镍铂合金、钛、钛钯、钴、钇、铝等单一金属，也可以为其他没有列在这里的金属，主要视具体应用需求而定，当然也可以由上述单一金属组成的多种金属的合金或叠层，在本实施例中采用钪作为源漏电极金属层。假栅电极107材料可以为氧化硅，氮氧化硅等传统栅氧材料，也可以为氧化铪，氧化锆，氧化钇，氧化钽，氧化镧或氧化镧铝等高K介质材料，厚度范围为1～10nm，本实施例中采用厚度为5nm的氧化硅。
接着按照步骤S2，如图4所示，在源漏电极金属层105和106、假栅结构107、侧墙108之上形成层间介质层(ILD0)109，并进行化学机械平坦化(CMP)，停止在假栅电极107表面上。其中层间介质层(ILD0)可以采用CVD方法如SACVD、PECVD、HDPCVD或应用于高深宽比结构上的流动性CVD技术(FCVD)或未来可能开发的其他更先进的CVD技术等方法沉积一层掺杂或无掺杂的氧化硅，或者采用旋涂的方法得到绝缘介质或者沉积上低k材料来形成。掺杂氧化硅包括硼硅酸盐玻璃(BSG)、磷硅酸盐玻璃(PSG)、硼磷硅玻璃(BPSG)等材料，低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料，例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃等，及多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)等。
进一步按照步骤S3，如图5所示，采用干法或湿法刻蚀技术，去除沟槽结构中的假栅电极107和栅氧化层104，直到暴露出碳纳米管层103。并进一步如图6所示，采用湿法腐蚀或气化腐蚀或其他合适的干 法刻蚀技术，部分去除碳纳米管层103下的电介质层102，直到碳纳米管层103能够完全悬空，形成无支撑的结构，形成两端分别与碳纳米管层103连接的悬空的横向棒状阵列110。此处102可以采用氧化硅、氮化硅、氮氧化硅或由上述任意两种或三种组成的复合材料，如先采用氮化硅，再在其上沉积氧化硅的复合叠层形式，除此之外，也可以采用其他易于去除的绝缘层材料。在本实施例中采用单一氧化硅，采用部分稀释的HF进行湿法腐蚀可将其有效去除。具体去除精度可以通过精确控制稀释比例来实现，从而减少横向腐蚀程度。
进一步按照步骤S4，如图7所示，在悬空的碳纳米管层110表面上生长依次沉积栅介质层111和高K金属材料层112分别包覆各悬空的横向棒状阵列110表面，形成环栅结构113，并继续在沟槽中沉积金属栅调制层、金属栅阻挡层及引线金属层等材料。图7中的虚线框部分的结构如图1中放大图所示。其中悬空的横向棒状阵列包括横向多个棒状悬空的环栅结构113。
进一步按照步骤S5，如图8所示，选择利用CMP技术对填充到侧墙之间的沟槽的高K金属材料(HKMG)填充薄膜进行平坦化，并继续进行后续接触孔光刻、薄膜填充工艺，具体而言，在步骤S5所获得的结构上沉积第二层间介质层(ILD1)115，可以采用PECVD、SACVD、LPCVD或HDPCVD等方法沉积氧化硅或者旋涂一层绝缘介质SOD形成。ILD1的材质选择可与ILD0相同或不同。进一步采用化学机械抛光(CMP)以对层间介质层(ILD1)115平坦化，根据要求，准确停止在栅极结构上方的一定厚度，以满足对局部互连线的要求。接下来如图9所示，在接触孔光刻及刻蚀后，沉积填充金属钨(W plug)116和接触孔互连金属117，如Ti/TiN/W堆叠层材料，然后进行接触孔CMP平坦化，形成图10所示的最终的器件结构。上述接触孔光刻可以由一步或两步光刻组成，在本实施例中采用一步光刻，即源漏接触孔、栅极引线金属接触孔一次形成。在另一个实施例中，在完成前述步骤后， 采用两步光刻形成接触孔，即先形成源漏接触区域的光刻图形，再形成接触孔互连金属和栅极连接引线金属两个区域的光刻图形，然后，进入后序工艺。
工业实用性
本发明通过全局地形成碳纳米管阵列薄膜，然后通过在其上形成一个栅介质层对碳纳米管阵列薄膜的沟道区进行保护，随后再其上形成假栅结构，而在形成假栅结构时，通常要经过光刻或刻蚀工艺，这无疑会对碳纳米管阵列薄膜造成损伤，此时由于在沟道区和源极区以及沟道区和漏极区具有该栅介质层，能够在对源极区或漏极区的碳纳米管阵列薄膜进行工艺处理时，起到对沟道区的碳纳米管薄膜的隔离保护作用，减少外部工艺对沟道区碳纳米管阵列薄膜的损伤。当假栅结构形成之后，通过腐蚀或气化方法去除沟道区的假栅以及栅介质层，并部分去除碳纳米管阵列薄膜下方的电介质层，从而形成悬空的碳纳米管棒状阵列。由于沟道区的碳纳米管之间悬空的碳纳米管进行释放，保留了在沟道区和源极区以及沟道区和漏极区之间的栅介质层也能够对悬空的棒状阵列起到固定和保护作用，最大限度的降低对沟道区棒状碳纳米管阵列的损伤。本发明可以采用能够与半导体工业兼容的方法将环栅碳纳米管器件制造出来，这将有效推动这一新型器件在半导体产业上的应用。
虽然，上文中已经用一般性说明、具体实施方式，对本发明作了详尽的描述，但在本发明基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本发明精神的基础上所做的这些修改或改进，均属于本发明要求保护的范围。

Claims (10)

  1. 一种碳纳米管器件，包括衬底(101)，覆盖衬底(101)上的电介质层(102)、碳纳米管层(103)和栅介质层(104)，栅介质层(104)上具有包括侧墙(108，108’)和高K金属栅材料的栅极结构，其特征在于：
    所述侧墙(108，108’)外侧具有源漏金属电极层(105、106)，在所述侧墙沟槽之间的碳纳米管层(103)所在平面具有一横向棒状环栅(113)阵列，该阵列两端分别与源漏金属电极下的碳纳米管层(103)连接，所述棒状环栅(113)中心层为棒状碳纳米管(110)、外层包覆栅介质层(111)和高K金属栅材料层(112)，同时在侧墙(108，108’)之间的沟槽中分别沉积由金属栅阈值调制层、金属栅阻挡层及引线金属层组成的各种单一金属或多种金属的组合材料。
  2. 如权利要求1所述的碳纳米管器件，其特征在于，所述衬底(101)选自硅片、SOI硅片、氧化硅、氮化硅、石英、玻璃、氧化铝等硬质绝缘材料，以及PET、PEN、聚酰亚胺等耐高温柔性绝缘材料，并优选为硅片。
  3. 如权利要求1所述的碳纳米管器件，其特征在于，所述碳纳米管层(103)可以是具有半导体比例>90％的碳纳米管薄膜，也可以是生长的碳纳米管阵列、碳纳米管网络状(Network)薄膜，碳管自组装薄膜，以及由上述任两者组合的复合层。
  4. 如权利要求1所述的碳纳米管器件，其特征在于，所述源漏金属电极层(105、106)选自钯、钪、镍铂合金、钛、钴、钇、铝、钼或其他金属等的单一金属或其合金。
  5. 如权利要求1所述的碳纳米管器件，其特征在于，所述电介质层(102)为氧化硅、氮化硅、氮氧化硅或由上述任意两种或三种组成的复合材料，也可以是其他易于去除的绝缘层材料。
  6. 一种制造如权利要求1-5所述的碳纳米管器件的方法，其特征在于，包含以下步骤：
    S1：提供一依次覆盖有电介质层(102)、碳纳米管层(103)以及栅介质层(104)的衬底(101)，在其上形成包括假栅电极(107)和侧墙(108，108’)的栅极结构，并在侧墙(108，108’)两侧形成源漏金属电极层(105、106)；
    S2：在上述步骤S1上形成的结构上沉积第一层间介质层ILD0(109)覆盖整个假栅结构，并进行CMP平坦化，停止在假栅电极(107)表面；
    S3：去除沟槽结构中的假栅电极(107)和栅介质层(104)，直到暴露出所述碳纳米管(103)，并部分去除所述碳纳米管层(103)下方的电介质层(102)，直到碳纳米管(103)能够完全悬空，形成两端分别与所述沟槽两侧的碳纳米管层(103)侧面连接的悬空的横向棒状碳纳米管(110)阵列；
    S4：在上述沟槽结构中依次沉积栅介质层(111)和高K金属栅材料层(112)分别包覆悬空的横向棒状碳纳米管(110)阵列外表面，形成横向棒状环栅(113)，并继续在沟槽中依次沉积金属栅调制层、金属栅阻挡层及引线金属层，直到填充整个沟槽；
    S5：选择合适的CMP技术进行高K金属栅材料(HKMG)填充薄膜后的平坦化，然后采取后续流程制作接触孔、孔薄膜填充以及局部和全局金属互连层。
  7. 根据权利要求6所述的碳纳米管器件的制备方法，其特征在于，其中所述第一层间介质层ILD0(109)采用PECVD、HDPCVD沉积氧化硅、流动性CVD(FCVD)沉积氧化硅、旋涂的绝缘介质SOD方法形成。
  8. 根据权利要求6所述的碳纳米管器件的制备方法，其特征在于，步骤S3中采用干法或湿法刻蚀技术去除所述假栅电极(107)。
  9. 根据权利要求6所述的碳纳米管器件的制备方法，其特征在于，步骤S4中采用湿法腐蚀或气化腐蚀或其他干法刻蚀技术去除所 述碳纳米管层(103)下的电介质层(102)。
  10. 如权利要求6所述的碳纳米管器件的制备方法，其特征在于，所述电介质层(102)为氧化硅、氮化硅、氮氧化硅或由上述任意两种或三种组成的复合材料，也可以是其他易于去除的绝缘层材料。
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CN112420821B (zh) * 2020-10-29 2021-11-19 北京元芯碳基集成电路研究院 一种基于碳基材料的y型栅结构及其制备方法
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