WO2021083298A1 - 一种显示基板及其制作方法、显示装置 - Google Patents

一种显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021083298A1
WO2021083298A1 PCT/CN2020/124967 CN2020124967W WO2021083298A1 WO 2021083298 A1 WO2021083298 A1 WO 2021083298A1 CN 2020124967 W CN2020124967 W CN 2020124967W WO 2021083298 A1 WO2021083298 A1 WO 2021083298A1
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Prior art keywords
sub
electrode
pixel
transistor
display substrate
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Application number
PCT/CN2020/124967
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English (en)
French (fr)
Inventor
董甜
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN201911038883.4A external-priority patent/CN110690265B/zh
Priority claimed from CN201911082352.5A external-priority patent/CN110707139A/zh
Priority to CN202080002859.XA priority Critical patent/CN115605999A/zh
Priority to AU2020376100A priority patent/AU2020376100B2/en
Priority to RU2021119000A priority patent/RU2770179C1/ru
Priority to MX2021008023A priority patent/MX2021008023A/es
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20824415.2A priority patent/EP4053903A4/en
Priority to US17/256,006 priority patent/US12041826B2/en
Priority to JP2020571364A priority patent/JP2022554043A/ja
Priority to BR112021012544-2A priority patent/BR112021012544A2/pt
Priority to KR1020207036474A priority patent/KR102476703B1/ko
Publication of WO2021083298A1 publication Critical patent/WO2021083298A1/zh
Priority to US17/489,771 priority patent/US20220328600A1/en

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H—ELECTRICITY
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • This article relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the organic light-emitting diode (Organic Light-Emitting Device, referred to as OLED) display substrate is a display substrate different from the traditional liquid crystal display (Liquid Crystal Display, referred to as LCD). It has active light emission, good temperature characteristics, low power consumption, and response. Fast, flexible, ultra-thin and low cost. Therefore, it has become one of the important development discoveries of a new generation of display devices, and has attracted more and more attention.
  • a dual data line OLED display substrate is proposed in the related art, that is, the same column of pixels is connected to two data lines.
  • the OLED display substrate in the related art can achieve high-frequency driving, the resolution is generally low, which cannot meet the market demand for high resolution of display devices.
  • a display substrate in a plane parallel to the display substrate, the display substrate includes a plurality of gate lines, a plurality of data lines, a plurality of power lines and a plurality of sub-pixels arranged on a base, at least one sub-pixel includes a light-emitting device And a drive circuit configured to drive the light emitting device to emit light, the drive circuit including a plurality of transistors and storage capacitors; in a plane perpendicular to the display substrate, the display substrate includes a base and a plurality of Functional layer; the plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence; a first insulating layer is respectively arranged between the plurality of functional layers Layer, the second insulating layer, the third insulating layer and the fourth insulating layer; in the extending direction of the gate lines, the power lines are connected to each other through at least one functional layer.
  • the power supply line in the extending direction of the data line, includes a plurality of sub-power supply lines connected in sequence, and at least one sub-power supply line is provided in one sub-pixel; the sub-power supply line of at least one sub-pixel includes Among the multiple power supply parts connected in sequence, an included angle between at least one power supply part and the power supply part connected to the power supply part is greater than 90 degrees and less than 180 degrees.
  • one of the power supply units is arranged in parallel with the data line.
  • the sub power supply line includes a first power supply unit, a second power supply unit, and a third power supply unit; the second power supply unit is configured to connect the first power supply unit and the third power supply unit, so The first power supply unit and the third power supply unit are arranged in parallel with the data line, the angle between the second power supply unit and the first power supply unit is greater than 90 degrees and less than 180 degrees, and the second power supply unit The included angle with the third power supply part is greater than 90 degrees and less than 180 degrees.
  • the first power source part is connected to a third power source part located in a row of sub-pixels on the same column, and the third power source part is connected to a first power source part located in a row of sub-pixels on the same column.
  • the length of the first power supply part extending in the extending direction of the data line is greater than the average width of the first power supply part, and the length of the second power supply part extending in the oblique direction is greater than that of the first power supply part.
  • the average width of the second power supply unit, the length of the third power supply unit extending along the extending direction of the data line is greater than the average width of the third power supply unit; the oblique direction is the second power supply unit and the first power supply unit There is the direction of the included angle between the parts.
  • the average width of the third power supply part is smaller than the average width of the first power supply part.
  • the edge of the first power supply part close to the side in the extension direction of the third power supply gate line and the third power supply part close to the side in the extension direction of the gate line of the first power supply part The distance between the edges is equivalent to the average width of the third power supply part.
  • the display substrate further includes a first connecting portion, and the second electrode of the storage capacitor in the at least one sub-pixel and the second electrode of the storage capacitor in the sub-pixel adjacent to the extension direction of the gate line pass through the first connection part.
  • the connecting portions are connected to each other; in at least one sub-pixel, there is an overlap area between the orthographic projection of the second power supply portion on the substrate and the orthographic projection of the second electrode of the storage capacitor on the substrate, or the second power supply portion There is an overlap area between the orthographic projection on the substrate and the orthographic projection of the first connecting portion on the substrate.
  • the plurality of transistors includes a second transistor, and the orthographic projection of the first power supply part on the substrate and the orthographic projection of the second transistor on the substrate have an overlapping area.
  • the display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer, on the fifth insulating layer A fifth via hole is provided, and the fifth via hole is configured to connect the fifth conductive layer and the fourth conductive layer; the orthographic projection of the fifth via hole on the substrate and the sub power line The orthographic projection on the substrate does not have overlapping areas.
  • the orthographic projection of the fifth via on the substrate and the virtual extension line of the first power portion in the sub-power line in the direction in which the data line extends are on the substrate.
  • the orthographic projection of has overlapping areas.
  • an eighth via is provided on the first insulating layer, the second insulating layer, and the third insulating layer, and the eighth via is configured to enable the data line to write data signals to The semiconductor layer; the orthographic projection of the eighth via on the substrate and the orthographic projection of the first power supply portion and the second power supply portion on the substrate in the sub-power line do not have an overlapping area.
  • the orthographic projection of the eighth via on the substrate and the virtual extension line of the third power portion in the sub-power line in the direction in which the data line extends are on the substrate.
  • the orthographic projection of has overlapping areas.
  • the power line is provided on the third conductive layer or the fourth conductive layer, and the power line and the data line are provided on the same layer.
  • the power line is provided on the third conductive layer
  • the data line is provided on the fourth conductive layer
  • the data line is provided on the third conductive layer
  • the The power supply line is arranged on the fourth conductive layer.
  • the display substrate further includes a first connecting portion, and the second electrode of the storage capacitor in the at least one sub-pixel and the second electrode of the storage capacitor in the sub-pixel adjacent to the extension direction of the gate line pass through the first connection part.
  • the connecting parts are connected to each other.
  • the second electrode of the storage capacitor in the second sub-pixel is directly connected to the second electrode of the storage capacitor in the third sub-pixel, and the second electrode of the storage capacitor in the third sub-pixel is connected to the second electrode of the storage capacitor in the fourth sub-pixel.
  • the second electrodes are connected to each other through the first connecting portion; the second electrode of the storage capacitor in the first sub-pixel in the other row is directly connected to the second electrode of the storage capacitor in the second sub-pixel, and the second electrode of the storage capacitor in the second sub-pixel is directly connected.
  • the second electrode and the second electrode of the storage capacitor in the third sub-pixel are connected to each other through the first connection portion, and the second electrode of the storage capacitor in the third sub-pixel is directly connected to the second electrode of the storage capacitor in the fourth sub-pixel .
  • the semiconductor layer in the first sub-pixel is spaced apart from the semiconductor layer in the second sub-pixel
  • the semiconductor layer in the second sub-pixel is spaced apart from the semiconductor layer in the third sub-pixel
  • the semiconductor layer in the third sub-pixel is spaced apart. It is arranged spaced apart from the semiconductor layer in the fourth sub-pixel.
  • the third conductive layer includes the first pole of the fifth transistor; the first pole of the fifth transistor in the first sub-pixel and the first pole of the fifth transistor in the second sub-pixel are spaced apart, The first pole of the fifth transistor in the second subpixel is spaced apart from the first pole of the fifth transistor in the third subpixel. The first pole of the fifth transistor in the third subpixel is opposite to that of the fifth transistor in the fourth subpixel. The first pole is set at intervals.
  • the second electrode of the storage capacitor in the second sub-pixel is disconnected from the second electrode of the storage capacitor in the third sub-pixel, and the second electrode of the storage capacitor in the third sub-pixel is connected to the storage capacitor in the fourth sub-pixel.
  • the second electrode of the storage capacitor in the first sub-pixel of the other row is disconnected from the second electrode of the storage capacitor in the second sub-pixel, and the second electrode of the storage capacitor in the second sub-pixel is connected to each other through the first connecting portion.
  • the second electrode of the capacitor and the second electrode of the storage capacitor in the third sub-pixel are connected to each other through the first connecting portion, and the second electrode of the storage capacitor in the third sub-pixel is connected to the second electrode of the storage capacitor in the fourth sub-pixel. Disconnect settings.
  • the third conductive layer includes the first electrode of the fifth transistor and the second connection part; the first electrode of the fifth transistor in the first sub-pixel of a row and the fifth transistor in the second sub-pixel
  • the first pole of the fifth transistor in the second sub-pixel and the first pole of the fifth transistor in the third sub-pixel are connected to each other through the second connecting portion, and the fifth transistor in the third sub-pixel is connected to each other.
  • the first pole of the transistor is disconnected from the first pole of the fifth transistor in the fourth sub-pixel; the first pole of the fifth transistor in the first sub-pixel and the first pole of the fifth transistor in the second sub-pixel in the other row
  • the first pole of the fifth transistor in the second sub-pixel is disconnected from the first pole of the fifth transistor in the third sub-pixel, and the first pole of the fifth transistor in the third sub-pixel is disconnected.
  • the electrode and the first electrode of the fifth transistor in the fourth sub-pixel are connected to each other through the second connection portion.
  • the power supply line in the extending direction of the gate line, is connected to each other through the second electrode of the storage capacitor and the first electrode of the fifth transistor.
  • a first via hole exposing the first electrode of the fifth transistor is provided on the fourth insulating layer, and a first via hole exposing the storage capacitor is provided on the third insulating layer.
  • a second via hole with two electrodes, the power line is connected to the first pole of the fifth transistor through the first via hole, and the first pole of the fifth transistor is connected to the first pole of the fifth transistor through the second via hole.
  • the second electrode of the storage capacitor is connected.
  • the number of the first via is one
  • the number of the second via is multiple
  • a plurality of second vias are arranged along the extending direction of the data line
  • the orthographic projection of the power line on the substrate includes the orthographic projection of the first via on the substrate
  • the orthographic projection of the first electrode of the fifth transistor on the substrate includes the second via on the substrate Orthographic projection.
  • the semiconductor layer includes a third connecting portion; the semiconductor layer in the first sub-pixel of a row is disconnected from the semiconductor layer in the second sub-pixel, and the semiconductor layer in the second sub-pixel is connected to the third sub-pixel.
  • the middle semiconductor layer is connected to each other through the third connecting portion, the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; the semiconductor layer in the first sub-pixel and the semiconductor layer in the second sub-pixel in the other row Connected to each other through the third connecting portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel and the semiconductor layer in the fourth sub-pixel are connected through the third connection Departments are connected to each other.
  • the power supply line in the extending direction of the gate line, is connected to each other through the third connection portion of the semiconductor layer and the second electrode of the storage capacitor.
  • the third insulating layer is provided with an eleventh via hole exposing the second electrode of the storage capacitor, and the first insulating layer, the second insulating layer, and the third insulating layer are provided with an eleventh via hole exposing the second electrode of the storage capacitor.
  • a twelfth via hole exposing the third connection portion of the semiconductor layer is provided, the power line is connected to the second electrode of the storage capacitor through the eleventh via hole, and the power line passes through the The twelfth via is connected to the third connection portion of the semiconductor layer.
  • the number of the eleventh via is one, the number of the twelfth via is multiple, and the plurality of twelfth vias are along the data line
  • the extension direction is arranged; the orthographic projection of the power cord on the substrate includes the orthographic projection of the eleventh via and the twelfth via on the substrate.
  • the plurality of transistors include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; in at least one sub-pixel, the semiconductor
  • the layer includes at least the first active area where the first transistor is located, the second active area where the second transistor is located, the third active area where the third transistor is located, and the fourth active area where the fourth transistor is located.
  • the third active area, the fourth active area, the fifth active area, the sixth active area and the seventh active area are integrated structure.
  • the distance between the second active region and the first active region in the extending direction of the gate line is smaller than the distance between the second active region and the seventh active region in the extending direction of the gate line. distance.
  • the seventh active area and the first active area are sequentially arranged along the direction from the data line for writing the data signal to the power supply line.
  • At least one sub-pixel includes a first area, a second area, and a third area that are sequentially arranged along the extending direction of the data line; the first active area and the seventh active area are arranged in the first active area.
  • the second active area and the fourth active area are arranged on the side close to the second area in the first area; the third active area is arranged on the side of the first area away from the second area.
  • the fifth active area and the sixth active area are arranged in the third area.
  • the first electrode of the first transistor is connected to the initial signal line
  • the second electrode of the first transistor T1 is connected to the first electrode of the storage capacitor
  • the first electrode of the second transistor is connected to the first electrode of the storage capacitor. Is connected to the first electrode of the storage capacitor, the second electrode of the second transistor is connected to the second electrode of the sixth transistor, the first electrode of the third transistor is connected to the second electrode of the fourth transistor, and the first electrode of the third transistor is connected to the second electrode of the fourth transistor.
  • the second electrode of the three transistor is connected to the second electrode of the sixth transistor, the first electrode of the fourth transistor is connected to the data line, the first electrode of the fifth transistor is connected to the power line, and the The second electrode is connected to the first electrode of the third transistor, the second electrode of the sixth transistor is connected to the anode of the light emitting device, the first electrode of the seventh transistor is connected to the initial signal line, and the The second electrode is connected to the anode of the light emitting device; the first active area is connected to the second active area and the seventh active area, respectively, and the second active area is connected to the third active area and the sixth active area, respectively.
  • the source area is connected, and the fourth active area is connected to the third active area and the fifth active area respectively.
  • the semiconductor layers of adjacent sub-pixels are in a symmetrical relationship with each other.
  • the shape of the semiconductor layer in the first sub-pixel of one row is the same as the shape of the semiconductor layer in the second sub-pixel of another row, and the shape of the semiconductor layer in the second sub-pixel of a row
  • the shape of the semiconductor layer is the same as the shape of the semiconductor layer in the first sub-pixel in another row.
  • the semiconductor layer includes a third connecting portion, and the semiconductor layer in at least one sub-pixel is connected to the semiconductor layer in the adjacent sub-pixel in the extending direction of the gate line through the third connecting portion.
  • the third connection part is connected to the active region of the fifth transistor.
  • the first insulating layer, the second insulating layer, and the third insulating layer are provided with a twelfth via hole exposing the third connection part, and the power line passes through the tenth The two via holes are connected with the third connecting portion.
  • the semiconductor layers in the sub-pixels are connected to each other through the third connecting portion, and the semiconductor layer in the third sub-pixel is disconnected from the semiconductor layer in the fourth sub-pixel; the semiconductor layer in the first sub-pixel and the second sub-pixel in the other row
  • the semiconductor layers are connected to each other through the third connecting portion, the semiconductor layer in the second sub-pixel is disconnected from the semiconductor layer in the third sub-pixel, and the semiconductor layer in the third sub-pixel and the semiconductor layer in the fourth sub-pixel pass through the first
  • the three connecting parts are connected to each other.
  • the data line includes a plurality of sub-data lines connected in sequence; there is at least one sub-pixel, and the sub-pixel and the gate line extend in the direction Two sub-data lines are arranged between adjacent sub-pixels.
  • the two sub-data lines are parallel to each other.
  • the first insulating layer, the second insulating layer, and the third insulating layer are provided with an eighth via hole exposing the semiconductor layer
  • the fourth insulating layer is provided with There is a third via hole exposing the first electrode of the fourth transistor
  • the data line is connected to the first electrode of the fourth transistor through the third via hole
  • the first electrode of the fourth transistor passes through the first electrode.
  • Eight vias are connected to the semiconductor layer.
  • the eighth vias of adjacent sub-pixels are in a symmetrical relationship with each other.
  • the data line is provided with the third conductor layer
  • the power line is provided with the third conductor layer
  • the data line is provided on the fourth conductor layer
  • the power line is provided on the third conductor layer or the fourth conductor layer.
  • the data line in at least one column of sub-pixels, includes a first sub-data line and a second sub-data line, and the first sub-data line and the second sub-data line are respectively located on two sub-pixels of the column. side.
  • the power supply line is located between the first sub-data line and the second sub-data line.
  • the pixel structures of adjacent sub-pixels are in a symmetrical relationship with each other.
  • the pixel structure in the first sub-pixel of one row is the same as the pixel structure in the second sub-pixel of another row, and the pixel structure in the second sub-pixel of a row
  • the pixel structure is the same as that of the first sub-pixel in the other row.
  • the display substrate further includes a reset signal line, a light emission control line, and an initial signal line;
  • the semiconductor layer includes at least an active region of a plurality of transistors, and the first conductor layer includes at least gate lines, The light-emitting control line, the reset signal line, the first electrode of the storage capacitor, and the gate electrode of a plurality of transistors,
  • the second conductor layer includes at least the initial signal line and the second electrode of the storage capacitor;
  • the third conductor layer at least includes more Source and drain electrodes of each transistor, the fourth conductor layer includes at least a data line and a power line.
  • At least one sub-pixel includes a first area, a second area, and a third area that are sequentially arranged along the extension direction of the data line; the gate line, the initial signal line, and the reset signal line are located in the first area. Area, the first electrode and the second electrode of the storage capacitor are located in the second area, and the light-emitting control line is located in the third area.
  • the second conductor layer further includes a shielding electrode, and in at least one sub-pixel, there is an overlap area between the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the power line on the substrate.
  • the power line is connected to the shield electrode through a via hole.
  • the shield electrode in the extending direction of the data line, is disposed between the gate line and the reset signal line.
  • the shield electrode includes a first portion extending along the extending direction of the gate line and a second portion extending along the extending direction of the data line. The ends of the parts close to the first part are connected to each other.
  • the first conductor layer further includes a gate block extending along the extension direction of the data line, the gate block is connected to the gate line; in the extension direction of the data line, the gate block is connected to the The second part of the shield electrode has a facing area.
  • the source and drain electrodes of the plurality of transistors include the first electrode of the second transistor, and the second insulating layer and the third insulating layer are provided with the first electrode exposing the storage capacitor.
  • a seventh via hole, the first insulating layer, the second insulating layer and the third insulating layer are provided with a ninth via hole exposing the active region of the second transistor, and one end of the first electrode of the second transistor It is connected to the first electrode of the storage capacitor through the seventh via hole, and the other end is connected to the active area of the second transistor through the ninth via hole.
  • the orthographic projection of the first electrode of the second transistor on the substrate there is an overlap area between the orthographic projection of the first electrode of the second transistor on the substrate and the orthographic projection of the gate line on the substrate, and the first electrode of the second transistor is on the substrate. There is no overlap area between the orthographic projection and the orthographic projection of the light-emitting control line, the reset signal line, and the initial signal line on the substrate.
  • the source and drain electrodes of the plurality of transistors include the first electrode of the first transistor, the third insulating layer is provided with a sixth via hole exposing the initial signal line, and the first insulating layer A tenth via hole exposing the active region of the first transistor is provided on the second insulating layer, the second insulating layer, and the third insulating layer.
  • One end of the first electrode of the first transistor is connected to the initial signal through the sixth via hole. Wire connection, and the other end is connected to the active area of the first transistor through the tenth via.
  • the display substrate further includes a fifth insulating layer disposed on the fourth conductive layer and a fifth conductive layer disposed on the fifth insulating layer; in the fourth conductive layer It also includes a connection electrode, the source and drain electrodes of the plurality of transistors include the second electrode of the sixth transistor; the fourth insulating layer is provided with a fourth via hole exposing the second electrode of the sixth transistor, and the fifth A fifth via hole exposing the connection electrode is provided on the insulating layer, the connection electrode is connected to the second electrode of the sixth transistor through the fourth via hole, and the fifth conductor layer is connected to the connection electrode through the fifth via hole. connection.
  • At least one sub-pixel includes at least: a first via hole exposing the first electrode of the fifth transistor, and the first via hole is configured to connect the first electrode of the fifth transistor to the power supply line. Connection; a second via hole exposing the second electrode of the storage capacitor, the second via hole is configured to connect the second electrode with the first electrode of the fifth transistor; exposing the third electrode of the fourth transistor Via, the third via is configured to connect the first pole of the fourth transistor to the data line; the fourth via exposing the second pole of the sixth transistor, the fourth via is configured to The second electrode of the sixth transistor is connected to the connection electrode; the fifth via hole of the connection electrode is exposed, and the fifth via hole is configured to connect the connection electrode to the anode of the fifth conductor layer; A via hole, the sixth via hole is configured to connect the initial signal line to the first electrode of the first transistor; a seventh via hole that exposes the first electrode of the storage capacitor, and the seventh via hole is configured to connect the first electrode The electrode is connected to the first electrode of the second transistor;
  • At least one sub-pixel includes at least: an eleventh via hole exposing the second electrode of the storage capacitor, and the eleventh via hole is configured to connect the second electrode with the power line;
  • the twelfth via hole of the three connecting portion, and the twelfth via hole is configured to connect the third connecting portion with the power line.
  • the display device includes the aforementioned display substrate.
  • a method for manufacturing a display substrate configured to manufacture the display substrate according to any one of claims 1 to 69, in a plane parallel to the display substrate, the display substrate includes gate lines and data lines arranged on a base , A power supply line and a plurality of sub-pixels, at least one sub-pixel includes a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light, the driving circuit including a plurality of transistors and storage capacitors; the manufacturing method includes:
  • a plurality of functional layers are formed on the substrate; the plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence; among the plurality of functional layers A first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer are respectively arranged between them; in the extending direction of the gate lines, the power lines are connected to each other through at least one functional layer.
  • FIG. 1 is a schematic diagram of the structure of a display substrate provided by the present disclosure
  • FIG. 2 is a side view of a sub-pixel in a display substrate provided by the present disclosure
  • FIG. 3 is a top view of a sub-pixel in a display substrate provided by the present disclosure.
  • FIG. 4A is an equivalent circuit diagram of the driving circuit provided by the present disclosure.
  • FIG. 4B is a working timing diagram of the driving circuit provided by the present disclosure.
  • FIG. 5 is a top view of a plurality of sub-pixels in a display substrate provided by the present disclosure
  • FIG. 6A is a top view of the sub-pixel corresponding to the first embodiment
  • 6B is another top view of the sub-pixel corresponding to the first embodiment
  • FIG. 7A is a top view of the second metal layer corresponding to the first embodiment
  • FIG. 7B is a top view of the third metal layer corresponding to the first embodiment
  • FIG. 8A is a top view of the sub-pixel corresponding to the second embodiment
  • FIG. 8B is another top view of the sub-pixel corresponding to the second embodiment
  • 9A is a top view of the second metal layer corresponding to the second embodiment.
  • 9B is a top view of the third metal layer corresponding to the second embodiment.
  • FIG. 10 is another top view of a plurality of sub-pixels in a display substrate provided by the present disclosure.
  • FIG. 11 is a flowchart of a manufacturing method of a display substrate provided by the present disclosure.
  • FIG. 12 is a schematic diagram of the first fabrication of a display substrate provided by the present disclosure.
  • FIG. 13 is a schematic diagram of a second manufacturing method of a display substrate provided by the present disclosure.
  • FIG. 14A is a schematic diagram of a third fabrication of a display substrate provided by the present disclosure.
  • 14B is another schematic diagram of another third fabrication of a display substrate provided by the present disclosure.
  • FIG. 15A is a fourth schematic diagram of manufacturing a display substrate provided by the present disclosure.
  • 15B is another fourth schematic diagram of manufacturing a display substrate provided by the present disclosure.
  • FIG. 16A is a fifth schematic diagram of manufacturing a display substrate provided by the present disclosure.
  • FIG. 16B is another fifth schematic diagram of manufacturing a display substrate provided by the present disclosure.
  • FIG. 17 is a top view of a plurality of sub-pixels in another display substrate provided by the present disclosure.
  • FIG. 19 is a partial top view of a sub-pixel in another display substrate provided by the present disclosure.
  • 20 is a top view of another part of sub-pixels in another display substrate provided by the present disclosure.
  • FIG. 21 is a top view of another part of sub-pixels in another display substrate provided by the present disclosure.
  • FIG. 22 is a flowchart of another method for manufacturing a display substrate provided by the present disclosure.
  • FIG. 23 is a schematic diagram of manufacturing an active region of another display substrate provided by the present disclosure.
  • FIG. 24 is a schematic diagram of manufacturing the first insulating layer and the first metal layer of another display substrate provided by the present disclosure.
  • FIG. 25 is a schematic diagram of manufacturing a second insulating layer and a second metal layer of another display substrate provided by the present disclosure
  • FIG. 26 is a schematic diagram of manufacturing a third insulating layer of another display substrate provided by the present disclosure.
  • the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique invention solution defined by the claims.
  • Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution defined by the claims. Therefore, it should be understood that any of the features shown and/or discussed in this disclosure can be implemented individually or in any suitable combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
  • various modifications and changes can be made within the protection scope of the appended claims.
  • the specification may have presented the method and/or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method and/or process should not be limited to performing their steps in the written order, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the present disclosure.
  • the display substrate In a plane parallel to the display substrate, the display substrate includes a gate line, a data line, a power supply line, and a plurality of sub-pixels provided on a base, at least one sub-pixel includes a light-emitting device And a drive circuit configured to drive the light emitting device to emit light, the drive circuit including a plurality of transistors and storage capacitors; in a plane perpendicular to the display substrate, the display substrate includes a base and a plurality of Functional layer; the plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence; a first insulating layer is respectively arranged between the plurality of functional layers Layer, the second insulating layer, the third insulating layer and the fourth insulating layer; in the extending direction of the gate lines, the power lines are connected to each other through at least one functional layer.
  • the display substrate includes a gate line, a data line,
  • FIG. 1 is a schematic structural diagram of a display substrate provided by the present disclosure
  • FIG. 2 is a side view of a sub-pixel in a display substrate provided by the present disclosure
  • FIG. 3 is a top view of a sub-pixel in a display substrate provided by the present disclosure.
  • the display substrate provided by the present disclosure is provided with a gate line G, a data line D, a power line VDD, a reset signal line Reset, a light-emitting control line EM, and an initial signal.
  • Each sub-pixel includes: a light-emitting device and a driving circuit configured to drive the light-emitting device to emit light.
  • the driving circuit includes: a plurality of transistors and storage capacitors.
  • the display substrate includes: The substrate 10 and the semiconductor layer 20, the first metal layer 30, the second metal layer 40, the third metal layer 50, the fourth metal layer 60 and the fifth metal layer 70 which are arranged on the substrate 10 and insulated from each other, the first metal The layer 30 serves as the first conductive layer, the second metal layer 40 serves as the second conductive layer, the third metal layer 50 serves as the third conductive layer, the fourth metal layer 60 serves as the fourth conductive layer, and the fifth metal layer 70 serves as the fifth conductive layer.
  • the display substrate includes: The substrate 10 and the semiconductor layer 20, the first metal layer 30, the second metal layer 40, the third metal layer 50, the fourth metal layer 60 and the fifth metal layer 70 which are arranged on the substrate 10 and insulated from each other, the first metal The layer 30 serves as the first conductive layer, the second metal layer 40 serves as the second conductive layer, the third metal layer 50 serves as the third conductive layer, the fourth metal layer 60 serves as the fourth conductive layer, and
  • the display substrate includes a display area (AA) and a frame area located at the periphery of the display area, the display area includes a plurality of display sub-pixels, and the frame area includes a plurality of dummy sub-pixels. Pixels refer to display sub-pixels in the display area.
  • the semiconductor layer 20 may include active regions of a plurality of transistors, and the first metal layer 30 may include a gate line G, an emission control line EM, a reset signal line Reset, a first electrode C1 of a storage capacitor, and a plurality of transistors.
  • the second metal layer 40 may include the initial signal line Vinit and the second electrode C2 of the storage capacitor;
  • the third metal layer 50 may include the first and second electrodes of a plurality of transistors, and the fourth metal layer 60
  • the data line D and the power supply line VDD may be included, and the fifth metal layer 70 may include the anode of the light emitting device.
  • the data line in the extending direction of the data line, may include a plurality of sub-data lines connected in sequence, and the plurality of sub-data lines correspond to the plurality of sub-pixels. There is at least one sub-pixel, and two sub-data lines are arranged between the sub-pixel and the adjacent sub-pixel in the extending direction of the gate line. In an exemplary embodiment, the two sub-data lines are parallel to each other.
  • the display substrate may be provided with M rows * N columns of sub-pixels, N columns of data lines D1 to DN, N columns of power lines VDD1 to VDDN, M rows of gate lines G1 to GM, M-1 row of light-emitting control lines EM1 to EMM-1, reset signal line Reset, and initial signal line Vinit.
  • the display substrate may further include: a data driver configured to provide data signals to the data lines, and a data driver configured to provide scan signals to the gate lines.
  • a scan driver configured to provide a light-emitting control signal to the light-emitting control line
  • a timing controller configured to provide a driving signal to the data driver, the scan driver, and the light-emitting driver.
  • the driving circuit in the i-th column of sub-pixels is connected to the i-th column of data lines, and each column of data lines includes a first sub-data line DO and a second sub-data line DE;
  • the first sub-data line DOi and the second sub-data line DEi in the i-th column of data lines are respectively located on both sides of the i-th column of sub-pixels, 1 ⁇ i ⁇ N, and N is the total number of sub-pixels.
  • two sub-data lines are arranged between two adjacent columns of sub-pixels, that is, between two adjacent columns of sub-pixels, the first sub-data line DO of the sub-pixel of the current column and the sub-data line DO of the adjacent column of sub-pixels are arranged.
  • the second sub-data line DE, or the second sub-data line DE of the sub-pixel of the current column and the first sub-data line DO of the sub-pixel of the adjacent column are arranged between two adjacent columns of sub-pixels.
  • the first sub-data line Doi of the data line in the i-th column is located on the side of the sub-pixel in the i-th column close to the sub-pixel in the i+1-th column, and the first sub-data line DOi+1 of the data line in the i+1-th column is located in the i+th column.
  • One column of sub-pixels is close to the side of the i-th column of sub-pixels; or, the second sub-data line DEi of the i-th column of data lines is located on the side of the i-th column of sub-pixels close to the i+1-th column of sub-pixels.
  • the second sub-data line DEi+1 is located on the side of the i+1-th column of sub-pixels close to the i-th column of sub-pixels.
  • the base 10 may be a rigid substrate or a flexible substrate.
  • the rigid substrate can be, but is not limited to, one or more of glass and metal sheet;
  • the flexible substrate can be, but is not limited to, polyethylene terephthalate, ethylene terephthalate, polyether One or more of ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.
  • the semiconductor layer 20 may be made of polysilicon or metal oxide, which is not limited in the present disclosure.
  • the material of the first metal layer can be metal materials such as silver, aluminum, or copper, which are not limited in this disclosure.
  • the material of the second metal layer may be a metal material such as silver, aluminum, or copper, which is not limited in the present disclosure.
  • the third metal layer may be made of metal materials such as silver, aluminum, or copper, which is not limited in the present disclosure
  • the fourth metal layer may be made of metal materials such as silver, aluminum, or copper, which is not limited in the present disclosure.
  • the fifth metal layer may be made of metal materials such as silver, aluminum, or copper, which is not limited in the present disclosure.
  • FIG. 4A is an equivalent circuit diagram of the driving circuit provided by the present disclosure
  • FIG. 4B is a working timing diagram of the driving circuit provided by the present disclosure, as shown in FIGS. 4A and 4B.
  • the driving circuit included in the column sub-pixels is described as an example.
  • the driving circuit provided in the present disclosure may have a 7T1C structure.
  • the driving circuit may include: a first transistor T1 to a seventh transistor T7 and a storage capacitor C, where the storage capacitor C includes the first The electrode C1 and the second electrode C2.
  • the gate electrode of the first transistor T1 is connected to the reset signal line Reset, the first electrode of the first transistor T1 is connected to the initial signal line Vinit, and the second electrode of the first transistor T1 is connected to the storage capacitor.
  • the first electrode C1 of C is connected, the gate electrode of the second transistor T2 is connected to the gate line G, the first electrode of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C, and the second electrode of the second transistor T2 is connected to the first electrode C1 of the storage capacitor C.
  • the second electrode of the six transistor T6 is connected, the gate electrode of the third transistor T3 is connected to the first electrode C1 of the storage capacitor C, the first electrode of the third transistor T3 is connected to the second electrode of the fourth transistor T4, and the third transistor T3
  • the second electrode of the fourth transistor T4 is connected to the second electrode of the sixth transistor T6, the gate electrode of the fourth transistor T4 is connected to the gate line G, the first electrode of the fourth transistor T4 is connected to the data line D, and the gate electrode of the fifth transistor T5 is connected to The emission control line EM is connected, the first pole of the fifth transistor T5 is connected to the power line VDD, the second pole of the fifth transistor T5 is connected to the first pole of the third transistor T3, and the gate electrode of the sixth transistor T6 is connected to the emission control line EM connection, the second electrode of the sixth transistor T6 is connected to the anode of the light emitting device, the gate electrode of the seventh transistor T7 is connected to the reset signal line Reset, the first electrode of the seventh transistor T7 is connected
  • the third transistor T3 is a driving transistor, all transistors except the third transistor T3 are switching transistors, and the first transistor T1 to the seventh transistor T7 may all be P-type transistors or N-type transistors, This disclosure does not make any limitation on this.
  • the working process of the driving circuit may include:
  • the reset signal line Reset provides an effective level
  • the first transistor T1 and the seventh transistor T7 are turned on
  • the initial signal provided by the initial signal line Vinit affects the signal of the second pole of the sixth transistor T6 and the second pole of the sixth transistor T6.
  • the signal of one electrode C1 is initialized.
  • the gate line G provides an effective level
  • the second transistor T2 and the fourth transistor T4 are turned on
  • the data signal provided by the data line D is written to the first pole of the third transistor T3, and makes The gate electrode of the second transistor T2 and the signal of the second electrode have the same potential, so that the third transistor T3 is turned on.
  • the light-emitting control line EM provides an effective level
  • the fifth transistor T5 and the sixth transistor T6 are turned on
  • the power line VDD provides a driving current to the light-emitting device OLED to drive the light-emitting device to emit light.
  • the light-emitting device in the present disclosure may be an OLED.
  • the display substrate provided by the present disclosure is provided with gate lines, data lines, power lines, reset signal lines, light emission control lines, initial signal lines, and a plurality of sub-pixels.
  • Each sub-pixel includes: a light-emitting device and a driver configured to drive the light-emitting device to emit light.
  • the circuit and the driving circuit may include: a plurality of transistors and storage capacitors; the display substrate may include: a substrate and a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a semiconductor layer that are sequentially arranged on the substrate and insulated from each other.
  • the fourth metal layer and the fifth metal layer; the semiconductor layer includes: active regions of a plurality of transistors, the first metal layer includes: gate lines, light-emitting control lines, reset signal lines, first electrodes of storage capacitors, and a plurality of transistors
  • the gate electrode, the second metal layer includes: the initial signal line and the second electrode of the storage capacitor;
  • the third metal layer includes: the source and drain electrodes of a plurality of transistors,
  • the fourth metal layer includes: data lines and power lines,
  • the fifth metal layer Including: the anode of the light emitting device, the i-th column of sub-pixels are connected to the i-th column of data lines, each column of data lines includes: a first sub-data line and a second sub-data line; the first sub-data line in the i-th column of data lines and
  • the second sub-data lines are respectively located on both sides of the i-th column of sub-pixels, 1 ⁇ i ⁇ N, and N is the total number of sub-pixels.
  • the present disclosure is provided with five metal layers. By arranging the data lines and power lines and the source and drain electrodes of multiple transistors in different layers, the volume occupied by the sub-pixels and the data lines connected to the sub-pixels can be reduced, thereby increasing the high frequency. The resolution of the driven OLED display substrate.
  • each sub-pixel in the display substrate provided by the present disclosure may be divided into a first region R1, a second region R2, and a third region that are sequentially arranged along the extending direction of the data line. R3.
  • the storage capacitor is located in the second region R2, the first region R1 and the third region R3 are respectively located on both sides of the second region R2, the initial signal line Vinit, the gate line G, and the reset signal line Reset connected to the sub-pixel drive circuit are located in the first region.
  • the light emission control line EM connected to the driving circuit of the sub-pixel is located in the third region R3.
  • the driving circuits of adjacent sub-pixels in the same column are connected to different sub-data lines, that is, if the sub-pixels in the i-th row and j-th column are connected to the first sub-data line DOj in the j-th column data line, then the i+1-th row
  • the sub-pixels in column j are connected to the second sub-data line Dej in the j-th column data line; if the sub-pixels in the i-th row and j-th column are connected to the second sub-data line DEj in the j-th column data line, then the i+1
  • the sub-pixels in the j-th column are connected to the first sub-data line DOj in the data line in the j-th column.
  • the driving circuit of the sub-pixel in the i-th column is also connected to the power line of the i-th column, and 1 ⁇ i ⁇ N.
  • the power line VDDi of the i-th column is located between the first sub-data line DOi and the second sub-data line DEi in the data line of the i-th column.
  • FIG. 5 is a top view of a plurality of sub-pixels in a display substrate provided by the present disclosure.
  • the pixel structure of adjacent sub-pixels in the same row is about the center of two sub-data lines between adjacent sub-pixels.
  • the lines CL are mirrored and symmetrical to each other.
  • the pixel structure of the sub-pixel located in the i-th row and the j-th column is the same as the pixel structure of the sub-pixel located in the i-th row and the j+2 column.
  • the pixel structure of the sub-pixel located in the i-th row and column j+1 is the same as that of the sub-pixel in the i-th row and column j+1.
  • the pixel structure of the sub-pixel in row j+3 column is the same.
  • the pixel structure of the sub-pixel in row i and column j is the same as the pixel structure of sub-pixel in row i+1 and column j+1.
  • the pixel structure of the sub-pixel in the j+1-th row and the j-th column is the same as that of the sub-pixel in the i+1-th row and j-th column.
  • the same pixel structure includes, but is not limited to, the same overall shape of the two, the connection relationship of each part, and the trend of signal flow.
  • two adjacent columns of power supply lines are mirror-symmetrical about the center line between two adjacent columns of power supply lines, that is, the power lines of adjacent sub-pixels are in a symmetrical relationship with each other.
  • the center line CL of the two sub-data lines between the sub-pixels in the i-th row and the j-th column and the i-th row and j+1-th column sub-pixels and the center line between the power line in the j-th column and the power line in the j+1-th column may be It is the same centerline.
  • the power line in the i-th column includes: a plurality of sub-power sources connected to each other The lines are respectively S1 to SN.
  • the multiple sub-power supply lines correspond to all the sub-pixels in each column of sub-pixels one-to-one, and the multiple sub-power supply lines are respectively arranged in the multiple sub-pixels in the column.
  • the shape of the sub-power supply line corresponding to the sub-pixel in the i-th row and the j-th column is mirrored along the center line of the first sub-data line and the second sub-data line in the j-th column of the data line.
  • the shapes of the sub-power supply lines corresponding to the sub-pixels in the i+1 row and the j-th column are the same.
  • the same shape of the power cord includes but is not limited to the same overall shape of the two, the connection relationship of each part, and the trend of the signal flow.
  • each sub power supply line may include a first power supply part SS1, a second power supply part SS2, and a third power supply part SS3 that are sequentially arranged along the second direction, and the second power supply part SS2 is configured to be connected to the first power supply part.
  • SS1 and the third power supply portion SS3, the first power supply portion SS1 and the third power supply portion SS3 may be arranged in parallel with the data line, the angle between the second power supply portion SS2 and the first power supply portion SS1 is greater than 90 degrees and less than 180 degrees, A broken line-shaped sub power line is formed, and the second direction is the extension direction of the data line.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore also includes a state where an angle of 85° or more and 95° or less is included.
  • the first power supply unit is parallel to the data line, which means that the main body of the first power supply unit is parallel to the main body of the data line. It does not limit the edge of the first power supply unit to be parallel to the edge of the data line.
  • connection area where the first power supply unit and the second power supply unit are connected to each other, the connection area may belong to the first power supply unit, or the connection area may belong to the second power supply unit.
  • the first power supply part SS1, the second power supply part SS2, and the third power supply part SS3 may be an integral structure.
  • the length of the first power supply portion SS1 extending in the second direction is greater than the average width of the first power supply portion SS1
  • the length of the second power supply portion SS2 extending along the oblique direction is greater than the average width of the second power supply portion SS2
  • the length of the third power supply portion SS3 extending along the second direction is greater than the average width of the third power supply portion SS3.
  • the inclination direction is the direction in which the included angle exists between the second power supply part and the first power supply part.
  • the average width of the third power supply portion SS3 is smaller than the average width of the first power supply portion SS1. On the one hand, it is for the layout of the pixel structure.
  • the average width of the second The three power supply part SS3 can reduce the parasitic capacitance.
  • the width of the first power supply part SS1 and the third power supply part SS3 refers to the size of the first power supply part SS1 and the third power supply part SS3 in the first direction
  • the width of the second power supply part SS2 refers to the dimension perpendicular to the oblique direction
  • the size and the average width refer to the average of the widths of multiple locations, and the first direction is the direction in which the gate lines extend.
  • the distance between the center line of the first power supply part SS1 and the center line of the third power supply part SS3 is equivalent to the average width of the third power supply part SS3.
  • the first power supply part SS1 in the sub-power supply line corresponding to the sub-pixel in the i-th row and the j-th column corresponds to the third power supply line in the sub-power supply line corresponding to the sub-pixel in the i-1th row and the jth column.
  • the power supply part SS3 is connected, and the third power supply part SS3 in the sub power supply line corresponding to the sub-pixel in the i-th row and j-th column is connected to the first power supply part in the sub-power supply line corresponding to the sub-pixel in the i+1-th row and j-th column
  • the SS1 is connected, and the mutually connected power supply units are sequentially arranged along the second direction (the direction in which the data line extends).
  • the power cord in the present disclosure may be in the shape of a broken line.
  • the working process of each sub-pixel includes: in the reset phase, the reset signal line Reset located in the first metal layer and the initial signal line Vinit located in the second metal layer provide signals to the driving circuit Perform initialization.
  • the gate line G located in the first metal layer and the data line D located in the fourth metal layer provide signals, and the data signal provided by the data line D is written to the drive circuit;
  • the light-emitting control line EM located in the first metal layer provides a signal
  • the power line VDD provides a power signal, so that the driving circuit provides a driving current to the light-emitting device OLED to drive the light-emitting device to emit light.
  • the pixels of the same row are displayed at the same time, and the pixels of adjacent rows are displayed in sequence.
  • the display substrate provided by the present disclosure may further include: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14.
  • the first insulating layer 11 is disposed between the semiconductor layer 20 and the first metal layer 30, the second insulating layer 12 is disposed between the first metal layer 30 and the second metal layer 40, and the third insulating layer 13 is disposed on the second metal layer. Between the layer 40 and the third metal layer 50, the fourth insulating layer 14 is provided between the third metal layer 50 and the fourth metal layer 60.
  • the material of the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 may be silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. This disclosure does not make any limitation on this.
  • the plurality of transistors for each sub-pixel may include: a first transistor to a seventh transistor, and the first pole of the fifth transistor is connected to the power supply line VDD and the second transistor of the storage capacitor, respectively.
  • the electrode C2 is connected.
  • the power supply line in each sub-pixel is connected to the second electrode of the storage capacitor through the first electrode of the fifth transistor.
  • the second electrodes of the storage capacitors of adjacent sub-pixels located on the second metal layer can be multiplexed as power signal lines, configured to ensure that the power signals provided by the power lines of adjacent sub-pixels are the same, to avoid poor display of the display substrate, and to ensure display The display effect of the substrate.
  • every four consecutive sub-pixels constitute one pixel.
  • the four consecutive sub-pixels are the i-th sub-pixel, the i+1-th sub-pixel, and the i+th sub-pixel in order along the first direction. 2 sub-pixels and i+3th sub-pixels, where i can take a value of 4j-3 in turn, and j is a positive integer.
  • FIG. 6A is a top view of the sub-pixel corresponding to the first embodiment
  • FIG. 6B is Another top view of the sub-pixel corresponding to Embodiment 1, where, as shown in FIG. 6A, the fourth insulating layer is provided with a first via hole V1 exposing a part of the first electrode 51 of the fifth transistor, and the power line passes through the first via hole V1.
  • the hole V1 is connected to the first electrode 51 of the fifth transistor.
  • the third insulating layer is provided with a second via hole V2 exposing part of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor passes through the second via hole V2 and the second electrode of the storage capacitor. C2 connection.
  • FIG. 3 and FIG. 5 are described by taking the first embodiment as an example.
  • the orthographic projection of the power line connected to the sub-pixel on the substrate includes the orthographic projection of the first via hole V1 on the substrate 10
  • the orthographic projection of the second electrode of the storage capacitor on the substrate includes the orthographic projection of the second via on the substrate. projection.
  • the orthographic projection of A includes the orthographic projection of B
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the number of the first via V1 may be one.
  • the number of second via holes V2 may be at least one. Since the width of the first electrode of the fifth transistor is relatively narrow, when the number of second via holes V2 is multiple, multiple The second via holes are arranged along the extending direction of the data line, wherein the plurality of second via holes have via holes along the extending direction of the data line, and multiple via holes can be provided. The more the number of via holes, the more conductive the components connected through the via holes. The better the performance, FIG. 6A is a first via V1, and FIG. 6B is illustrated with two second vias V2 as an example, and the present disclosure does not make any limitation on this.
  • the fourth insulating layer further includes a third via hole V3 exposing the first electrode of the fourth transistor T4, and the data line passes through the third via hole V3 and the fourth transistor T4.
  • the first electrode of the fourth insulating layer further includes a fourth via hole V4 exposing the second electrode of the sixth transistor T6.
  • the first insulating layer, the second insulating layer, and the third insulating layer further include: via holes exposing part of the active region, so that the source and drain electrodes of the transistor pass through these via holes.
  • the source and drain electrodes of the transistor Connected to the active region, the source and drain electrodes of the transistor include the first electrode of the transistor and the second electrode of the transistor.
  • the first electrode of the fifth transistor is also connected to the active region through via holes on the first insulating layer, the second insulating layer, and the third insulating layer.
  • each pixel may include four sub-pixels.
  • FIG. 7A is a top view of the second metal layer corresponding to the first embodiment
  • FIG. 7B is a top view of the third metal layer corresponding to the first embodiment.
  • FIGS. 7A and 7B take two pixels arranged in the column direction as an example for description.
  • the second electrodes of the storage capacitors in the adjacent sub-pixels in the same row are directly connected.
  • the first electrodes 51 of the fifth transistors in the adjacent sub-pixels in the same row are spaced apart. .
  • the second electrodes of the storage capacitors arranged on the second metal layer through a plurality of sub-pixels are connected to each other to make the power signals provided by the power lines of adjacent sub-pixels the same, avoid display defects of the display substrate, and ensure display The display effect of the substrate.
  • the conductive layers of multiple sub-pixels can be connected to each other only through the semiconductor layer, or the conductive layers of multiple sub-pixels can be connected to each other through only the first metal layer, or The conductive layers of multiple sub-pixels can be connected to each other only through the second metal layer, or the conductive layers of multiple sub-pixels can be connected to each other only through the third metal layer, so as to realize the function of passing the power lines of the sub-pixels in the same row.
  • the layers are connected to each other in the extending direction of the gate line, which will not be repeated here.
  • At least one sub-pixel further includes a first connecting portion C3, and the first connecting portion C3 is disposed on one side of the second electrode C2 in the first direction.
  • the second electrode C2 of the i-th sub-pixel of one row of pixels is connected to the second electrode C2 of the i+1-th sub-pixel through the first connecting portion C3, and the i+1-th
  • the second electrode C2 of the subpixel is directly connected to the second electrode C2 of the i+2th subpixel, and the second electrode C2 of the i+2th subpixel and the second electrode C2 of the i+3th subpixel pass through the first connecting portion C3 connection.
  • the second electrode C2 of the i-th sub-pixel of another row of pixels is directly connected to the second electrode C2 of the i+1-th sub-pixel, and the second electrode C2 of the i+1-th sub-pixel is connected to the second electrode C2 of the i+2-th sub-pixel.
  • C2 is connected through the first connection portion C3, and the second electrode C2 of the i+2th sub-pixel is directly connected to the second electrode C2 of the i+3th sub-pixel.
  • FIG. 8A is a top view of the sub-pixel corresponding to the second embodiment
  • FIG. 8B is another top view of the sub-pixel corresponding to the second embodiment.
  • the fourth insulating layer is provided with a first via hole V1 exposing a part of the first pole 51 of the fifth transistor T5, and the power line is connected to the first pole 51 of the fifth transistor T5 through the first via hole V1.
  • the third insulating layer is provided with a second via hole V2 exposing part of the second electrode C2 of the storage capacitor, and the first electrode 51 of the fifth transistor T5 passes through the second via hole V2 and the second via hole V2 of the storage capacitor. The electrode C2 is connected.
  • the second embodiment is compared with the first embodiment in that the area occupied by the second electrode of the storage capacitor of each sub-pixel is different, and the first embodiment of the fifth transistor T5 of each sub-pixel is different.
  • the shape of the pole 51 is also different.
  • the fourth insulating layer further includes a third via hole V3 exposing the first electrode of the fourth transistor T4, and the data line passes through the third via hole V3 and the fourth transistor T4.
  • the first electrode of the fourth insulating layer further includes a fourth via hole V4 exposing the second electrode of the sixth transistor T6.
  • the first insulating layer, the second insulating layer, and the third insulating layer may further include via holes exposing a part of the active region, so that the source and drain electrodes of the transistor pass through the via holes and the active region. connection.
  • the first electrode of the fifth transistor may also be connected to the active area through the via holes on the first insulating layer, the second insulating layer and the third insulating layer.
  • the orthographic projection of the power line in the sub-pixel on the substrate includes the orthographic projection of the first via hole V1 on the substrate 10
  • the orthographic projection of the second electrode of the storage capacitor on the substrate includes the orthographic projection of the second via on the substrate. projection.
  • the number of the first via V1 may be one.
  • the number of the second via hole V2 is at least one. Since the width of the first electrode of the fifth transistor is relatively narrow, the plurality of second via holes are arranged along the extending direction of the data line. Ensure that the number of vias is set. The greater the number of vias, the better the conductivity of the components connected through the vias.
  • Figure 8A is a first via V1
  • Figure 8B is an example of two second vias V2. It is noted that the present disclosure does not make any limitation on this.
  • FIG. 9A is a top view of the second metal layer corresponding to the second embodiment
  • FIG. 9B is a top view of the third metal layer corresponding to the second embodiment
  • FIG. 10 is another top view of a plurality of sub-pixels in a display substrate provided by the present disclosure.
  • FIGS. 9A and 9B are illustrated with two pixels arranged in the column direction as an example.
  • FIG. 10 includes other layers except the anode of the light-emitting device, and FIG. 10 includes The multiple sub-pixels are the sub-pixels corresponding to the second embodiment.
  • the second electrode of the storage capacitor of the i-th sub-pixel and the second electrode of the storage capacitor of the i+1-th sub-pixel pass through the A connecting portion C3 is connected, the second electrode of the storage capacitor of the i+1th subpixel and the second electrode of the storage capacitor of the i+2th subpixel are arranged at intervals, and the second electrode of the storage capacitor of the i+2th subpixel is connected to The second electrode of the storage capacitor of the i+3th sub-pixel is connected through the first connecting portion C3; in each pixel in the other row of two adjacent rows of pixels, the second electrode of the storage capacitor of the i+th subpixel is connected to the i+th The second electrode of the storage capacitor of 1 sub-pixel is arranged at intervals, the second electrode of the storage capacitor of the i+1th sub-pixel and the second electrode of the storage capacitor of the i+2th sub-pixel are connected through the first connecting portion C
  • the second electrode C2 of the storage capacitor in at least one sub-pixel may have a rectangular shape
  • the first connecting portion C3 may have a strip shape
  • the first connecting portion C3 is disposed on one side of the second electrode C2 in the first direction.
  • the second electrode C2 of the i-th sub-pixel of one row of pixels and the second electrode C2 of the i+1-th sub-pixel are connected to each other through the first connecting portion C3, and the i+th
  • the second electrode C2 of 1 sub-pixel and the second electrode C2 of the i+2th sub-pixel are spaced apart, and the second electrode C2 of the i+2th sub-pixel is connected to the second electrode C2 of the i+3th sub-pixel through the first connection.
  • the parts C3 are connected to each other.
  • the second electrode C2 of the i-th sub-pixel of another row of pixels and the second electrode C2 of the i+1-th sub-pixel are spaced apart, and the second electrode C2 of the i+1-th sub-pixel and the second electrode C2 of the i+2-th sub-pixel C2 is connected to each other through the first connecting portion C3, and the second electrode C2 of the i+2th sub-pixel is spaced apart from the second electrode C2 of the i+3th sub-pixel.
  • the second electrode of the storage capacitor of the i-th sub-pixel in the first row of pixels is directly connected to the second electrode of the storage capacitor of the i+1-th sub-pixel through the first connecting portion C3,
  • the second electrode of the storage capacitor of the i+2th sub-pixel and the second electrode of the storage capacitor of the i+3th sub-pixel are directly connected through the first connection portion C3 as an example for description.
  • the orthographic projection of the first electrode of the fifth transistor on the substrate and the orthographic projection of the connected data line on the substrate have an overlapping area.
  • the second connection portion 56 may be included. Under the condition that the second electrode C2 of the storage capacitor of the i+1th subpixel is connected to the second electrode C2 of the storage capacitor of the i+1th subpixel, the first electrode 51 of the fifth transistor T5 in the i+1th subpixel is The first electrode 51 of the fifth transistor T5 in the i+2th sub-pixel is connected through the second connection portion 56.
  • the second electrode C2 of the storage capacitor in the i-th sub-pixel in the second metal layer passes through the first electrode 51 and the second connecting portion of the fifth transistor T5 in the i+1-th sub-pixel in the third metal layer.
  • the first electrode 51 of the fifth transistor T5 in the 56 and i+2th sub-pixels is connected to the second electrode C2 of the storage capacitor in the i+3th sub-pixel in the second metal layer.
  • the ith The first pole 51 of the fifth transistor T5 in the subpixel is connected to the first pole 51 of the fifth transistor T5 in the i+1th subpixel through the second connecting portion 56, and the fifth transistor in the i+2th subpixel
  • the first pole 51 of T5 and the first pole 51 of the fifth transistor T5 in the i+3th sub-pixel are connected through the second connection portion 56.
  • the second electrode C2 of the storage capacitor of the i-th sub-pixel located in the second metal layer passes through the first electrode 51, the second connection portion 56 and the fifth transistor T5 in the i-th sub-pixel located in the third metal layer.
  • the first electrode 51 of the fifth transistor T5 in the (i+1)th sub-pixel is connected to the second electrode C2 of the storage capacitor of the (i+1)th sub-pixel in the second metal layer, and is located in the (i+2)th electrode of the second metal layer.
  • the second electrode C2 of the storage capacitor of the sub-pixel passes through the first electrode 51 of the fifth transistor T5 in the i+2th sub-pixel located in the third metal layer, the second connecting portion 56 and the first electrode in the i+3th sub-pixel.
  • the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor of the i+3th sub-pixel located in the second metal layer.
  • the second metal layer and the third metal layer jointly complete the lateral (first direction) crossover to realize the function of the power connection line, so that the power signal provided to each sub-pixel is the same, which ensures Display the display effect of the substrate.
  • the display substrate provided in the second embodiment can further reduce dynamic crosstalk compared with the display substrate provided in the first embodiment. .
  • the display substrate provided by the present disclosure may further include: a fifth insulating layer 15 and a flat layer 16 arranged between the fourth metal layer 60 and the fifth metal layer 70, and The organic light-emitting layer and the cathode (not shown in the figure) of the light-emitting device disposed on the side of the fifth metal layer 70 away from the substrate 10.
  • the fifth insulating layer 15 is arranged on the side of the flat layer 16 close to the substrate 10; the cathode is arranged on the side of the organic light-emitting layer away from the substrate 10.
  • the fourth metal layer provided by the present disclosure may further include a connection electrode 61, wherein the connection electrode 61 is respectively connected to the fifth metal layer and the second electrode of the sixth transistor.
  • the fifth insulating layer and the flat layer are provided with a fifth via hole V5 exposing the connecting electrode, the fifth metal layer is connected with the connecting electrode 61 through the fifth via hole V5 exposing the connecting electrode 61, and the fourth insulating layer is provided with exposing the sixth transistor.
  • the fourth via hole V4 of the second electrode, and the connection electrode 61 is connected to the second electrode of the sixth transistor through the fourth via hole V4 exposing the second electrode of the sixth transistor.
  • Exemplary embodiments of the present disclosure can reduce the occupied area of the sub-pixel and the data line connected to the sub-pixel by arranging the data line and the power line with the first and second electrodes of the plurality of transistors, thereby increasing the high frequency.
  • the resolution of the driven OLED display substrate can reduce the occupied area of the sub-pixel and the data line connected to the sub-pixel by arranging the data line and the power line with the first and second electrodes of the plurality of transistors, thereby increasing the high frequency.
  • the present disclosure also provides a manufacturing method of a display substrate to manufacture the display substrate provided in the above embodiment.
  • the display substrate in a plane parallel to the display substrate, the display substrate includes a gate line, a data line, a power supply line, and a plurality of sub-pixels disposed on a base, and at least one sub-pixel includes a light-emitting device and is configured to drive
  • the driving circuit for the light-emitting device to emit light the driving circuit includes a plurality of transistors and storage capacitors; the manufacturing method may include:
  • a plurality of functional layers are formed on the substrate; the plurality of functional layers include a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence; among the plurality of functional layers A first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer are respectively arranged between them; in the extending direction of the gate lines, the power lines are connected to each other through at least one functional layer.
  • FIG. 11 is a flowchart of a method for manufacturing a display substrate provided by the present disclosure. As shown in FIG. 11, the method for manufacturing a display substrate provided by the present disclosure may include the following steps:
  • Step B1 Provide a substrate.
  • Step B2 sequentially forming a mutually insulated semiconductor layer, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer on the substrate.
  • the semiconductor layer may include: active regions of a plurality of transistors, and the first metal layer may include: gate lines, light emission control lines, reset signal lines, first electrodes of storage capacitors, and gates of a plurality of transistors.
  • the second metal layer may include: the initial signal line and the second electrode of the storage capacitor; the third metal layer may include: the source and drain electrodes of a plurality of transistors, and the fourth metal layer may include: data lines and power lines.
  • the metal layer may include: the anode of the light emitting device.
  • the driving circuit of the sub-pixel in the i-th column is connected to the data line in the i-th column, and each column of the data line includes: a first sub-data line and a second sub-data line; the first sub-data line and the second sub-data in the data line in the i-th column
  • the lines are respectively located on both sides of the i-th column of sub-pixels, and all the sub-data lines between two adjacent columns of sub-pixels are only the first sub-data line or the second sub-data line.
  • N is the total number of columns of sub-pixels.
  • step 200 may include: forming a semiconductor layer and a first insulating layer sequentially on a substrate; sequentially forming a first metal layer and a second insulating layer on the first insulating layer; A second metal layer and a third insulating layer are sequentially formed on the upper; a third metal layer and a fourth insulating layer are sequentially formed on the third insulating layer; a fourth metal layer, a fifth insulating layer, and a flat layer are sequentially formed on the fourth insulating layer ; A fifth metal layer, an organic light-emitting layer of the light-emitting device and a cathode of the light-emitting device are sequentially formed on the flat layer.
  • FIG. 12 is a schematic diagram of the first production of a display substrate provided by the present disclosure
  • FIG. 13 is a schematic diagram of the second production of a display substrate provided by the present disclosure
  • FIG. 14A is a third production of a display substrate provided by the present disclosure Schematic diagram
  • FIG. 14B is another third manufacturing schematic diagram of a display substrate provided by the present disclosure
  • FIG. 15A is a fourth manufacturing schematic diagram of a display substrate provided by the disclosure
  • FIG. 15B is a display substrate provided by the present disclosure
  • FIG. 16A is a fifth schematic diagram of a display substrate provided by the present disclosure
  • FIG. 16B is another fifth schematic diagram of a display substrate provided by the present disclosure.
  • the "patterning process” mentioned in the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping photoresist.
  • the deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition
  • the coating can be any one or more of spraying, spin coating and inkjet printing
  • the etching can be dry etching and wet etching. Any one or more of the moments are not limited in the present disclosure.
  • Thin film refers to a layer of thin film made by depositing a certain material on a substrate or other processes.
  • the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be referred to as a "layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • the manufacturing process of the display substrate provided by the present disclosure may include the following operations.
  • Step 100 Provide a substrate 10, deposit a semiconductor film on the substrate 10, and process the semiconductor film by a patterning process to form a semiconductor layer 20, as shown in FIG. 12.
  • the semiconductor layer 20 of each sub-pixel may include the first active region 101 where the first transistor T1 is located, the second active region 102 where the second transistor T2 is located, and the location where the third transistor T3 is located.
  • the seventh active region 107 where the seventh transistor T7 is located, and the first active region 101 to the seventh active region 107 are an integral structure connected to each other.
  • the first active region 101 and the seventh active region 107 are disposed on the side of the first region R1 away from the second region R2, and the second active region 102 and the fourth active region 104 are disposed on the The first region R1 is close to the side of the second region R2; the third active region 103 is disposed in the second region R2; the fifth active region 105 and the sixth active region 106 are disposed in the third region R3.
  • the first active region 101 is connected to the second active region 102 and the seventh active region 107, respectively, and the second active region 102 is connected to the third active region 103 and the sixth active region, respectively.
  • 106 is connected, and the fourth active region 104 is connected to the third active region 103 and the fifth active region 105 respectively.
  • the first active region 101 is in an "n" shape
  • the seventh active region 107 is in an "L” shape
  • the seventh active region 107 is located in the first active region 101 away from the center line of the sub-pixel.
  • the center line of the sub-pixel is a straight line extending along the second direction with iso-molecular pixels in the first direction.
  • the second active region 102 has a shape of "7” and is located on one side of the center line of the sub-pixel
  • the fourth active region 104 has a shape of "1" and is located on the other side of the center line of the sub-pixel.
  • the third active region 103 is in the shape of a "ji", which may be mirror-symmetrical with respect to the center line of the sub-pixel.
  • the fifth active region 105 has an “L” shape, and the shape of the sixth active region 106 and the shape of the fifth active region 15 are mirror-symmetrical with respect to the center line of the sub-pixel.
  • the shape of the active region of a transistor refers to the shape of the active region near the gate of the transistor, including but not limited to the channel region, source and drain regions of the active region of the transistor, and the source and drain regions of other transistors. Connect the extended area of the active area part used.
  • the active region of each transistor includes a first region, a second region, and a channel region located between the first region and the second region.
  • the first area of the first active area 101 serves as the first area of the seventh active area 107 at the same time
  • the second area of the first active area 101 serves as the second area of the second active area 102 at the same time. a district.
  • the second area of the second active area 102, the second area of the third active area 103, and the first area of the sixth active area 106 are connected to each other, and the first area and the fourth area of the third active area 103
  • the second area of the active area 104 and the second area of the fifth active area 105 are connected to each other.
  • the first region of the fourth active region 14 is arranged on the side far away from the third active region 103, and the first region of the fifth active region 105 is arranged on the other side away from the third active region 103.
  • the second area of the sixth active area 106 serves as the second area of the seventh active area 107 at the same time.
  • the distance in the first direction between the second active region 102 and the first active region 101 is smaller than the distance in the first direction between the second active region 102 and the seventh active region 107.
  • the distance in the first direction between the second active region 102 and the third active region 103 is smaller than the distance in the first direction between the second active region 102 and the fourth active region 104.
  • the distance in the first direction between the three active regions 103 is smaller than the distance in the first direction between the second active region 102 and the fifth active region 105; the second active region 102 and the first active region 101 are in the first direction.
  • the distance in one direction is equivalent to the distance in the first direction between the second active region 102 and the third active region 103.
  • the seventh active region 107 and the first active region 101 are sequentially arranged along the direction from the data line for writing the data signal to the power supply line.
  • the shape of the semiconductor layer 20 of the sub-pixel in the i-th row and the j-th column is the same as the shape of the semiconductor layer 20 of the sub-pixel in the i+1-th row and j+1-th column.
  • the shape of 20 is the same as the shape of the semiconductor layer 20 of the sub-pixel in the i+1th row and jth column.
  • the semiconductor layers 20 of adjacent sub-pixels are mirror-symmetrical about the center line, that is, in the first direction, the semiconductor layers of adjacent sub-pixels are in a symmetric relationship with each other.
  • the same shape of the semiconductor layer includes, but is not limited to, the same overall shape of the two, the connection relationship of each part, and the trend of the signal flow direction.
  • the manufacturing schematic diagram of the active region in the first embodiment is the same as the manufacturing schematic diagram of the active region in the second embodiment.
  • the semiconductor layer of the exemplary embodiment of the present disclosure has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.
  • Step 200 sequentially deposit a first insulating film and a first metal film on the semiconductor layer 20, and process the first metal film by a patterning process to form a first insulating layer covering the semiconductor layer 20, and set it on the first insulating layer
  • the first metal layer 30 is shown in FIG. 13.
  • the first metal layer 30 may include a gate line G, a reset signal line Reset, an emission control line EM, and a first electrode C1 of a storage capacitor.
  • the gate line G, the reset signal line Reset, and the emission control line EM extend in the first direction
  • the gate line G and the reset signal line Reset are disposed in the first region R1
  • the emission control line EM is disposed in the third region.
  • the first electrode C1 of the storage capacitor may be rectangular, and the corners of the rectangular shape may be chamfered.
  • the first electrode C1 is disposed in the second region R2, between the gate line G and the light-emitting control line EM, and the first electrode C1 is There is an overlap area between the orthographic projection on the substrate and the orthographic projection of the third active region on the substrate.
  • the first plate C1 simultaneously serves as the gate electrode of the third transistor.
  • the reset signal line Reset of the first region R1 may be provided with unequal widths, and the width of the reset signal line Reset is the size of the reset signal line Reset in the second direction.
  • the reset signal line Reset includes an area overlapping with the semiconductor layer 20 and an area not overlapping with the semiconductor layer 20.
  • the width of the reset signal line Reset in the area overlapping with the semiconductor layer 20 may be larger than the area not overlapping with the semiconductor layer 20 The width of the reset signal line Reset.
  • the gate lines G of the first region R1 may be arranged with unequal widths, and the width of the gate lines G is the size of the gate lines G in the second direction.
  • the width of the gate line G in the area where the gate line G overlaps with the semiconductor layer 20 and the area not overlapped with the semiconductor layer 20, and the gate line G in the area overlapping with the semiconductor layer 20 may be greater than the gate line in the area not overlapping with the semiconductor layer 20 The width of G.
  • the light emission control line EM of the third region R3 may be arranged with unequal widths, and the width of the light emission control line EM is the size of the light emission control line EM in the second direction.
  • the emission control line EM includes an area overlapping with the semiconductor layer 20 and an area not overlapping with the semiconductor layer 20.
  • the width of the emission control line EM in the area overlapping with the semiconductor layer 20 may be larger than the area not overlapping with the semiconductor layer 20 The width of the luminous control line EM.
  • the gate line G of the i-th row may include a first gate line segment that extends along the first direction from the j-th column of sub-pixels to the j+1-th column of sub-pixels, and the first gate line segment is One end is connected to the gate line G through the connecting bar located in the i-th row and the jth column sub-pixel, and the second end of the first gate line segment is connected to the gate line G through the connecting bar located in the i-th row and the j+1 column sub-pixel.
  • a dual gate structure is simultaneously formed in the sub-pixels in the i-th row and the j-th column and the i-th row and the j+1-th column.
  • the gate line G in the i+1th row may include a second gate line segment, which extends along the first direction from the j+1th column of sub-pixels to the j+2th column of sub-pixels, and the first end of the second gate line segment passes
  • the connecting bar of the sub-pixel in the i+1th row and the j+1th column is connected to the gate line G
  • the second end of the second gate line segment is connected to the gate line G through the connecting bar of the sub-pixel in the i+1th row and j+2th column
  • a dual gate structure is simultaneously formed in the sub-pixels in the (i+1)th row and the j+1th column and the sub-pixels in the (i+1)th row and j+2th column. In this way, the second transistor T2 of the double-gate structure is formed in the sub-pixel of the jth column and the sub-pixel of the j+1th column at the same time. 110.
  • the area where the first electrode C1 overlaps the third active area serves as the third gate electrode (double gate structure), and the area where the gate line G overlaps the second active area serves as the second gate electrode (Double gate structure), the area where the reset signal line Reset and the first active area overlap is used as the first gate electrode (double gate structure), and the area where the gate line G overlaps the fourth active area is used as the fourth gate electrode,
  • the area where the reset signal line Reset overlaps with the seventh active area serves as the seventh gate electrode
  • the area where the emission control line EM overlaps with the fifth active area serves as the fifth gate electrode
  • the emission control line EM overlaps with the sixth active area.
  • the overlapping area serves as the sixth gate electrode.
  • the double-gate second transistor T2 is compatible with other double-gate transistors (the first transistor T1 and the third transistor).
  • the distance in the first direction between T3) is smaller than the distance in the first direction between the second transistor T2 and the single-gate fourth transistor T4, the fifth transistor T5, and the seventh transistor T7.
  • the first metal layer 30 can be used as a shield to conduct a conductive process on the semiconductor layer, and the semiconductor layer in the region shielded by the first metal layer 30 forms the first transistor T1 To the channel region of the seventh transistor T7, the semiconductor layer in the region not covered by the first metal layer 30 is conductive, that is, the first region and the second region of the first transistor T1 to the seventh transistor T7 are conductive.
  • the schematic diagram of the production of the first metal layer in the first embodiment is the same as the schematic diagram of the production of the first metal layer in the second embodiment.
  • the first metal layer of the exemplary embodiment of the present disclosure has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.
  • Step 300 sequentially deposit a second insulating film and a second metal film on the first metal layer 30, and process the second metal film by a patterning process to form a second insulating layer covering the first metal layer 30, and set it on the first metal layer 30
  • the second metal layer 40 on the two insulating layers at least includes the initial signal line Vinit and the second electrode C2 of the storage capacitor.
  • a third insulating film is deposited on the second metal layer 40, and the third insulating film is processed by a patterning process to form a third insulating layer covering the second metal layer 40.
  • the third insulating layer is provided with a plurality of vias. , As shown in Figures 14A and 14B.
  • the plurality of via holes on the third insulating layer at least includes: a second via hole V2 exposing the second electrode C2, a sixth via hole V6 exposing the initial signal line Vinit, and a first via hole V6 exposing the initial signal line Vinit.
  • the seventh via hole V7 of the electrode C1 exposes the eighth via hole V8 of the fourth active region, the ninth via hole V9 of the second active region is exposed, and the tenth via hole V10 of the first active region is exposed , And a plurality of via holes exposing other active regions in the semiconductor layer.
  • the third insulating layer in the second via hole V2 exposing the second electrode C2 and the sixth via hole V6 exposing the initial signal line Vinit is etched away, exposing the third insulating layer in the seventh via hole V7 of the first electrode C1
  • the second insulating layer and the third insulating layer are etched away, exposing the eighth via hole V8 of the fourth active region, exposing the ninth via hole V9 of the second active region, and exposing the first active region.
  • the tenth via hole V10 and the first insulating layer, the second insulating layer and the third insulating layer in the via holes exposing other active regions in the semiconductor layer are etched away.
  • the second via hole V2 is configured to connect the second electrode C2 with the first electrode of the fifth transistor T5 formed subsequently
  • the sixth via hole V6 is configured to connect the initial signal line Vinit with the first electrode formed subsequently
  • the first electrode of a transistor T1 is connected
  • the seventh via hole V7 is configured to connect the first electrode C1 with the first electrode of the second transistor T2 to be formed later
  • the eighth via hole V8 is configured to make the fourth transistor T4 active
  • the ninth via hole V9 is configured to connect the active layer of the second transistor T2 to the first pole of the second transistor T2 formed subsequently
  • the tenth via hole V10 is connected to the first electrode of the fourth transistor T4 formed subsequently. It is configured to connect the active layer of the first transistor T1 with the first electrode of the first transistor T1 formed later. Since the first electrode of the fourth transistor T4 formed subsequently is connected to the data line D formed subsequently, the eighth via V8 is a data writing hole.
  • the distance between the data writing hole and the second transistor T2 in the first direction is greater than the distance between the data writing hole and the first transistor T1 in the first direction, the data writing hole and the The distance in the first direction between the seventh transistors T7.
  • the distance in the second direction between the data writing hole and the third transistor T3 is smaller than the distance in the second direction between the data writing hole and the fifth transistor T5, and the distance between the data writing hole and the sixth transistor T6. The distance in two directions.
  • the number of the second via holes V2 may be two, and the two second via holes are sequentially arranged along the second direction. Since the width of the fifth first electrode is relatively narrow, two second via holes V2 are provided, which can improve the reliability of the connection between the second electrode and the fifth first electrode.
  • the initial signal line Vinit extends in the first direction, is disposed in the first region R1, and is located at a side of the reset signal line Reset away from the second region R2.
  • the outline of the second electrode C2 of the storage capacitor in each sub-pixel may be rectangular, which is arranged in the second region R2 and is located between the gate line G and the emission control line EM.
  • the outline of the second electrode C2 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the second electrode C2 on the substrate and the orthographic projection of the first electrode C1 on the substrate exist. Overlapping area.
  • An opening 111 is provided in the middle of the second electrode C2, and the opening 111 may be rectangular, so that the second electrode C2 forms a ring structure.
  • the opening 111 exposes the second insulating layer covering the first electrode C1, and the orthographic projection of the first electrode C1 on the substrate includes the orthographic projection of the opening 111 on the substrate.
  • the orthographic projection of the opening 111 on the substrate includes an orthographic projection of the seventh via hole V7 exposing the first electrode C1 on the substrate.
  • the orthographic projection of the second electrode C2 on the substrate close to the edge of the first region R1 overlaps with the orthographic projection of the boundary line of the first region R1 and the second region R2 on the substrate.
  • the second electrode C2 is close to the edge of the third region R3.
  • the orthographic projection on the substrate overlaps the orthographic projection of the boundary line between the second region R2 and the third region R3 on the substrate, that is, the second length of the second electrode C2 is equal to the second length of the second region R2, and the second length refers to The size in the second direction.
  • the second electrodes C2 of adjacent sub-pixels in a row have an integral structure connected to each other. This structure allows the second electrodes C2 of adjacent sub-pixels to be multiplexed as power signal lines, which can ensure that the power signals provided by the power lines of adjacent sub-pixels are the same, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • the second electrode C2 of the sub-pixel in the i-th row and the j-th column and the second electrode C2 of the i-th row and the j+1-th column sub-pixel are in an integrated structure connected to each other by the first connecting portion.
  • the second electrode C2 of the +1 column of sub-pixels is disconnected from the second electrode C2 of the i-th row and j+2 column of the sub-pixels.
  • the second electrode C2 of the i-th row and j+2 column of the sub-pixel is connected to the i-th row and j+
  • the second electrodes C2 of the three columns of sub-pixels have an integral structure connected to each other through the first connection portion.
  • the second electrode C2 of the sub-pixel in row i+1 and column j is disconnected from the second electrode C2 of the sub-pixel in row i+1 and column j+1.
  • the second electrode C2 of the sub-pixel in row i+1 and column j+1 is disconnected.
  • the electrode C2 and the second electrode C2 of the sub-pixel in the i+1th row and j+2th column are an integrated structure connected to each other through the first connecting portion.
  • the second electrode C2 of the sub-pixel in the i+1th row and j+2th column is connected to the i-th
  • the second electrode C2 of the sub-pixel in row +1 and column j+3 is in an off setting.
  • This structure enables the second electrode C2 of adjacent sub-pixels to be multiplexed as power signal lines, which can ensure that the power signals provided by the power lines of adjacent sub-pixels are the same, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • FIG. 14A is a schematic diagram of the production of the first embodiment
  • FIG. 14B is a schematic diagram of the production of the second embodiment.
  • the layout of the second metal layer and the via holes of the exemplary embodiment of the present disclosure is reasonable, and the structure is simple, which can ensure the display effect of the display substrate.
  • Step 400 Deposit a third metal film on the third insulating layer, and process the third metal film through a patterning process to form a third metal layer 50.
  • the third metal layer 50 includes at least the first electrode 51 of the fifth transistor T5.
  • the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 through the second via hole V2
  • the second electrode 52 of the sixth transistor T6 is connected to the active layer of the sixth transistor through the via hole
  • the fourth transistor T4 is connected to the active layer of the sixth transistor.
  • One pole 53 is connected to the active layer of the fourth transistor T4 through the eighth via hole V8, one end of the first pole 54 of the first transistor T1 is connected to the initial signal line Vinit through the sixth via hole V6, and the other end is connected through the tenth via hole.
  • the hole V10 is connected to the active layer of the first transistor T1.
  • One end of the first electrode 55 of the second transistor T2 is connected to the first electrode C1 through the seventh via hole V7, and the other end is connected to the second transistor T2 through the ninth via hole V9.
  • the active layer is connected.
  • a fourth insulating film is deposited on the third metal layer 50, and the fourth insulating film is processed by a patterning process to form a fourth insulating layer covering the third metal layer 50.
  • the fourth insulating layer is provided with a plurality of vias, As shown in Figure 15A and Figure 15B.
  • the plurality of via holes on the fourth insulating layer at least include: a first via hole V1 exposing the first electrode 51 of the fifth transistor T5, and a first via hole V1 exposing the second electrode 52 of the sixth transistor T6.
  • the four via holes V4 expose the third via hole V3 of the first pole 53 of the fourth transistor T4.
  • the first via hole V1 exposing the first electrode 51 of the fifth transistor T5 is configured to connect the first electrode 51 of the fifth transistor T5 to the subsequently formed power line VDD, and exposing the fourth electrode 52 of the sixth transistor T6.
  • the via hole V4 is configured to connect the second pole 52 of the sixth transistor T6 with the subsequently formed connecting electrode, and the third via hole V3 exposing the first pole 53 of the fourth transistor T4 is configured to make the first pole of the fourth transistor T4
  • the pole 53 is connected to the data line D formed later.
  • the first electrodes 51 of the fifth transistor T5 of adjacent sub-pixels in the same row are arranged at intervals.
  • the first pole 51 of the fifth transistor T5 in the sub-pixel in the i-th row and the j+1th column and the first pole 51 of the fifth transistor T5 in the sub-pixel in the i-th row and j+2th column pass through the second The connecting portion is connected, the first electrode 51 of the fifth transistor T5 in the sub-pixel in the i+1th row and the jth column and the first electrode 51 of the fifth transistor T5 in the i+1th row and j+1th column of the sub-pixel pass through the second connecting portion Connected, the first electrode 51 of the fifth transistor T5 in the sub-pixel in the i+1th row and the j+2th column and the first electrode 51 of the fifth transistor T5 in the sub-pixel in the i+th row and j+3th column pass through the second connecting portion connection.
  • FIG. 15A is a schematic diagram of the production of the first embodiment
  • FIG. 15B is a schematic diagram of the production of the second embodiment.
  • the layout of the third metal layer and the via holes is reasonable, the structure is simple, and the display effect of the display substrate can be ensured.
  • Step 500 A fourth metal film is deposited on the fourth insulating layer, and the fourth metal film is processed by a patterning process to form a structure including the first sub-data line DO, the second sub-data line DE, the power supply line VDD, and the connection electrode 61.
  • the fourth metal layer 60, the first sub-data line DO and the second sub-data line DE respectively pass through the third via hole V3 of the sub-pixel where the first electrode 53 of the fourth transistor T4 is exposed and the first electrode 53 of the fourth transistor T4.
  • the electrode 53 is connected, the power line VDD is connected to the first electrode 51 of the fifth transistor T5 through the first via hole V1 exposing the first electrode 51 of the fifth transistor T5, and the connecting electrode 61 is connected to the first electrode 51 of the fifth transistor T5 by exposing the second electrode 52 of the sixth transistor T6.
  • the fourth via hole V4 is connected to the second pole 52 of the sixth transistor T6.
  • a fifth insulating film is deposited on the fourth metal layer 60, a flat film is coated on the fifth insulating film, and the flat film and the fifth insulating film are processed through a patterning process to form a fifth insulating film covering the fourth metal layer 60.
  • the insulating layer, and the flat layer provided on the fifth insulating layer, the flat layer is provided with a plurality of via holes, as shown in FIGS. 16A and 16B.
  • the first sub-data line DO, the second sub-data line DE, and the power supply line VDD extend in the second direction
  • the first sub-data line DO is located at one side of the sub-pixel
  • the second sub-data line DE is located at On the other side of the sub-pixel
  • the power supply line VDD is located between the first sub-data line DO and the second sub-data line DE.
  • the first sub data line DO and the second sub data line DE may be straight lines of equal width, and the width of the first sub data line DO and the second sub data line DE is equal to that of the first sub data line DO and the second sub data line DE.
  • the first electrodes of the fourth transistors of adjacent sub-pixels located in the same column are connected to different sub-data lines.
  • the sub-pixels in the i-th row and j-th column are connected to the first sub-data line in the j-th column data line
  • the sub-pixels in the i+1-th row and j-th column are connected to the second sub-data line in the j-th column data line.
  • the sub-pixels in the i-th row and j-th column are connected to the second sub-data line in the j-th column data line, and the sub-pixels in the i+1-th row and j-th column are connected to the first sub-data line in the j-th column data line.
  • the first sub-data line DO is connected to the first electrode 53 of the fourth transistor T4 through the third via hole V3 in the sub-pixel, and the first electrode of the fourth transistor T4 is 53 is connected to the fourth active region through the eighth via hole V8, the eighth via hole V8 is a data writing hole, and the first sub-data line DO is the data line of the writing data line number of the sub-pixel.
  • the second sub-data line DE is connected to the first electrode 53 of the fourth transistor T4 through the third via hole V3 in the sub-pixel, and the first electrode 53 of the fourth transistor T4 passes through the eighth via hole V8.
  • the eighth via hole V8 is a data writing hole
  • the second sub-data line DE is a data line of the writing data line number of the sub-pixel.
  • the power supply line VDD of each sub-pixel is connected to the first electrode 51 of the fifth transistor T5 through the first via hole V1, because the first electrode 51 of the fifth transistor T5 is connected to the second electrode C2 of the storage capacitor.
  • the second electrodes C2 of the storage capacitors of adjacent sub-pixels are connected to each other, thus not only the power supply line VDD is connected to the second electrode C2, but also the power supply connection line function of the second electrode C2 is realized, so that each sub-pixel is provided with The power signals are the same to ensure the display effect of the display substrate.
  • the power supply line VDD of each sub-pixel may be a broken line.
  • the power supply line VDD of each sub-pixel may include a first power supply part, a second power supply part, and a third power supply part that are sequentially connected.
  • the first end of the first power supply part is connected to the second end of the third power-supply part in the sub-pixel in the i-1th row and jth column.
  • the second end of the power supply unit extends along the second direction and is connected to the first end of the second power supply unit; the second end of the second power supply unit extends along the oblique direction, and is connected to the first end of the third power supply unit, and is inclined
  • the direction and the second direction have an included angle, and the included angle can be greater than 0 degrees and less than 90 degrees; the second end of the third power supply part extends along the second direction and is located in the sub-pixel in the i+1th row and the jth column.
  • the first end of the first power supply unit is connected.
  • the first power source part may be a straight line of equal width
  • the second power source part may be a diagonal line of equal width
  • the third power source part may be a straight line of equal width.
  • the first power part and the second power part are parallel to the first sub-data line (or the second sub-data line)
  • the angle between the second power part and the first power part may be greater than 90 degrees and less than 180 degrees
  • the second The included angle between the power supply part and the third power supply part may be greater than 90 degrees and less than 180 degrees.
  • the length of the first power supply part extending in the first direction is greater than the average width of the first power supply part
  • the length of the second power supply part extending in the oblique direction is greater than the average width of the second power supply part
  • the third The length of the power supply part extending along the first direction is greater than the average width of the third power supply part
  • the oblique direction is a direction with an angle between the second power supply part and the first power supply part.
  • the average width of the third power source part may be smaller than the average width of the first power source part, and the average width of the third power source part may be smaller than the average width of the second power source part.
  • the power line VDD adopts a variable-width folding line arrangement, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance of the power line VDD and the data line. Since the distance between the third power supply part and the data line is relatively short, the average width of the third power supply part is reduced, and the parasitic capacitance between the third power supply part and the data line can be reduced.
  • the average width of the first power supply part may be greater than or equal to the average width of the second power supply part, or the average width of the first power supply part may be less than the average width of the second power supply part.
  • the length of the extending direction of the second power supply part is equivalent to the second length of the first electrode C1
  • the second length of the first electrode C1 is the dimension of the first electrode C1 in the second direction.
  • the length in the extending direction of the first power supply portion is equivalent to the second length of the second electrode C2
  • the length in the extending direction of the third power supply portion is equivalent to the second length of the second electrode C2
  • the second length of the second electrode C2 is the second electrode C2 The size in the second direction.
  • the orthographic projection of the first power supply portion on the substrate and the orthographic projection of the first pole 55 of the second transistor T2 and the ninth via V9 on the substrate are There is an overlap area, so there is an overlap area between the orthographic projection of the first power supply portion on the substrate and the orthographic projection of the second transistor T2 on the substrate. There is an overlap area between the orthographic projection of the second power supply unit on the substrate and the orthographic projection of the first via hole V1 on the substrate.
  • the orthographic projection of the third power supply unit on the substrate and the first electrode 51 of the fifth transistor T5 are on the substrate. There is an overlap area in the orthographic projection, so the orthographic projections of the second power supply part and the third power supply part on the substrate both have an overlap area with the first pole 51 of the fifth transistor T5.
  • the orthographic projection of the first via hole V1 on the substrate and the orthographic projection of the extension line of the first power supply portion in the second direction on the substrate overlap, and the orthographic projection of the first via hole V1 on the substrate There is an overlap area with the orthographic projection of the extension line of the third power supply part in the second direction on the substrate.
  • the distance between the first power supply part and the third power supply part in the first direction is smaller than the first via hole V1
  • the first length or the average width of the third power section that is, the distance between the edge of the first power section on the side close to the third power section and the edge of the third power section on the side close to the first power section is smaller than the first via
  • the first length of V1 or the width of the third power supply part, and the first length of the first via V1 refers to the size of the first via V1 in the first direction. Therefore, for the second power supply part extending along the oblique direction, it can be understood that the second power supply part has turned the power supply line VDD.
  • the degree of turning is equivalent to the first length of the first via hole V1, or equivalent to the width of the third power supply part; in the second direction, the degree of turning is equivalent to the second length of the first electrode C1 .
  • the edges of the two power supply parts refer to the edges of the overall outline of the two power supply parts.
  • the connecting electrode 61 has a strip shape extending along the second direction, the extending direction of the connecting electrode 61 is parallel to the extending direction of the third power supply part, and the length of the connecting electrode 61 in the second direction is the same as that of the third power supply part.
  • the length in the second direction is equivalent.
  • connection electrode 61 on the substrate there is an overlap area between the orthographic projection of the connection electrode 61 on the substrate and the orthographic projection of the second electrode C2 on the substrate.
  • connection electrode 61 on the substrate there is an overlap area between the orthographic projection of the connection electrode 61 on the substrate and the orthographic projection of the opening 111 in the middle of the second electrode C2 on the substrate.
  • connection electrode 61 on the substrate there is an overlap area between the orthographic projection of the connection electrode 61 on the substrate and the orthographic projection of the second first electrode 55 on the substrate.
  • the extension direction of the connection electrode 61 overlaps with the extension direction of the first power supply portion, that is, the orthographic projection of the connection electrode 61 on the substrate and the alignment of the virtual extension line of the second direction of the first power supply portion on the substrate.
  • the projections have overlapping areas.
  • the eighth via hole V8 (that is, the data writing hole) is located on the virtual extension line in the second direction of the third power supply part, that is, the orthographic projection of the eighth via hole V8 on the substrate and the third power supply part
  • the orthographic projection of the virtual extension line in the second direction on the substrate has an overlapping area.
  • the power supply line VDD of each sub-pixel is connected to the first electrode 51 of the fifth transistor T5 through the first via V1
  • the first electrode 51 of the fifth transistor T5 is connected to the first electrode 51 of the fifth transistor T5 through the second via V2.
  • the second electrode C2 of the storage capacitor is connected, and the power line VDD is connected to the second electrode C2 of the storage capacitor. Therefore, the first via V1 is called a power write hole.
  • the orthographic projection of the power writing hole on the substrate is within the orthographic projection range of the second power supply part on the substrate.
  • the distance in the first direction between the power writing hole and the fourth transistor T4 is equivalent to the distance in the first direction between the power writing hole and the second transistor T2.
  • the distance in the second direction between the power writing hole and the second transistor T2 is smaller than the distance in the second direction between the power writing hole and the first transistor T1, and the distance between the power writing hole and the seventh transistor T7.
  • the distance in the two directions, the distance in the second direction between the power writing hole and the third transistor T3, is smaller than the distance in the second direction between the power writing hole and the fifth transistor T5, the power writing hole and the third transistor T5, respectively.
  • the distance in the second direction between the six transistors T6 is smaller than the distance in the second direction between the six transistors T6.
  • the plurality of via holes on the fifth insulating layer and the planarization layer at least include: a fifth via hole V5 exposing the connection electrode 61, and a fifth via hole V5 exposing the connection electrode 61 is configured to connect
  • the electrode 61 is connected to a fifth metal layer (anode) formed later. Due to the connection between the connection electrode 61 and the sixth second electrode 52, the connection between the sixth second electrode 52 and the fifth metal layer is realized, and the driving circuit can drive the light emitting device to emit light.
  • connection electrode 61 is connected to the second electrode 52 of the sixth transistor T6 through a fourth via V4, and the fourth via V4 is located at an end of the connection electrode 61 away from the second power supply part.
  • the connecting electrode 61 is connected to the subsequently formed anode through the fifth via hole V5.
  • the fifth via hole V5 is located at one end of the connecting electrode 61 close to the second power supply.
  • the orthographic projection of the fifth via hole V5 on the substrate is the second of the storage capacitor. There is an overlap area in the orthographic projection of the electrode C2 on the substrate.
  • the fifth via hole V5 is located on the virtual extension line in the second direction of the first power supply part, that is, the orthographic projection of the fifth via hole V5 on the substrate and the virtual extension line in the second direction of the first power supply part
  • the orthographic projection on the substrate has overlapping areas.
  • FIG. 16A is a schematic diagram of the production of the first embodiment
  • FIG. 16B is a schematic diagram of the production of the second embodiment.
  • the layout of the fourth metal layer and the via holes is reasonable, the structure is simple, and the display effect of the display substrate can be ensured.
  • Step 600 A fifth metal film is deposited on the flat layer, and the fifth metal film is processed by a patterning process to form a fifth metal layer 70.
  • the fifth metal layer 70 includes at least an anode, which exposes the fifth via hole of the connection electrode 61 It is connected to the connection electrode 61. Since the anode is connected to the connecting electrode 61 and the connecting electrode 61 is connected to the second electrode 52 of the sixth transistor T6, the second electrode 52 of the sixth transistor T6 is connected to the anode, and the sixth transistor can drive the light emitting device to emit light. Subsequently, a pixel definition film is coated on the fifth metal layer, and the pixel definition film is processed through a patterning process to form a pixel definition layer.
  • the pixel definition layer of each sub-pixel is provided with a pixel opening, and the pixel opening exposes the anode. Subsequently, an organic light-emitting layer is formed by an evaporation process, and a cathode is formed on the organic light-emitting layer.
  • the power line VDD and the first electrode or the second electrode of some transistors may be located on the third metal layer 50, and the data line D and the first electrode or the second electrode of some transistors may be located on the fourth metal layer 60.
  • the data line D and the first electrode or the second electrode of some transistors may be located on the third metal layer 50, and the power line VDD and the first electrode or the second electrode of some transistors may be located on the fourth metal layer 60.
  • the power line VDD and the data line D may be located on the third metal layer 50, and the first and second electrodes of the first to seventh transistors may be located on the fourth metal layer 60, which is not limited in the present disclosure. .
  • FIG. 17 is a top view of a plurality of sub-pixels in another display substrate provided by the present disclosure
  • FIG. 18 is a cross-sectional view of a plurality of sub-pixels in another display substrate provided by the present disclosure.
  • the row sub-pixel) is taken as an example for schematic description.
  • the display substrate provided by the present disclosure includes: a substrate 10, a plurality of sub-pixels P arranged on the substrate 10, a plurality of columns of power lines VDD, and data lines arranged in the same layer as the power lines VDD D.
  • Each sub-pixel P includes a driving circuit; the driving circuit may include a plurality of transistors and a storage capacitor, the storage capacitor includes a first electrode C1 and a second electrode C2 disposed oppositely, and the active region 21 of the transistor is located at the second electrode of the storage capacitor C2 is close to the side of the substrate 10, and the power line VDD is located on the side of the second electrode C2 of the storage capacitor away from the substrate 10.
  • the driving circuit may include a plurality of transistors and a storage capacitor
  • the storage capacitor includes a first electrode C1 and a second electrode C2 disposed oppositely, and the active region 21 of the transistor is located at the second electrode of the storage capacitor C2 is close to the side of the substrate 10, and the power line VDD is located on the side of the second electrode C2 of the storage capacitor away from the substrate 10.
  • the power supply line VDD is respectively connected to the second electrode C2 of the storage capacitor and the third connecting portion of the semiconductor layer, and the second electrode C2 of the storage capacitor of each sub-pixel is connected to the second electrode C2 of the storage capacitor in the same row.
  • the second electrode C2 of the storage capacitor of one adjacent sub-pixel is connected, and the semiconductor layer of each sub-pixel and the semiconductor layer of another adjacent sub-pixel in the same row are connected to each other through a third connection portion.
  • the driving circuit of the sub-pixel in the i-th column is connected to the data line in the i-th column and the power line in the i-th column, and 1 ⁇ i ⁇ N.
  • Each column of data lines includes: a first sub-data line and a second sub-data line.
  • the first sub-data line DOi and the second sub-data line DEi in the i-th column of data line Di are respectively located on both sides of the i-th column of sub-pixels.
  • the i-column power line VDDi is located between the first sub-data line DOi and the second sub-data line DEi in the i-th column data line Di.
  • adjacent sub-pixels located in the same column are connected to different sub-data lines, that is, if the sub-pixels in the i-th row and j-th column are connected to the first sub-data line DOj in the j-th column data line, then The sub-pixel in the i+1th row and the jth column is connected to the second sub-data line DEj in the j-th column data line, if the sub-pixel in the i-th row and jth column is connected to the second sub-data line DEj in the jth column data line , Then the sub-pixels in the i+1th row and jth column are connected to the first sub-data line DOj in the jth column data line.
  • the arrangement of the first sub-data line and the second sub-data line in adjacent data lines is opposite, that is, when the first sub-data line DOi of the data line Di of the i-th column is located in the i-th column.
  • the second sub-data line DEi of the data line Di of the i-th column is located on the second side of the sub-pixel of the i-th column
  • the second sub-data line DEi+1 of the data line Di+1 of the i+1-th column is located
  • the first sub-data line DOi+1 of the data line Di+1 in the i+1th column is located on the second side of the sub-pixel in the i+1th column; or when the data line Di in the i+1th column is
  • the first sub-data line DOi of the i-th column is located on the second side of the sub-pixel, and the second sub-data line DEi of the i-th column of data
  • the display substrate may include: a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13, which are sequentially disposed on the base 10, gate lines G, The reset signal line Reset, the light emission control signal line EM, and the initial signal line Vinit.
  • the gate line G, the reset signal line Reset, the light emission control signal line EM, the first electrode C1 of the storage capacitor and the gate electrode of the transistor are arranged in the same layer, the second electrode C2 of the storage capacitor and the initial signal line Vinit are arranged in the same layer, and the data line D ,
  • the power supply VDD line and the source and drain electrodes of the transistor are arranged in the same layer, and the source and drain electrodes of the transistor include the first electrode and the second electrode of the transistor.
  • the first insulating layer 11 is provided between the active region 21 of the transistor and the gate electrode of the transistor, and the second insulating layer 12 is provided between the gate electrode of the transistor and the second electrode C2 of the storage capacitor,
  • the third insulating layer 13 is provided between the second electrode C2 of the storage capacitor and the data line.
  • the gate electrode of the transistor, the source and drain electrodes of the transistor, the data line D, and the power line VDD are made of metal, for example, metal materials such as silver, aluminum, or copper, and the present disclosure does not do anything about this. limited.
  • the active region 21 is made of polysilicon, which is not limited in the present disclosure.
  • the present disclosure ensures that the power supply signals provided by the power supply lines in all sub-pixels in the same row are the same through the second electrodes of the storage capacitors connected to each other and the semiconductor layers connected to each other, avoiding poor display of the display substrate, and ensuring the display of the display substrate effect.
  • the second electrode of the storage capacitor and the semiconductor layer are multiplexed as a power connection line to transmit the power signal of the power line. Because the distance between the active area of the transistor and the data line is greater than the distance between the second electrode of the storage capacitor and the data line Therefore, the technical solution of the present disclosure increases the distance between part of the power line and the data line, reduces the load of the data line, thereby reduces the power consumption of the display substrate and shortens the writing time of the data signal.
  • the active regions of adjacent sub-pixels located in the same column are connected to each other through the third connection part.
  • the pixel structure of the sub-pixel located in the i-th row and j-th column is the same as the pixel structure of the sub-pixel located in the i+1-th row and j+1-th column.
  • adjacent power supply lines are symmetrical to each other, and the power supply line VDDi of the i-th column and the power supply line VDDi+1 of the i+1-th column are symmetrically arranged along the extending direction of the data line.
  • the power supply line VDD has a broken line shape.
  • each pixel in the display substrate may include four sub-pixels, and the pixels may include a first pixel and a second pixel.
  • the first pixel the second electrode of the storage capacitor in the i-th sub-pixel and the second electrode of the storage capacitor in the i+1-th sub-pixel are connected to each other through the first connecting portion, and the active area of the transistor in the i-th sub-pixel is connected to The active area of the transistor in the (i+1)th sub-pixel is disconnected, the active area of the transistor in the second sub-pixel and the active area of the transistor in the third sub-pixel are connected to each other through the third connecting portion, and in the second sub-pixel The second electrode of the storage capacitor is disconnected from the second electrode of the storage capacitor in the third sub-pixel.
  • the second electrode of the storage capacitor in the second sub-pixel and the second electrode of the storage capacitor in the third sub-pixel are connected to each other through the first connecting portion, and the active area of the transistor in the second sub-pixel is connected to the third
  • the active area of the transistor in the sub-pixel is disconnected, the active area of the transistor in the i-th sub-pixel and the active area of the transistor in the i+1-th sub-pixel are connected to each other through a third connection portion, and the storage capacitor in the i-th sub-pixel
  • the second electrode of is disconnected from the second electrode of the storage capacitor in the (i+1)th sub-pixel.
  • i is an odd number less than 4.
  • the 17 is an example of two pixels arranged in the column direction.
  • the pixel located above is the first pixel, and the pixel located below is the second pixel.
  • the present disclosure does not make any limitation on this, because the adjacent sub-pixels
  • the pixel structure is symmetrical, so the first pixel in the display substrate is arranged between adjacent second pixels, and the second pixel is arranged between adjacent first pixels.
  • FIG. 19 is a partial top view of sub-pixels in another display substrate provided by the present disclosure, excluding power supply lines, data lines, and source and drain electrodes of transistors.
  • FIG. 20 is a partial top view of sub-pixels in another display substrate provided by the present disclosure. Another part of the top view, including only the film layer where the second electrode of the storage capacitor is located and the film layer where the data line is located,
  • FIG. 21 is another part of the top view of the sub-pixels in another display substrate provided by the present disclosure, which only includes the active transistors The film layer where the zone and the data line are located.
  • an eleventh via V11 is provided on the third insulating layer in the display substrate.
  • the orthographic projection of the second electrode C2 of the storage capacitor on the substrate includes the orthographic projection of the eleventh via V11 on the substrate, and the power line passes through The eleventh via V11 is connected to the second electrode C2 of the storage capacitor.
  • the number of the eleventh via V11 is at least one. Specifically, the greater the number of the eleventh via V11, the better the conductivity between the power line and the second electrode of the storage capacitor.
  • a twelfth via V12 is provided in the first insulating layer, the second insulating layer, and the third insulating layer in the display substrate.
  • the orthographic projection of the twelfth via V12 on the substrate and the orthographic projection of the third connecting portion 22 on the substrate have an overlapping area, and the power line It is connected to the third connecting portion 22 of the transistor through the twelfth via V12.
  • the number of the twelfth via hole V12 is at least one, and the greater the number of via holes, the better the conductivity of the components connected through the via holes.
  • FIGS. 19 to 21 show two eleventh via holes V11, and one twelfth via hole V12 is taken as an example for description, and the present disclosure does not make any limitation on this.
  • the conductive layers of multiple sub-pixels can be connected to each other only through the semiconductor layer, or the conductive layers of multiple sub-pixels can be connected to each other through only the first metal layer, or The conductive layers of multiple sub-pixels can be connected to each other only through the second metal layer, or the conductive layers of multiple sub-pixels can be connected to each other only through the third metal layer, so that the power lines of the sub-pixels in the same row can be driven by The circuits are connected to each other in the extending direction of the gate line, which will not be repeated here.
  • FIG. 22 is a flowchart of another method for manufacturing a display substrate provided by the present disclosure, as shown in FIG. 22 As shown, another method for manufacturing a display substrate provided by the present disclosure includes the following steps:
  • Step B11 Provide a substrate.
  • Step B12 forming a plurality of sub-pixels, a plurality of columns of power lines, and data lines arranged on the same layer as the power lines on the substrate.
  • each sub-pixel may include a driving circuit; the driving circuit may include a plurality of transistors and a storage capacitor; the storage capacitor may include a first electrode and a second electrode disposed oppositely; The second electrode is close to the side of the substrate, and the power line is located on the side of the second electrode of the storage capacitor away from the substrate.
  • the power supply line is respectively connected to the second electrode of the storage capacitor and the third connecting portion of the semiconductor layer, and the second electrode of the storage capacitor of each sub-pixel is adjacent to one located in the same row.
  • the second electrode of the storage capacitor of the sub-pixel is connected through the first connecting portion, and the active area of the transistor of each sub-pixel is connected with the active area of the transistor of another adjacent sub-pixel located in the same row through the third connecting portion.
  • the manufacturing method of another display substrate provided by the present disclosure is used to manufacture another display substrate provided in the above-mentioned embodiment, and its implementation principle and effect are similar, and will not be repeated here.
  • each pixel includes four sub-pixels.
  • FIG. 23 is a schematic diagram of manufacturing the active region of another display substrate provided by the present disclosure
  • FIG. 24 is a schematic diagram of manufacturing the first insulating layer and the first metal layer of another display substrate provided by the present disclosure
  • FIG. 25 is provided for this disclosure
  • the second insulating layer and the second metal layer of another display substrate are manufactured in a schematic diagram.
  • FIG. 26 is a schematic diagram of manufacturing the third insulating layer of another display substrate provided by the present disclosure.
  • the display substrate Production methods can include:
  • step 1001 a substrate is provided, and a semiconductor layer is formed on the substrate, as shown in FIG. 23.
  • the semiconductor layer of each sub-pixel may include a first active region to a seventh active region, and the first active region to the seventh active region are an integral structure connected to each other.
  • the positions of the first active region to the seventh active region are similar to the foregoing embodiment, and will not be repeated here.
  • the semiconductor layers of adjacent sub-pixels are mirror-symmetrical about the center line.
  • the shape of the semiconductor layer of the sub-pixel in the i-th row and the j-th column is the same as that of the sub-pixel in the i+1-th row and the j+1-th column.
  • the semiconductor layer shape of the sub-pixel in the i-th row and j+1-th column is the same as that of the i+1-th row and j
  • the semiconductor layers of the sub-pixels in the columns have the same shape.
  • the semiconductor layer of each sub-pixel is connected to the semiconductor layer of another adjacent sub-pixel located in the same row through a third connecting portion, and the semiconductor layer of each sub-pixel is connected to the semiconductor layer of the adjacent sub-pixel located in the same column.
  • the semiconductor layers are connected to each other.
  • the semiconductor layer of at least one sub-pixel further includes a third connection part 22.
  • the semiconductor layer of the j-th column of sub-pixels is disconnected from the semiconductor layer of the j+1-th column of sub-pixels, and the semiconductor layer of the j+1-th column of sub-pixels and the semiconductor layer of the j+2th column of sub-pixels pass through the third
  • the connecting portion 22 is connected to each other, and the semiconductor layer of the sub-pixel in the j+2th column is disconnected from the semiconductor layer of the sub-pixel in the j+3th column.
  • the sub-pixel in the i+1th row, the semiconductor layer of the j-th column sub-pixel and the semiconductor layer of the j+1-th column sub-pixel are connected to each other through the third connecting portion 22, the semiconductor layer of the j+1-th column sub-pixel and the j+2th column sub-pixel.
  • the semiconductor layer of the sub-pixel in the j+2 column and the semiconductor layer of the sub-pixel in the j+3 column are connected to each other through the third connecting portion 22.
  • the first end of the third connecting portion 22 is connected to the active region 105 of the fifth transistor in the sub-pixel, and the second end of the third connecting portion 22 is connected to the fifth transistor in the adjacent sub-pixel.
  • the source area 105 is connected.
  • the orthographic projection of the third connecting portion 22 on the substrate and the orthographic projection of the subsequently formed data line and power line on the substrate respectively have overlapping areas.
  • the third connection portion 22 of the semiconductor layer may be multiplexed as a power connection line to transmit the power signal of the power line.
  • the semiconductor layer of the exemplary embodiment of the present disclosure has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.
  • Step 1002 forming a first insulating layer on the semiconductor layer, and forming a first metal layer on the first insulating layer, as shown in FIG. 24.
  • the first metal layer may include a gate line G, a reset signal line Reset, an emission control signal line EM, and a first electrode C1 of a storage capacitor.
  • the gate line G, the reset signal line Reset, and the emission control line EM extend in the first direction, and the gate line G is disposed between the reset signal line Reset and the emission control line EM.
  • the first electrode C1 of the storage capacitor can be rectangular, and the corners of the rectangular shape can be chamfered, which is arranged between the gate line G and the light-emitting control line EM.
  • the orthographic projection of the first electrode C1 on the substrate and the third active There are overlapping areas in the orthographic projections of the regions on the substrate.
  • the first plate C1 simultaneously serves as the gate electrode of the third transistor.
  • the gate line G, the reset signal line Reset, and the light emission control line EM may be provided with unequal widths.
  • the gate line G is provided with a gate block protruding toward the reset side of the reset signal line, and the orthographic projection of the gate block on the substrate and the orthographic projection of the second active region on the substrate overlap to form a double gate structure.
  • the first metal layer can be used as a shield to conduct a conductive process on the semiconductor layer, and the semiconductor layer in the region shielded by the first metal layer forms the first transistor T1 to the seventh transistor.
  • the semiconductor layer in the region not covered by the first metal layer is conductive.
  • the first metal layer of the exemplary embodiment of the present disclosure has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.
  • Step 1003 forming a second insulating layer on the first metal layer, and forming a second metal layer on the second insulating layer, as shown in FIG. 25.
  • the second metal layer may include: the initial signal line Vinit and the second electrode C2 of the storage capacitor.
  • the initial signal line Vinit extends in the first direction and is disposed on a side of the reset signal line Reset away from the gate line G.
  • the outline of the second electrode C2 of the storage capacitor in each sub-pixel may be rectangular and located between the gate line G and the emission control line EM.
  • the outline of the second electrode C2 may be rectangular, the corners of the rectangular shape may be chamfered, and the orthographic projection of the second electrode C2 on the substrate and the orthographic projection of the first electrode C1 on the substrate exist. Overlapping area.
  • An opening is provided in the middle of the second electrode C2, and the opening may be rectangular, so that the second electrode C2 forms a ring structure. The opening exposes the second insulating layer covering the first electrode C1, and the orthographic projection of the first electrode C1 on the substrate includes the orthographic projection of the opening on the substrate.
  • the second electrode C2 of the sub-pixel in the i-th row and the j-th column and the second electrode C2 of the i-th row and the j+1-th column sub-pixel are an integrated structure connected to each other through the first connecting portion C3, and the i-th row
  • the second electrode C2 of the sub-pixel in the j+1 column is disconnected from the second electrode C2 of the sub-pixel in the i-th row and j+2 column.
  • the second electrode C2 of the sub-pixel in the i-th row and j+2 column is connected to the second electrode C2 of the sub-pixel in the i-th row and j+2 column.
  • the second electrodes C2 of the sub-pixels of the j+3 column have an integral structure connected to each other through the first connection portion C3.
  • the second electrode C2 of the sub-pixel in row i+1 and column j is disconnected from the second electrode C2 of the sub-pixel in row i+1 and column j+1.
  • the second electrode C2 of the sub-pixel in row i+1 and column j+1 is disconnected.
  • the electrode C2 and the second electrode C2 of the sub-pixel in the i+1th row and j+2th column are an integrated structure connected to each other through the first connecting portion C3.
  • the second electrode C2 of the sub-pixel in the i+1th row and j+2th column is connected to the The second electrode C2 of the sub-pixel in row i+1 and column j+3 is in an off setting.
  • This structure allows the second electrodes C2 of adjacent sub-pixels to be multiplexed as power signal lines, which can ensure that the power signals provided by the power lines of adjacent sub-pixels are the same, avoid display defects of the display substrate, and ensure the display effect of the display substrate.
  • the second metal layer may further include a shielding electrode C4.
  • the orthographic projection of the shielding electrode C4 on the substrate overlaps with the orthographic projection of the subsequently formed power line on the substrate.
  • the power line passes through the via hole and is shielded.
  • the electrode C4 is connected.
  • the shield electrode C4 is configured to shield the influence of the data line on the driving circuit.
  • the shape of the shield electrode C4 is a "7" shape, and includes a first part extending in a first direction and a second part extending in a second direction. The ends of the two parts close to the first part are connected to each other to form a fold line with a right angle.
  • the shield electrode C4 in the second direction, is disposed between the gate line G and the reset signal line Reset, and in the first direction, the second portion of the shield electrode C4 is disposed on the subsequently formed data line and power line. between.
  • the second portion of the shielding electrode C4 and the gate block of the first metal layer both extend in the second direction, and both have a facing area, that is, the shielding electrode C4 is close to one side of the gate block in the first direction. There is an area opposite to the edge of the gate block on the first direction side of the gate block close to the shield electrode C4.
  • the second metal layer of the exemplary embodiment of the present disclosure has a reasonable layout and a simple structure, which can ensure the display effect of the display substrate.
  • Step 1004 forming a third insulating layer on the second metal layer, the third insulating layer is provided with an eleventh via hole V11 exposing the second electrode of the storage capacitor, the first insulating layer, the second insulating layer, and the third insulating layer A twelfth via V12 exposing the third connecting portion is provided, as shown in FIG. 26.
  • the eleventh via hole V11 is configured to connect the second electrode C2 to the power line formed later
  • the twelfth via hole V12 is configured to connect the third connection portion of the semiconductor layer to the power line formed later Connect, so that the second electrode C2 connected to each other in adjacent sub-pixels and the third connecting portion connected to each other in adjacent sub-pixels are multiplexed together as a power connection line.
  • the number of the eleventh via V11 may be two, and the two eleventh vias V11 are sequentially arranged along the second direction, which can improve the reliability of the connection between the second electrode and the power line.
  • the via hole layout of the exemplary embodiment of the present disclosure is reasonable, the structure is simple, and the display effect of the display substrate can be ensured.
  • Step 1005 forming a third metal layer on the third insulating layer, as shown in FIG. 17.
  • the third metal layer includes a data line D, a power supply line VDD, and source and drain electrodes of a plurality of transistors, and the data line D includes a first sub-data line DO and a second sub-data line DE.
  • the first sub-data line DO, the second sub-data line DE, and the power supply line VDD extend in the second direction
  • the first sub-data line DO is located at one side of the sub-pixel
  • the second sub-data line DE is located at On the other side of the sub-pixel
  • the power supply line VDD is located between the first sub-data line DO and the second sub-data line DE.
  • adjacent sub-pixels located in the same column are connected to different sub-data lines.
  • the sub-pixels in the i-th row and j-th column are connected to the first sub-data line in the j-th column data line
  • the sub-pixels in the i+1-th row and j-th column are connected to the second sub-data line in the j-th column data line.
  • the sub-pixels in the i-th row and j-th column are connected to the second sub-data line in the j-th column data line
  • the sub-pixels in the i+1-th row and j-th column are connected to the first sub-data line in the j-th column data line.
  • the power line VDD of each sub-pixel is connected to the second electrode C2 through the eleventh via V11, and the power line VDD of each sub-pixel is connected to the third connection portion of the semiconductor layer through the twelfth via V12. connection.
  • the second electrode C2 of the storage capacitor of one adjacent sub-pixel is connected to each other
  • the third connecting portion of the semiconductor layer of another adjacent sub-pixel is connected to each other
  • the second connected to each other in adjacent sub-pixels is connected to each other.
  • the electrode C2 and the interconnected semiconductor layers in adjacent sub-pixels are multiplexed together as a power connection line, so that the power signal provided to each sub-pixel is the same, and the display effect of the display substrate is ensured.
  • the power supply line VDD of each sub-pixel may be a broken line.
  • the power supply line VDD of each sub-pixel may include a first power supply part, a second power supply part, and a third power supply part that are sequentially connected.
  • the first end of the first power supply part is connected to the second end of the third power-supply part in the sub-pixel in the i-1th row and jth column.
  • the second end of the power supply unit extends along the second direction and is connected to the first end of the second power supply unit; the second end of the second power supply unit extends along the oblique direction, and is connected to the first end of the third power supply unit, and is inclined
  • the direction and the second direction have an included angle, and the included angle can be greater than 0 degrees and less than 90 degrees; the second end of the third power supply part extends along the second direction and is located in the sub-pixel in the i+1th row and the jth column.
  • the first end of the first power supply unit is connected.
  • the first power source part may be a straight line of equal width
  • the second power source part may be a diagonal line of variable width
  • the third power source part may be a straight line of equal width.
  • the first power part and the second power part are parallel to the first sub-data line (or the second sub-data line)
  • the angle between the second power part and the first power part may be greater than 90 degrees and less than 180 degrees
  • the second The included angle between the power supply part and the third power supply part may be greater than 90 degrees and less than 180 degrees.
  • the width of the third power supply part may be smaller than the width of the first power supply part.
  • the power line VDD adopts a variable-width folding line arrangement, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance of the power line VDD and the data line.
  • the display substrate may include a fourth metal layer, and the data line D, the power supply line VDD, and the source and drain electrodes of a plurality of transistors may be located on different metal layers, which is not limited in the present disclosure.
  • the present disclosure multiplexes the second plate of the storage capacitor and the active area of the transistor as a power connection line to transmit the power signal of the power line. Since the active area of the transistor is far away from the data line, the solution of the present disclosure is increased. The distance between a part of the power connection line and the data line is increased, and the load of the data line is reduced, thereby reducing the power consumption of the display substrate and shortening the writing time of the data signal.
  • the present disclosure also provides a display device.
  • the display device includes the aforementioned display substrate.
  • the display substrate may be an OLED display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
  • the embodiment of the present invention is not limited thereto.
  • the display substrate is the display substrate provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.

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Abstract

一种显示基板及其制作方法、显示装置。显示基板包括：在平行于显示基板的平面内，所述显示基板包括设置在基底上的多条栅线、多条数据线、多条电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；在垂直于显示基板的平面内，所述显示基板包括基底和多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。

Description

一种显示基板及其制作方法、显示装置
本公开要求于2019年11月7日提交中国专利局、公开号为201911082352.5、发明名称为“一种显示基板及其制作方法、显示装置”的中国专利公开的优先权，以及要求于2019年10月29日提交中国专利局、公开号为201911038883.4、发明名称为“一种显示基板及其制作方法、显示装置”的中国专利公开的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本文涉及显示技术领域，具体涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Device，简称OLED)显示基板，是一种与传统的液晶显示(Liquid Crystal Display，简称LCD)不同的显示基板，具备主动发光、温度特性好、功耗小、响应快、可弯曲、超轻薄和成本低等优点。因此已经成为新一代显示装置的重要发展发现之一，并且受到越来越多的关注。
为了实现OLED显示基板的高频驱动，相关技术中提出了一种双数据线的OLED显示基板，即同一列像素与两条数据线连接。然而相关技术中的OLED显示基板虽然能够实现高频驱动，但分辨率普遍较低，无法满足市场关于显示器件高分辨率的需求。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一种显示基板，在平行于显示基板的平面内，所述显示基板包括设置在基底上的多条栅线、多条数据线、多条电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；在垂直于显示基板的平面内，所述显示基板包 括基底和设置在所述基底上的多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。
在示例性实施方式中，在所述数据线延伸方向，所述电源线包括多个依次连接的子电源线，至少一个子电源线设置在一个子像素中；至少一个子像素的子电源线包括依次连接的多个电源部，至少一个电源部和与所述电源部相连接的电源部之间存在大于90度且小于180度的夹角。
在示例性实施方式中，所述至少一个电源部和与所述电源部相连接的电源部中，其中一个电源部与所述数据线平行设置。
在示例性实施方式中，所述子电源线包括第一电源部、第二电源部和第三电源部；所述第二电源部配置为连接所述第一电源部和第三电源部，所述第一电源部和第三电源部与所述数据线平行设置，所述第二电源部与所述第一电源部之间的夹角大于90度且小于180度，所述第二电源部与所述第三电源部之间的夹角大于90度且小于180度。
在示例性实施方式中，所述第一电源部与位于相同列上一行子像素中的第三电源部连接，所述第三电源部与位于相同列下一行子像素中的第一电源部连接。
在示例性实施方式中，所述第一电源部沿着数据线延伸方向延伸的长度大于所述第一电源部的平均宽度，所述第二电源部沿着倾斜方向延伸的长度大于所述第二电源部的平均宽度，所述第三电源部沿着数据线延伸方向延伸的长度大于所述第三电源部的平均宽度；所述倾斜方向是所述第二电源部与所述第一电源部之间具有所述夹角的方向。
在示例性实施方式中，所述第三电源部的平均宽度小于所述第一电源部的平均宽度。
在示例性实施方式中，所述第一电源部靠近所述第三电源部栅线延伸方向上一侧的边缘与所述第三电源部靠近所述第一电源部栅线延伸方向上一侧的边缘之间的距离，与所述第三电源部的平均宽度相当。
在示例性实施方式中，所述显示基板还包括第一连接部，至少一个子像素中存储电容的第二电极与栅线延伸方向相邻子像素中存储电容的第二电极 通过所述第一连接部相互连接；至少一个子像素中，所述第二电源部在基底上的正投影与所述存储电容的第二电极在基底上的正投影存在重叠区域，或者，所述第二电源部在基底上的正投影与所述第一连接部在基底上的正投影存在重叠区域。
在示例性实施方式中，所述第二电源部在基底上的正投影与所述存储电容的第一电极在基底上的正投影存在重叠区域。
在示例性实施方式中，所述第二电源部在基底上的正投影与所述栅线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述多个晶体管包括第二晶体管，所述第一电源部在基底上的正投影与所述第二晶体管在基底上的正投影存在重叠区域。
在示例性实施方式中，所述显示基板还包括设置在所述第四导电层上的第五绝缘层和设置在所述第五绝缘层上的第五导电层，所述第五绝缘层上设置有第五过孔，所述第五过孔配置为使所述第五导电层与所述第四导电层连接；所述第五过孔在基底上的正投影与所述子电源线在基底上的正投影不存在重叠区域。
在示例性实施方式中，至少一个子像素中，所述第五过孔在基底上的正投影与所述子电源线中第一电源部在所述数据线延伸方向的虚拟延长线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有第八过孔，所述第八过孔配置为使所述数据线将数据信号写入到所述半导体层；所述第八过孔在基底上的正投影与所述子电源线中第一电源部和第二电源部在基底上的正投影不存在重叠区域。
在示例性实施方式中，至少一个子像素中，所述第八过孔在基底上的正投影与所述子电源线中第三电源部在所述数据线延伸方向的虚拟延长线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述电源线设置在所述第三导电层，或者设置在所述第四导电层，所述电源线与所述数据线同层设置。
在示例性实施方式中，所述电源线设置在所述第三导电层，所述数据线设置在所述第四导电层，或者，所述数据线设置在所述第三导电层，所述电源线设置在所述第四导电层。
在示例性实施方式中，所述显示基板还包括第一连接部，至少一个子像素中存储电容的第二电极与栅线延伸方向相邻子像素中存储电容的第二电极通过所述第一连接部相互连接。
在示例性实施方式中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极通过所述第一连接部相互连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极直接连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极通过所述第一连接部相互连接；另一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极直接连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极通过所述第一连接部相互连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极直接连接。
在示例性实施方式中，第1子像素中半导体层与第2子像素中半导体层间隔设置，第2子像素中半导体层与第3子像素中半导体层间隔设置，第3子像素中半导体层与第4子像素中半导体层间隔设置。
在示例性实施方式中，所述第三导电层包括第五晶体管的第一极；第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极间隔设置，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极间隔设置，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极间隔设置。
在示例性实施方式中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极通过所述第一连接部相互连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极断开设置，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极通过所述第一连接部相互连接；另一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极断开设置，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极通过所述第一连接部相互连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极断开设置。
在示例性实施方式中，所述第三导电层包括第五晶体管的第一极和第二 连接部；一行的第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极断开设置，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极通过所述第二连接部相互连接，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极断开设置；另一行的第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极通过所述第二连接部相互连接，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极断开设置，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极通过所述第二连接部相互连接。
在示例性实施方式中，在栅线延伸方向，所述电源线通过所述存储电容的第二电极和第五晶体管的第一极相互连接。
在示例性实施方式中，所述第四绝缘层上设置有暴露出所述第五晶体管的第一极的第一过孔，所述第三绝缘层上设置有暴露出所述存储电容的第二电极的第二过孔，所述电源线通过所述第一过孔与所述第五晶体管的第一极连接，所述第五晶体管的第一极通过所述第二过孔与所述存储电容的第二电极连接。
在示例性实施方式中，至少一个子像素中，所述第一过孔的数量为一个，所述第二过孔的数量为多个，多个第二过孔沿所述数据线延伸方向设置；所述电源线在基底上的正投影包含所述第一过孔在基底上的正投影，所述第五晶体管的第一极在基底上的正投影包含所述第二过孔在基底上的正投影。
在示例性实施方式中，所述半导体层包括第三连接部；一行的第1子像素中半导体层与第2子像素中半导体层断开设置，第2子像素中半导体层与第3子像素中半导体层通过所述第三连接部相互连接，第3子像素中半导体层与第4子像素中半导体层断开设置；另一行的第1子像素中半导体层与第2子像素中半导体层通过所述第三连接部相互连接，第2子像素中半导体层与第3子像素中半导体层断开设置，第3子像素中半导体层与第4子像素中半导体层通过所述第三连接部相互连接。
在示例性实施方式中，在栅线延伸方向，所述电源线通过所述半导体层的第三连接部和存储电容的第二电极相互连接。
在示例性实施方式中，所述第三绝缘层上设置有暴露出所述存储电容的 第二电极的第十一过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出所述半导体层的第三连接部的第十二过孔，所述电源线通过所述第十一过孔与所述存储电容的第二电极连接，所述电源线通过所述第十二过孔与所述半导体层的第三连接部连接。
在示例性实施方式中，至少一个子像素中，所述第十一过孔的数量为一个，所述第十二过孔的数量为多个，多个第十二过孔沿所述数据线延伸方向设置；所述电源线在基底上的正投影包含所述第十一过孔和第十二过孔在基底上的正投影。
在示例性实施方式中，所述多个晶体管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；至少一个子像素中，所述半导体层至少包括第一晶体管所在位置的第一有源区、第二晶体管所在位置的第二有源区、第三晶体管所在位置的第三有源区、第四晶体管所在位置的第四有源区、第五晶体管所在位置的第五有源区、第六晶体管所在位置的第六有源区和第七晶体管所在位置的第七有源区，所述第一有源区、第二有源区、第三有源区、第四有源区、第五有源区、第六有源区和第七有源区为一体结构。
在示例性实施方式中，所述第二有源区与第一有源区之间栅线延伸方向的距离，小于所述第二有源区与第七有源区之间栅线延伸方向的距离。
在示例性实施方式中，沿着写入数据信号的数据线到电源线的方向，所述第七有源区和第一有源区依次设置。
在示例性实施方式中，至少一个子像素包括沿数据线延伸方向依次设置的第一区域、第二区域和第三区域；所述第一有源区和第七有源区设置在所述第一区域内远离第二区域的一侧，所述第二有源区和第四有源区设置在所述第一区域内靠近第二区域的一侧；所述第三有源区设置在所述第二区域内；所述第五有源区和第六有源区设置在所述第三区域内。
在示例性实施方式中，所述第一晶体管的第一极与初始信号线连接，第一晶体管T1的第二极与所述存储电容的第一电极连接，所述第二晶体管的第一极与存储电容的第一电极连接，所述第二晶体管的第二极与第六晶体管的第二极连接，所述第三晶体管的第一极与第四晶体管的第二极连接，所述第三晶体管的第二极与第六晶体管的第二极连接，所述第四晶体管的第一极 与数据线连接，所述第五晶体管的第一极与电源线连接，所述第五晶体管的第二极与第三晶体管的第一极连接，所述第六晶体管的第二极与发光器件的阳极连接，所述第七晶体管的第一极与初始信号线连接，所述第七晶体管的第二极与发光器件的阳极连接；所述第一有源区分别与第二有源区和第七有源区连接，所述第二有源区分别与第三有源区和第六有源区连接，所述第四有源区分别与第三有源区和第五有源区连接。
在示例性实施方式中，在栅线延伸方向，相邻子像素的半导体层互为对称关系。
在示例性实施方式中，至少存在一个包括2*2个子像素的区域，一行的第1子像素中半导体层形状与另一行的第2子像素中半导体层形状相同，一行的第2子像素中半导体层形状与另一行的第1子像素中半导体层形状相同。
在示例性实施方式中，所述半导体层包括第三连接部，至少一个子像素中半导体层通过所述第三连接部与栅线延伸方向相邻子像素中半导体层连接。
在示例性实施方式中，所述第三连接部与第五晶体管的有源区连接。
在示例性实施方式中，所述第三连接部在基底上的正投影与所述电源线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出所述第三连接部的第十二过孔，所述电源线通过所述第十二过孔与所述第三连接部连接。
在示例性实施方式中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中半导体层与第2子像素中半导体层断开设置，第2子像素中半导体层与第3子像素中半导体层通过所述第三连接部相互连接，第3子像素中半导体层与第4子像素中半导体层断开设置；另一行的第1子像素中半导体层与第2子像素中半导体层通过所述第三连接部相互连接，第2子像素中半导体层与第3子像素中半导体层断开设置，第3子像素中半导体层与第4子像素中半导体层通过所述第三连接部相互连接。
在示例性实施方式中，至少存在一个像素列，在所述数据线延伸方向，所述数据线包括多个依次连接的子数据线；至少存在一个子像素，所述子像 素与栅线延伸方向相邻子像素之间设置有两条子数据线。
在示例性实施方式中，所述两条子数据线相互平行。
在示例性实施方式中，至少一个子像素内，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出半导体层的第八过孔，所述第四绝缘层上设置有暴露出第四晶体管的第一极的第三过孔，所述数据线通过所述第三过孔与第四晶体管的第一极连接，所述第四晶体管的第一极通过所述第八过孔与半导体层连接。
在示例性实施方式中，在栅线延伸方向，相邻子像素的第八过孔互为对称关系。
在示例性实施方式中，所述数据线设置所述第三导体层，所述电源线设置所述第三导体层。
在示例性实施方式中，所述数据线设置在所述第四导体层，所述电源线设置在所述第三导体层或第四导体层。
在示例性实施方式中，至少一列子像素中，所述数据线包括第一子数据线和第二子数据线，所述第一子数据线和第二子数据线分别位于该列子像素的两侧。
在示例性实施方式中，所述电源线位于所述第一子数据线和第二子数据线之间。
在示例性实施方式中，在栅线延伸方向，相邻子像素的像素结构互为对称关系。
在示例性实施方式中，至少存在一个包括2*2个子像素的区域，一行的第1子像素中像素结构与另一行的第2子像素中像素结构相同，一行的第2子像素中像素结构与另一行的第1子像素中像素结构相同。
在示例性实施方式中，所述显示基板还包括复位信号线、发光控制线和初始信号线；所述半导体层至少包括多个晶体管的有源区，所述第一导体层至少包括栅线、发光控制线、复位信号线、存储电容的第一电极和多个晶体管的栅电极，所述第二导体层至少包括初始信号线和存储电容的第二电极；所述第三导体层至少包括多个晶体管的源漏电极，所述第四导体层至少包括数据线和电源线。
在示例性实施方式中，至少一个子像素包括沿着数据线延伸方向依次设 置的第一区域、第二区域和第三区域；所述栅线、初始信号线、复位信号线位于所述第一区域，所述存储电容的第一电极和第二电极位于所述第二区域，所述发光控制线位于所述第三区域。
在示例性实施方式中，所述第二导体层还包括屏蔽电极，至少一个子像素中，所述屏蔽电极在基底上的正投影与所述电源线在基底上的正投影存在重叠区域。
在示例性实施方式中，所述电源线通过过孔与所述屏蔽电极连接。
在示例性实施方式中，在数据线延伸方向，所述屏蔽电极设置在栅线与复位信号线之间。
在示例性实施方式中，所述屏蔽电极包括沿栅线延伸方向延伸的第一部和沿数据线延伸方向延伸的第二部，所述第一部靠近第二部的一端与所述第二部靠近第一部的一端相互连接。
在示例性实施方式中，所述第一导体层还包括沿数据线延伸方向延伸的栅极块，所述栅极块与所述栅线连接；在数据线延伸方向，所述栅极块与所述屏蔽电极的第二部存在正对区域。
在示例性实施方式中，所述多个晶体管的源漏电极包括第二晶体管的第一极，所述第二绝缘层和第三绝缘层上设置有暴露出所述存储电容的第一电极的第七过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出第二晶体管的有源区的第九过孔，所述第二晶体管的第一极的一端通过第七过孔与所述存储电容的第一电极连接，另一端通过第九过孔与第二晶体管的有源区连接。
在示例性实施方式中，所述第二晶体管的第一极在基底上的正投影与所述栅线在基底上的正投影存在重叠区域，所述第二晶体管的第一极在基底上的正投影与所述发光控制线、复位信号线和初始信号线在基底上的正投影没有重叠区域。
在示例性实施方式中，所述多个晶体管的源漏电极包括第一晶体管的第一极，所述第三绝缘层上设置有暴露出初始信号线的第六过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出第一晶体管的有源区的第十过孔，所述第一晶体管的第一极的一端通过第六过孔与所述初始信号线连接，另一端通过第十过孔与第一晶体管的有源区连接。
在示例性实施方式中，所述第一晶体管的第一极在基底上的正投影与所述复位信号线在基底上的正投影存在重叠区域，所述所述第一晶体管的第一极在基底上的正投影与所述栅线和发光控制线在基底上的正投影没有重叠区域。
在示例性实施方式中，所述显示基板还包括设置在所述第四导电层上的第五绝缘层和设置在所述第五绝缘层上的第五导电层；所述第四导体层中还包括连接电极，所述多个晶体管的源漏电极包括第六晶体管的第二极；所述第四绝缘层设置有暴露出第六晶体管的第二极的第四过孔，所述第五绝缘层上设置有暴露出连接电极的第五过孔，所述连接电极通过第四过孔与第六晶体管的第二极连接，所述第五导体层通过第五过孔与所述连接电极连接。
在示例性实施方式中，所述连接电极在基底上的正投影与第二晶体管的第一极在基底上的正投影存在重叠区域。
在示例性实施方式中，至少一个子像素至少包括：暴露出第五晶体管的第一极的第一过孔，所述第一过孔配置为使第五晶体管的第一极与所述电源线连接；暴露出存储电容的第二电极的第二过孔，所述第二过孔配置为使第二电极与第五晶体管的第一极连接；暴露出第四晶体管的第一极的第三过孔，所述第三过孔配置为使第四晶体管的第一极与所述数据线连接；暴露出第六晶体管的第二极的第四过孔，所述第四过孔配置为使第六晶体管的第二极与连接电极连接；暴露出连接电极的第五过孔，所述第五过孔配置为使连接电极与第五导体层的阳极连接；暴露出初始信号线的第六过孔，所述第六过孔配置为使初始信号线与第一晶体管的第一极连接；暴露出存储电容的第一电极的第七过孔，所述第七过孔配置为使第一电极与第二晶体管的第一极连接；暴露出第四晶体管的有源区的第八过孔，所述第八过孔配置为使第四晶体管的有源区与第四晶体管的第一极连接；暴露出第二晶体管的有源区的第九过孔，所述第九过孔配置为使第二晶体管的有源区与第二晶体管的第一极连接；暴露出第一晶体管的有源区的第十过孔，所述第十过孔配置为使第一晶体管的有源区与第一晶体管的第一极连接。
在示例性实施方式中，至少一个子像素至少包括：暴露出存储电容的第二电极的第十一过孔，所述第十一过孔配置为使第二电极与电源线连接；暴露出第三连接部的第十二过孔，所述第十二过孔配置为使第三连接部与电源 线连接。
显示装置，包括前述的显示基板。
一种显示基板的制作方法，配置为制作如权利要求1至69任一项所述的显示基板，在平行于显示基板的平面内，所述显示基板包括设置在基底上的栅线、数据线、电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；所述制作方法包括：
提供一基底；
在所述基底形成多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开提供的显示基板的结构示意图；
图2为本公开提供的一种显示基板中一个子像素的侧视图；
图3为本公开提供的一种显示基板中一个子像素的俯视图；
图4A为本公开提供的驱动电路的等效电路图；
图4B为本公开提供的驱动电路的工作时序图；
图5为本公开提供的一种显示基板中多个子像素的一个俯视图；
图6A为实施方式一对应的子像素的一个俯视图；
图6B为实施方式一对应的子像素的另一俯视图；
图7A为实施方式一对应的第二金属层的俯视图；
图7B为实施方式一对应的第三金属层的俯视图；
图8A为实施方式二对应的子像素的一个俯视图；
图8B为实施方式二对应的子像素的另一俯视图；
图9A为实施方式二对应的第二金属层的俯视图；
图9B为实施方式二对应的第三金属层的俯视图；
图10为本公开提供的一种显示基板中多个子像素的另一俯视图；
图11为本公开提供的一种显示基板的制作方法的流程图；
图12为本公开提供的一种显示基板的第一制作示意图；
图13为本公开提供的一种显示基板的第二制作示意图；
图14A为本公开提供的一种显示基板的一个第三制作示意图；
图14B为本公开提供的一种显示基板的另一第三制作示意图；
图15A为本公开提供的一种显示基板的一个第四制作示意图；
图15B为本公开提供的一种显示基板的另一第四制作示意图；
图16A为本公开提供的一种显示基板的一个第五制作示意图；
图16B为本公开提供的一种显示基板的另一第五制作示意图；
图17为本公开提供的另一种显示基板中多个子像素的俯视图；
图18为本公开提供的另一种显示基板中多个子像素的剖视图；
图19为本公开提供的另一种显示基板中子像素的一个部分俯视图；
图20为本公开提供的另一种显示基板中子像素的另一部分俯视图；
图21为本公开提供的另一种显示基板中子像素的又一部分俯视图；
图22为本公开提供的另一种显示基板的制作方法的流程图；
图23为本公开提供的另一种显示基板的有源区制作示意图；
图24为本公开提供的另一种显示基板的第一绝缘层和第一金属层制作示意图；
图25为本公开提供的另一种显示基板的第二绝缘层和第二金属层制作示意图；
图26为本公开提供的另一种显示基板的第三绝缘层的制作示意图。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开的精神和范围内。
除非另外定义，本发明实施例公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现 该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本文中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。本文中的“相当”，是指一个尺寸与另一个尺寸之比为0.8至1.2的状态。
本公开一些实施例提供一种显示基板，在平行于显示基板的平面内，所述显示基板包括设置在基底上的栅线、数据线、电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；在垂直于显示基板的平面内，所述显示基板包括基底和设置在所述基底上的多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。在示例性实施例中，显示基板还包括设置在所述第四导电层上的第五绝缘层和设置在所述第五绝缘层上的第五导电层。
图1为本公开提供的显示基板的结构示意图，图2为本公开提供的一种显示基板中一个子像素的侧视图，图3为本公开提供的一种显示基板中一个子像素的俯视图，如图1～3所示，在平行于显示基板的平面内，本公开提供的显示基板中设置有栅线G、数据线D、电源线VDD、复位信号线Reset、发光控制线EM、初始信号线Vinit和多个子像素P，每个子像素包括：发光器件和配置为驱动发光器件发光的驱动电路，驱动电路包括：多个晶体管和存储电容，在垂直于显示基板的平面内，显示基板包括：基底10以及设置在基底10上、且相互绝缘的半导体层20、第一金属层30、第二金属层40、第三金属层50、第四金属层60和第五金属层70，第一金属层30作为第一导电层，第二金属层40作为第二导电层，第三金属层50作为第三导电层，第四金属层60作为第四导电层，第五金属层70作为第五导电层。在示例性实施例中，显示基板包括显示区域(AA)和位于显示区域外围的边框区域，显示 区域包括多个显示子像素，边框区域包括多个虚拟(Dummy)子像素，本文所述的子像素是指显示区域的显示子像素。
在示例性实施例中，半导体层20可以包括多个晶体管的有源区，第一金属层30可以包括栅线G、发光控制线EM、复位信号线Reset、存储电容的第一电极C1和多个晶体管的栅电极，第二金属层40可以包括初始信号线Vinit和存储电容的第二电极C2；第三金属层50可以包括多个晶体管的第一极和第二极，第四金属层60可以包括数据线D和电源线VDD，第五金属层70可以包括发光器件的阳极。
在示例性实施例中，在数据线的延伸方向，数据线可以包括多个依次连接的子数据线，多个子数据线与多个子像素向对应。至少存在一个子像素，子像素与栅线延伸方向相邻子像素之间设置有两条子数据线。在示例性实施例中，所述两条子数据线相互平行。
如图1所示，在示例性实施例中，显示基板中可以设置有M行*N列子像素，N列数据线D1～DN、N列电源线VDD1～VDDN、M行栅线G1～GM、M-1行发光控制线EM1～EMM-1、复位信号线Reset以及初始信号线Vinit，显示基板还可以包括：配置为向数据线提供数据信号的数据驱动器、配置为向栅线提供扫描信号的扫描驱动器、配置为向发光控制线提供发光控制信号的发光驱动器、以及配置为向数据驱动器、扫描驱动器和发光驱动器提供驱动信号的时序控制器。
在一些可能的实现方式中，如图1所示，第i列子像素中的驱动电路与第i列数据线连接，每列数据线包括第一子数据线DO和第二子数据线DE；第i列数据线中的第一子数据线DOi和所述第二子数据线DEi分别位于第i列子像素的两侧，1≤i≤N，N为子像素的总列数。
在一些可能的实现方式中，相邻的两列子像素之间设置有两条子数据线，即相邻的两列子像素之间设置有本列子像素的第一子数据线DO和相邻列子像素的第二子数据线DE，或者，相邻的两列子像素之间设置有本列子像素的第二子数据线DE和相邻列子像素的第一子数据线DO。
例如，第i列数据线的第一子数据线Doi位于第i列子像素靠近第i+1列子像素的一侧，第i+1列数据线的第一子数据线DOi+1位于第i+1列子像 素靠近第i列子像素的一侧；或者，第i列数据线的第二子数据线DEi位于第i列子像素靠近第i+1列子像素的一侧，第i+1列数据线的第二子数据线DEi+1位于第i+1列子像素靠近第i列子像素的一侧。
在一些可能的实现方式中，基底10可以为刚性衬底或柔性衬底。刚性衬底可以为但不限于玻璃、金属萡片中的一种或多种；柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一些可能的实现方式中，半导体层20的制作材料可以为多晶硅或者金属氧化物，本公开对此不作任何限定。
在一些可能的实现方式中，第一金属层的制作材料可以为银、铝或铜等金属材料，本公开对此不作任何限定
在一些可能的实现方式中，第二金属层的制作材料可以为银、铝或铜等金属材料，本公开对此不作任何限定。
在一些可能的实现方式中，第三金属层的制作材料可以为银、铝或铜等金属材料，本公开对此不作任何限定；
在一些可能的实现方式中，第四金属层的制作材料可以为银、铝或铜等金属材料，本公开对此不作任何限定。
在一些可能的实现方式中，第五金属层的制作材料可以为银、铝或铜等金属材料，本公开对此不作任何限定。
图4A为本公开提供的驱动电路的等效电路图，图4B为本公开提供的驱动电路的工作时序图，如图4A和图4B所示，图4A是以第i列子像素和第i+1列子像素包括的驱动电路为例进行说明的，本公开提供的驱动电路可以为7T1C结构，驱动电路可以包括:第一晶体管T1～第七晶体管T7和存储电容C，其中，存储电容C包括第一电极C1和第二电极C2。
在示例性实施方式中，具体的，第一晶体管T1的栅电极与复位信号线Reset连接，第一晶体管T1的第一极与初始信号线Vinit连接，第一晶体管T1的第二极与存储电容C的第一电极C1连接，第二晶体管T2的栅电极与 栅线G连接，第二晶体管T2的第一极与存储电容C的第一电极C1连接，第二晶体管T2的第二极与第六晶体管T6的第二极连接，第三晶体管T3的栅电极与存储电容C的第一电极C1连接，第三晶体管T3的第一极与第四晶体管T4的第二极连接，第三晶体管T3的第二极与第六晶体管T6的第二极连接，第四晶体管T4的栅电极与栅线G连接，第四晶体管T4的第一极与数据线D连接，第五晶体管T5的栅电极与发光控制线EM连接，第五晶体管T5的第一极与电源线VDD连接，第五晶体管T5的第二极与第三晶体管T3的第一极连接，第六晶体管T6的栅电极与发光控制线EM连接，第六晶体管T6的第二极与发光器件的阳极连接，第七晶体管T7的栅电极与复位信号线Reset连接，第七晶体管T7的第一极与初始信号线Vinit连接，第七晶体管T7的第二极与发光器件的阳极连接，存储电容的第二电极C2与电源线VDD连接，发光器件OLED的阴极与低电平电源端VSS连接。
在示例性实施例中，第三晶体管T3为驱动晶体管，除第三晶体管T3之外的其他晶体管均为开关晶体管，第一晶体管T1至第七晶体管T7可以均为P型晶体管或者N型晶体管，本公开对此不作任何限定。
以第一晶体管T1至第七晶体管T7均为P型晶体管为例，驱动电路的工作过程可以包括：
第一阶段P1、复位阶段，复位信号线Reset提供有效电平，第一晶体管T1和第七晶体管T7导通，初始信号线Vinit提供的初始信号对第六晶体管T6的第二极的信号和第一电极C1的信号进行初始化。
第二阶段P2、写入阶段，栅线G提供有效电平，第二晶体管T2和第四晶体管T4导通，向第三晶体管T3的第一极写入数据线D提供的数据信号，并使得第二晶体管T2的栅电极和第二极的信号的电位相同，以使得第三晶体管T3导通。
第三阶段P3、发光阶段，发光控制线EM提供有效电平，第五晶体管T5和第六晶体管T6导通，电源线VDD向发光器件OLED提供驱动电流以驱动发光器件发光。
在一些可能的实现方式中，如图4A所示，本公开中的发光器件可以为OLED。
本公开提供的显示基板中设置有栅线、数据线、电源线、复位信号线、发光控制线、初始信号线和多个子像素，每个子像素包括：发光器件和配置为驱动发光器件发光的驱动电路，驱动电路可以包括：多个晶体管和存储电容；显示基板可以包括：基底以及依次设置在基底上的，且相互绝缘的半导体层、第一金属层、第二金属层、第三金属层、第四金属层和第五金属层；半导体层包括：多个晶体管的有源区，第一金属层包括：栅线、发光控制线、复位信号线、存储电容的第一电极和多个晶体管的栅电极，第二金属层包括：初始信号线和存储电容的第二电极；第三金属层包括：多个晶体管的源漏电极，第四金属层包括：数据线和电源线，第五金属层包括：发光器件的阳极，第i列子像素与第i列数据线连接，每列数据线包括：第一子数据线和第二子数据线；第i列数据线中的第一子数据线和第二子数据线分别位于第i列子像素的两侧，1≤i≤N，N为子像素的总列数。
本公开设置有五层金属层，通过将数据线和电源线与多个晶体管的源漏电极异层设置，能够减少子像素与子像素所连接的数据线所占用的体积，进而提高了高频驱动的OLED显示基板的分辨率。
在一些可能的实现方式中，如图3所示，本公开提供的显示基板中的每个子像素可以被划分为沿数据线延伸方向依次设置的第一区域R1、第二区域R2和第三区域R3。
存储电容位于第二区域R2，第一区域R1和第三区域R3分别位于第二区域R2的两侧，子像素的驱动电路连接的初始信号线Vinit、栅线G和复位信号线Reset位于第一区域R1，子像素的驱动电路连接的发光控制线EM位于第三区域R3。
位于同一列的相邻子像素的驱动电路连接不同子数据线，即若第i行第j列的子像素连接第j列数据线中的第一子数据线DOj，则第i+1行第j列的子像素连接第j列数据线中的第二子数据线Dej；若第i行第j列的子像素连接第j列数据线中的第二子数据线DEj，则第i+1行第j列的子像素连接第j列数据线中的第一子数据线DOj。
在一些可能的实现方式中，如图1和图3可知，第i列子像素的驱动电路还与第i列电源线连接，1≤i≤N。第i列电源线VDDi位于第i列数据线中 的第一子数据线DOi和第二子数据线DEi之间。
图5为本公开提供的一种显示基板中多个子像素的一个俯视图，如图5所示，位于同一行的相邻子像素的像素结构关于相邻子像素之间的两个子数据线的中心线CL相互镜像对称。位于第i行第j列的子像素的像素结构与位于第i行第j+2列的子像素的像素结构相同，位于第i行第j+1列的子像素的像素结构与位于第i行第j+3列的子像素的像素结构相同，位于第i行第j列的子像素的像素结构与位于第i+1行第j+1列的子像素的像素结构相同，位于第i行第j+1列的子像素的像素结构与位于第i+1行第j列的子像素的像素结构相同。本文中，像素结构相同包括但不限于两者的整体形状、各个部分的连接关系以及信号流向的走势相同。
如图5所示，相邻两列电源线关于位于相邻两列电源线之间的中心线镜像对称，即相邻子像素的电源线互为对称关系。位于第i行第j列子像素和第i行第j+1列子像素之间的两个子数据线的中心线CL与位于第j列电源线和第j+1列电源线之间的中心线可以为同一中心线。
在一些可能的实现方式中，如图5所示，以两行四列的8个子像素(包括2*4个子像素的区域)为例，第i列电源线包括：多个相互连接的子电源线，分别为S1至SN，多个子电源线与每列子像素中的所有子像素一一对应，多个子电源线分别设置在该列的多个子像素中。
在示例性实施例中，第i行第j列的子像素对应的子电源线沿位于第j列数据线中的第一子数据线和第二子数据线的中心线镜像之后的形状与第i+1行第j列的子像素对应的子电源线的形状相同。本文中，电源线形状相同包括但不限于两者的整体形状、各个部分的连接关系以及信号流向的走势相同。
在示例性实施例中，每个子电源线可以包括沿第二方向依次设置的第一电源部SS1、第二电源部SS2和第三电源部SS3，第二电源部SS2配置为连接第一电源部SS1和第三电源部SS3，第一电源部SS1和第三电源部SS3可以与数据线平行设置，第二电源部SS2与第一电源部SS1之间的夹角大于90度且小于180度，形成折线形的子电源线，第二方向是数据线的延伸方向。
在本文中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状 态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。在本文中，第一电源部与数据线平行，是指第一电源部的主体部与数据线的主体部平行，并非限制第一电源部的边缘与数据线的边缘平行，第一电源部的边缘和数据线的边缘允许有因工艺误差造成的不平齐。第一电源部与第二电源部相互连接的连接区域内，该连接区域可以属于第一电源部，或者该连接区域可以属于第二电源部。
在示例性实施例中，第一电源部SS1、第二电源部SS2和第三电源部SS3可以是一体结构。
如图5所示，第一电源部SS1沿着第二方向延伸的长度大于第一电源部SS1的平均宽度，第二电源部SS2沿着倾斜方向延伸的长度大于第二电源部SS2的平均宽度，第三电源部SS3沿着第二方向延伸的长度大于第三电源部SS3的平均宽度。倾斜方向是第二电源部与第一电源部之间具有所述夹角的方向。第三电源部SS3的平均宽度小于第一电源部SS1的平均宽度，一方面是为了像素结构的布局，另一方面，由于第三电源部SS3与数据线距离比较近，平均宽度较小的第三电源部SS3可以降低寄生电容。本公开中，第一电源部SS1和第三电源部SS3的宽度是指第一电源部SS1和第三电源部SS3第一方向的尺寸，第二电源部SS2的宽度是指垂直于倾斜方向的尺寸，平均宽度是指多个位置宽度的平均值，第一方向是栅线延伸方向。
在示例性实施例中，在第一方向上，第一电源部SS1的中心线与第三电源部SS3的中心线之间的距离，与第三电源部SS3的平均宽度相当。
在示例性实施例中，第i行第j列的子像素对应的子电源线中的第一电源部SS1与位于第i-1行第j列的子像素对应的子电源线中的第三电源部SS3连接，第i行第j列的子像素对应的子电源线中的第三电源部SS3与位于第i+1行第j列的子像素对应的子电源线中的第一电源部SS1连接，相互连接的电源部沿第二方向(数据线延伸方向)依次设置。
如图5所示，本公开中的电源线可以为折线形。
在示例性实施例中，结合图5，每个子像素的工作过程包括：在复位阶段，位于第一金属层的复位信号线Reset和位于第二金属层的初始信号线 Vinit提供信号，对驱动电路进行初始化，在写入阶段，位于第一金属层中的栅线G和位于第四金属层中的数据线D提供信号，向驱动电路中写入数据线D提供的数据信号；在发光阶段，位于第一金属层的发光控制线EM提供信号，电源线VDD提供电源信号，使得驱动电路向发光器件OLED提供驱动电流以驱动发光器件发光。
其中，同一行像素同时显示，相邻行像素按照顺序依次进行显示。
在一些可能的实现方式中，如图2所示，本公开提供的显示基板还可以包括：第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14。
第一绝缘层11设置在半导体层20和第一金属层30之间，第二绝缘层12设置在第一金属层30和第二金属层40之间，第三绝缘层13设置在第二金属层40和第三金属层50之间，第四绝缘层14设置在第三金属层50和第四金属层60之间。
在一些可能的实现方式中，第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14的材料可以为氧化硅、氮化硅或者氧化硅和氮化硅的复合物，本公开对此不作任何限定。
在示例性实施例中，如图4A所示，对于每个子像素的多个晶体管可以包括：第一晶体管至第七晶体管，第五晶体管的第一极分别与电源线VDD和存储电容的第二电极C2连接。
本公开中，对于每个子像素，每个子像素中的电源线通过第五晶体管的第一极与存储电容的第二电极连接。
位于第二金属层的相邻子像素的存储电容的第二电极可以复用为电源信号线，配置为保证相邻子像素的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，每四个连续子像素构成一个像素，在第j个像素中，四个连续子像素沿第一方向依次为第i子像素、第i+1子像素、第i+2子像素和第i+3子像素，其中，i可依次取值为4j-3，j为正整数。
在示例性实施例中，多个子像素的存储电容的第二电极与电源线连接有多种实施方式，作为一种实施方式，图6A为实施方式一对应的子像素的一 个俯视图，图6B为实施方式一对应的子像素的另一俯视图，其中，如图6A所示，第四绝缘层设置有暴露出部分第五晶体管的第一极51的第一过孔V1，电源线通过第一过孔V1与第五晶体管的第一极51连接。如图6B所示，第三绝缘层设置有暴露出部分存储电容的第二电极C2的第二过孔V2，第五晶体管的第一极51通过第二过孔V2与存储电容的第二电极C2连接。需要说明的是，图3和图5是以实施方式一为例为例进行说明的。
其中，子像素连接的电源线在基底上的正投影包含第一过孔V1在基底10上的正投影，存储电容的第二电极在基底上的正投影包含第二过孔在基底上的正投影。本文中，“A的正投影包含B的正投影”或者“B的正投影位于A的正投影范围之内”，是指B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在一些可能的实现方式中，第一过孔V1的数量可以为一个。
在一些可能的实现方式中，第二过孔V2的数量可以为至少一个，由于第五晶体管的第一极的宽度较窄，因此，当第二过孔V2的数量为多个时，多个第二过孔沿数据线延伸方向设置，其中，多个第二过孔沿数据线延伸方向设置过孔，可以设置多个过孔，过孔的数量越多，通过过孔连接的部件的导电性越好，图6A是一个第一过孔V1，图6B是以两个第二过孔V2为例进行说明的，本公开对此不作任何限定。
在示例性实施例中，如图6A所示，第四绝缘层还包括暴露出第四晶体管T4的第一极的第三过孔V3，数据线通过该第三过孔V3与第四晶体管T4的第一极连接，第四绝缘层还包括暴露出第六晶体管T6的第二极的第四过孔V4。
在示例性实施例中，如图6B所示，第一绝缘层、第二绝缘层和第三绝缘层还包括：暴露出部分有源区的过孔，使得晶体管的源漏电极通过这些过孔与有源区连接，晶体管的源漏电极包括晶体管的第一极和晶体管的第二极。
在示例性实施例中，第五晶体管的第一极还通过第一绝缘层、第二绝缘层和第三绝缘层上的过孔与有源区连接。
在示例性实施例中，每个像素可以包括四个子像素，图7A为实施方式一对应的第二金属层的俯视图，图7B为实施方式一对应的第三金属层的俯 视图。为了更加清晰的说明显示基板的结构，图7A和图7B是以沿列方向排列的两个像素为例进行说明的。
如图7A所示，位于同一行的相邻子像素中的存储电容的第二电极直接连接，如图7B所示，位于同一行的相邻子像素的第五晶体管的第一极51间隔设置。
在实施方式一中，通过多个子像素设置在第二金属层上的存储电容的第二电极相互连接能够使得相邻子像素的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，通过版图布局的合理设计，可以仅通过半导体层实现多个子像素的导电层的相互连接，或者可以仅通过第一金属层实现多个子像素的导电层的相互连接，或者可以仅通过第二金属层实现多个子像素的导电层的相互连接，或者可以仅通过第三金属层实现多个子像素的导电层的相互连接，从而实现位于同一行的子像素的电源线通过功能层在栅线延伸方向相互连接，在此不再赘述。
如图7A所示，至少一个子像素中还包括第一连接部C3，第一连接部C3设置在第二电极C2第一方向的一侧。
在示例性实施例中，相邻两行像素中，一行像素的第i子像素的第二电极C2与第i+1子像素的第二电极C2通过第一连接部C3连接，第i+1子像素的第二电极C2与第i+2子像素的第二电极C2直接连接，第i+2子像素的第二电极C2与第i+3子像素的第二电极C2通过第一连接部C3连接。另一行像素的第i子像素的第二电极C2与第i+1子像素的第二电极C2直接连接，第i+1子像素的第二电极C2与第i+2子像素的第二电极C2通过第一连接部C3连接，第i+2子像素的第二电极C2与第i+3子像素的第二电极C2直接连接。
作为另一种实施方式，图8A为实施方式二对应的子像素的一个俯视图，图8B为实施方式二对应的子像素的另一俯视图。如图8A所示，第四绝缘层设置有暴露出部分第五晶体管T5的第一极51的第一过孔V1，电源线通过第一过孔V1与第五晶体管T5的第一极51连接。如图8B所示，第三绝缘层设置有暴露出部分存储电容的第二电极C2的第二过孔V2，第五晶体管T5 的第一极51通过第二过孔V2与存储电容的第二电极C2连接。
如图8A和图8B所示，实施方式二与实施方式一相比，提供的每个子像素的存储电容的第二电极所占用的面积有所不同以及每个子像素的第五晶体管T5的第一极51的形状也有所不同。
在示例性实施例中，如图8A所示，第四绝缘层还包括暴露出第四晶体管T4的第一极的第三过孔V3，数据线通过该第三过孔V3与第四晶体管T4的第一极连接，第四绝缘层还包括暴露出第六晶体管T6的第二极的第四过孔V4。
如图3和8B所示，第一绝缘层、第二绝缘层和第三绝缘层还可以包括：暴露出部分有源区的过孔，使得晶体管的源漏电极通过这些过孔与有源区连接。第五晶体管的第一极还可以通过第一绝缘层、第二绝缘层和第三绝缘层上的过孔与有源区连接。
其中，子像素中的电源线在基底上的正投影包含第一过孔V1在基底10上的正投影，存储电容的第二电极在基底上的正投影包含第二过孔在基底上的正投影。
在一些可能的实现方式中，第一过孔V1的数量可以为一个。
在一些可能的实现方式中，第二过孔V2的数量为至少一个，由于第五晶体管的第一极的宽度较窄，因此，多个第二过孔沿数据线延伸方向设置过孔，可以保证设置过孔的数量，过孔的数量越多，通过过孔连接的部件的导电性越好，图8A是一个第一过孔V1，图8B是以两个第二过孔V2为例进行说明的，本公开对此不作任何限定。
图9A为实施方式二对应的第二金属层的俯视图，图9B为实施方式二对应的第三金属层的俯视图，图10为本公开提供的一种显示基板中多个子像素的另一俯视图。为了更加清晰的说明显示基板的结构，图9A和图9B是以沿列方向排列的两个像素为例进行说明的，图10包括除了发光器件的阳极之外的其他膜层，图10中包括的多个子像素为实施方式二对应的子像素。
如图9A和图9B所示，相邻两行像素中其中一行的每个像素中，第i子像素的存储电容的第二电极与第i+1子像素的存储电容的第二电极通过第一 连接部C3连接，第i+1子像素的存储电容的第二电极和第i+2子像素的存储电容的第二电极间隔设置，第i+2子像素的存储电容的第二电极与第i+3子像素的存储电容的第二电极通过第一连接部C3连接；相邻两行像素中另一行的每个像素中，第i子像素的存储电容的第二电极与第i+1子像素的存储电容的第二电极间隔设置，第i+1子像素的存储电容的第二电极与第i+2子像素的存储电容的第二电极通过第一连接部C3连接，第i+2子像素的存储电容的第二电极与第i+3子像素的存储电容的第二电极间隔设置。
如图8A所示，至少一个子像素中存储电容的第二电极C2可以为矩形状，第一连接部C3可以为条形状，第一连接部C3设置在第二电极C2第一方向的一侧。
在示例性实施例中，相邻两行像素中，一行像素的第i子像素的第二电极C2与第i+1子像素的第二电极C2通过第一连接部C3相互连接，第i+1子像素的第二电极C2与第i+2子像素的第二电极C2间隔设置，第i+2子像素的第二电极C2与第i+3子像素的第二电极C2通过第一连接部C3相互连接。另一行像素的第i子像素的第二电极C2与第i+1子像素的第二电极C2间隔设置，第i+1子像素的第二电极C2与第i+2子像素的第二电极C2通过第一连接部C3相互连接，第i+2子像素的第二电极C2与第i+3子像素的第二电极C2间隔设置。
需要说明的是，图9A是以第一行像素中的第i子像素的存储电容的第二电极与第i+1子像素的存储电容的第二电极通过第一连接部C3直接连接，第二行像素中第i+2子像素的存储电容的第二电极与第i+3子像素的存储电容的第二电极通过第一连接部C3直接连接为例进行说明的。
在一些可能的实现方式中，如图10所示，对于每个子像素，第五晶体管的第一极在基底上的正投影与所连接的数据线在基底上的正投影存在重叠区域。
在示例性实施例中，结合图9A、图9B和图10，对于第j个像素，可以包括第二连接部56。在第i子像素的存储电容的第二电极C2与第i+1子像素的存储电容的第二电极C2连接的状况下，第i+1子像素中的第五晶体管T5的第一极51与第i+2子像素中的第五晶体管T5的第一极51通过第二连 接部56连接。位于第二金属层中的第i子像素中的存储电容的第二电极C2通过位于第三金属层中的第i+1子像素中的第五晶体管T5的第一极51、第二连接部56和第i+2子像素中的第五晶体管T5的第一极51与位于第二金属层中的第i+3子像素中的存储电容的第二电极C2连接。
在示例性实施例中，对于第j个像素，在第i+1子像素的存储电容的第二电极C2与第i+2子像素的存储电容的第二电极C2连接的状况下，第i子像素中的第五晶体管T5的第一极51与第i+1子像素中的第五晶体管T5的第一极51通过第二连接部56连接，第i+2子像素中的第五晶体管T5的第一极51与第i+3子像素中的第五晶体管T5的第一极51通过第二连接部56连接。其中，位于第二金属层的第i子像素的存储电容的第二电极C2通过位于第三金属层中的第i子像素中的第五晶体管T5的第一极51、第二连接部56和第i+1子像素中的第五晶体管T5的第一极51与位于第二金属层的第i+1子像素的存储电容的第二电极C2连接，位于第二金属层的第i+2子像素的存储电容的第二电极C2通过位于第三金属层中的第i+2子像素中的第五晶体管T5的第一极51、第二连接部56和第i+3子像素中的第五晶体管T5的第一极51与位于第二金属层的第i+3子像素的存储电容的第二电极C2连接。
在实施方式二中，本公开通过第二金属层和第三金属层共同完成横向(第一方向)跨接，实现电源连接线的功能，使得向每个子像素提供的电源信号均相同，保证了显示基板的显示效果。
需要说明的是，由于第三金属层的电阻率要小于第二金属层的电阻率，因此，实施方式二提供的显示基板与实施例方式一提供的显示基板相比，能够进一步地降低动态串扰。
在一些可能的实现方式中，如图2所示，本公开提供的显示基板还可以包括：设置在第四金属层60和第五金属层70之间的第五绝缘层15和平坦层16以及设置在第五金属层70远离基底10一侧的发光器件的有机发光层和阴极(图中未示出)。第五绝缘层15设置在平坦层16靠近基底10的一侧；阴极设置在有机发光层远离基底10的一侧。
如图3所示，本公开提供的第四金属层还可以包括连接电极61，其中，连接电极61分别与第五金属层和第六晶体管的第二极连接。第五绝缘层和平 坦层设置有暴露连接电极的第五过孔V5，第五金属层通过暴露连接电极61的第五过孔V5与连接电极61连接，第四绝缘层设置暴露第六晶体管的第二极的第四过孔V4，连接电极61通过暴露第六晶体管的第二极的第四过孔V4与第六晶体管的第二极连接。
本公开示例性实施例通过将数据线和电源线与多个晶体管的第一极和第二极异层设置，能够减少子像素与子像素所连接的数据线的占用面积，进而提高了高频驱动的OLED显示基板的分辨率。
基于同一发明构思，本公开还提供一种显示基板的制作方法，以制作上述实施例提供的显示基板。在示例性实施例中,在平行于显示基板的平面内，所述显示基板包括设置在基底上的栅线、数据线、电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；所述制作方法可以包括：
提供一基底；
在所述基底形成多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。
图11为本公开提供的一种显示基板的制作方法的流程图，如图11所示，本公开提供的显示基板的制作方法可以包括以下步骤：
步骤B1、提供一基底。
步骤B2、在基底上依次形成相互绝缘的半导体层、第一金属层、第二金属层、第三金属层、第四金属层和第五金属层。
在示例性实施例中,半导体层可以包括：多个晶体管的有源区，第一金属层可以包括：栅线、发光控制线、复位信号线、存储电容的第一电极和多个晶体管的栅电极，第二金属层可以包括：初始信号线和存储电容的第二电极；第三金属层可以包括：多个晶体管的源漏电极，第四金属层可以包括：数据线和电源线，第五金属层可以包括：发光器件的阳极。第i列子像素的驱动电路与第i列数据线连接，每列数据线包括：第一子数据线和第二子数据线； 第i列数据线中的第一子数据线和第二子数据线分别位于第i列子像素的两侧，相邻两列子像素之间的全部子数据线仅为第一子数据线或者第二子数据线。
其中，1≤i≤N，N为子像素的总列数。
本公开提供的显示基板的制作方法所制作的显示基板，其实现原理和实现效果类似，在此不再赘述。
在一些可能的实现方式中，步骤200可以包括：在基底上形成依次形成半导体层和第一绝缘层；在第一绝缘层上依次形成第一金属层和第二绝缘层；在第二绝缘层上依次形成第二金属层和第三绝缘层；在第三绝缘层上依次形成第三金属层和第四绝缘层；在第四绝缘层依次形成第四金属层、第五绝缘层和平坦层；在平坦层上依次形成第五金属层、发光器件的有机发光层和发光器件的阴极。
图12为本公开提供的一种显示基板的第一制作示意图，图13为本公开提供的一种显示基板的第二制作示意图，图14A为本公开提供的一种显示基板的一个第三制作示意图，图14B为本公开提供的一种显示基板的另一第三制作示意图，图15A为本公开提供的一种显示基板的一个第四制作示意图，图15B为本公开提供的一种显示基板的另一第四制作示意图，图16A为本公开提供的一种显示基板的一个第五制作示意图，图16B为本公开提供的一种显示基板的另一第五制作示意图。
本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
结合图12～图16B，本公开提供的显示基板的制作过程可以包括如下操作。
步骤100、提供一基底10，在基底10上沉积半导体薄膜，采用构图工艺对半导体薄膜进行处理形成半导体层20，如图12所示。
在示例性实施例中，每个子像素的半导体层20可以包括第一晶体管T1所在位置的第一有源区101、第二晶体管T2所在位置的第二有源区102、第三晶体管T3所在位置的第三有源区103、第四晶体管T4所在位置的第四有源区104、第五晶体管T5所在位置的第五有源区105、第六晶体管T6所在位置的第六有源区106和第七晶体管T7所在位置的第七有源区107，且第一有源区101至第七有源区107为相互连接的一体结构。
在示例性实施例中，第一有源区101和第七有源区107设置在第一区域R1远离第二区域R2的一侧，第二有源区102和第四有源区104设置在第一区域R1靠近第二区域R2的一侧；第三有源区103设置在第二区域R2；第五有源区105和第六有源区106设置在第三区域R3。
在示例性实施例中，第一有源区101分别与第二有源区102和第七有源区107连接，第二有源区102分别与第三有源区103和第六有源区106连接，第四有源区104分别与第三有源区103和第五有源区105连接。
在示例性实施例中，第一有源区101呈“n”字形，第七有源区107呈“L”字形，第七有源区107位于第一有源区101远离子像素中心线的一侧，子像素中心线是第一方向上等分子像素、沿第二方向延伸的直线。第二有源区102呈“7”字形，位于子像素中心线的一侧，第四有源区104呈“1”字形，位于子像素中心线的另一侧。第三有源区103呈“几”字形，“几”字形可以相对于子像素中心线镜像对称。第五有源区105呈“L”字形，第六有源区106的形状与第五有源区15的形状相对于子像素中心线镜像对称。本文中，晶体管的有源区呈某种形状，是指该晶体管栅极附近有源区的形状，包括但不限于该晶体管有源区的沟道区、源漏区以及与其它晶体管源漏区连接所使用的有源区部分的延伸区域。
在示例性实施例中，每个晶体管的有源区包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施例中，第一有源区101的第一区同时作为第七有源区107的第一区，第一有源区101的第二区同时作为第二有源区102的第一区。第二有源区102的第二区、第三有源区103的第二 区和第六有源区106的第一区之间相互连接，第三有源区103的第一区、第四有源区104的第二区和第五有源区105的第二区之间相互连接。第四有源区14的第一区设置在远离第三有源区103的一侧，第五有源区105的第一区设置在远离第三有源区103的另一侧。第六有源区106的第二区同时作为第七有源区107的第二区。
在示例性实施例中，第二有源区102与第一有源区101之间第一方向的距离小于第二有源区102与第七有源区107之间第一方向的距离。第二有源区102与第三有源区103之间第一方向的距离小于第二有源区102与第四有源区104之间第一方向的距离，第二有源区102与第三有源区103之间第一方向的距离小于第二有源区102与第五有源区105之间第一方向的距离；第二有源区102与第一有源区101之间第一方向的距离，与第二有源区102与第三有源区103之间第一方向的距离相当。
在示例性实施例中，沿着写入数据信号的数据线到电源线的方向，第七有源区107和第一有源区101依次设置。
在示例性实施例中，第i行第j列子像素的半导体层20形状与第i+1行第j+1列子像素的半导体层20形状相同，第i行第j+1列子像素的半导体层20形状与第i+1行第j列子像素的半导体层20形状相同。在第一方向，对于相邻子像素之间的中心线，相邻子像素的半导体层20关于该中心线镜像对称，即在第一方向，相邻子像素的半导体层互为对称关系。本文中，半导体层形状相同包括但不限于两者的整体形状、各个部分的连接关系以及信号流向的走势相同。
在示例性实施例中，实施方式一中有源区的制作示意图与实施方式二中有源区的制作示意图相同。
本公开示例性实施例的半导体层布局合理，结构简洁，能够保证显示基板的显示效果。
步骤200、在半导体层20上依次沉积第一绝缘薄膜和第一金属薄膜，采用构图工艺对第一金属薄膜进行处理，形成覆盖半导体层20的第一绝缘层，以及设置在第一绝缘层上的第一金属层30，如图13所示。
在示例性实施例中，第一金属层30可以包括：栅线G、复位信号线Reset、 发光控制线EM和存储电容的第一电极C1。
在示例性实施例中，栅线G、复位信号线Reset和发光控制线EM沿第一方向延伸，栅线G和复位信号线Reset设置在第一区域R1，发光控制线EM设置在第三区域R3。存储电容的第一电极C1可以为矩形状，矩形状的角部可以设置倒角，第一电极C1设置在第二区域R2，位于栅线G和发光控制线EM之间，第一电极C1在基底上的正投影与第三有源区在基底上的正投影存在重叠区域。在示例性实施例中，第一极板C1同时作为第三晶体管的栅电极。
在示例性实施例中，第一区域R1的复位信号线Reset可以为非等宽度设置，复位信号线Reset的宽度为复位信号线Reset第二方向的尺寸。复位信号线Reset包括与半导体层20相重叠的区域和与半导体层20不相重叠的区域，与半导体层20相重叠的区域的复位信号线Reset的宽度可以大于与半导体层20不相重叠的区域的复位信号线Reset的宽度。
在示例性实施例中，第一区域R1的栅线G可以为非等宽度设置，栅线G的宽度为栅线G第二方向的尺寸。栅线G与半导体层20相重叠的区域和与半导体层20不相重叠的区域，与半导体层20相重叠的区域的栅线G的宽度可以大于与半导体层20不相重叠的区域的栅线G的宽度。
在示例性实施例中，第三区域R3的发光控制线EM可以为非等宽度设置，发光控制线EM的宽度为发光控制线EM第二方向的尺寸。发光控制线EM包括与半导体层20相重叠的区域和与半导体层20不相重叠的区域，与半导体层20相重叠的区域的发光控制线EM的宽度可以大于与半导体层20不相重叠的区域的发光控制线EM的宽度。
在示例性实施例中，第i行的栅线G可以包括第一栅线段，第一栅线段沿着第一方向从第j列子像素延伸到第j+1列子像素，第一栅线段的第一端通过位于第i行第j列子像素的连接条与栅线G连接，第一栅线段的第二端通过位于第i行第j+1列子像素的连接条与栅线G连接，在第i行第j列子像素和第i行第j+1列子像素内同时形成双栅结构。第i+1行的栅线G可以包括第二栅线段，第二栅线段沿着第一方向从第j+1列子像素延伸到第j+2列子像素，第二栅线段的第一端通过位于第i+1行第j+1列子像素的连接条与 栅线G连接，第二栅线段的第二端通过位于第i+1行第j+2列子像素的连接条与栅线G连接，在第i+1行第j+1列子像素和第i+1行第j+2列子像素内同时形成双栅结构。这样，在第j列子像素和第j+1列子像素同时形成双栅结构的第二晶体管T2，第j列子像素的第二晶体管T2和第j+1列子像素的第二晶体管T2形成双栅区110。
在示例性实施例中，第一电极C1与第三有源区相重叠的区域作为第三栅电极(双栅结构)，栅线G与第二有源区相重叠的区域作为第二栅电极(双栅结构)，复位信号线Reset与第一有源区相重叠的区域作为第一栅电极(双栅结构)，栅线G与第四有源区相重叠的区域作为第四栅电极，复位信号线Reset与第七有源区相重叠的区域作为第七栅电极，发光控制线EM与第五有源区相重叠的区域作为第五栅电极，发光控制线EM与第六有源区相重叠的区域作为第六栅电极。
在示例性实施例中，由于第一晶体管T1、第二晶体管T2和第三晶体管T3均为双栅晶体管，因此双栅的第二晶体管T2与其它双栅晶体管(第一晶体管T1和第三晶体管T3)之间第一方向的距离，小于第二晶体管T2与单栅的第四晶体管T4、第五晶体管T5和第七晶体管T7之间第一方向的距离。
在示例性实施例中，形成第一金属层30图案后，可以利用第一金属层30作为遮挡，对半导体层进行导体化处理，被第一金属层30遮挡区域的半导体层形成第一晶体管T1至第七晶体管T7的沟道区域，未被第一金属层30遮挡区域的半导体层被导体化，即第一晶体管T1至第七晶体管T7的第一区和第二区被导体化。
在示例性实施例中，实施方式一中第一金属层的制作示意图与实施方式二中第一金属层的制作示意图相同。
本公开示例性实施例的第一金属层布局合理，结构简洁，能够保证显示基板的显示效果。
步骤300、在第一金属层30上依次沉积第二绝缘薄膜和第二金属薄膜，采用构图工艺对第二金属薄膜进行处理，形成覆盖第一金属层30的第二绝缘层，以及设置在第二绝缘层上的第二金属层40，第二金属层40至少包括初始信号线Vinit和存储电容的第二电极C2。随后，在第二金属层40上沉积第 三绝缘薄膜，采用构图工艺对第三绝缘薄膜进行处理，形成覆盖第二金属层40的第三绝缘层，第三绝缘层上设置有多个过孔，如图14A和14B所示。
在示例性实施例中，第三绝缘层上的多个过孔至少包括：暴露出第二电极C2的第二过孔V2，暴露出初始信号线Vinit的第六过孔V6，暴露出第一电极C1的第七过孔V7，暴露出第四有源区的第八过孔V8，暴露出第二有源区的第九过孔V9，暴露出第一有源区的第十过孔V10，以及暴露出半导体层中其它有源区的多个过孔。暴露出第二电极C2的第二过孔V2和暴露出初始信号线Vinit的第六过孔V6中的第三绝缘层被刻蚀掉，暴露出第一电极C1的第七过孔V7中的第二绝缘层和第三绝缘层被刻蚀掉，暴露出第四有源区的第八过孔V8、暴露出第二有源区的第九过孔V9、暴露出第一有源区的第十过孔V10以及暴露出半导体层中其它有源区的过孔中的第一绝缘层、第二绝缘层和第三绝缘层被刻蚀掉。
在示例性实施例中，第二过孔V2配置为使第二电极C2与后续形成的第五晶体管T5的第一极连接，第六过孔V6配置为使初始信号线Vinit与后续形成的第一晶体管T1的第一极连接，第七过孔V7配置为使第一电极C1与后续形成的第二晶体管T2的第一极连接，第八过孔V8配置为使第四晶体管T4的有源层与后续形成的第四晶体管T4的第一极连接，第九过孔V9配置为使第二晶体管T2的有源层与后续形成的第二晶体管T2的第一极连接，第十过孔V10配置为使第一晶体管T1的有源层与后续形成的第一晶体管T1的第一极连接。由于后续形成的第四晶体管T4的第一极与后续形成的数据线D连接，因而第八过孔V8是数据写入孔。
在示例性实施例中，数据写入孔与第二晶体管T2之间第一方向上的距离，分别大于数据写入孔与第一晶体管T1第一方向上之间的距离、数据写入孔与第七晶体管T7之间第一方向上的距离。数据写入孔与第三晶体管T3之间第二方向上的距离，分别小于数据写入孔与第五晶体管T5之间第二方向上的距离、数据写入孔与第六晶体管T6之间第二方向上的距离。
在示例性实施例中，第二过孔V2的数量可以为两个，两个第二过孔沿第二方向依次设置。由于第五第一极的宽度较窄，因此设置两个第二过孔V2，可以提高第二电极与第五第一极之间连接的可靠性。
在示例性实施例中，初始信号线Vinit沿第一方向延伸，设置在第一区域R1，位于复位信号线Reset远离第二区域R2的一侧。每个子像素中存储电容的第二电极C2的轮廓可以为矩形状，设置在第二区域R2，位于栅线G和发光控制线EM之间。
在示例性实施例中，第二电极C2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二电极C2在基底上的正投影与第一电极C1在基底上的正投影存在重叠区域。第二电极C2的中部设置有开口111，开口111可以为矩形，使第二电极C2形成环形结构。开口111暴露出覆盖第一电极C1的第二绝缘层，且第一电极C1在基底上的正投影包含开口111在基底上的正投影。在示例性实施例中，开口111在基底上的正投影包含暴露出第一电极C1的第七过孔V7在基底上的正投影。
第二电极C2靠近第一区域R1的边缘在基底上的正投影与第一区域R1与第二区域R2的交界线在基底上的正投影重叠，第二电极C2靠近第三区域R3的边缘在基底上的正投影与第二区域R2与第三区域R3的交界线在基底上的正投影重叠，即第二电极C2的第二长度等于第二区域R2的第二长度，第二长度是指第二方向上的尺寸。
在实施方式一中，一行中相邻子像素的第二电极C2为相互连接的一体结构。该结构使相邻子像素的第二电极C2可以复用为电源信号线，可以保证相邻子像素的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
在实施方式二中，第i行第j列子像素的第二电极C2与第i行第j+1列子像素的第二电极C2为通过第一连接部相互连接的一体结构，第i行第j+1列子像素的第二电极C2与第i行第j+2列子像素的第二电极C2为断开设置，第i行第j+2列子像素的第二电极C2与第i行第j+3列子像素的第二电极C2为通过第一连接部相互连接的一体结构。第i+1行第j列子像素的第二电极C2与第i+1行第j+1列子像素的第二电极C2为断开设置，第i+1行第j+1列子像素的第二电极C2与第i+1行第j+2列子像素的第二电极C2为通过第一连接部相互连接的一体结构，第i+1行第j+2列子像素的第二电极C2与第i+1行第j+3列子像素的第二电极C2为断开设置。该结构使相邻子像素的第 二电极C2可以复用为电源信号线，可以保证相邻子像素的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
图14A为实施方式一的制作示意图，图14B为实施方式二的制作示意图。
本公开示例性实施例的第二金属层和过孔布局合理，结构简洁，能够保证显示基板的显示效果。
步骤400、在第三绝缘层上沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行处理，形成第三金属层50，第三金属层50至少包括第五晶体管T5的第一极51、第六晶体管T6的第二极52、第四晶体管T4的第一极53、第一晶体管T1的第一极54和第二晶体管T2的第一极55。第五晶体管T5的第一极51通过第二过孔V2与第二电极C2连接，第六晶体管T6的第二极52通过过孔与第六晶体管的有源层连接，第四晶体管T4的第一极53通过第八过孔V8与第四晶体管T4的有源层连接，第一晶体管T1的第一极54的一端通过第六过孔V6与初始信号线Vinit连接，另一端通过第十过孔V10与第一晶体管T1的有源层连接，第二晶体管T2的第一极55的一端通过第七过孔V7与第一电极C1连接，另一端通过第九过孔V9与第二晶体管T2的有源层连接。随后，在第三金属层50上沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行处理形成覆盖第三金属层50的第四绝缘层，第四绝缘层上设置有多个过孔，如图15A和图15B所示。
在示例性实施例中，第四绝缘层上的多个过孔至少包括：暴露出第五晶体管T5的第一极51的第一过孔V1，暴露第六晶体管T6的第二极52的第四过孔V4，暴露出第四晶体管T4的第一极53的第三过孔V3。暴露第五晶体管T5的第一极51的第一过孔V1配置为使第五晶体管T5的第一极51与后续形成的电源线VDD连接，暴露第六晶体管T6的第二极52的第四过孔V4配置为使第六晶体管T6的第二极52与后续形成的连接电极连接，暴露出第四晶体管T4的第一极53的第三过孔V3配置为使第四晶体管T4的第一极53与后续形成的数据线D连接。
在示例性实施例中，第一过孔V1在基底上的正投影与栅线G在基底上的正投影存在重叠区域。
在示例性实施例中，第一过孔V1在基底上的正投影与第二电极C2在基 底上的正投影存在重叠区域。
在示例性实施例中，第三过孔V3在基底上的正投影与栅线G在基底上的正投影存在重叠区域。
在示例性实施例中，第四过孔V4在基底上的正投影与发光控制线EM在基底上的正投影存在重叠区域。
在实施方式一中，位于同一行的相邻子像素的第五晶体管T5的第一极51间隔设置。
在实施方式二中，第i行第j+1列子像素中的第五晶体管T5的第一极51与第i行第j+2列子像素中的第五晶体管T5的第一极51通过第二连接部连接，第i+1行第j列子像素中的第五晶体管T5的第一极51与第i行第j+1列子像素中的第五晶体管T5的第一极51通过第二连接部连接，第i+1行第j+2列子像素中的第五晶体管T5的第一极51与第i行第j+3列子像素中的第五晶体管T5的第一极51通过第二连接部连接。
图15A为实施方式一的制作示意图，图15B为实施方式二的制作示意图。
本公开示例性实施例的第三金属层和过孔布局合理，结构简洁，能够保证显示基板的显示效果。
步骤500、在第四绝缘层上沉积第四金属薄膜，通过构图工艺对第四金属薄膜进行处理，形成包括第一子数据线DO、第二子数据线DE、电源线VDD和连接电极61的第四金属层60，第一子数据线DO和第二子数据线DE分别通过所在子像素的暴露出第四晶体管T4的第一极53的第三过孔V3与第四晶体管T4的第一极53连接，电源线VDD通过暴露第五晶体管T5的第一极51的第一过孔V1与第五晶体管T5的第一极51连接，连接电极61通过暴露第六晶体管T6的第二极52的第四过孔V4与第六晶体管T6的第二极52连接。随后，在第四金属层60上沉积第五绝缘薄膜，在第五绝缘薄膜上涂覆平坦薄膜，通过构图工艺对平坦薄膜和第五绝缘薄膜进行处理，形成覆盖第四金属层60的第五绝缘层，以及设置在第五绝缘层上的平坦层，平坦层上设置有多个过孔，如图16A和16B所示。
在示例性实施例中，第一子数据线DO、第二子数据线DE和电源线VDD 沿第二方向延伸，第一子数据线DO位于子像素的一侧，第二子数据线DE位于子像素的另一侧，电源线VDD位于第一子数据线DO和第二子数据线DE之间。
在示例性实施例中，第一子数据线DO和第二子数据线DE可以为等宽度的直线，第一子数据线DO和第二子数据线DE的宽度为第一子数据线DO和第二子数据线DE第一方向的尺寸。
在示例性实施例中，位于同一列的相邻子像素的第四晶体管的第一极连接不同子数据线。例如，第i行第j列的子像素连接第j列数据线中的第一子数据线，第i+1行第j列的子像素连接第j列数据线中的第二子数据线。或者，第i行第j列的子像素连接第j列数据线中的第二子数据线，第i+1行第j列的子像素连接第j列数据线中的第一子数据线。
在示例性实施例中，至少一个子像素中，第一子数据线DO通过所在子像素中的第三过孔V3与第四晶体管T4的第一极53连接，第四晶体管T4的第一极53通过第八过孔V8与第四有源区连接，第八过孔V8为数据写入孔，第一子数据线DO为该子像素的写入数据线号的数据线。至少一个子像素中，第二子数据线DE通过所在子像素中的第三过孔V3与第四晶体管T4的第一极53连接，第四晶体管T4的第一极53通过第八过孔V8与第四有源区连接，第八过孔V8为数据写入孔，第二子数据线DE为该子像素的写入数据线号的数据线。
在示例性实施例中，每个子像素的电源线VDD通过第一过孔V1与第五晶体管T5的第一极51连接，由于第五晶体管T5的第一极51与存储电容的第二电极C2连接，相邻子像素的存储电容的第二电极C2相互连接，因而不仅实现了电源线VDD与第二电极C2连接，而且实现了第二电极C2的电源连接线功能，使得向每个子像素提供的电源信号均相同，保证了显示基板的显示效果。
在示例性实施例中，每个子像素的电源线VDD可以为折线。沿着第二方向，每个子像素的电源线VDD可以包括依次连接的第一电源部、第二电源部和第三电源部。第i行第j列的子像素对应的电源线中，第一电源部的第一端与位于第i-1行第j列的子像素中的第三电源部的第二端连接，第一电 源部的第二端沿着第二方向延伸，与第二电源部的第一端连接；第二电源部的第二端沿着倾斜方向延伸，与第三电源部的第一端连接，倾斜方向与第二方向具有夹角，夹角可以大于0度，且小于90度；第三电源部的第二端沿着第二方向延伸，与位于第i+1行第j列的子像素中的第一电源部的第一端连接。
在示例性实施例中，第一电源部可以为等宽度的直线，第二电源部可以为等宽度的斜线，第三电源部可以为等宽度的直线。第一电源部和第二电源部与第一子数据线(或第二子数据线)平行，第二电源部与第一电源部之间的夹角可以大于90度且小于180度，第二电源部与第三电源部之间的夹角可以大于90度且小于180度。
在示例性实施例中，第一电源部沿着第一方向延伸的长度大于第一电源部的平均宽度，第二电源部沿着倾斜方向延伸的长度大于第二电源部的平均宽度，第三电源部沿着第一方向延伸的长度大于第三电源部的平均宽度，倾斜方向是第二电源部与第一电源部之间具有夹角的方向。
在示例性实施例中，第三电源部的平均宽度可以小于第一电源部的平均宽度，第三电源部的平均宽度可以小于第二电源部的平均宽度。电源线VDD采用变宽度的折线设置，不仅可以便于像素结构的布局，而且可以降低电源线VDD与数据线的寄生电容。由于第三电源部与数据线距离比较近，将第三电源部的平均宽度减小，可以减小第三电源部与数据线的寄生电容。
在示例性实施例中，第一电源部的平均宽度可以大于或等于第二电源部的平均宽度，或者第一电源部的平均宽度可以小于第二电源部的平均宽度。
在示例性实施例中，第二电源部延伸方向的长度与第一电极C1的第二长度相当，第一电极C1的第二长度是第一电极C1第二方向上的尺寸。第一电源部延伸方向的长度与第二电极C2的第二长度相当，第三电源部延伸方向的长度与第二电极C2的第二长度相当，第二电极C2的第二长度是第二电极C2第二方向上的尺寸。
如图3、图16A和16B所示，在示例性实施例中，第一电源部在基底上的正投影与第二晶体管T2的第一极55和第九过孔V9在基底上的正投影存在重叠区域，因而第一电源部在基底上的正投影与第二晶体管T2在基底上 的正投影存在重叠区域。第二电源部在基底上的正投影与第一过孔V1在基底上的正投影存在重叠区域，第三电源部在基底上的正投影与第五晶体管T5的第一极51在基底上的正投影存在重叠区域，因而第二电源部和第三电源部在基底上的正投影均与第五晶体管T5的第一极51存在重叠区域。
在示例性实施例中，第一过孔V1在基底上的正投影与第一电源部第二方向的延长线在基底上的正投影存在重叠区域，第一过孔V1在基底上的正投影与第三电源部第二方向的延长线在基底上的正投影存在重叠区域，因而在第一方向上，第一电源部与第三电源部之间第一方向的距离小于第一过孔V1的第一长度或者第三电源部的平均宽度，即第一电源部靠近第三电源部一侧的边缘与第三电源部靠近第一电源部一侧的边缘之间的距离小于第一过孔V1的第一长度或者第三电源部的宽度，第一过孔V1的第一长度是指第一过孔V1第一方向上的尺寸。因此，对于沿着倾斜方向延伸的第二电源部，可以理解成第二电源部将电源线VDD拐了个弯。在第一方向上，拐弯的程度相当于第一过孔V1的第一长度，或者相当于第三电源部的宽度；在第二方向上，拐弯的程度相当于第一电极C1的第二长度。本文中，两个电源部的边缘是指两个电源部整体轮廓的边缘。
在示例性实施例中，第二电源部在基底上的正投影与第二电极在基底上的正投影存在重叠区域。
在示例性实施例中，第二电源部在基底上的正投影与第一连接部在基底上的正投影存在重叠区域。
在示例性实施例中，第二电源部在基底上的正投影与第一电极C1在基底上的正投影存在重叠区域。
在示例性实施例中，第二电源部在基底上的正投影与栅线G在基底上的正投影存在重叠区域，即第二电源部在基底上的正投影与第二晶体管T2的栅电极和第四晶体管T4的栅电极在基底上的正投影存在重叠区域。
在示例性实施例中，连接电极61为沿着第二方向延伸的条形状，连接电极61的延伸方向与第三电源部的延伸方向平行，连接电极61第二方向的长度与第三电源部第二方向的长度相当。
在示例性实施例中，连接电极61在基底上的正投影与第二电极C2在基 底上的正投影存在重叠区域。
在示例性实施例中，连接电极61在基底上的正投影与第二电极C2中部的开口111在基底上的正投影存在重叠区域。
在示例性实施例中，连接电极61在基底上的正投影与第二第一极55在基底上的正投影存在重叠区域。
在示例性实施例中，连接电极61的延伸方向与第一电源部的延伸方向重叠，即连接电极61在基底上的正投影与第一电源部第二方向的虚拟延长线在基底上的正投影存在重叠区域。
在示例性实施例中，第八过孔V8(即数据写入孔)位于第三电源部第二方向的虚拟延长线上，即第八过孔V8在基底上的正投影与第三电源部第二方向的虚拟延长线在基底上的正投影存在重叠区域。
在示例性实施例中，由于每个子像素的电源线VDD通过第一过孔V1与第五晶体管T5的第一极51连接，而第五晶体管T5的第一极51通过第二过孔V2与存储电容的第二电极C2连接，进而使电源线VDD与存储电容的第二电极C2连接，因而第一过孔V1称为电源写入孔。
在示例性实施例中，电源写入孔在基底上的正投影位于第二电源部在基底上的正投影范围之内。电源写入孔与第四晶体管T4之间第一方向上的距离与电源写入孔与第二晶体管T2之间第一方向上的距离相当。电源写入孔与第二晶体管T2之间第二方向上的距离，分别小于电源写入孔与第一晶体管T1之间第二方向上的距离、电源写入孔与第七晶体管T7之间第二方向上的距离，电源写入孔与第三晶体管T3之间第二方向上的距离，分别小于电源写入孔与第五晶体管T5之间第二方向上的距离、电源写入孔与第六晶体管T6之间第二方向上的距离。
在示例性实施例中，第五绝缘层和平坦层上的多个过孔至少包括：暴露出连接电极61的第五过孔V5，暴露出连接电极61的第五过孔V5配置为使连接电极61与后续形成的第五金属层(阳极)连接。由于连接电极61与第六第二极52的连接，因此实现了第六第二极52与第五金属层之间的连接，驱动电路可以驱动发光器件发光。
在示例性实施例中，连接电极61通过第四过孔V4与第六晶体管T6的第二极52连接，第四过孔V4位于连接电极61远离第二电源部的一端。连接电极61通过第五过孔V5与后续形成的阳极连接，第五过孔V5位于连接电极61靠近第二电源部的一端，第五过孔V5在基底上的正投影与存储电容的第二电极C2在基底上的正投影存在重叠区域。
在示例性实施例中，第五过孔V5位于第一电源部第二方向的虚拟延长线上，即第五过孔V5在基底上的正投影与第一电源部第二方向的虚拟延长线在基底上的正投影存在重叠区域。
图16A为实施方式一的制作示意图，图16B为实施方式二的制作示意图。
本公开示例性实施例的第四金属层和过孔布局合理，结构简洁，能够保证显示基板的显示效果。
步骤600、在平坦层上沉积第五金属薄膜，通过构图工艺对第五金属薄膜进行处理形成第五金属层70，第五金属层70至少包括阳极，阳极通过暴露连接电极61的第五过孔与连接电极61连接。由于阳极与连接电极61连接，连接电极61与第六晶体管T6的第二极52的连接，因此实现了第六晶体管T6的第二极52与阳极的连接，第六晶体管可以驱动发光器件发光。随后，在第五金属层上涂覆像素定义薄膜，通过构图工艺对像素定义薄膜进行处理，形成像素定义层，每个子像素的像素定义层设置有像素开口，像素开口暴露出阳极。随后，采用蒸镀工艺形成有机发光层，在有机发光层上形成阴极。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，电源线VDD以及部分晶体管的第一极或第二极可以位于第三金属层50上，数据线D以及部分晶体管的第一极或第二极可以位于第四金属层60上。又如，数据线D以及部分晶体管的第一极或第二极可以位于第三金属层50上，电源线VDD以及部分晶体管的第一极或第二极可以位于第四金属层60上。再如，电源线VDD和数据线D可以位于第三金属层50上，第一晶体管至第七晶体管的第一极和第二极可以位于第四金属层60上，本公开在此不做限定。
图17为本公开提供的另一种显示基板中多个子像素的俯视图，图18为 本公开提供的另一种显示基板中多个子像素的剖视图，图17以8个子像素(前四列前两行子像素)为例进行示意说明。如图1、图17和图18所示，本公开提供的显示基板包括：基底10以及设置在基底10上的多个子像素P、多列电源线VDD以及与电源线VDD同层设置的数据线D，每个子像素P包括驱动电路；驱动电路可以包括多个晶体管和存储电容，存储电容包括相对设置的第一电极C1和第二电极C2，晶体管的有源区21位于存储电容的第二电极C2靠近基底10的一侧，电源线VDD位于存储电容的第二电极C2远离基底10的一侧。
在示例性实施例中，至少一个子像素，电源线VDD分别与存储电容的第二电极C2和半导体层的第三连接部连接，每个子像素的存储电容的第二电极C2与位于同一行的一个相邻子像素的存储电容的第二电极C2连接，每个子像素的半导体层与位于同一行的另一相邻子像素的半导体层通过第三连接部相互连接。
在一些可能的实现方式中，如图17所示，第i列子像素的驱动电路与第i列数据线和第i列电源线连接，1≤i≤N。每列数据线包括：第一子数据线和第二子数据线，第i列数据线Di中的第一子数据线DOi和第二子数据线DEi分别位于第i列子像素的两侧，第i列电源线VDDi位于第i列数据线Di中的第一子数据线DOi和第二子数据线DEi之间。
在一些可能的实现方式中，位于同一列的相邻子像素连接不同的子数据线，即若第i行第j列的子像素连接第j列数据线中的第一子数据线DOj，则第i+1行第j列的子像素连接第j列数据线中的第二子数据线DEj，若第i行第j列的子像素连接第j列数据线中的第二子数据线DEj，则第i+1行第j列的子像素连接第j列数据线中的第一子数据线DOj。
在一些可能的实现方式中，相邻数据线中的第一子数据线和第二子数据线的排布方式相反，即当第i列数据线Di的第一子数据线DOi位于第i列子像素的第一侧，第i列数据线Di的第二子数据线DEi位于第i列子像素的第二侧时，第i+1列数据线Di+1的第二子数据线DEi+1位于第i+1列子像素的第一侧，第i+1列数据线Di+1的第一子数据线DOi+1位于第i+1列子像素的第二侧；或者当第i列数据线Di的第一子数据线DOi位于第i列子像素的 第二侧，第i列数据线Di的第二子数据线DEi位于第i列子像素的第一侧时，第i+1列数据线Di+1的第二子数据线DEi+1位于第i+1列子像素的第二侧，第i+1列数据线Di+1的第一子数据线DOi+1位于第i+1列子像素的第一侧。
如图17和图18所示，在示例性实施例中，显示基板可以包括：依次设置在基底10上的第一绝缘层11、第二绝缘层12、第三绝缘层13，栅线G、复位信号线Reset、发光控制信号线EM和初始信号线Vinit。栅线G、复位信号线Reset、发光控制信号线EM、存储电容的第一电极C1和晶体管的栅电极同层设置，存储电容的第二电极C2和初始信号线Vinit同层设置，数据线D、电源VDD线和晶体管的源漏电极同层设置，晶体管的源漏电极包括晶体管的第一极和第二极。
在示例性实施例中，第一绝缘层11设置在晶体管的有源区21和晶体管的栅电极之间，第二绝缘层12设置在晶体管的栅电极和存储电容的第二电极C2之间，第三绝缘层13设置在存储电容的第二电极C2和数据线之间。
在示例性实施例中，晶体管的栅电极、晶体管的源漏电极、数据线D和电源线VDD的制作材料均为金属，例如可以为银、铝或铜等金属材料，本公开对此不作任何限定。
在示例性实施例中，有源区21的制作材料为多晶硅，本公开对此不作任何限定。
本公开通过相互连接的存储电容的第二电极以及相互连接的半导体层，保证了位于同一行的所有子像素中的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
本公开通过存储电容的第二电极和半导体层复用为电源连接线传输电源线的电源信号，由于晶体管的有源区与数据线的距离比存储电容的第二电极与数据线之间的距离远，因此，本公开技术方案增大了部分电源线与数据线之间的距离，降低了数据线的负载，进而降低了显示基板的功耗并缩短了数据信号的写入时间。
在示例性实施例中，位于同一列的相邻子像素的有源区通过第三连接部相互连接。
在示例性实施例中，位于第i行第j列的子像素的像素结构与位于第i+1行第j+1列的子像素的像素结构相同。
在示例性实施例中，相邻电源线之间相互对称，第i列电源线VDDi与第i+1列电源线VDDi+1沿数据线延伸方向对称设置。
在示例性实施例中，电源线VDD为折线形。
在示例性实施例中，显示基板中每个像素可以包括四个子像素，像素可以包括第一像素和第二像素。在第一像素中，第i子像素中存储电容的第二电极与第i+1子像素中存储电容的第二电极通过第一连接部相互连接，第i子像素中晶体管的有源区与第i+1子像素中晶体管的有源区断开设置，第二子像素中晶体管的有源区与第三子像素中晶体管的有源区通过第三连接部相互连接，第二子像素中存储电容的第二电极与第三子像素中存储电容的第二电极断开设置。在第二像素中，第二子像素中存储电容的第二电极与第三子像素中存储电容的第二电极通过第一连接部相互连接，第二子像素中晶体管的有源区与第三子像素中晶体管的有源区断开设置，第i子像素中晶体管的有源区与第i+1子像素中晶体管的有源区通过第三连接部相互连接，第i子像素中存储电容的第二电极与第i+1子像素中存储电容的第二电极断开设置。其中，i为小于4的奇数。
图17是以2个沿列方向设置的像素为例进行说明的，位于上方的像素为第一像素，位于下方的像素为第二像素，本公开对此不作任何限定，由于相邻子像素的像素结构对称，因此显示基板中第一像素设置在相邻第二像素之间，第二像素设置在相邻第一像素之间。
图19为本公开提供的另一种显示基板中子像素的一个部分俯视图，未包括电源线、数据线和晶体管的源漏电极，图20为本公开提供的另一种显示基板中子像素的另一部分俯视图，仅包括存储电容的第二电极所在的膜层和数据线所在的膜层，图21为本公开提供的另一种显示基板中子像素的又一部分俯视图，仅包括晶体管的有源区和数据线所在的膜层。如图19所示，显示基板中第三绝缘层上设置有第十一过孔V11。
在示例性实施例中，结合图19和图21，在每个子像素中，存储电容的第二电极C2在基底上的正投影包含第十一过孔V11在基底上的正投影，电 源线通过第十一过孔V11与存储电容的第二电极C2连接。
在示例性实施例中，第十一过孔V11的数量为至少一个。具体的，第十一过孔V11的数量越多，电源线与存储电容的第二电极之间的导电性越好。
在示例性实施例中，如图19所示，显示基板中第一绝缘层、第二绝缘层和第三绝缘层中设置有第十二过孔V12。
在示例性实施例中，结合图19和图21，在每个子像素中，第十二过孔V12在基底上的正投影与第三连接部22在基底上的正投影存在重叠区域，电源线通过第十二过孔V12与晶体管的第三连接部22连接。
在示例性实施例中，第十二过孔V12的数量为至少一个，过孔的数量越多，通过过孔连接的部件的导电性越好。
图19至图21是两个第十一过孔V11，一个第十二过孔V12为例进行说明的，本公开对此不作任何限定。
在示例性实施例中，通过版图布局的合理设计，可以仅通过半导体层实现多个子像素的导电层的相互连接，或者可以仅通过第一金属层实现多个子像素的导电层的相互连接，或者可以仅通过第二金属层实现多个子像素的导电层的相互连接，或者可以仅通过第三金属层实现多个子像素的导电层的相互连接，从而实现位于同一行的子像素的电源线通过驱动电路在栅线延伸方向相互连接，在此不再赘述。
本公开还提供另一种显示基板的制作方法，用于制作上述实施例提供的另一种显示基板，图22为本公开提供的另一种显示基板的制作方法的流程图，如图22所示，本公开提供的另一种显示基板的制作方法包括以下步骤：
步骤B11、提供一基底。
步骤B12、在基底上形成多个子像素、多列电源线以及与电源线同层设置的数据线。
在示例性实施例中，每个子像素可以包括驱动电路；驱动电路可以包括多个晶体管和存储电容；存储电容可以包括相对设置的第一电极和第二电极；晶体管的有源区位于存储电容的第二电极靠近基底的一侧，电源线位于存储电容的第二电极远离基底的一侧。
在示例性实施例中，对于每个子像素，电源线分别与存储电容的第二电极和半导体层的第三连接部连接，每个子像素的存储电容的第二电极与位于同一行的一个相邻子像素的存储电容的第二电极通过第一连接部连接，每个子像素的晶体管的有源区与位于同一行的另一相邻子像素的晶体管的有源区通过第三连接部连接。
本公开提供的另一种显示基板的制作方法用于制作上述实施例提供的另一种显示基板，其实现原理和实现效果类似，在此不再赘述。
以形成两个沿数据线延伸方向设置的像素为例，每个像素包括四个子像素。图23为本公开提供的另一种显示基板的有源区制作示意图，图24为本公开提供的另一种显示基板的第一绝缘层和第一金属层制作示意图，图25为本公开提供的另一种显示基板的第二绝缘层和第二金属层制作示意图，图26为本公开提供的另一种显示基板的第三绝缘层的制作示意图，结合图23～图26，显示基板的制作方法可以包括：
步骤1001、提供一基底，在基底上形成半导体层，如图23所示。
在示例性实施例中，每个子像素的半导体层可以包括第一有源区至第七有源区，且第一有源区至第七有源区为相互连接的一体结构。在示例性实施例中，第一有源区至第七有源区的位置与前述实施例类似，这里不再赘述
在示例性实施例中，在第一方向，对于相邻子像素之间的中心线，相邻子像素的半导体层关于该中心线镜像对称。第i行第j列子像素的半导体层形状与第i+1行第j+1列子像素的半导体层形状相同，第i行第j+1列子像素的半导体层形状与第i+1行第j列子像素的半导体层形状相同。
在示例性实施例中，每个子像素的半导体层与位于同一行的另一相邻子像素的半导体层通过第三连接部连接，每个子像素的半导体层与位于同一列的相邻子像素的半导体层相互连接。
在示例性实施例中，至少一个子像素的半导体层还包括第三连接部22。第i行子像素中，第j列子像素的半导体层与第j+1列子像素的半导体层断开设置，第j+1列子像素的半导体层与第j+2列子像素的半导体层通过第三连接部22相互连接，第j+2列子像素的半导体层与第j+3列子像素的半导体层断开设置。第i+1行子像素，第j列子像素的半导体层与第j+1列子像素的半 导体层通过第三连接部22相互连接，第j+1列子像素的半导体层与第j+2列子像素的半导体层断开设置，第j+2列子像素的半导体层与第j+3列子像素的半导体层通过第三连接部22相互连接。
在示例性实施例中，第三连接部22的第一端与本子像素中第五晶体管的有源区105连接，第三连接部22的第二端与相邻子像素中第五晶体管的有源区105连接。
在示例性实施例中，第三连接部22在基底上的正投影分别与后续形成的数据线和电源线在基底上的正投影存在重叠区域。
在示例性实施例中，通过设置相邻子像素的半导体层相互连接，可以使半导体层的第三连接部22复用为电源连接线，以传输电源线的电源信号。
本公开示例性实施例的半导体层布局合理，结构简洁，能够保证显示基板的显示效果。
步骤1002、在半导体层上形成第一绝缘层，在第一绝缘层上形成第一金属层，如图24所示。
在示例性实施例中，第一金属层可以包括：栅线G、复位信号线Reset、发光控制信号线EM和存储电容的第一电极C1。
在示例性实施例中，栅线G、复位信号线Reset和发光控制线EM沿第一方向延伸，栅线G设置在复位信号线Reset和发光控制线EM之间。存储电容的第一电极C1可以为矩形状，矩形状的角部可以设置倒角，设置在栅线G和发光控制线EM之间，第一电极C1在基底上的正投影与第三有源区在基底上的正投影存在重叠区域。在示例性实施例中，第一极板C1同时作为第三晶体管的栅电极。
在示例性实施例中，栅线G、复位信号线Reset和发光控制线EM可以为非等宽度设置。栅线G设置有向复位信号线Reset一侧凸起的栅极块，栅极块在基底上的正投影与第二有源区在基底上的正投影存在重叠区域，以形成双栅结构。
在示例性实施例中，形成第一金属层图案后，可以利用第一金属层作为遮挡，对半导体层进行导体化处理，被第一金属层遮挡区域的半导体层形成 第一晶体管T1至第七有源区的沟道区域，未被第一金属层遮挡区域的半导体层被导体化。
本公开示例性实施例的第一金属层布局合理，结构简洁，能够保证显示基板的显示效果。
步骤1003、在第一金属层上形成第二绝缘层，在第二绝缘层上形成第二金属层，如图25所示。
在示例性实施例中，第二金属层可以包括：初始信号线Vinit和存储电容的第二电极C2。
在示例性实施例中，初始信号线Vinit沿第一方向延伸，设置在复位信号线Reset远离栅线G的一侧。每个子像素中存储电容的第二电极C2的轮廓可以为矩形状，位于栅线G和发光控制线EM之间。
在示例性实施例中，第二电极C2的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二电极C2在基底上的正投影与第一电极C1在基底上的正投影存在重叠区域。第二电极C2的中部设置有开口，开口可以为矩形，使第二电极C2形成环形结构。开口暴露出覆盖第一电极C1的第二绝缘层，且第一电极C1在基底上的正投影包含开口在基底上的正投影。
在示例性实施例中，第i行第j列子像素的第二电极C2与第i行第j+1列子像素的第二电极C2为通过第一连接部C3相互连接的一体结构，第i行第j+1列子像素的第二电极C2与第i行第j+2列子像素的第二电极C2为断开设置，第i行第j+2列子像素的第二电极C2与第i行第j+3列子像素的第二电极C2为通过第一连接部C3相互连接的一体结构。第i+1行第j列子像素的第二电极C2与第i+1行第j+1列子像素的第二电极C2为断开设置，第i+1行第j+1列子像素的第二电极C2与第i+1行第j+2列子像素的第二电极C2为通过第一连接部C3相互连接的一体结构，第i+1行第j+2列子像素的第二电极C2与第i+1行第j+3列子像素的第二电极C2为断开设置。该结构使相邻子像素的第二电极C2可以复用为电源信号线，可以保证相邻子像素的电源线提供的电源信号相同，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施例中，第二金属层还可以包括屏蔽电极C4，屏蔽电极C4 在基底上的正投影与后续形成的电源线在基底上的正投影存在重叠区域，电源线通过过孔与屏蔽电极C4连接。在示例性实施例中，屏蔽电极C4配置为屏蔽数据线对驱动电路的影响。
在示例性实施例中，屏蔽电极C4的形状呈“7”字形，包括沿第一方向延伸的第一部和沿第二方向延伸的第二部，第一部靠近第二部的一端与第二部靠近第一部的一端相互连接，形成具有直角的折线。
在示例性实施例中，在第二方向，屏蔽电极C4设置在栅线G与复位信号线Reset之间，在第一方向，屏蔽电极C4的第二部设置在后续形成的数据线与电源线之间。
在示例性实施例中，屏蔽电极C4的第二部与第一金属层的栅极块均沿第二方向延伸，两者存在正对区域，即屏蔽电极C4靠近栅极块第一方向一侧的边缘与栅极块靠近屏蔽电极C4第一方向一侧的边缘存在相对设置的区域。
本公开示例性实施例的第二金属层布局合理，结构简洁，能够保证显示基板的显示效果。
步骤1004、在第二金属层上形成第三绝缘层，第三绝缘层设置暴露出存储电容的第二电极的第十一过孔V11，第一绝缘层、第二绝缘层和第三绝缘层设置暴露出第三连接部的第十二过孔V12，如图26所示。
在示例性实施例中，第十一过孔V11配置为使第二电极C2与后续形成的电源线连接，第十二过孔V12配置为使半导体层的第三连接部与后续形成的电源线连接，使相邻子像素中相互连接的第二电极C2和相邻子像素中相互连接的第三连接部一起复用为电源连接线。
在示例性实施例中，第十一过孔V11的数量可以为两个，两个第十一过孔V11沿第二方向依次设置，可以提高第二电极与电源线之间连接的可靠性。
本公开示例性实施例的过孔布局合理，结构简洁，能够保证显示基板的显示效果。
步骤1005，在第三绝缘层上形成第三金属层，如图17所示。
在示例性实施例中，第三金属层包括数据线D、电源线VDD和多个晶 体管的源漏电极，数据线D包括第一子数据线DO和第二子数据线DE。
在示例性实施例中，第一子数据线DO、第二子数据线DE和电源线VDD沿第二方向延伸，第一子数据线DO位于子像素的一侧，第二子数据线DE位于子像素的另一侧，电源线VDD位于第一子数据线DO和第二子数据线DE之间。
在示例性实施例中，位于同一列的相邻子像素连接不同子数据线。例如，第i行第j列的子像素连接第j列数据线中的第一子数据线，第i+1行第j列的子像素连接第j列数据线中的第二子数据线。或者，第i行第j列的子像素连接第j列数据线中的第二子数据线，第i+1行第j列的子像素连接第j列数据线中的第一子数据线。
在示例性实施例中，每个子像素的电源线VDD通过第十一过孔V11与第二电极C2连接，每个子像素的电源线VDD通过第十二过孔V12与半导体层的第三连接部连接。这样，在一行中，通过一个相邻子像素的存储电容的第二电极C2相互连接，另一个相邻子像素的半导体层的第三连接部相互连接，相邻子像素中相互连接的第二电极C2和相邻子像素中相互连接的半导体层一起复用为电源连接线，使得向每个子像素提供的电源信号均相同，保证了显示基板的显示效果。
在示例性实施例中，每个子像素的电源线VDD可以为折线。沿着第二方向，每个子像素的电源线VDD可以包括依次连接的第一电源部、第二电源部和第三电源部。第i行第j列的子像素对应的电源线中，第一电源部的第一端与位于第i-1行第j列的子像素中的第三电源部的第二端连接，第一电源部的第二端沿着第二方向延伸，与第二电源部的第一端连接；第二电源部的第二端沿着倾斜方向延伸，与第三电源部的第一端连接，倾斜方向与第二方向具有夹角，夹角可以大于0度，且小于90度；第三电源部的第二端沿着第二方向延伸，与位于第i+1行第j列的子像素中的第一电源部的第一端连接。
在示例性实施例中，第一电源部可以为等宽度的直线，第二电源部可以为变宽度的斜线，第三电源部可以为等宽度的直线。第一电源部和第二电源部与第一子数据线(或第二子数据线)平行，第二电源部与第一电源部之间 的夹角可以大于90度且小于180度，第二电源部与第三电源部之间的夹角可以大于90度且小于180度。
在示例性实施例中，第三电源部的宽度可以小于第一电源部的宽度。电源线VDD采用变宽度的折线设置，不仅可以便于像素结构的布局，而且可以降低电源线VDD与数据线的寄生电容。
在示例性实施例中，第三电源部在基底上的正投影与第二电极C2在基底上的正投影存在重叠区域。
在示例性实施例中，第三电源部在基底上的正投影与第一电极C1在基底上的正投影存在重叠区域。
在示例性实施例中，第三电源部在基底上的正投影与栅线G在基底上的正投影存在重叠区域。
本公开所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，显示基板可以包括第四金属层，数据线D、电源线VDD和多个晶体管的源漏电极可以位于不同的金属层上，本公开在此不做限定。
本公开通过将存储电容的第二极板和晶体管的有源区复用为电源连接线传输电源线的电源信号，由于晶体管的有源区与数据线的距离较远，因此，本公开方案增大了部分电源连接线与数据线之间的距离，降低了数据线的负载，进而降低了显示基板的功耗并缩短了数据信号的写入时间。
本公开还提供一种显示装置，在示例性实施例中，显示装置包括前述的显示基板。
在一些可能的实现方式中，显示基板可以为OLED显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本发明实施例并不以此为限。
其中，显示基板为前述实施例提供的显示基板，其实现原理和实现效果类似，在此不再赘述。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作 位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (70)

  1. 一种显示基板，在平行于显示基板的平面内，所述显示基板包括设置在基底上的多条栅线、多条数据线、多条电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；在垂直于显示基板的平面内，所述显示基板包括基底和设置在所述基底上的多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。
  2. 根据权利要求1所述的显示基板，其中，在所述数据线延伸方向，所述电源线包括多个依次连接的子电源线，至少一个子电源线设置在一个子像素中；至少一个子像素的子电源线包括依次连接的多个电源部，至少一个电源部和与所述电源部相连接的电源部之间存在大于90度且小于180度的夹角。
  3. 根据权利要求1至2任一项所述的显示基板，其中，所述至少一个电源部和与所述电源部相连接的电源部中，其中一个电源部与所述数据线平行设置。
  4. 根据权利要求1至3任一项所述的显示基板，其中，所述子电源线包括第一电源部、第二电源部和第三电源部；所述第二电源部配置为连接所述第一电源部和第三电源部，所述第一电源部和第三电源部与所述数据线平行设置，所述第二电源部与所述第一电源部之间的夹角大于90度且小于180度，所述第二电源部与所述第三电源部之间的夹角大于90度且小于180度。
  5. 根据权利要求1至4任一项所述的显示基板，其中，所述第一电源部与位于相同列上一行子像素中的第三电源部连接，所述第三电源部与位于相同列下一行子像素中的第一电源部连接。
  6. 根据权利要求1至5任一项所述的显示基板，其中，所述第一电源部沿着数据线延伸方向延伸的长度大于所述第一电源部的平均宽度，所述第二电源部沿着倾斜方向延伸的长度大于所述第二电源部的平均宽度，所述第三 电源部沿着数据线延伸方向延伸的长度大于所述第三电源部的平均宽度；所述倾斜方向是所述第二电源部与所述第一电源部之间具有所述夹角的方向。
  7. 根据权利要求1至6任一项所述的显示基板，其中，所述第三电源部的平均宽度小于所述第一电源部的平均宽度。
  8. 根据权利要求1至7任一项所述的显示基板，其中，所述第一电源部靠近所述第三电源部栅线延伸方向上一侧的边缘与所述第三电源部靠近所述第一电源部栅线延伸方向上一侧的边缘之间的平均距离，与所述第三电源部的平均宽度相当。
  9. 根据权利要求1至8任一项所述的显示基板，其中，所述显示基板还包括第一连接部，至少一个子像素中存储电容的第二电极与栅线延伸方向相邻子像素中存储电容的第二电极通过所述第一连接部相互连接；至少一个子像素中，所述第二电源部在基底上的正投影与所述存储电容的第二电极在基底上的正投影存在重叠区域，或者，所述第二电源部在基底上的正投影与所述第一连接部在基底上的正投影存在重叠区域。
  10. 根据权利要求1至9任一项所述的显示基板，其中，所述第二电源部在基底上的正投影与所述存储电容的第一电极在基底上的正投影存在重叠区域。
  11. 根据权利要求1至10任一项所述的显示基板，其中，所述第二电源部在基底上的正投影与所述栅线在基底上的正投影存在重叠区域。
  12. 根据权利要求1至11任一项所述的显示基板，其中，所述多个晶体管包括第二晶体管，所述第一电源部在基底上的正投影与所述第二晶体管在基底上的正投影存在重叠区域。
  13. 根据权利要求1至12任一项所述的显示基板，其中，所述显示基板还包括设置在所述第四导电层上的第五绝缘层和设置在所述第五绝缘层上的第五导电层，所述第五绝缘层上设置有第五过孔，所述第五过孔配置为使所述第五导电层与所述第四导电层连接；所述第五过孔在基底上的正投影与所述子电源线在基底上的正投影不存在重叠区域。
  14. 根据权利要求1至13任一项所述的显示基板，其中，至少一个子像 素中，所述第五过孔在基底上的正投影与所述子电源线中第一电源部在所述数据线延伸方向的虚拟延长线在基底上的正投影存在重叠区域。
  15. 根据权利要求1至14任一项所述的显示基板，其中，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有第八过孔，所述第八过孔配置为使所述数据线将数据信号写入到所述半导体层；所述第八过孔在基底上的正投影与所述子电源线中第一电源部和第二电源部在基底上的正投影不存在重叠区域。
  16. 根据权利要求1至15任一项所述的显示基板，其中，至少一个子像素中，所述第八过孔在基底上的正投影与所述子电源线中第三电源部在所述数据线延伸方向的虚拟延长线在基底上的正投影存在重叠区域。
  17. 根据权利要求1至16任一项所述的显示基板，其中，所述电源线设置在所述第三导电层，或者设置在所述第四导电层，所述电源线与所述数据线同层设置。
  18. 根据权利要求1至17任一项所述的显示基板，其中，所述电源线设置在所述第三导电层，所述数据线设置在所述第四导电层，或者，所述数据线设置在所述第三导电层，所述电源线设置在所述第四导电层。
  19. 根据权利要求1至18任一项所述的显示基板，其中，所述显示基板还包括第一连接部，至少一个子像素中存储电容的第二电极与栅线延伸方向相邻子像素中存储电容的第二电极通过所述第一连接部相互连接。
  20. 根据权利要求19所述的显示基板，其中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极通过所述第一连接部相互连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极直接连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极通过所述第一连接部相互连接；另一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极直接连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极通过所述第一连接部相互连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极直接连接。
  21. 根据权利要求20所述的显示基板，其中，第1子像素中半导体层与第2子像素中半导体层间隔设置，第2子像素中半导体层与第3子像素中半导体层间隔设置，第3子像素中半导体层与第4子像素中半导体层间隔设置。
  22. 根据权利要求20所述的显示基板，其中，所述第三导电层包括第五晶体管的第一极；第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极间隔设置，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极间隔设置，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极间隔设置。
  23. 根据权利要求19所述的显示基板，其中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极通过所述第一连接部相互连接，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极断开设置，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极通过所述第一连接部相互连接；另一行的第1子像素中存储电容的第二电极与第2子像素中存储电容的第二电极断开设置，第2子像素中存储电容的第二电极与第3子像素中存储电容的第二电极通过所述第一连接部相互连接，第3子像素中存储电容的第二电极与第4子像素中存储电容的第二电极断开设置。
  24. 根据权利要求23所述的显示基板，其中，所述第三导电层包括第五晶体管的第一极和第二连接部；一行的第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极断开设置，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极通过所述第二连接部相互连接，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极断开设置；另一行的第1子像素中第五晶体管的第一极与第2子像素中第五晶体管的第一极通过所述第二连接部相互连接，第2子像素中第五晶体管的第一极与第3子像素中第五晶体管的第一极断开设置，第3子像素中第五晶体管的第一极与第4子像素中第五晶体管的第一极通过所述第二连接部相互连接。
  25. 根据权利要求22或24所述的显示基板，其中，在栅线延伸方向，所述电源线通过所述存储电容的第二电极和第五晶体管的第一极相互连接。
  26. 根据权利要求25所述的显示基板，其中，所述第四绝缘层上设置有 暴露出所述第五晶体管的第一极的第一过孔，所述第三绝缘层上设置有暴露出所述存储电容的第二电极的第二过孔，所述电源线通过所述第一过孔与所述第五晶体管的第一极连接，所述第五晶体管的第一极通过所述第二过孔与所述存储电容的第二电极连接。
  27. 根据权利要求26所述的显示基板，其中，至少一个子像素中，所述第一过孔的数量为一个，所述第二过孔的数量为多个，多个第二过孔沿所述数据线延伸方向设置；所述电源线在基底上的正投影包含所述第一过孔在基底上的正投影，所述第五晶体管的第一极在基底上的正投影包含所述第二过孔在基底上的正投影。
  28. 根据权利要求23所述的显示基板，其中，所述半导体层包括第三连接部；一行的第1子像素中半导体层与第2子像素中半导体层断开设置，第2子像素中半导体层与第3子像素中半导体层通过所述第三连接部相互连接，第3子像素中半导体层与第4子像素中半导体层断开设置；另一行的第1子像素中半导体层与第2子像素中半导体层通过所述第三连接部相互连接，第2子像素中半导体层与第3子像素中半导体层断开设置，第3子像素中半导体层与第4子像素中半导体层通过所述第三连接部相互连接。
  29. 根据权利要求28所述的显示基板，其中，在栅线延伸方向，所述电源线通过所述半导体层的第三连接部和存储电容的第二电极相互连接。
  30. 根据权利要求29所述的显示基板，其中，所述第三绝缘层上设置有暴露出所述存储电容的第二电极的第十一过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出所述半导体层的第三连接部的第十二过孔，所述电源线通过所述第十一过孔与所述存储电容的第二电极连接，所述电源线通过所述第十二过孔与所述半导体层的第三连接部连接。
  31. 根据权利要求30所述的显示基板，其中，至少一个子像素中，所述第十一过孔的数量为一个，所述第十二过孔的数量为多个，多个第十二过孔沿所述数据线延伸方向设置；所述电源线在基底上的正投影包含所述第十一过孔和第十二过孔在基底上的正投影。
  32. 根据权利要求1至31任一项所述的显示基板，其中，所述多个晶体 管包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；至少一个子像素中，所述半导体层至少包括第一晶体管所在位置的第一有源区、第二晶体管所在位置的第二有源区、第三晶体管所在位置的第三有源区、第四晶体管所在位置的第四有源区、第五晶体管所在位置的第五有源区、第六晶体管所在位置的第六有源区和第七晶体管所在位置的第七有源区，所述第一有源区、第二有源区、第三有源区、第四有源区、第五有源区、第六有源区和第七有源区为一体结构。
  33. 根据权利要求32所述的显示基板，其中，所述第二有源区与第一有源区之间栅线延伸方向的距离，小于所述第二有源区与第七有源区之间栅线延伸方向的距离。
  34. 根据权利要求32所述的显示基板，其中，沿着写入数据信号的数据线到电源线的方向，所述第七有源区和第一有源区依次设置。
  35. 根据权利要求32所述的显示基板，其中，至少一个子像素包括沿数据线延伸方向依次设置的第一区域、第二区域和第三区域；所述第一有源区和第七有源区设置在所述第一区域内远离第二区域的一侧，所述第二有源区和第四有源区设置在所述第一区域内靠近第二区域的一侧；所述第三有源区设置在所述第二区域内；所述第五有源区和第六有源区设置在所述第三区域内。
  36. 根据权利要求32所述的显示基板，其中，所述第一晶体管的第一极与初始信号线连接，第一晶体管T1的第二极与所述存储电容的第一电极连接，所述第二晶体管的第一极与存储电容的第一电极连接，所述第二晶体管的第二极与第六晶体管的第二极连接，所述第三晶体管的第一极与第四晶体管的第二极连接，所述第三晶体管的第二极与第六晶体管的第二极连接，所述第四晶体管的第一极与数据线连接，所述第五晶体管的第一极与电源线连接，所述第五晶体管的第二极与第三晶体管的第一极连接，所述第六晶体管的第二极与发光器件的阳极连接，所述第七晶体管的第一极与初始信号线连接，所述第七晶体管的第二极与发光器件的阳极连接；所述第一有源区分别与第二有源区和第七有源区连接，所述第二有源区分别与第三有源区和第六有源区连接，所述第四有源区分别与第三有源区和第五有源区连接。
  37. 根据权利要求32所述的显示基板，其中，在栅线延伸方向，相邻子像素的半导体层互为对称关系。
  38. 根据权利要求32所述的显示基板，其中，至少存在一个包括2*2个子像素的区域，一行的第1子像素中半导体层形状与另一行的第2子像素中半导体层形状相同，一行的第2子像素中半导体层形状与另一行的第1子像素中半导体层形状相同。
  39. 根据权利要求32所述的显示基板，其中，所述半导体层包括第三连接部，至少一个子像素中半导体层通过所述第三连接部与栅线延伸方向相邻子像素中半导体层连接。
  40. 根据权利要求39所述的显示基板，其中，所述第三连接部与第五晶体管的有源区连接。
  41. 根据权利要求39所述的显示基板，其中，所述第三连接部在基底上的正投影与所述电源线在基底上的正投影存在重叠区域。
  42. 根据权利要求39所述的显示基板，其中，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出所述第三连接部的第十二过孔，所述电源线通过所述第十二过孔与所述第三连接部连接。
  43. 根据权利要求39所述的显示基板，其中，至少存在一个包括2*4个子像素的区域，一行的第1子像素中半导体层与第2子像素中半导体层断开设置，第2子像素中半导体层与第3子像素中半导体层通过所述第三连接部相互连接，第3子像素中半导体层与第4子像素中半导体层断开设置；另一行的第1子像素中半导体层与第2子像素中半导体层通过所述第三连接部相互连接，第2子像素中半导体层与第3子像素中半导体层断开设置，第3子像素中半导体层与第4子像素中半导体层通过所述第三连接部相互连接。
  44. 根据权利要求1至43任一项所述的显示基板，其中，在所述数据线延伸方向，所述数据线包括多个依次连接的子数据线；至少存在一个子像素，所述子像素与栅线延伸方向相邻子像素之间设置有两条子数据线。
  45. 根据权利要求44所述的显示基板，其中，所述两条子数据线相互平行。
  46. 根据权利要求44所述的显示基板，其中，至少一个子像素内，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出半导体层的第八过孔，所述第四绝缘层上设置有暴露出第四晶体管的第一极的第三过孔，所述数据线通过所述第三过孔与第四晶体管的第一极连接，所述第四晶体管的第一极通过所述第八过孔与半导体层连接。
  47. 根据权利要求46所述的显示基板，其中，在栅线延伸方向，相邻子像素的第八过孔互为对称关系。
  48. 根据权利要求44所述的显示基板，其中，所述数据线设置所述第三导体层，所述电源线设置所述第三导体层。
  49. 根据权利要求44所述的显示基板，其中，所述数据线设置在所述第四导体层，所述电源线设置在所述第三导体层或第四导体层。
  50. 根据权利要求44所述的显示基板，其中，至少一列子像素中，所述数据线包括第一子数据线和第二子数据线，所述第一子数据线和第二子数据线分别位于该列子像素的两侧。
  51. 根据权利要求50所述的显示基板，其中，所述电源线位于所述第一子数据线和第二子数据线之间。
  52. 根据权利要求1至51任一项所述的显示基板，其中，在栅线延伸方向，相邻子像素的像素结构互为对称关系。
  53. 根据权利要求52所述的显示基板，其中，至少存在一个包括2*2个子像素的区域，一行的第1子像素中像素结构与另一行的第2子像素中像素结构相同，一行的第2子像素中像素结构与另一行的第1子像素中像素结构相同。
  54. 根据权利要求1至53任一项所述的显示基板，其中，所述显示基板还包括复位信号线、发光控制线和初始信号线；所述半导体层至少包括多个晶体管的有源区，所述第一导体层至少包括栅线、发光控制线、复位信号线、存储电容的第一电极和多个晶体管的栅电极，所述第二导体层至少包括初始信号线和存储电容的第二电极；所述第三导体层至少包括多个晶体管的源漏电极，所述第四导体层至少包括数据线和电源线。
  55. 根据权利要求54所述的显示基板，其中，至少一个子像素包括沿着数据线延伸方向依次设置的第一区域、第二区域和第三区域；所述栅线、初始信号线、复位信号线位于所述第一区域，所述存储电容的第一电极和第二电极位于所述第二区域，所述发光控制线位于所述第三区域。
  56. 根据权利要求54所述的显示基板，其中，所述第二导体层还包括屏蔽电极，至少一个子像素中，所述屏蔽电极在基底上的正投影与所述电源线在基底上的正投影存在重叠区域。
  57. 根据权利要求56所述的显示基板，其中，所述电源线通过过孔与所述屏蔽电极连接。
  58. 根据权利要求56所述的显示基板，其中，在数据线延伸方向，所述屏蔽电极设置在栅线与复位信号线之间。
  59. 根据权利要求56所述的显示基板，其中，所述屏蔽电极包括沿栅线延伸方向延伸的第一部和沿数据线延伸方向延伸的第二部，所述第一部靠近第二部的一端与所述第二部靠近第一部的一端相互连接。
  60. 根据权利要求59所述的显示基板，其中，所述第一导体层还包括沿数据线延伸方向延伸的栅极块，所述栅极块与所述栅线连接；在数据线延伸方向，所述栅极块与所述屏蔽电极的第二部存在正对区域。
  61. 根据权利要求54所述的显示基板，其中，所述多个晶体管的源漏电极包括第二晶体管的第一极，所述第二绝缘层和第三绝缘层上设置有暴露出所述存储电容的第一电极的第七过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出第二晶体管的有源区的第九过孔，所述第二晶体管的第一极的一端通过第七过孔与所述存储电容的第一电极连接，另一端通过第九过孔与第二晶体管的有源区连接。
  62. 根据权利要求61所述的显示基板，其中，所述第二晶体管的第一极在基底上的正投影与所述栅线在基底上的正投影存在重叠区域，所述第二晶体管的第一极在基底上的正投影与所述发光控制线、复位信号线和初始信号线在基底上的正投影没有重叠区域。
  63. 根据权利要求54所述的显示基板，其中，所述多个晶体管的源漏电 极包括第一晶体管的第一极，所述第三绝缘层上设置有暴露出初始信号线的第六过孔，所述第一绝缘层、第二绝缘层和第三绝缘层上设置有暴露出第一晶体管的有源区的第十过孔，所述第一晶体管的第一极的一端通过第六过孔与所述初始信号线连接，另一端通过第十过孔与第一晶体管的有源区连接。
  64. 根据权利要求63所述的显示基板，其中，所述第一晶体管的第一极在基底上的正投影与所述复位信号线在基底上的正投影存在重叠区域，所述所述第一晶体管的第一极在基底上的正投影与所述栅线和发光控制线在基底上的正投影没有重叠区域。
  65. 根据权利要求54所述的显示基板，其中，所述显示基板还包括设置在所述第四导电层上的第五绝缘层和设置在所述第五绝缘层上的第五导电层；所述第四导体层中还包括连接电极，所述多个晶体管的源漏电极包括第六晶体管的第二极；所述第四绝缘层设置有暴露出第六晶体管的第二极的第四过孔，所述第五绝缘层上设置有暴露出连接电极的第五过孔，所述连接电极通过第四过孔与第六晶体管的第二极连接，所述第五导体层通过第五过孔与所述连接电极连接。
  66. 根据权利要求65所述的显示基板，其中，所述连接电极在基底上的正投影与第二晶体管的第一极在基底上的正投影存在重叠区域。
  67. 根据权利要求54所述的显示基板，其中，至少一个子像素至少包括：暴露出第五晶体管的第一极的第一过孔，所述第一过孔配置为使第五晶体管的第一极与所述电源线连接；暴露出存储电容的第二电极的第二过孔，所述第二过孔配置为使第二电极与第五晶体管的第一极连接；暴露出第四晶体管的第一极的第三过孔，所述第三过孔配置为使第四晶体管的第一极与所述数据线连接；暴露出第六晶体管的第二极的第四过孔，所述第四过孔配置为使第六晶体管的第二极与连接电极连接；暴露出连接电极的第五过孔，所述第五过孔配置为使连接电极与第五导体层的阳极连接；暴露出初始信号线的第六过孔，所述第六过孔配置为使初始信号线与第一晶体管的第一极连接；暴露出存储电容的第一电极的第七过孔，所述第七过孔配置为使第一电极与第二晶体管的第一极连接；暴露出第四晶体管的有源区的第八过孔，所述第八过孔配置为使第四晶体管的有源区与第四晶体管的第一极连接；暴露出第二 晶体管的有源区的第九过孔，所述第九过孔配置为使第二晶体管的有源区与第二晶体管的第一极连接；暴露出第一晶体管的有源区的第十过孔，所述第十过孔配置为使第一晶体管的有源区与第一晶体管的第一极连接。
  68. 根据权利要求54所述的显示基板，其中，至少一个子像素至少包括：暴露出存储电容的第二电极的第十一过孔，所述第十一过孔配置为使第二电极与电源线连接；暴露出第三连接部的第十二过孔，所述第十二过孔配置为使第三连接部与电源线连接。
  69. 一种显示装置，包括如权利要求1至68任一项所述的显示基板。
  70. 一种显示基板的制作方法，配置为制作如权利要求1至69任一项所述的显示基板，在平行于显示基板的平面内，所述显示基板包括设置在基底上的栅线、数据线、电源线和多个子像素，至少一个子像素包括发光器件和配置为驱动所述发光器件发光的驱动电路，所述驱动电路包括多个晶体管和存储电容；所述制作方法包括：
    提供一基底；
    在所述基底形成多个功能层；所述多个功能层包括依次设置的半导体层、第一导电层、第二导电层、第三导电层和第四导电层；所述多个功能层之间分别设置有第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层；在栅线延伸方向，所述电源线通过至少一个功能层相互连接。
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