WO2021083226A1 - 一种显示基板及其制作方法、显示装置 - Google Patents

一种显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021083226A1
WO2021083226A1 PCT/CN2020/124452 CN2020124452W WO2021083226A1 WO 2021083226 A1 WO2021083226 A1 WO 2021083226A1 CN 2020124452 W CN2020124452 W CN 2020124452W WO 2021083226 A1 WO2021083226 A1 WO 2021083226A1
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Prior art keywords
electrode
pixel
transistors
sub
light
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PCT/CN2020/124452
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English (en)
French (fr)
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WO2021083226A9 (zh
Inventor
徐攀
林奕呈
王玲
王国英
张星
韩影
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京东方科技集团股份有限公司
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Priority to US17/298,032 priority Critical patent/US20220102460A1/en
Priority to EP20878024.7A priority patent/EP4053905A4/en
Priority to KR1020217035675A priority patent/KR20220088634A/ko
Priority to JP2021564799A priority patent/JP2023501023A/ja
Publication of WO2021083226A1 publication Critical patent/WO2021083226A1/zh
Publication of WO2021083226A9 publication Critical patent/WO2021083226A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • OLED Organic Light-Emitting Device
  • LCD Liquid Crystal Display
  • OLED display substrates can be divided into three types according to the direction of light emission: bottom-emitting OLED, top-emitting OLED, and double-side emitting OLED.
  • bottom-emitting OLED means that the light in the OLED device is emitted toward the substrate.
  • the bottom-emission OLED display substrate is limited by the pixel opening area, so that each sub-pixel occupies a large area, which in turn leads to a low number of pixels per unit area (Pixels Per Inch, PPI) in the bottom-emission OLED display substrate. Unable to achieve high PPI.
  • the present disclosure provides a display substrate, including: a substrate and a plurality of sub-pixels disposed on the substrate, each sub-pixel includes a light-emitting area and a non-light-emitting area, each sub-pixel is provided with a driving circuit;
  • the driving The circuit includes: a storage capacitor and a plurality of transistors; the plurality of transistors includes: a switching transistor, a driving transistor, and a sensing transistor;
  • the plurality of transistors are located in the non-light-emitting area
  • the storage capacitor is a transparent capacitor
  • the orthographic projection of the storage capacitor on the substrate overlaps with the light-emitting area
  • the storage The first electrode of the capacitor is arranged in the same layer as the active layers of the plurality of transistors, and is arranged in a different layer with the source and drain electrodes of the plurality of transistors, and the second electrode of the storage capacitor is located near the first electrode. Said one side of the base;
  • the first electrode of the driving transistor is electrically connected to the second electrode, and the first electrode of the sensing transistor is electrically connected to the second electrode.
  • the display substrate further includes: a buffer layer and a light-shielding layer disposed on a side of the active layer of the plurality of transistors close to the base, the light-shielding layer and the second The electrode is arranged on the side of the buffer layer close to the substrate;
  • the orthographic projection of the second electrode on the substrate covers the orthographic projection of the light shielding layer on the substrate, and the surface of the light shielding layer close to the second electrode is in full contact with the second electrode.
  • the light shielding layer is disposed on the side of the second electrode close to the substrate, or the second electrode is disposed on the side of the light shielding layer close to the substrate.
  • the display substrate further includes: an interlayer insulating layer disposed between the source and drain electrodes of the plurality of transistors and the active layer of the plurality of transistors;
  • the buffer layer includes a first via hole and a second via hole exposing the second electrode
  • the interlayer insulating layer includes: a third via hole exposing the first via hole and a third via hole exposing the first via hole.
  • the first electrode of the driving transistor is connected to the second electrode through the first via hole and the third via hole, and the first electrode of the sensing transistor passes through the second via hole And the fourth via is connected to the second electrode.
  • the display substrate further includes: a plurality of rows of gate lines and a plurality of columns of data lines arranged on the substrate; each sub-pixel is defined by the intersection of the gate line and the data line, and the plurality of sub-pixels Corresponding to the multiple rows of gate lines and the multiple columns of data lines respectively, the multiple rows of gate lines include: a first gate line and a second gate line,
  • the first gate line and the second gate line are arranged in the same layer as the gate electrodes of the plurality of transistors, and the multiple columns of data lines are arranged in the same layer as the source and drain electrodes of the plurality of transistors.
  • the first electrode is respectively connected to the first electrode of the switching transistor and the gate electrode of the driving transistor;
  • the gate electrode of the switching transistor is connected to the first gate line of the gate lines corresponding to the sub-pixel; the second electrode of the switching transistor is connected to the data line corresponding to the sub-pixel, and the gate electrode of the sensing transistor is connected to the sub-pixel The second gate line of the corresponding gate lines is connected.
  • the non-light-emitting area includes: a first non-light-emitting area and a second non-light-emitting area, and the first non-light-emitting area and the second non-light-emitting area are located at the same location. On both sides of the light-emitting area, and arranged along the extending direction of the multiple columns of data lines;
  • the sensing transistor and the second gate line are all located in the first non-emitting area, and the switching transistor, the driving transistor, and the first gate line are all located in the second non-emitting area.
  • the display substrate further includes: power lines and sensing lines arranged in the same layer as the multiple columns of data lines, each pixel includes: four sub-pixels arranged along the extending direction of the gate lines, Each pixel corresponds to two columns of power lines and one column of sensing lines;
  • the sensing line corresponding to the pixel is located between the second sub-pixel and the third sub-pixel, and a column of power lines corresponding to the pixel is located at a distance of the first sub-pixel away from the second sub-pixel.
  • a column of power lines corresponding to the pixel is located at a distance of the first sub-pixel away from the second sub-pixel.
  • another column of power lines corresponding to the pixel is located on a side of the fourth sub-pixel away from the third sub-pixel;
  • the data line corresponding to the first sub-pixel is located on the side of the first sub-pixel close to the second sub-pixel; the data line corresponding to the second sub-pixel is located in the second sub-pixel close to the first sub-pixel.
  • the display substrate further includes: a power connection line provided on the same layer as the gate electrodes of the plurality of transistors and a sensing connection line provided on the same layer as the light shielding layer, and each pixel corresponds to two power sources provided along the extending direction of the gate line A connecting wire and two sensing connecting wires arranged along the extending direction of the gate wire; the power connecting wire corresponds to the power wire respectively; the power connecting wire is connected to the corresponding power wire; the two sensing connecting wires are connected to the sensing wire;
  • the second pole of the driving transistor of the second sub-pixel is connected to a power connection line
  • the second pole of the driving transistor of the third sub-pixel is connected to another power connection line
  • the second electrode of the sensing transistor of the first sub-pixel is connected to a sensing connection line
  • the second electrode of the sensing transistor of the fourth sub-pixel is connected to another sensing connection line.
  • the buffer layer is further provided with a fifth via hole exposing the sensing connection line
  • the interlayer insulating layer is further provided with a sixth via hole exposing the fifth via hole.
  • the second electrode of the sensing transistor is connected to the sensing connection line through the fifth via hole and the sixth via hole.
  • the display substrate further includes: a gate insulating layer disposed between the gate electrodes of the plurality of transistors and the active layer of the plurality of transistors;
  • the orthographic projection of the gate insulating layer on the substrate coincides with the orthographic projection of the gate electrodes of the plurality of transistors on the substrate.
  • the material of the first electrode includes a transparent metal oxide
  • the material of the second electrode includes a transparent conductive material
  • each sub-pixel is further provided with a light-emitting element and a filter with the same color as the sub-pixel;
  • the light-emitting element includes: an anode, an organic light-emitting layer and a cathode arranged in sequence, the anode and the The first electrode of the sensing transistor is connected, the anode is a transmissive electrode, and the cathode is a reflective electrode;
  • the orthographic projection of the light-emitting element on the substrate overlaps the light-emitting area, the filter is located in the light-emitting area, and is arranged on the side of the light-emitting element close to the substrate, and the anode
  • the orthographic projection on the substrate covers the orthographic projection of the filter on the substrate.
  • the display substrate further includes a passivation layer and a flat layer disposed on a side of the source and drain electrodes of the plurality of transistors away from the base;
  • the passivation layer is provided on the side of the filter close to the substrate, the flat layer is provided between the light-emitting element and the filter; the passivation layer is provided with exposing the A seventh via hole of the first electrode of the sensing transistor, the flat layer is provided with an eighth via hole exposing the seventh via hole;
  • the anode is connected to the first electrode of the sensing transistor through the seventh via hole and the eighth via hole;
  • the orthographic projection of the eighth via on the substrate and the orthographic projection of the fourth via on the substrate do not completely overlap.
  • the present disclosure provides a display device including any of the above-mentioned display substrates.
  • the present disclosure provides a method for manufacturing a display substrate for manufacturing any of the above-mentioned display substrates, and the method includes:
  • each sub-pixel includes a light-emitting area and a non-light-emitting area, and each sub-pixel is provided with a driving circuit;
  • the driving circuit includes: a storage capacitor and a plurality of transistors;
  • the plurality of transistors includes: Switching transistors, driving transistors and sensing transistors;
  • the plurality of transistors are located in the non-light-emitting area
  • the storage capacitor is a transparent capacitor
  • the orthographic projection of the storage capacitor on the substrate overlaps with the light-emitting area
  • the storage The first electrode of the capacitor is arranged in the same layer as the active layers of the plurality of transistors, and is arranged in a different layer with the source and drain electrodes of the plurality of transistors, and the second electrode of the storage capacitor is located near the first electrode. Said one side of the base;
  • the first electrode of the driving transistor is electrically connected to the second electrode, and the first electrode of the sensing transistor is electrically connected to the second electrode.
  • the display substrate further includes: a gate line, a data line, a power line, and a sensing line; the gate line includes: a first gate line and a second gate line;
  • the step of forming a plurality of sub-pixels on the substrate includes:
  • the data line, the power supply line, the sensing line, and the source and drain electrodes of the plurality of transistors are formed on the gate electrodes of the plurality of transistors, the first gate line, and the second gate line ;
  • a filter and a light emitting element are sequentially formed on the data line, the power line, the sensing line, and the source and drain electrodes of the plurality of transistors.
  • the step of forming a light shielding layer and the second electrode on the substrate includes:
  • the light-shielding layer and the second electrode are sequentially formed on the substrate, or the second electrode and the light-shielding layer are sequentially formed on the substrate, or the second electrode is simultaneously formed on the substrate And the light-shielding layer.
  • the step of simultaneously forming the second electrode and the light shielding layer on the substrate includes:
  • a halftone mask is used to simultaneously form the second electrode and the light shielding layer.
  • the active layer and the first electrode of the plurality of transistors are formed on the light shielding layer and the second electrode; the active layer and the first electrode of the plurality of transistors are formed on the active layer and the first electrode of the plurality of transistors.
  • the gate electrodes, first gate lines, and second gate lines of the plurality of transistors are formed; on the gate electrodes, first gate lines, and second gate lines of the plurality of transistors, data lines, power lines,
  • the step of sensing the line and the source and drain electrodes of the plurality of transistors includes:
  • a buffer layer including a first via, a second via, and a fifth via is formed on the light shielding layer and the second electrode; the first via and the second via expose the first via Two electrodes, the fifth via hole exposes a sensing connection line;
  • An interlayer insulating layer including a third via hole, a fourth via hole, and a sixth via hole is formed on the gate electrodes of the plurality of transistors, the first gate line, and the second gate line; the third A via hole exposes the first via hole, the fourth via hole exposes the second via hole, and the sixth via hole exposes the fifth via hole;
  • the first insulating film and the second insulating film are processed by a patterning process to form a buffer layer including a first via hole, a second via hole and a fifth via hole and a third via hole and a fourth via hole And the interlayer insulating layer of the sixth via.
  • the step of sequentially forming a filter and a light-emitting element on the data line, the power line, the sensing line, and the source and drain electrodes of the plurality of transistors includes:
  • a passivation layer including a seventh via is formed on the data line, the power line, the sensing line, and the source and drain electrodes of the plurality of transistors; the seventh via exposes the sensing The first pole of the transistor;
  • a light-emitting element is formed on the flat layer.
  • FIG. 1 is an equivalent circuit diagram of the drive circuit
  • 2A is a cross-sectional view of a display substrate provided by an embodiment of the disclosure.
  • 2B is another cross-sectional view of the display substrate provided by the embodiment of the disclosure.
  • FIG. 3 is a top view of a display substrate provided by an embodiment of the disclosure.
  • FIG. 5 is another top view of the display substrate provided by the embodiment of the disclosure.
  • FIG. 6 is still another top view of the display substrate provided by the embodiment of the disclosure.
  • FIG. 7 is a flowchart of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • 8A to 8H are schematic diagrams of manufacturing the light-shielding layer and the second electrode provided by the embodiments of the disclosure.
  • FIG. 9 is a schematic diagram of step 100 of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of step 200 of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • FIG. 11 is a schematic diagram of step 300 of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • step 400 of a manufacturing method of a display substrate provided by an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of step 500 of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • FIG. 14 is a schematic diagram of step 600 of a manufacturing method of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of step 700 of a manufacturing method of a display substrate provided by an embodiment of the disclosure.
  • the specification may have presented the method and/or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described in the present disclosure, the method or process should not be limited to the steps in the specific order. As those of ordinary skill in the art will understand, other sequence of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims for the method and/or process should not be limited to performing their steps in the written order. Those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present disclosure. Inside.
  • the display substrate includes a plurality of sub-pixels, and each sub-pixel includes a driving circuit and a light-emitting element.
  • Figure 1 is an equivalent circuit diagram of the drive circuit, which illustrates a 3T1C drive circuit. As shown in Figure 1, the drive circuit is connected to the first gate line G1, the sensing line Sense, the power line VDD, the data line Data, and the second gate line.
  • the line G2 is electrically connected and includes: a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.
  • the gate electrode of the switching transistor T1 in the driving circuit is connected to the first gate line G1, the second electrode of the switching transistor T1 is connected to the data line Data, and the first electrode of the switching transistor T1 is connected to the node N1
  • the gate electrode of the driving transistor T2 is connected to the node N1
  • the second electrode of the driving transistor T2 is connected to the power supply line VDD
  • the first electrode of the driving transistor T2 is connected to the node N2
  • the gate electrode of the sensing transistor T3 is connected to the second gate line G2
  • the second pole of the sensing transistor T3 is connected to the sensing line Sense
  • the first pole of the sensing transistor T3 is connected to the node N2
  • the anode of the light emitting element OLED is connected to the node N2
  • the cathode of the light emitting element OLED is connected to the low power line VSS , Is configured to emit light of corresponding brightness in response to the current of the first pole of the driving transistor.
  • the driving circuit turns on the switching transistor T1 through the first gate line G1
  • the data voltage Vdata provided by the data line Data is stored in the storage capacitor Cst via the switching transistor T1, thereby controlling the driving transistor T2 to generate current to drive the organic light emitting diode OLED to emit light.
  • the sensing transistor T3 can respond to the sensing timing to extract the threshold voltage Vth and the mobility of the driving transistor T2, and the storage capacitor Cst is used to maintain the voltage difference between the node N1 and the node N2 in one frame of light emission period.
  • the first electrode of any one of the foregoing transistors has one electrode in the source and drain electrodes, and the second electrode has the other electrode in the source and drain electrodes.
  • FIG. 2A is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2B is another cross-sectional view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 3 is an embodiment of the present disclosure.
  • the display substrate provided by an embodiment of the present disclosure includes: a base 10 and a plurality of sub-pixels arranged on the base 10, and each sub-pixel includes a light-emitting area AA and In the non-light emitting area NA, each sub-pixel is provided with a driving circuit;
  • the driving circuit includes: a storage capacitor Cst and a plurality of transistors;
  • the plurality of transistors includes: a switching transistor T1, a driving transistor T2, and a sensing transistor T3.
  • the storage capacitor Cst is a transparent capacitor, and the orthographic projection of the storage capacitor Cst on the substrate 10 overlaps with the light-emitting area AA.
  • the first electrode C1 of the storage capacitor Cst is The active layers of the transistors are arranged in the same layer, and are arranged in different layers with the source and drain electrodes of multiple transistors.
  • the second electrode C2 of the storage capacitor Cst is located on the side of the first electrode C1 close to the substrate 10; the first electrode of the driving transistor T2 23 is in direct contact with the second electrode C2 to achieve electrical connection, and the first electrode 43 of the sensing transistor T3 is in direct contact with the second electrode C2 to achieve electrical connection.
  • the first electrode 23 of the driving transistor T2 and the second electrode C2 may be in direct contact for electrical connection, or the first electrode 23 of the driving transistor T2 may be electrically connected to the second electrode C2 through the light shielding layer 11
  • the connection depends on the connection relationship between the light shielding layer 11 and the second electrode C2.
  • the first electrode 23 of the driving transistor T2 and the second electrode C2 Direct contact is used for electrical connection;
  • the second electrode C2 is disposed on the side of the light shielding layer 11 close to the substrate 10
  • the first electrode 23 of the driving transistor T2 is electrically connected to the second electrode C2 through the light shielding layer.
  • the first electrode 43 of the sensing transistor T3 and the second electrode C2 have the same principle, which will not be repeated here.
  • the array of sub-pixels on the substrate is arranged. It should be noted that FIGS. 2A-2B and 3 take one sub-pixel as an example, and FIGS. 2A and 2B are cross-sectional views from different angles.
  • the base 10 may be a rigid substrate or a flexible substrate, where the rigid substrate may be but not limited to one or more of glass and metal sheet; the flexible substrate may be but Not limited to polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, poly One or more of vinyl chloride, polyethylene, and textile fibers.
  • the switching transistor T1 in the embodiment of the present disclosure includes: an active layer 31, a gate electrode 32, a first electrode 33, and an active layer 31 disposed on a substrate.
  • the second electrode 34, the driving transistor T2 includes: an active layer 21, a gate electrode 22, a first electrode 23 and a second electrode 24 arranged on the substrate, and the sensing transistor T3 includes: an active layer 41 arranged on the substrate, The gate electrode 42, the first electrode 43 and the second electrode 44.
  • the display substrate provided by the embodiment of the present disclosure is a bottom emission OLED display substrate.
  • the storage capacitor in the embodiment of the present disclosure is a transparent capacitor, which does not affect the light-emitting effect of the display substrate, and can ensure smooth light-emitting.
  • each sub-pixel is further provided with a light-emitting element, and the light-emitting element may be an OLED.
  • each sub-pixel includes a light-emitting area and a non-light-emitting area, and each sub-pixel is provided with a driving circuit;
  • the driving circuit includes : Storage capacitor and multiple transistors; multiple transistors include: switching transistors, driving transistors, and sensing transistors; for each sub-pixel, multiple transistors are located in the non-light emitting area, the storage capacitor is a transparent capacitor, and the storage capacitor is positive on the substrate There is an overlap area between the projection and the light-emitting area.
  • the first electrode of the storage capacitor is arranged in the same layer as the active layer of the multiple transistors, and is arranged in a different layer with the source and drain electrodes of the multiple transistors.
  • the second electrode of the storage capacitor is located close to the first electrode.
  • One side of the substrate; the first electrode of the driving transistor is in direct contact with the second electrode, and the first electrode of the sensing transistor is in direct contact with the second electrode.
  • the present disclosure can greatly reduce the area ratio of the storage capacitor in the non-emitting area by setting the transparent storage capacitor on the substrate where the orthographic projection on the substrate overlaps with the light-emitting area, thereby greatly reducing the area ratio of the storage capacitor in the non-light-emitting area, thereby reducing the occupation of each sub-pixel. A large area to achieve high PPI of the display substrate.
  • the display substrate provided by an embodiment of the present disclosure further includes: a light-shielding layer 11 and a buffer layer 12 disposed on the side of the active layer of the transistor close to the substrate 10,
  • the light shielding layer 11 and the second electrode C2 are disposed on the side of the buffer layer 12 close to the substrate 10.
  • the orthographic projection of the second electrode C2 on the substrate 10 covers the orthographic projection of the light shielding layer 11 on the substrate 10, and the surface of the light shielding layer 11 close to the second electrode C2 is in full contact with the second electrode C2.
  • the light-shielding layer 11 is disposed on the side of the second electrode C2 close to the substrate 10, or the second electrode C2 is disposed on the side of the light-shielding layer 11 close to the substrate 10.
  • 2A-2B and FIG. 3 both take the light shielding layer 11 disposed on the side of the second electrode C2 close to the substrate 10 as an example.
  • the first electrode 23 of the driving transistor T2 is electrically connected to the second electrode C2 through the conductive light shielding layer 11, and the first electrode 43 of the sensing transistor T3
  • the light shielding layer 11 is electrically connected to the second electrode C2.
  • the surface of the light-shielding layer 11 close to the second electrode C2 is in complete contact with the second electrode C2, avoiding the provision of an insulating layer between the light-shielding layer and the second electrode, which not only reduces the number and thickness of the display substrate, but also reduces The number of times the mask is used is simplified, the manufacturing process is simplified, and the manufacturing cost of the display substrate is reduced.
  • the orthographic projection of the light shielding layer 11 on the substrate 10 covers the orthographic projection of the channel region A1 of the active layer 21 of the driving transistor T2 on the substrate 10.
  • the light-shielding layer 11 is made of metal, such as silver, aluminum, etc., which is not limited in the embodiment of the present disclosure.
  • the display substrate provided by an embodiment of the present disclosure further includes: an interlayer insulating layer 14 disposed between the source and drain electrodes of the transistor and the active layer of the transistor.
  • the buffer layer 12 in the display substrate provided by the embodiment of the present disclosure includes: a first via hole V1 and a second via hole exposing the second electrode V2, the interlayer insulating layer 14 includes: a third via V3 exposing the first via V1 and a fourth via V4 exposing the second via V2.
  • the first electrode 23 of the driving transistor T2 is connected to the second electrode C2 through the first via hole V1 and the third via hole V3, and the first electrode 43 of the sensing transistor T3 passes through the second via hole.
  • V2 and the fourth via hole V4 are connected to the second electrode C2.
  • the interlayer insulating layer 14 is further provided with via holes exposing the active layers of a plurality of transistors, and the source and drain electrodes of the plurality of transistors pass through The hole is connected to the active layer.
  • FIG. 4 is another top view of the display substrate provided by the embodiment of the present disclosure.
  • the display substrate provided by the embodiment of the present disclosure further includes:
  • Each sub-pixel is defined by the intersection of a gate line and a data line, and the gate line includes a first gate line G1 and a second gate line G2.
  • FIG. 4 takes four sub-pixels as an example.
  • FIG. 2A is a cross-sectional view of FIG. 4 along the A-A direction
  • FIG. 2B is a cross-sectional view of FIG. 4 along the B-B direction.
  • the first gate line G1 and the second gate line G2 are arranged in the same layer as the gate electrode of the transistor, and the data line Data is arranged in the same layer as the source and drain electrodes of the transistor.
  • the first electrode C1 is respectively connected to the first electrode 33 of the switching transistor T1 and the gate electrode 22 of the driving transistor T2, and the second electrode C2 is respectively connected to the first electrode of the driving transistor T2.
  • the pole 23 is connected to the first pole 43 of the sensing transistor T3;
  • the gate electrode of the switching transistor T1 is connected to the first gate line G1 of the gate lines corresponding to the sub-pixel;
  • the second pole 34 of the switching transistor T1 is connected to the data corresponding to the sub-pixel
  • the line Data is connected, and the gate electrode of the sensing transistor T3 is connected to the second gate line G2 among the gate lines corresponding to the sub-pixels.
  • the light-emitting area AA includes: a first side and a second side that are arranged along the extending direction of the data line Data and are arranged oppositely.
  • the sensing transistor T3 and the second gate line G2 are both located on the first side of the light-emitting area AA, and the switching transistor T1, the driving transistor T2, and the first gate line G1 are all located on the first side of the light-emitting area AA. Located on the second side of the light-emitting area AA.
  • the display substrate further includes: a power line VDD and a sensing line Sense arranged in the same layer as the data line Data, and each pixel includes: four lines arranged along the extending direction of the gate line. Sub-pixels, each pixel corresponds to two columns of power lines and one column of sensing lines.
  • the pixel structures of the second sub-pixel and the third sub-pixel are arranged symmetrically, and the first sub-pixel and the fourth sub-pixel are arranged symmetrically.
  • the sensing line Sense corresponding to the pixel is located between the second sub-pixel P2 and the third sub-pixel P3, and a column of power supply lines VDD corresponding to the pixel is located on the side of the first sub-pixel P1 away from the second sub-pixel P2,
  • the power supply line VDD of another column corresponding to the pixel is located on the side of the fourth sub-pixel P4 away from the third sub-pixel P3.
  • the data line Data corresponding to the first sub-pixel P1 is located on the side of the first sub-pixel P1 close to the second sub-pixel P2; the data line corresponding to the second sub-pixel P2 is located on the side of the second sub-image P2 close to the first sub-pixel P1 ;
  • the data line corresponding to the third sub-pixel P3 is located on the side of the third sub-pixel P3 close to the fourth sub-pixel P4, and the data line corresponding to the fourth sub-pixel P4 is located on the side of the fourth sub-pixel P4 close to the third sub-pixel P3 .
  • the display substrate provided by the embodiment of the present disclosure further includes: a power connection line VL provided in the same layer as the gate electrode of the transistor, and a sensing line provided in the same layer as the light shielding layer 11.
  • the connection line SL, each pixel corresponds to two power connection lines arranged along the extending direction of the gate line and two sensing connection lines SL arranged along the extending direction of the gate line;
  • the power connection line VL corresponds to the power line VDD respectively;
  • the power connection line VL is connected to the corresponding power line;
  • two sensing connection lines SL are connected to the sensing line Sense.
  • the second electrode of the driving transistor of the second sub-pixel P2 is connected to one power connection line VL; the second electrode of the driving transistor of the third sub-pixel P3 is connected to the other power connection line VL;
  • the second electrode of the sensing transistor of the first sub-pixel P1 is connected to one sensing connection line SL; the second electrode of the sensing transistor of the fourth sub-pixel P4 is connected to the other sensing connection line SL.
  • the sensing connection line SL may have a single-layer structure or a double-layer structure.
  • the sensing connection line is the same as the light shielding layer or the second electrode.
  • Layer arrangement when the sensing connection line SL has a double-layer structure, the first layer of the sensing connection line is arranged in the same layer as the light shielding layer, and the second layer is arranged in the same layer as the second electrode.
  • FIG. 4 takes as an example that the sensing connection line and the light shielding layer are arranged in the same layer.
  • the display substrate provided by an embodiment of the present disclosure further includes: a gate insulating layer 13 disposed between the gate electrode of the transistor and the active layer of the transistor.
  • the orthographic projection of the gate insulating layer 13 on the substrate 10 coincides with the orthographic projection of the gate electrode of the transistor on the substrate 10.
  • the buffer layer 12, the gate insulating layer 13, and the interlayer insulating layer 14 are made of silicon oxide silicon nitride or a composite of silicon oxide and silicon nitride, which is not the case in the embodiments of the present disclosure. Pretend to be any restrictions.
  • the buffer layer 12 is further provided with a fifth via V5, and the fifth via V5 exposes the sensing connection line SL; the interlayer insulating layer 14 A sixth via hole V6 exposing the fifth via hole V5 is also provided, wherein the second electrode 44 of the sensing transistor T3 is connected to the sensing connection line SL through the fifth via hole V5 and the sixth via hole V6.
  • the material of the first electrode C1 includes: transparent metal oxide, the transparent metal oxide includes indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO for short), etc. This is the case in the embodiment of the present disclosure. There are no restrictions.
  • the second electrode C2 is made of a transparent conductive material, and the transparent conductive material includes indium tin oxide (ITO), zinc tin oxide, etc., and the embodiments of the present disclosure do not do anything about this limited.
  • ITO indium tin oxide
  • zinc tin oxide etc.
  • FIG. 5 is another top view of the display substrate provided by the embodiment of the present disclosure
  • FIG. 6 is another top view of the display substrate provided by the embodiment of the present disclosure, as shown in FIGS. 2A to 6,
  • the light-emitting element includes: an anode 61, an organic light-emitting layer 62 and a cathode 63 arranged in sequence, the anode 61 and the first electrode of the sensing transistor T3 43 is connected, the anode 61 is a transmissive electrode, and the cathode 63 is a reflective electrode.
  • the anode 61 may be made of a transparent conductive material, such as indium tin oxide ITO, zinc tin oxide, etc., which are not limited in the embodiments of the present disclosure.
  • the cathode 63 is made of metal, such as silver, aluminum, etc., which is not limited in the embodiment of the present disclosure.
  • the orthographic projection of the light-emitting element on the substrate 10 overlaps the light-emitting area AA
  • the filter 50 is located in the light-emitting area AA, and is arranged on the side of the light-emitting element close to the substrate 10, and the anode 61 is located
  • the orthographic projection on the substrate 10 covers the orthographic projection of the filter 50 on the substrate 10.
  • the display substrate provided by an embodiment of the present disclosure further includes: a passivation layer 15 disposed on the side of the source and drain electrodes of the transistor away from the substrate 10, and disposed on the anode 61
  • the passivation layer 15 is disposed on the side of the filter 50 close to the substrate 10, and the flat layer 16 is disposed between the light-emitting element and the filter 50;
  • the passivation layer 15 is provided with a seventh via hole V7 exposing the first electrode 43 of the sensing transistor T3, and the flat layer 16 is provided with an eighth via hole V8 exposing the seventh via hole V7.
  • the anode 61 is connected to the first electrode 43 of the sensing transistor T3 through the seventh via V7 and the eighth via V8;
  • the orthographic projection of the eighth via hole V8 on the substrate 10 and the orthographic projection of the fourth via hole V4 on the substrate 10 do not completely overlap.
  • the display substrate provided by an embodiment of the present disclosure further includes: a supporting portion 70 arranged on the side of the light-emitting element away from the base 10 and a supporting portion 70 arranged away from the base 10 Cover plate 80 on one side.
  • the cover plate 80 is used to protect the light-emitting element.
  • the cover plate 80 may be a glass cover plate.
  • FIG. 7 is a flowchart of the manufacturing method of the display substrate provided by the embodiments of the disclosure, as shown in FIG. 7,
  • the manufacturing method of the display substrate provided by the embodiment of the present disclosure specifically includes the following steps:
  • Step S1 Provide a substrate.
  • the substrate may be a rigid substrate or a flexible substrate, where the rigid substrate may be, but not limited to, one or more of glass and metal sheet; the flexible substrate may be, but not Limited to polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polychloride One or more of ethylene, polyethylene, and textile fibers.
  • Step S2 forming a plurality of sub-pixels on the substrate.
  • the sub-pixel array on the substrate is arranged.
  • Figures 2A-2B take one sub-pixel as an example.
  • each sub-pixel includes a light-emitting area and a non-light-emitting area, and each sub-pixel is provided with a driving circuit;
  • the driving circuit includes: a storage capacitor and a plurality of transistors;
  • the plurality of transistors includes: a switching transistor, a driving transistor And sense transistors.
  • the storage capacitor is a transparent capacitor, and the orthographic projection of the storage capacitor on the substrate overlaps the light emitting area.
  • the first electrode of the storage capacitor is the same as the active layer of the multiple transistors.
  • Layer arrangement, the second electrode of the storage capacitor is located on the side of the first electrode close to the substrate.
  • the first electrode of the driving transistor is in direct contact with the second electrode, and the first electrode of the sensing transistor is in direct contact with the second electrode.
  • the display substrate is the display substrate provided in the foregoing embodiment, and its implementation principles and effects are similar, and will not be repeated here.
  • the display substrate further includes a gate line, a data line, a power line, and a sensing line.
  • the gate line includes a first gate line and a second gate line.
  • Step S2 specifically includes:
  • a light-shielding layer and a second electrode are formed on the substrate; the active layer and first electrode of a plurality of transistors are formed on the light-shielding layer and the second electrode; the active layer and the first electrode of a plurality of transistors are formed on the active layer and the first electrode of the plurality of transistors
  • the gate electrode, the first gate line and the second gate line; the data line, the power supply line, the sensing line and the source and drain electrodes of a plurality of transistors are formed on the gate electrode, the first gate line and the second gate line of the transistor; Lines, power lines, sensing lines, and source and drain electrodes of a plurality of transistors are formed to sequentially form a filter and a light-emitting element.
  • forming the light-shielding layer and the second electrode on the substrate includes: sequentially forming the light-shielding layer and the second electrode on the substrate, or sequentially forming the second electrode and the light-shielding layer on the substrate, or on the substrate The second electrode and the light shielding layer are formed at the same time.
  • sequentially forming the light-shielding layer and the second electrode on the substrate includes: using a first mask on the substrate to form the light-shielding layer, and using a second mask on the light-shielding layer to form the second electrode.
  • sequentially forming the second electrode and the light-shielding layer on the substrate includes: using a second mask on the substrate to form the second electrode through a patterning process, and using the first mask on the second electrode Form a light-shielding layer.
  • simultaneously forming the second electrode and the light-shielding layer on the substrate includes: sequentially depositing a light-shielding film and a transparent conductive film on the substrate, and simultaneously forming the second electrode and the light-shielding layer using a halftone mask.
  • the patterning process includes: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the process includes the following steps:
  • Step 110 deposit a light-shielding film 110 on the substrate, coat photoresist 101 on the light-shielding film 110, and expose the photoresist through the first mask M1, as shown in FIG. 8A.
  • Step 120 develop the photoresist 101, as shown in FIG. 8B.
  • Step 130 etch away the light-shielding film that is not covered with the photoresist 101, as shown in FIG. 8C.
  • step 140 the photoresist 101 is stripped to form a light-shielding layer 11, as shown in FIG. 8D.
  • Step 150 depositing a transparent conductive film 120 on the light shielding layer 11, coating a photoresist 101 on the transparent conductive film 120, and exposing the photoresist through the second mask M2, as shown in FIG. 8E.
  • Step 160 develop the photoresist 101, as shown in FIG. 8F.
  • Step 170 etch away the transparent conductive film that is not covered with the photoresist 101, as shown in FIG. 8G.
  • step 180 the photoresist 101 is stripped to form a second electrode C2, as shown in FIG. 8H.
  • the active layer and the first electrode of the plurality of transistors are formed on the light shielding layer and the second electrode; the active layer and the first electrode of the plurality of transistors are formed on the active layer and the first electrode of the plurality of transistors.
  • the electrode includes: forming a buffer layer including a first via hole, a second via hole and a fifth via hole on the light shielding layer and the second electrode through a patterning process; using the same process to form an active layer of multiple transistors on the buffer layer and The first electrode; the gate electrode, the first gate line and the second gate line of the plurality of transistors are formed on the active layer and the first electrode of the plurality of transistors; the gate electrode, the first gate line and the second gate line of the transistor are formed An interlayer insulating layer including a third via, a fourth via, and a sixth via is formed by a patterning process; data lines, power lines, sensing lines, and source and drain electrodes of a plurality of transistors are formed on the interlayer insulating layer
  • the first via hole and the second via hole expose the second electrode
  • the fifth via hole exposes the sensing connection line
  • the third via hole exposes the first via hole
  • the fourth via hole exposes the second electrode.
  • the second via hole is exposed, and the fifth via hole is exposed by the sixth via hole.
  • the active layer and the first electrode of the plurality of transistors are formed on the light shielding layer and the second electrode; the gate electrode and the first electrode of the plurality of transistors are formed on the active layer and the first electrode of the plurality of transistors.
  • a gate line and a second gate line; forming data lines, power lines, sensing lines, and source and drain electrodes of a plurality of transistors on the gate electrode of the transistor, the first gate line and the second gate line include: the light shielding layer and the first gate line
  • a first insulating film is formed on the two electrodes; the active layer and first electrode of multiple transistors are formed on the first insulating film using the same process; the gate of the multiple transistors is formed on the active layer and first electrode of the multiple transistors
  • the formation of filters and light-emitting elements in sequence on data lines, power lines, sensing lines, and source and drain electrodes of multiple transistors includes: forming on data lines, power lines, sense lines, and source and drain electrodes of multiple transistors A passivation layer including a seventh via hole; the seventh via hole exposes the first electrode of the sensing transistor; a filter and a flat layer including an eighth via hole are sequentially formed on the passivation layer; the eighth via The via hole exposes the seventh via hole; a light emitting element is formed on the flat layer.
  • the above embodiments can simplify the manufacturing process of the display substrate.
  • the sensing connection line is a single-layer structure and is provided in the same layer as the light-shielding layer, and the light-shielding layer is provided on the side of the second electrode close to the substrate as an example.
  • the implementation of the present disclosure will be further described below with reference to FIGS. 9-15.
  • the manufacturing method of the display substrate provided in the example includes the following steps:
  • Step 100 forming a light shielding layer 11 and a sensing connection line SL on the substrate 10, as shown in FIG. 9.
  • step 200 a second electrode C2 and a buffer layer (not shown in the figure) are sequentially formed on the light shielding layer 11 and the sensing connection line SL, as shown in FIG. 10.
  • Step 300 forming the first electrode C1, the active layer 31 of the switching transistor, the active layer 21 of the driving transistor T2, and the active layer 41 of the sensing transistor on the buffer layer, as shown in FIG. 11.
  • Step 400 forming a gate insulating layer on the active layer 31 of the switching transistor, the active layer 21 of the driving transistor T2 and the active layer 41 of the sensing transistor, and forming the gate electrode 32 of the switching transistor and the driving transistor on the gate insulating layer
  • the gate electrode 22 and the gate electrode 42 of the sensing transistor, the first gate line G1, the second gate line G2, and the power connection line VL are on the gate electrode of the transistor, the first gate line, the second gate line and the power connection line
  • An interlayer insulating layer is formed, as shown in FIG. 12.
  • the interlayer insulating layer includes: a third via V3, a fourth via V4, and a sixth via V6, and the buffer layer includes: a first via V1, a second via V2, and a second via V1. Five vias V5.
  • Step 500 forming the data line Data, the power supply line VDD, the sensing line Sense, the first pole 33 of the switching transistor, the second pole 34 of the switching transistor, the first pole 23 of the driving transistor, and the second pole of the driving transistor on the interlayer insulating layer
  • the second pole 24, the first pole 43 of the sensing transistor, and the second pole 44 of the sensing transistor are as shown in FIG. 13.
  • Step 600 forming a passivation layer including the seventh via hole on the data line, the power line, the sensing line and the source and drain electrodes of the multiple transistors, forming a filter 50 on the passivation layer, and forming on the filter
  • the flat layer including the eighth via V8 is shown in FIG. 14.
  • step 700 an anode 61 is formed on the flat layer, as shown in FIG. 15.
  • step 800 a pixel defining layer, an organic light-emitting layer, and a cathode are sequentially formed on the anode, and a support portion and a cover plate are sequentially arranged on the cathode.
  • embodiments of the present disclosure also provide a display device including a display substrate.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the other indispensable components of the display device are well known to those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.
  • the implementation of the display device can refer to the embodiment of the above in-cell touch screen, and the repetition will not be repeated.
  • the display substrate may be the display substrate provided in any of the foregoing embodiments, and its implementation principles and effects are the same or similar, and will not be repeated here.

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Abstract

一种显示基板及其制作方法、显示装置，其中，显示基板包括：多个子像素，每个子像素包括发光区域（AA）和非发光区域（NA），每个子像素中设置有驱动电路；驱动电路包括：存储电容（Cst）和多个晶体管；多个晶体管包括：开关晶体管（T1）、驱动晶体管（T2）和感测晶体管（T3）；对于每个子像素，多个晶体管位于非发光区域，存储电容为透明电容，且存储电容在基底（10）上的正投影与发光区域存在重叠区域，存储电容的第一电极（C1）与多个晶体管的有源层同层设置，且与多个晶体管的源漏电极异层设置，存储电容的第二电极（C2）位于第一电极靠近基底的一侧；驱动晶体管的第一极（23）与第二电极电连接，感测晶体管的第一极（43）与第二电极电连接。

Description

一种显示基板及其制作方法、显示装置
本申请要求于2019年10月29日提交中国专利局、申请号为201911038401.5、发明名称为“一种显示基板及其制作方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开涉及显示技术领域，具体涉及一种显示基板及其制作方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Device，简称OLED)显示是一种与传统的液晶显示(Liquid Crystal Display，简称LCD)不同的显示技术，具备主动发光、温度特性好、功耗小、响应快、可弯曲、超轻薄和成本低等优点，已经成为新一代显示装置的重要发现之一，并且受到越来越多的关注。
OLED显示基板按照出光方向可以分为三种：底发射OLED、顶发射OLED与双面发射OLED。其中，底发射OLED指的是OLED器件中的光线朝基底方向射出。但是，底发射OLED显示基板中受到像素开口区域的限制，使得每个子像素所占用的面积较大，进而导致底发射OLED显示基板中的单位面积像素数量(Pixels Per Inch，简称PPI)较低，无法实现高PPI。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。一方面，本公开提供了一种显示基板，包括：基底以及设置在所述基底上的多个子像素，每个子像素包括发光区域和非发光区域，每个子像素中设置有驱动电路；所述驱动电路包括：存储电容和多个晶体管；所述多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管；
对于每个子像素，所述多个晶体管位于所述非发光区域，所述存储电容 为透明电容，且所述存储电容在所述基底上的正投影与所述发光区域存在重叠区域，所述存储电容的第一电极与所述多个晶体管的有源层同层设置，且与所述多个晶体管的源漏电极异层设置，所述存储电容的第二电极位于所述第一电极靠近所述基底的一侧；
所述驱动晶体管的第一极与所述第二电极电连接，所述感测晶体管的第一极与所述第二电极电连接。
在一示例性的实施方式中，所述显示基板还包括：设置在所述多个晶体管的有源层靠近所述基底的一侧的缓冲层和遮光层，所述遮光层和所述第二电极设置在所述缓冲层靠近所述基底的一侧；
所述第二电极在所述基底上的正投影覆盖所述遮光层在所述基底上的正投影，所述遮光层靠近所述第二电极的表面与所述第二电极完全接触。
在一示例性的实施方式中，所述遮光层设置在所述第二电极靠近所述基底的一侧，或者，所述第二电极设置在所述遮光层靠近所述基底的一侧。
在一示例性的实施方式中，所述显示基板还包括：设置在所述多个晶体管的源漏电极和所述多个晶体管的有源层之间的层间绝缘层；
所述缓冲层包括暴露出所述第二电极的第一过孔和第二过孔，所述层间绝缘层包括：暴露出所述第一过孔的第三过孔和暴露出所述第二过孔的第四过孔；
所述驱动晶体管的所述第一极通过所述第一过孔和所述第三过孔与所述第二电极连接，所述感测晶体管的所述第一极通过所述第二过孔和所述第四过孔与所述第二电极连接。
在一示例性的实施方式中，所述显示基板还包括：设置在所述基底上的多行栅线和多列数据线；每个子像素由栅线和数据线交叉限定，所述多个子像素分别与所述多行栅线和所述多列数据线一一对应，所述多行栅线包括：第一栅线和第二栅线，
所述第一栅线和所述第二栅线与所述多个晶体管的栅电极同层设置，所述多列数据线与所述多个晶体管的源漏电极同层设置。
在一示例性的实施方式中，对于每个子像素，所述第一电极分别与所述 开关晶体管的第一极和所述驱动晶体管的栅电极连接；
所述开关晶体管的栅电极与子像素对应的栅线中的第一栅线连接；所述开关晶体管的第二极与子像素对应的数据线连接，所述感测晶体管的栅电极与子像素对应的栅线中的第二栅线连接。
在一示例性的实施方式中，对于每个子像素，所述非发光区域包括：第一非发光区域和第二非发光区域，所述第一非发光区域和所述第二非发光区域位于所述发光区域的两侧，且沿所述多列数据线延伸方向设置；
所述感测晶体管和所述第二栅线均位于所述第一非发光区域，所述开关晶体管、所述驱动晶体管和所述第一栅线均位于所述第二非发光区域。
在一示例性的实施方式中，所述显示基板还包括：与所述多列数据线同层设置的电源线和感测线，每个像素包括：沿栅线延伸方向设置的四个子像素，每个像素对应两列电源线和一列感测线；
对于每个像素，像素对应的感测线位于所述第二子像素和所述第三子像素之间，像素对应的一列电源线位于所述第一子像素远离所述第二子像素的一侧，像素对应的另一列电源线位于所述第四子像素远离所述第三子像素的一侧；
所述第一子像素对应的数据线位于所述第一子像素靠近所述第二子像素的一侧；所述第二子像素对应的数据线位于所述第二子像素靠近所述第一子像素的一侧；所述第三子像素对应的数据线位于所述第三子像素靠近所述第四子像素的一侧，所述第四子像素对应的数据线位于所述第四子像素靠近所述第三子像素的一侧；
所述显示基板还包括：与所述多个晶体管的栅电极同层设置的电源连接线以及与遮光层同层设置的感测连接线，每个像素对应两个沿栅线延伸方向设置的电源连接线和两个沿栅线延伸方向设置的感测连接线；电源连接线分别与电源线对应；所述电源连接线与对应的电源线连接；两个感测连接线与感测线连接；
所述第二子像素的驱动晶体管的第二极与一个电源连接线连接；
所述第三子像素的驱动晶体管的第二极与另一电源连接线连接；
所述第一子像素的感测晶体管的第二极与一个感测连接线连接；
所述第四子像素的感测晶体管的第二极另一感测连接线连接。
在一示例性的实施方式中，所述缓冲层还设置有暴露出所述感测连接线的第五过孔，所述层间绝缘层还设置有暴露出所述第五过孔的第六过孔；
所述感测晶体管的第二极通过所述第五过孔和所述第六过孔与所述感测连接线连接。
在一示例性的实施方式中，所述显示基板还包括：设置在所述多个晶体管的栅电极和所述多个晶体管的有源层之间的栅绝缘层；
其中，所述栅绝缘层在所述基底上的正投影与所述多个晶体管的栅电极在所述基底上的正投影重合。
在一示例性的实施方式中，所述第一电极的制作材料包括透明金属氧化物，所述第二电极的制作材料包括透明导电材料。
在一示例性的实施方式中，每个子像素中还设置有发光元件和与子像素颜色相同的滤光片；所述发光元件包括：依次设置的阳极、有机发光层和阴极，所述阳极与所述感测晶体管的所述第一极连接，所述阳极为透射电极，所述阴极为反射电极；
所述发光元件在所述基底上的正投影与所述发光区域存在重叠区域，所述滤光片位于所述发光区域，且设置在所述发光元件靠近所述基底的一侧，所述阳极在所述基底上的正投影覆盖所述滤光片在所述基底上的正投影。
在一示例性的实施方式中，所述显示基板还包括设置在所述多个晶体管的源漏电极远离所述基底一侧的钝化层和平坦层；
所述钝化层设置在所述滤光片靠近所述基底的一侧，所述平坦层设置在所述发光元件和所述滤光片之间；所述钝化层设置有暴露出所述感测晶体管的所述第一极的第七过孔，所述平坦层设置有暴露出所述第七过孔的第八过孔；
所述阳极通过所述第七过孔和所述第八过孔与所述感测晶体管的所述第一极连接；
所述第八过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影不完全重叠。
另一方面，本公开提供了一种显示装置，包括上述任意的显示基板。
再一方面，本公开提供了一种显示基板的制作方法，用于制作上述任意的显示基板，所述方法包括：
提供一基底；
在所述基底上形成多个子像素，每个子像素包括发光区域和非发光区域，每个子像素中设置有驱动电路；所述驱动电路包括：存储电容和多个晶体管；所述多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管；
对于每个子像素，所述多个晶体管位于所述非发光区域，所述存储电容为透明电容，且所述存储电容在所述基底上的正投影与所述发光区域存在重叠区域，所述存储电容的第一电极与所述多个晶体管的有源层同层设置，且与所述多个晶体管的源漏电极异层设置，所述存储电容的第二电极位于所述第一电极靠近所述基底的一侧；
所述驱动晶体管的第一极与所述第二电极电连接，所述感测晶体管的第一极与所述第二电极电连接。
在一示例性的实施方式中，所述显示基板还包括：栅线、数据线、电源线、感测线，所述栅线包括：第一栅线和第二栅线，所述在所述基底上形成多个子像素的步骤包括：
在所述基底上形成遮光层和所述第二电极；
在所述遮光层和所述第二电极上形成所述多个晶体管的有源层和所述第一电极；
在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极；
在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极 上依次形成滤光片和发光元件。
在一示例性的实施方式中，所述在所述基底上形成遮光层和所述第二电极的步骤包括：
在所述基底上依次形成所述遮光层和所述第二电极，或者在所述基底上依次形成所述第二电极和所述遮光层，或者在所述基底上同时形成所述第二电极和所述遮光层。
在一示例性的实施方式中，所述在所述基底上同时形成所述第二电极和所述遮光层的步骤包括：
在所述基底上依次沉积遮光薄膜和透明导电薄膜；
采用半色调掩膜版同时形成所述第二电极和所述遮光层。
在一示例性的实施方式中，所述在所述遮光层和所述第二电极上形成所述多个晶体管的有源层和第一电极；在所述多个晶体管的有源层和第一电极上形成所述多个晶体管的栅电极、第一栅线和第二栅线；在所述多个晶体管的栅电极、第一栅线和第二栅线上形成数据线、电源线、感测线和所述多个晶体管的源漏电极的步骤包括：
在所述遮光层和所述第二电极上形成包括第一过孔、第二过孔和第五过孔的缓冲层；所述第一过孔和所述第二过孔暴露出所述第二电极，所述第五过孔暴露出感测连接线；
在所述缓冲层上采用同一制程形成所述多个晶体管的所述有源层和所述第一电极；
在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成包括第三过孔、第四过孔和第六过孔的层间绝缘层；所述第三过孔暴露出所述第一过孔，所述第四过孔暴露出所述第二过孔，所述第六过孔暴露出所述第五过孔；
在所述层间绝缘层上形成所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极；或者，
在所述遮光层和所述第二电极上形成第一绝缘薄膜；
在第一绝缘薄膜上采用同一制程形成所述多个晶体管的有源层和所述第一电极；
在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成第二绝缘薄膜；
采用构图工艺对所述第一绝缘薄膜和所述第二绝缘薄膜进行处理，形成包括第一过孔、第二过孔和第五过孔的缓冲层和包括第三过孔、第四过孔和第六过孔的层间绝缘层。
在一示例性的实施方式中，所述在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极上依次形成滤光片和发光元件的步骤包括：
在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极上形成包括第七过孔的钝化层；所述第七过孔暴露出所述感测晶体管的所述第一极；
在所述钝化层上依次形成所述滤光片和包括第八过孔的平坦层；所述第八过孔暴露出所述第七过孔；
在所述平坦层上形成发光元件。本申请的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本申请而了解。本申请的其他优点可通过在说明书、权利要求书以及附图中所描述的方案来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本申请技术方案的理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。
图1为驱动电路的等效电路图；
图2A为本公开实施例提供的显示基板的一个剖视图；
图2B为本公开实施例提供的显示基板的另一剖视图；
图3为本公开实施例提供的显示基板的一个俯视图；
图4为本公开实施例提供的显示基板的另一俯视图；
图5为本公开实施例提供的显示基板的又一俯视图；
图6为本公开实施例提供的显示基板的再一俯视图；
图7为本公开实施例提供的显示基板的制作方法的流程图；
图8A～图8H为本公开实施例提供的遮光层和第二电极的制作示意图；
图9为本公开实施例提供的显示基板的制作方法步骤100示意图；
图10为本公开实施例提供的显示基板的制作方法步骤200示意图；
图11为本公开实施例提供的显示基板的制作方法步骤300示意图；
图12为本公开实施例提供的显示基板的制作方法步骤400示意图；
图13为本公开实施例提供的显示基板的制作方法步骤500示意图；
图14为本公开实施例提供的显示基板的制作方法步骤600示意图；
图15为本公开实施例提供的显示基板的制作方法步骤700示意图。
详述
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。 本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的独特的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本公开所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
除非另外定义，本公开实施例公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本实施例中，显示基板包括多个子像素，每个子像素包括驱动电路和发光元件。图1为驱动电路的等效电路图，示意了一种3T1C的驱动电路，如图1所示，驱动电路与第一栅线G1、感测线Sense、电源线VDD、数据线Data和第二栅线G2电连接，包括：开关晶体管T1、驱动晶体管T2、感测 晶体管T3和存储电容Cst。
在一示例性的实施方式中，驱动电路中开关晶体管T1的栅电极连接第一栅线G1，开关晶体管T1的第二极与数据线Data连接，开关晶体管T1的第一极与节点N1连接，驱动晶体管T2的栅电极与节点N1连接，驱动晶体管T2的第二极与电源线VDD连接，驱动晶体管T2的第一极与节点N2连接，感测晶体管T3的栅电极与第二栅线G2连接，感测晶体管T3的第二极与感测线Sense连接，感测晶体管T3的第一极与节点N2连接，发光元件OLED的阳极与节点N2连接，发光元件OLED的阴极与低电源线VSS连接，被配置为响应驱动晶体管的第一极的电流而发出相应亮度的光。驱动电路通过第一栅线G1打开开关晶体管T1时，数据线Data提供的数据电压Vdata经由开关晶体管T1存储到存储电容Cst，从而控制驱动晶体管T2产生电流，以驱动有机发光二极管OLED发光，另外，感测晶体管T3能够响应感测时序，提取驱动晶体管T2的阈值电压Vth以及迁移率，存储电容Cst用于保持在一帧发光周期内节点N1和节点N2之间的电压差。
在一示例性的实施方式中，上述任意一个晶体管的第一极为源漏电极中的一个电极，第二极为源漏电极中的另一个电极。
本公开一些实施例提供了一种显示基板，图2A为本公开实施例提供的显示基板的一个剖视图，图2B为本公开实施例提供的显示基板的另一剖视图，图3为本公开实施例提供的显示基板的一个俯视图，如图2A-2B和图3所示，本公开实施例提供的显示基板包括：基底10以及设置在基底10上的多个子像素，每个子像素包括发光区域AA和非发光区域NA，每个子像素中设置有驱动电路；驱动电路包括：存储电容Cst和多个晶体管；多个晶体管包括：开关晶体管T1、驱动晶体管T2和感测晶体管T3。
对于每个子像素，多个晶体管位于非发光区域NA，存储电容Cst为透明电容，且存储电容Cst在基底10上的正投影与发光区域AA存在重叠区域，存储电容Cst的第一电极C1与多个晶体管的有源层同层设置，且与多个晶体管的源漏电极异层设置，存储电容Cst的第二电极C2位于第一电极C1靠近基底10的一侧；驱动晶体管T2的第一极23与第二电极C2直接接触实现电连接，感测晶体管T3的第一极43与第二电极C2直接接触实现电连接。结 合下面的描述可知，驱动晶体管T2的第一极23与第二电极C2可以是直接接触进行电连接，也可以是驱动管晶体管T2的第一极23通过遮光层11与第二电极C2形成电连接，这取决于遮光层11与第二电极C2的连接关系，当遮光层11设置在所述第二电极C2靠近基底10的一侧时，驱动晶体管T2的第一极23与第二电极C2直接接触进行电连接；当第二电极C2设置在遮光层11靠近所述基底10的一侧时，驱动管晶体管T2的第一极23通过遮光层与第二电极C2形成电连接。感测晶体管T3的第一极43与第二电极C2同理，在此不再赘述。
在一示例性的实施方式中，基底上的子像素阵列排布，需要说明的是，图2A-2B和图3以一个子像素为例，且图2A和图2B是不同角度的剖视图。
在一示例性的实施方式中，基底10可以为刚性衬底或柔性衬底，其中，刚性衬底可以为但不限于玻璃、金属萡片中的一种或多种；柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一示例性的实施方式中，如图2A-2B和图3所示，本公开实施例中的开关晶体管T1包括：设置在基底上的有源层31、栅电极32、第一极33和第二极34，驱动晶体管T2包括：设置在基底上的有源层21、栅电极22、第一极23和第二极24，感测晶体管T3包括：设置在基底上的有源层41、栅电极42、第一极43和第二极44。
在一示例性的实施方式中，本公开实施例提供的显示基板为底发射OLED显示基板。
本公开实施例中的存储电容为透明电容，不影响显示基板的出光效果，可以保证出光顺利。
在一示例性的实施方式中，每个子像素还设置发光元件，发光元件可以为OLED。
本公开实施例提供的显示基板，其中，该显示基板包括：基底以及设置在基底上的多个子像素，每个子像素包括发光区域和非发光区域，每个子像 素中设置有驱动电路；驱动电路包括：存储电容和多个晶体管；多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管；对于每个子像素，多个晶体管位于非发光区域，存储电容为透明电容，且存储电容在基底上的正投影与发光区域存在重叠区域，存储电容的第一电极与多个晶体管的有源层同层设置，且与多个晶体管的源漏电极异层设置，存储电容的第二电极位于第一电极靠近基底的一侧；驱动晶体管的第一极与第二电极直接接触，感测晶体管的第一极与第二电极直接接触。本公开通过设置透明的存储电容在基底上的正投影与发光区域存在重叠区域可以在保证开口率的同时极大地降低存储电容在非发光区域占的面积比例，进而能够减小每个子像素所占用的面积，实现显示基板的高PPI。
在一示例性的实施方式中，如图2A-2B和图3所示，对于每个晶体管，晶体管的有源层在基底上的正投影与晶体管的栅电极在基底上的正投影存在重叠区域。
在一示例性的实施方式中，如图2A-2B所示，本公开实施例提供的显示基板还包括：设置在晶体管的有源层靠近基底10的一侧的遮光层11和缓冲层12，遮光层11和第二电极C2设置在缓冲层12靠近基底10的一侧。
在一示例性的实施方式中，第二电极C2在基底10上的正投影覆盖遮光层11在基底10上的正投影，遮光层11靠近第二电极C2的表面与第二电极C2完全接触。
在一示例性的实施方式中，遮光层11设置在所述第二电极C2靠近基底10的一侧，或者，第二电极C2设置在遮光层11靠近所述基底10的一侧，其中，图2A-2B和图3均以遮光层11设置在第二电极C2靠近基底10的一侧为例。
当第二电极C2设置在遮光层11靠近基底10的一侧，则驱动晶体管T2的第一极23通过可导电的遮光层11与第二电极C2电连接，感测晶体管T3的第一极43通过遮光层11与第二电极C2电连接。
本公开实施例通过遮光层11靠近第二电极C2的表面与第二电极C2完全接触，避免了在遮光层和第二电极之间设置绝缘层，不仅减少了显示基板层数和厚度，同时减少了掩膜版的使用次数，简化了制作工艺，并降低了显 示基板的制作成本。
在一示例性的实施方式中，遮光层11在基底10上的正投影覆盖驱动晶体管T2的有源层21的沟道区域A1在基底10上的正投影。
在一示例性的实施方式中，遮光层11的制作材料为金属，例如银、铝等，本公开实施例对此不作任何限定。
在一示例性的实施方式中，如图2A-2B所示，本公开实施例提供的显示基板还包括：设置在晶体管的源漏电极和晶体管的有源层之间的层间绝缘层14。
在一示例性的实施方式中，如图2A-2B和图3所示，本公开实施例提供的显示基板中缓冲层12包括：暴露出第二电极的第一过孔V1和第二过孔V2，层间绝缘层14包括：暴露出第一过孔V1的第三过孔V3和暴露出第二过孔V2的第四过孔V4。
在一示例性的实施方式中，驱动晶体管T2的第一极23通过第一过孔V1和第三过孔V3与第二电极C2连接，感测晶体管T3的第一极43通过第二过孔V2和第四过孔V4与第二电极C2连接。
在一示例性的实施方式中，如图2A-2B和图3所示，层间绝缘层14还设置有暴露出多个晶体管的有源层的过孔，多个晶体管的源漏电极通过过孔与有源层连接。
在一示例性的实施方式中，图4为本公开实施例提供的显示基板的另一俯视图，如图4所示，本公开实施例提供的显示基板还包括：设置在基底上的多行栅线和多列数据线；每个子像素由栅线和数据线交叉限定，栅线包括：第一栅线G1和第二栅线G2。其中，图4以四个子像素为例。
其中，图2A是图4沿A-A方向的剖视图，图2B是图4沿B-B方向的剖视图。
在一示例性的实施方式中，第一栅线G1和第二栅线G2与晶体管的栅电极同层设置，数据线Data与晶体管的源漏电极同层设置。
在一示例性的实施方式中，对于每个子像素，第一电极C1分别与开关晶体管T1的第一极33和驱动晶体管T2的栅电极22连接，第二电极C2分 别与驱动晶体管T2的第一极23和感测晶体管T3的第一极43连接；开关晶体管T1的栅电极与子像素对应的栅线中的第一栅线G1连接；开关晶体管T1的第二极34与子像素对应的数据线Data连接，感测晶体管T3的栅电极与子像素对应的栅线中的第二栅线G2连接。
在一示例性的实施方式中，如图4所示，对于每个子像素，发光区域AA包括：沿数据线Data延伸方向设置的，且相对设置的第一侧和第二侧。
在一示例性的实施方式中，结合图2A-2B可知，感测晶体管T3和第二栅线G2均位于发光区域AA的第一侧，开关晶体管T1、驱动晶体管T2和第一栅线G1均位于发光区域AA的第二侧。
在一示例性的实施方式中，如图4所示，显示基板还包括：与数据线Data同层设置的电源线VDD和感测线Sense，每个像素包括：沿栅线延伸方向设置的四个子像素，每个像素对应两列电源线和一列感测线。
在一示例性的实施方式中，第二子像素和第三子像素的像素结构对称设置，第一子像素和第四子像素对称设置。
对于每个像素，像素对应的感测线Sense位于第二子像素P2和第三子像素P3之间，像素对应的一列电源线VDD位于第一子像素P1远离第二子像素P2的一侧，像素对应的另一列电源线VDD位于第四子像素P4远离第三子像素P3的一侧。
第一子像素P1对应的数据线Data位于第一子像素P1靠近第二子像素P2的一侧；第二子像素P2对应的数据线位于第二子像P2靠近第一子像素P1的一侧；第三子像素P3对应的数据线位于第三子像素P3靠近第四子像素P4的一侧，第四子像素P4对应的数据线位于第四子像素P4靠近第三子像素P3的一侧。
在一示例性的实施方式中，如图4所示，本公开实施例提供的显示基板还包括：与晶体管的栅电极同层设置的电源连接线VL以及与遮光层11同层设置的感测连接线SL，每个像素对应两个沿栅线延伸方向设置的电源连接线和两个沿栅线延伸方向设置的感测连接线SL；电源连接线VL分别与电源线VDD对应；电源连接线VL与对应的电源线连接；两个感测连接线SL与感 测线Sense连接。
在一示例性的实施方式中，第二子像素P2的驱动晶体管的第二极与一个电源连接线VL连接；第三子像素P3的驱动晶体管的第二极与另一电源连接线VL连接；第一子像素P1的感测晶体管的第二极与一个感测连接线SL连接；第四子像素P4的感测晶体管的第二极与另一感测连接线SL连接。
在一示例性的实施方式中，感测连接线SL可以为单层结构，还可以双层结构，当感测连接线SL为单层结构时，感测连接线与遮光层或者第二电极同层设置，当感测连接线SL为双层结构时，感测连接线的第一层与遮光层同层设置，第二层与第二电极同层设置。其中，图4以感测连接线与遮光层同层设置为例。
在一示例性的实施方式中，如图2A-2B所示，本公开实施例提供的显示基板还包括：设置在晶体管的栅电极和晶体管的有源层之间的栅绝缘层13。
其中，栅绝缘层13在基底10上的正投影与晶体管的栅电极在基底10上的正投影重合。
在一示例性的实施方式中，缓冲层12、栅绝缘层13和层间绝缘层14的制作材料为氧化硅氮化硅或者氧化硅和氮化硅的复合物，本公开实施例对此不做作任何限定。
在一示例性的实施方式中，如图3所示，对于每个子像素，缓冲层12还设置有第五过孔V5，第五过孔V5暴露出感测连接线SL；层间绝缘层14还设置有暴露出第五过孔V5的第六过孔V6，其中，感测晶体管T3的第二极44通过第五过孔V5和第六过孔V6与感测连接线SL连接。
在一示例性的实施方式中，第一电极C1的制作材料包括：透明金属氧化物，透明金属氧化物包括铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)等，本公开实施例对此不作任何限定。
在一示例性的实施方式中，第二电极C2的制作材料为透明导电材料，透明导电材料包括氧化铟锡(Indium Tin Oxides，简称ITO)、氧化锌锡等，本公开实施例对此不作任何限定。
在一示例性的实施方式中，图5为本公开实施例提供的显示基板的又一 俯视图，图6为本公开实施例提供的显示基板的再一俯视图，如图2A至图6所示，每个子像素中还设置有发光元件和与子像素颜色相同的滤光片50；发光元件包括：依次设置的阳极61、有机发光层62和阴极63，阳极61与感测晶体管T3的第一极43连接，阳极61为透射电极，阴极63为反射电极。
在一示例性的实施方式中，阳极61的制作材料可以为透明导电材料，例如氧化铟锡ITO，氧化锌锡等，本公开实施例对此不作任何限定。
在一示例性的实施方式中，阴极63的制作材料为金属，例如银、铝等，本公开实施例对此不作任何限定。
在一示例性的实施方式中，发光元件在基底10上的正投影与发光区域AA存在重叠区域，滤光片50位于发光区域AA，且设置在发光元件靠近基底10的一侧，阳极61在基底10上的正投影覆盖滤光片50在基底10上的正投影。
在一示例性的实施方式中，如图2A-2B所示，本公开实施例提供的显示基板还包括：设置在晶体管的源漏电极远离基底10一侧的钝化层15，设置在阳极61和滤光片50之间的平坦层16以及设置在平坦层16远离基底10的一侧用于界定子像素区域的像素界定层17。
在一示例性的实施方式中，结合图2A-2B和图5，钝化层15设置在滤光片50靠近基底10的一侧，平坦层16设置在发光元件和滤光片50之间；钝化层15设置有暴露出感测晶体管T3的第一极43的第七过孔V7，平坦层16设置有暴露出第七过孔V7的第八过孔V8。
阳极61通过第七过孔V7和第八过孔V8与感测晶体管T3的第一极43连接；
其中，第八过孔V8在基底10上的正投影与第四过孔V4在基底10上的正投影不完全重叠。
在一示例性的实施方式中，如图2A-2B所示，本公开实施例提供的显示基板还包括：设置在发光元件远离基底10一侧的支撑部70以及设置在支撑部70远离基底10一侧的盖板80。
在一示例性的实施方式中，盖板80用来保护发光元件。其中，盖板80 可以为玻璃盖板。
基于同一发明构思，本公开一些实施例还提供一种显示基板的制作方法，用于制作显示基板，图7为本公开实施例提供的显示基板的制作方法的流程图，如图7所示，本公开实施例提供的显示基板的制作方法具体包括以下步骤：
步骤S1、提供一基底。
在一示例性的实施方式中，基底可以为刚性衬底或柔性衬底，其中，刚性衬底可以为但不限于玻璃、金属萡片中的一种或多种；柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
步骤S2、在基底上形成多个子像素。
在一示例性的实施方式中，基底上的子像素阵列排布。其中，图2A-2B以一个子像素为例。
在一示例性的实施方式中，每个子像素包括发光区域和非发光区域，每个子像素中设置有驱动电路；驱动电路包括：存储电容和多个晶体管；多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管。
对于每个子像素，多个晶体管位于非发光区域，存储电容为透明电容，且存储电容在基底上的正投影与发光区域存在重叠区域，存储电容的第一电极与多个晶体管的有源层同层设置，存储电容的第二电极位于第一电极靠近基底的一侧。
驱动晶体管的第一极与第二电极直接接触，感测晶体管的第一极与第二电极直接接触。
其中，显示基板为前述实施例提供的显示基板，其实现原理和实现效果类似，在此不再赘述。
在一示例性的实施方式中，显示基板还包括：栅线、数据线、电源线和感测线，栅线包括：第一栅线和第二栅线，步骤S2具体包括：
在基底上形成遮光层和第二电极；在遮光层和第二电极上形成多个晶体 管的有源层和第一电极；在多个晶体管的有源层和第一电极上形成多个晶体管的栅电极、第一栅线和第二栅线；在晶体管的栅电极、第一栅线和第二栅线上形成数据线、电源线、感测线和多个晶体管的源漏电极；在数据线、电源线、感测线和多个晶体管的源漏电极上形成依次形成滤光片和发光元件。
在一示例性的实施方式中，在基底上形成遮光层和第二电极包括：在基底上依次形成遮光层和第二电极，或者在基底上依次形成第二电极和遮光层，或者在基底上同时形成第二电极和遮光层。
在一示例性的实施方式中，在基底上依次形成遮光层和第二电极包括：在基底上采用第一掩膜版形成遮光层，在遮光层上采用第二掩膜版形成第二电极。
在一示例性的实施方式中，在基底上依次形成第二电极和遮光层包括：在基底上采用第二掩膜版通过构图工艺形成第二电极，在第二电极上采用第一掩膜版形成遮光层。
在一示例性的实施方式中，在基底上同时形成第二电极和遮光层包括：在基底上依次沉积遮光薄膜和透明导电薄膜，采用半色调掩膜版同时形成第二电极和遮光层。
其中，构图工艺包括：光刻胶涂覆、曝光、显影、刻蚀以及光刻胶剥离等工艺。
下面以遮光层设置在第二电极靠近基底的一侧为例，结合图8A至图8H进一步说明遮光层和第二电极的制作过程，该过程包括如下步骤：
步骤110、在基底上沉积遮光薄膜110、在遮光薄膜110上涂覆光刻胶101，透过第一掩膜版M1对光刻胶曝光，如图8A所示。
步骤120、对光刻胶101进行显影，如图8B所示。
步骤130、将未覆盖光刻胶101的遮光薄膜刻蚀掉，如图8C所示。
步骤140、将光刻胶101剥离，形成遮光层11，如图8D所示。
步骤150、在遮光层11上沉积透明导电薄膜120，在透明导电薄膜120上上涂覆光刻胶101，透过第二掩膜版M2对光刻胶曝光，如图8E所示。
步骤160、对光刻胶101进行显影，如图8F所示。
步骤170、将未覆盖光刻胶101的透明导电薄膜刻蚀掉，如图8G所示。
步骤180、将光刻胶101剥离，形成第二电极C2，如图8H所示。
在一示例性的实施方式中，作为一种实施方式，在遮光层和第二电极上形成多个晶体管的有源层和第一电极；在多个晶体管的有源层和第一电极上形成多个晶体管的栅电极、第一栅线和第二栅线；在晶体管的栅电极、第一栅线和第二栅线上形成数据线、电源线、感测线和多个晶体管的源漏电极包括：在遮光层和第二电极上通过构图工艺形成包括第一过孔、第二过孔和第五过孔的缓冲层；在缓冲层上采用同一制程形成多个晶体管的有源层和第一电极；在多个晶体管的有源层和第一电极上形成多个晶体管的栅电极、第一栅线和第二栅线；在晶体管的栅电极、第一栅线和第二栅线上通过构图工艺形成包括第三过孔、第四过孔和第六过孔的层间绝缘层；在层间绝缘层上形成数据线、电源线、感测线和多个晶体管的源漏电极。
在一示例性的实施方式中，第一过孔和第二过孔暴露出第二电极，第五过孔暴露出感测连接线，第三过孔暴露出第一过孔，第四过孔暴露出第二过孔，第六过孔暴露出第五过孔。
作为另一种实施方式，在遮光层和第二电极上形成多个晶体管的有源层和第一电极；在多个晶体管的有源层和第一电极上形成多个晶体管的栅电极、第一栅线和第二栅线；在晶体管的栅电极、第一栅线和第二栅线上形成数据线、电源线、感测线和多个晶体管的源漏电极包括：在遮光层和第二电极上形成第一绝缘薄膜；在第一绝缘薄膜上采用同一制程形成多个晶体管的有源层和第一电极；在多个晶体管的有源层和第一电极上形成多个晶体管的栅电极、第一栅线和第二栅线；在晶体管的栅电极、第一栅线和第二栅线上形成第二绝缘薄膜；采用构图工艺对第一绝缘薄膜和第二绝缘薄膜进行处理，形成包括第一过孔、第二过孔和第五过孔的缓冲层和包括第三过孔、第四过孔和第六过孔的层间绝缘层。
在数据线、电源线、感测线和多个晶体管的源漏电极上形成依次形成滤光片和发光元件包括：在数据线、电源线、感测线和多个晶体管的源漏电极上形成包括第七过孔的钝化层；所述第七过孔暴露出感测晶体管的第一极； 在钝化层上依次形成滤光片和包括第八过孔的平坦层；所述第八过孔暴露出第七过孔；在平坦层上形成发光元件。
上述实施方式能够简化显示基板的制作工艺。
以四个子像素，感测连接线为单层结构，且与遮光层同层设置，遮光层设置在第二电极靠近基底的一侧为例，下面结合图9至图15进一步地说明本公开实施例提供的显示基板的制作方法，该方法包括如下步骤：
步骤100、在基底10上形成遮光层11和感测连接线SL，如图9所示。
步骤200、在遮光层11和感测连接线SL上依次形成第二电极C2和缓冲层(图中未示出)，如图10所示。
步骤300、在缓冲层上形成第一电极C1、开关晶体管的有源层31、驱动晶体管T2的有源层21和感测晶体管的有源层41，如图11所示。
步骤400、在开关晶体管的有源层31、驱动晶体管T2的有源层21和感测晶体管的有源层41上形成栅绝缘层，在栅绝缘层上形成开关晶体管的栅电极32、驱动晶体管的栅电极22和感测晶体管的栅电极42、第一栅线G1、第二栅线G2和电源连接线VL，在晶体管的栅电极、第一栅线、第二栅线和电源连接线上形成层间绝缘层，如图12所示。
在一示例性的实施方式中，层间绝缘层包括：第三过孔V3、第四过孔V4和第六过孔V6，缓冲层包括：第一过孔V1、第二过孔V2和第五过孔V5。
步骤500、在层间绝缘层上形成数据线Data、电源线VDD、感测线Sense、开关晶体管的第一极33、开关晶体管的第二极34，驱动晶体管的第一极23，驱动晶体管的第二极24、感测晶体管的第一极43和感测晶体管的第二极44，如图13所示。
步骤600、在数据线、电源线、感测线和多个晶体管的源漏电极上形成包括第七过孔的钝化层，在钝化层上形成滤光片50，在滤光片上形成包括第八过孔V8的平坦层，如图14所示。
步骤700、在平坦层上形成阳极61，如图15所示。
步骤800，在阳极上依次形成像素界定层、有机发光层和阴极，并在阴 极上依次设置支撑部和盖板。
基于同一发明构思，本公开实施例还提供一种显示装置，包括显示基板。
在一示例性的实施方式中，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分对于本领域的普通技术人员熟知的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述内嵌式触摸屏的实施例，重复之处不再赘述。
其中，显示基板可以为前述任意实施例提供的显示基板，其实现原理和实现效果相同或者类似，在此不再赘述。
本公开实施例附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示基板，包括：基底以及设置在所述基底上的多个子像素，每个子像素包括发光区域和非发光区域，每个子像素中设置有驱动电路；所述驱动电路包括：存储电容和多个晶体管；所述多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管；
    对于每个子像素，所述多个晶体管位于所述非发光区域，所述存储电容为透明电容，且所述存储电容在所述基底上的正投影与所述发光区域存在重叠区域，所述存储电容的第一电极与所述多个晶体管的有源层同层设置，且与所述多个晶体管的源漏电极异层设置，所述存储电容的第二电极位于所述第一电极靠近所述基底的一侧；
    所述驱动晶体管的第一极与所述第二电极电连接，所述感测晶体管的第一极与所述第二电极电连接。
  2. 根据权利要求1所述的显示基板，所述显示基板还包括：设置在所述多个晶体管的有源层靠近所述基底的一侧的缓冲层和遮光层，所述遮光层和所述第二电极设置在所述缓冲层靠近所述基底的一侧；
    所述第二电极在所述基底上的正投影覆盖所述遮光层在所述基底上的正投影，所述遮光层靠近所述第二电极的表面与所述第二电极完全接触。
  3. 根据权利要求2所述的显示基板，其中，所述遮光层设置在所述第二电极靠近所述基底的一侧，或者，所述第二电极设置在所述遮光层靠近所述基底的一侧。
  4. 根据权利要求1～3中任一项所述的显示基板，所述显示基板还包括：设置在所述多个晶体管的源漏电极和所述多个晶体管的有源层之间的层间绝缘层；
    所述缓冲层包括暴露出所述第二电极的第一过孔和第二过孔，所述层间绝缘层包括：暴露出所述第一过孔的第三过孔和暴露出所述第二过孔的第四过孔；
    所述驱动晶体管的所述第一极通过所述第一过孔和所述第三过孔与所述第二电极连接，所述感测晶体管的所述第一极通过所述第二过孔和 所述第四过孔与所述第二电极连接。
  5. 根据权利要求4所述的显示基板，所述显示基板还包括：设置在所述基底上的多行栅线和多列数据线；每个子像素由栅线和数据线交叉限定，所述多个子像素分别与所述多行栅线和所述多列数据线一一对应，所述多行栅线包括：第一栅线和第二栅线，
    所述第一栅线和所述第二栅线与所述多个晶体管的栅电极同层设置，所述多列数据线与所述多个晶体管的源漏电极同层设置。
  6. 根据权利要求5所述的显示基板，其中，对于每个子像素，所述第一电极分别与所述开关晶体管的第一极和所述驱动晶体管的栅电极连接；
    所述开关晶体管的栅电极与子像素对应的栅线中的第一栅线连接；所述开关晶体管的第二极与子像素对应的数据线连接，所述感测晶体管的栅电极与子像素对应的栅线中的第二栅线连接。
  7. 根据权利要求6所述的显示基板，其中，对于每个子像素，所述非发光区域包括：第一非发光区域和第二非发光区域，所述第一非发光区域和所述第二非发光区域位于所述发光区域的两侧，且沿所述多列数据线延伸方向设置；
    所述感测晶体管和所述第二栅线均位于所述第一非发光区域，所述开关晶体管、所述驱动晶体管和所述第一栅线均位于所述第二非发光区域。
  8. 根据权利要求5所述的显示基板，所述显示基板还包括：与所述多列数据线同层设置的电源线和感测线，每个像素包括：沿栅线延伸方向设置的四个子像素，每个像素对应两列电源线和一列感测线；
    对于每个像素，像素对应的感测线位于所述第二子像素和所述第三子像素之间，像素对应的一列电源线位于所述第一子像素远离所述第二子像素的一侧，像素对应的另一列电源线位于所述第四子像素远离所述第三子像素的一侧；
    所述第一子像素对应的数据线位于所述第一子像素靠近所述第二子像素的一侧；所述第二子像素对应的数据线位于所述第二子像素靠近所述第一子像素的一侧；所述第三子像素对应的数据线位于所述第三子像素靠近所述第四子像素的一侧，所述第四子像素对应的数据线位于所述第四子像素靠近所述第三子像素的一侧；
    所述显示基板还包括：与所述多个晶体管的栅电极同层设置的电源连接线以及与遮光层同层设置的感测连接线，每个像素对应两个沿栅线延伸方向设置的电源连接线和两个沿栅线延伸方向设置的感测连接线；电源连接线分别与电源线对应；所述电源连接线与对应的电源线连接；两个感测连接线与感测线连接；
    所述第二子像素的驱动晶体管的第二极与一个电源连接线连接；
    所述第三子像素的驱动晶体管的第二极与另一电源连接线连接；
    所述第一子像素的感测晶体管的第二极与一个感测连接线连接；
    所述第四子像素的感测晶体管的第二极另一感测连接线连接。
  9. 根据权利要求8所述的显示基板，其中，所述缓冲层还设置有暴露出所述感测连接线的第五过孔，所述层间绝缘层还设置有暴露出所述第五过孔的第六过孔；
    所述感测晶体管的第二极通过所述第五过孔和所述第六过孔与所述感测连接线连接。
  10. 根据权利要求9所述的显示基板，所述显示基板还包括：设置在所述多个晶体管的栅电极和所述多个晶体管的有源层之间的栅绝缘层；
    其中，所述栅绝缘层在所述基底上的正投影与所述多个晶体管的栅电极在所述基底上的正投影重合。
  11. 根据权利要求2所述的显示基板，其中，所述第一电极的制作材料包括透明金属氧化物，所述第二电极的制作材料包括透明导电材料。
  12. 根据权利要求10所述的显示基板，其中，每个子像素中还设置有发光元件和与子像素颜色相同的滤光片；所述发光元件包括：依次设置的阳极、有机发光层和阴极，所述阳极与所述感测晶体管的所述第一极连接，所述阳极为透射电极，所述阴极为反射电极；
    所述发光元件在所述基底上的正投影与所述发光区域存在重叠区域，所述滤光片位于所述发光区域，且设置在所述发光元件靠近所述基底的一侧，所述阳极在所述基底上的正投影覆盖所述滤光片在所述基底上的正投影。
  13. 根据权利要求12所述的显示基板，所述显示基板还包括设置在所述多个晶体管的源漏电极远离所述基底一侧的钝化层和平坦层；
    所述钝化层设置在所述滤光片靠近所述基底的一侧，所述平坦层设置在所述发光元件和所述滤光片之间；所述钝化层设置有暴露出所述感测晶体管的所述第一极的第七过孔，所述平坦层设置有暴露出所述第七过孔的第八过孔；
    所述阳极通过所述第七过孔和所述第八过孔与所述感测晶体管的所述第一极连接；
    所述第八过孔在所述基底上的正投影与所述第四过孔在所述基底上的正投影不完全重叠。
  14. 一种显示装置，包括如权利要求1～13中任一项所述的显示基板。
  15. 一种显示基板的制作方法，用于制作如权利要求1～13中任一项所述的显示基板，所述方法包括：
    提供一基底；
    在所述基底上形成多个子像素，每个子像素包括发光区域和非发光区域，每个子像素中设置有驱动电路；所述驱动电路包括：存储电容和多个晶体管；所述多个晶体管包括：开关晶体管、驱动晶体管和感测晶体管；
    对于每个子像素，所述多个晶体管位于所述非发光区域，所述存储电容为透明电容，且所述存储电容在所述基底上的正投影与所述发光区域存在重叠区域，所述存储电容的第一电极与所述多个晶体管的有源层同层设置，且与所述多个晶体管的源漏电极异层设置，所述存储电容的第二电极位于所述第一电极靠近所述基底的一侧；
    所述驱动晶体管的第一极与所述第二电极电连接，所述感测晶体管的第一极与所述第二电极电连接。
  16. 根据权利要求15所述的方法，其中，所述显示基板还包括：栅线、数据线、电源线、感测线，所述栅线包括：第一栅线和第二栅线，所述在所述基底上形成多个子像素的步骤包括：
    在所述基底上形成遮光层和所述第二电极；
    在所述遮光层和所述第二电极上形成所述多个晶体管的有源层和所述第一电极；
    在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
    在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极；
    在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极上依次形成滤光片和发光元件。
  17. 根据权利要求16所述的方法，其中，所述在所述基底上形成遮光层和所述第二电极的步骤包括：
    在所述基底上依次形成所述遮光层和所述第二电极，或者在所述基底上依次形成所述第二电极和所述遮光层，或者在所述基底上同时形成所述第二电极和所述遮光层。
  18. 根据权利要求17所述的方法，其中，所述在所述基底上同时形成所述第二电极和所述遮光层的步骤包括：
    在所述基底上依次沉积遮光薄膜和透明导电薄膜；
    采用半色调掩膜版同时形成所述第二电极和所述遮光层。
  19. 根据权利要求16-18中任一项所述的方法，其中，所述在所述遮光层和所述第二电极上形成所述多个晶体管的有源层和第一电极；在所述多个晶体管的有源层和第一电极上形成所述多个晶体管的栅电极、第一栅线和第二栅线；在所述多个晶体管的栅电极、第一栅线和第二栅线上形成数据线、电源线、感测线和所述多个晶体管的源漏电极的步骤包括：
    在所述遮光层和所述第二电极上形成包括第一过孔、第二过孔和第五过孔的缓冲层；所述第一过孔和所述第二过孔暴露出所述第二电极，所述第五过孔暴露出感测连接线；
    在所述缓冲层上采用同一制程形成所述多个晶体管的所述有源层和所述第一电极；
    在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
    在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成包括第三过孔、第四过孔和第六过孔的层间绝缘层；所述第三过孔暴露出所述第一过孔，所述第四过孔暴露出所述第二过孔，所述第六过孔暴露出所述第五过孔；
    在所述层间绝缘层上形成所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极；或者，
    在所述遮光层和所述第二电极上形成第一绝缘薄膜；
    在第一绝缘薄膜上采用同一制程形成所述多个晶体管的有源层和所述第一电极；
    在所述多个晶体管的有源层和所述第一电极上形成所述多个晶体管的栅电极、所述第一栅线和所述第二栅线；
    在所述多个晶体管的栅电极、所述第一栅线和所述第二栅线上形成第二绝缘薄膜；
    采用构图工艺对所述第一绝缘薄膜和所述第二绝缘薄膜进行处理，形成包括第一过孔、第二过孔和第五过孔的缓冲层和包括第三过孔、第四过孔和第六过孔的层间绝缘层。
  20. 根据权利要求16-18中任一项所述的方法，其中，所述在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极上依次形成滤光片和发光元件的步骤包括：
    在所述数据线、所述电源线、所述感测线和所述多个晶体管的源漏电极上形成包括第七过孔的钝化层；所述第七过孔暴露出所述感测晶体管的所述第一极；
    在所述钝化层上依次形成所述滤光片和包括第八过孔的平坦层；所述第八过孔暴露出所述第七过孔；
    在所述平坦层上形成发光元件。
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