WO2021082170A1 - 阵列基板及其制备方法、显示面板 - Google Patents

阵列基板及其制备方法、显示面板 Download PDF

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Publication number
WO2021082170A1
WO2021082170A1 PCT/CN2019/122905 CN2019122905W WO2021082170A1 WO 2021082170 A1 WO2021082170 A1 WO 2021082170A1 CN 2019122905 W CN2019122905 W CN 2019122905W WO 2021082170 A1 WO2021082170 A1 WO 2021082170A1
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Prior art keywords
layer
area
thickness
array substrate
goa
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PCT/CN2019/122905
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English (en)
French (fr)
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奚苏萍
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/626,600 priority Critical patent/US11289517B2/en
Publication of WO2021082170A1 publication Critical patent/WO2021082170A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • This application relates to the field of display, and in particular to an array substrate, a preparation method thereof, and a display panel.
  • GOA Gate Driver On Array, gate drive integrated on the array substrate
  • the width of the black matrix is set within a certain range and cannot be increased. This will cause the light entering the edge of the black matrix to pass through diffuse reflection, refraction and other reasons. It is illuminated on the array substrate; the gate terminal of the array substrate in the display area is exposed to negative voltage for a long time, and the array substrate is often exposed to light, which will accelerate the negative bias of the thin film transistor.
  • the GOA area due to the large-area shielding of the black matrix, the possibility of light leakage is very small; and for the array substrate in the GOA area to achieve rapid response, the thickness of its active area is usually investigated in detail. Therefore, how to reduce the negative bias of the array substrate in the display area and improve the response speed of the array substrate in the GOA area, thereby improving the display quality, is particularly important.
  • the negative bias of the array substrate in the display area of the existing display panel needs to be avoided, and the response speed of the array substrate in the GOA area needs to be improved.
  • the present application provides an array substrate, a preparation method thereof, and a display panel to alleviate the problem that the negative bias of the array substrate in the display area of the existing display panel needs to be avoided, and the response speed of the array substrate in the GOA area needs to be improved.
  • the present application provides an array substrate, which includes a display area and a GOA area, and the array substrate includes:
  • An active layer formed on the substrate, and patterned to form an active area
  • the source and drain layers are formed on the active layer
  • the thickness of the active area located in the display area is greater than the thickness of the active area located in the GOA area.
  • the array substrate further includes a gate layer, a gate insulating layer, an etching stop layer, a passivation layer, and a planarization layer stacked on the substrate.
  • the source layer is located between the gate insulating layer and the etch stop layer, and the source drain layer is located between the etch stop layer and the passivation layer.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the thickness of the passivation layer located in the display area is smaller than the thickness of the passivation layer located in the GOA area.
  • the thickness of the planarization layer located in the display area is smaller than the thickness of the planarization layer located in the GOA area.
  • the array substrate further includes a gate insulating layer, a gate layer, an interlayer insulating layer, a passivation layer, and a planarization layer stacked on the substrate.
  • the source layer is located between the substrate and the gate insulating layer, and the source drain layer is located between the interlayer insulating layer and the passivation layer.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the thickness of the interlayer insulating layer located in the display area is smaller than the thickness of the interlayer insulating layer located in the GOA area.
  • the thickness of the passivation layer located in the display area is smaller than the thickness of the passivation layer located in the GOA area.
  • the thickness of the planarization layer located in the display area is smaller than the thickness of the planarization layer located in the GOA area.
  • the material of the active layer of the array substrate is amorphous silicon or indium gallium zinc oxide compound.
  • this application also provides a method for manufacturing an array substrate, which includes:
  • the semiconductor active layer is patterned to obtain an active area.
  • the thickness of the active area in the display area is greater than the thickness of the active area in the GOA area.
  • the specific steps of patterning the semiconductor active layer include:
  • the semiconductor active layer is patterned by using a half-mask mask technology.
  • the specific steps of patterning the semiconductor active layer include:
  • a gray tone mask technology is used to pattern the semiconductor active layer.
  • the present application also provides a display panel.
  • the display panel includes an array substrate.
  • the array substrate includes a display area and a GOA area.
  • the thickness of the active layer in the display area is greater than that in the GOA area.
  • the thickness of the active layer is greater than that in the GOA area.
  • the array substrate further includes a gate layer, a gate insulating layer, an etching stop layer, a passivation layer, and a planarization layer stacked on the substrate.
  • the source layer is located between the gate insulating layer and the etch stop layer, and the source drain layer is located between the etch stop layer and the passivation layer.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the thickness of the passivation layer located in the display area is smaller than the thickness of the passivation layer located in the GOA area.
  • the array substrate further includes a gate insulating layer, a gate layer, an interlayer insulating layer, a passivation layer, and a planarization layer stacked on the substrate.
  • the source layer is located between the substrate and the gate insulating layer, and the source drain layer is located between the interlayer insulating layer and the passivation layer.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the present application provides an array substrate, a preparation method thereof, and a display panel.
  • the substrate includes a display area and a GOA area.
  • the thickness of the active layer of the array substrate located in the AA area is greater than the thickness of the active layer located in the GOA area;
  • the active layer of the array substrate in the GOA area and the display area are set to different thicknesses, and the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the demand for rapid response of thin film transistors in the GOA area;
  • the thickness of the active layer is set to be larger, which can alleviate the diffusion of photons in the active layer, so as to reduce the influence of the negative bias of the thin film transistor in the display area; in this way, the different thicknesses of the active layer in the GOA area and the display area are set At the same time, it meets the different feature requirements of the array substrate in the display area and the GOA area, and improves the quality of the display panel.
  • FIG. 1 is a schematic diagram of the first structure of an array substrate provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of a first structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a preparation flow chart of the array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the principle of the half-mask mask technology provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of the principle of the gray mask technology provided by an embodiment of the application.
  • Fig. 6 is a partial enlarged view of area 501 in Fig. 5.
  • this application provides a Micro-LED chip that can alleviate this problem.
  • the Micro-LED chip 10 provided in the present application includes the following layers stacked from top to bottom:
  • the buffer layer 101 in an embodiment, is a thicker gallium nitride intrinsic layer with a thickness greater than 2um. This embodiment is only an exemplary description and is not a limitation.
  • the first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 are an N-type gallium nitride layer, and the active layer 103 is a gallium nitride multiple quantum well layer,
  • the second semiconductor layer 104 is a P-type gallium nitride layer, the P-type gallium nitride layer may be a magnesium (Mg) doped gallium nitride layer, and the N-type gallium nitride layer may be a silicon (Si) doped nitride layer.
  • the gallium layer and the gallium nitride quantum well layer may be an indium gallium nitride/gallium nitride (InGaN/GaN) layer repeatedly arranged in sequence.
  • InGaN/GaN indium gallium nitride/gallium nitride
  • This embodiment is only an exemplary illustration and is not limited.
  • the first The materials of the semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 can be set according to the actual requirements of the Micro-LED chip.
  • the insulating layer 105 is used to separate the first semiconductor layer 102, the active layer 103 and the second semiconductor layer 104 into at least two independent sub-chips; in one embodiment, the material of the insulating layer 105 is silicon oxide, nitrogen One or more of silicon oxide, silicon oxynitride, aluminum nitride, coated glass, and polyimide, preferably silicon oxide with good light transmittance.
  • the current diffusion layer 106 is used to connect the second semiconductor layer 104 in each sub-chip with the first semiconductor layer 102 in the next sub-chip to form an ohmic contact, so as to make the holes and/or generated in the P-type semiconductor layer Or electrons generated in the N-type semiconductor layer can be effectively injected into the active layer, thereby increasing the luminous efficiency of the Micro-LED display panel.
  • the current diffusion layer 106 also plays a role of reflecting light.
  • the material of the current diffusion layer 106 is graphene, indium tin oxide, zinc oxide, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten and other materials with good conductivity and reflectivity.
  • the current diffusion layer 106 may be a single-layer structure or a multi-layer structure.
  • the protective layer 107 is used to cover and insulate the current diffusion layer 106, while isolating water and oxygen and heat conduction, and slowing down the performance degradation of each film layer in the Micro-LED chip 10, thereby prolonging the service life of the Micro-LED chip.
  • the material of the protective layer 107 is any one of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, preferably silicon nitride, silicon oxynitride, aluminum nitride, etc., which have good thermal conductivity. material.
  • the first electrode 108 and the second electrode 109, the first electrode 108 is electrically connected to the first semiconductor layer 102 of the first sub-chip, and the second electrode 109 is electrically connected to the second semiconductor layer 104 of the last sub-chip.
  • the first electrode 108 is an N-type electrode
  • the second electrode 109 is a P-type electrode.
  • the material is indium, tin, zinc, nickel, silver, aluminum, gold, platinum, palladium, magnesium, tungsten, etc.
  • One or more of the metals or alloys can adopt a single-layer metal structure or a multi-layer metal structure.
  • the N-type semiconductor layer 102, the active layer 103, and the P-type semiconductor layer 104 constitute a light-emitting PN junction.
  • the light-emitting PN junction is connected to an external circuit, it is possible to apply the light-emitting PN junction through the external circuit.
  • voltage When voltage is applied, electrons are generated in the N-type semiconductor layer 102 and the P-type semiconductor layer 104, respectively, and the negative bias of the array substrate in the display area of the existing display panel needs to be avoided.
  • the response speed of the array substrate in the GOA area needs to be improved.
  • the application provides an array substrate and a preparation method thereof to alleviate this problem.
  • the array substrate provided by the present application includes a display area AA and a GOA area, and the array substrate includes:
  • the active layer is formed on the substrate and patterned to form the active area
  • the source and drain layers are formed on the active layer
  • the thickness of the active area located in the display area is greater than the thickness of the active area located in the GOA area.
  • This embodiment provides an array substrate, which includes a display area and a GOA area.
  • the thickness of the active layer of the array substrate located in the AA area is greater than the thickness of the active layer located in the GOA area; by combining the GOA area and the display area
  • the active layer of the inner array substrate is set to different thicknesses, and the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the demand for rapid response of the thin film transistor in the GOA area; the thickness of the active layer in the display area is set It can alleviate the diffusion of photons in the active layer, so as to reduce the negative bias of the thin film transistor in the display area; this way, the different thickness settings of the active layer in the GOA area and the display area can meet the requirements of the display area.
  • the different feature requirements of the array substrate have improved the quality of the display panel.
  • the array substrate provided by the present application has a bottom gate structure, and the array substrate includes:
  • the substrate 110 is a glass substrate or a flexible substrate.
  • the glass substrate is composed of aluminosilicate and other components, and the requirements are low alkali, high flatness, high temperature resistance and low thermal expansion coefficient.
  • the flexible substrate generally includes a first flexible substrate, a second flexible substrate, and an inorganic layer located between the first flexible substrate and the second flexible substrate; the materials of the first flexible substrate and the second flexible substrate Polyacetamide or polyethylene terephthalate is used to ensure the flexibility of the flexible substrate; the material of the inorganic layer is silicon nitride or silicon oxide, which is used to block water or oxygen outside the array substrate from entering the thin film transistor.
  • the gate layer 120 is formed on the substrate 110 and is patterned to form gates and scan signal lines.
  • the material of the gate layer 120 is generally molybdenum, aluminum or aluminum alloy.
  • the gate insulating layer 130 is formed on the gate layer 120 and covers the gate layer 120 and the substrate 110.
  • the gate insulating layer is generally a stacked structure formed by silicon oxide/silicon nitride. Silicon nitride has a higher breakdown voltage and can be used as a good gate insulating material. The surface of silicon oxide and polysilicon has good grain boundary matching and stress Matching, while silicon oxide has good step coverage.
  • the active layer 140 is formed on the gate insulating layer 130, and is patterned to form an active region.
  • the active region is doped to form a doped region and a channel region.
  • the material of the active layer is indium gallium zinc oxide or amorphous silicon; the doped region is high-concentration phosphorous ion implantation and doping to form the source and drain of the N-type thin film transistor Region, or high-concentration boron ion implantation doping to form the source and drain regions of the P-type thin film transistor.
  • the active layer includes an active area 141 located in the GOA area and an active area 142 located in the AA area.
  • the thickness of the active area 141 is smaller than the thickness of the active area 142.
  • the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the fast response requirements of the thin film transistors in the GOA area; the active layer in the AA area
  • the thickness of the layer is set to be larger, which can alleviate the diffusion of photons in the active layer, thereby reducing the influence of the negative bias of the thin film transistor in the AA area; this way, the different thickness of the active layer in the GOA area and the AA area is set, and at the same time
  • the different feature requirements of the array substrate in the display area and the GOA area are met, and the quality of the display panel is improved.
  • the etch stop layer 150 is formed on the active layer 140 and covers the channel region of the active layer 140, and can also cover the channel region and the doped region at the same time.
  • the material of the etching stop layer is silicon oxide, or silicon nitride, or a stacked structure of silicon oxide and silicon nitride.
  • the etching stop layer 150 is used to protect the channel region of the active layer 140 from the etching solution during the subsequent preparation process of the source and drain layers.
  • the source and drain layer 160 is formed on the etch stop layer 150 and patterned to form source, drain, data signal lines, power signal lines, etc., the source and drain are respectively connected to the doped regions located on both sides of the active region Connected.
  • the material of the source and drain layer 160 is a stacked structure of titanium/aluminum/titanium or a stacked structure of molybdenum/aluminum/molybdenum.
  • the passivation layer 170 is formed on the source and drain layer 160 to cover the source and drain layer 160, the etching stop layer 150 and the gate insulating layer 130.
  • the passivation layer 170 is mainly used to isolate the source, drain, data signal line, power signal line, etc. in the open source drain layer to avoid shorting between them. At the same time, it is used to keep the source and drain layer from being connected to each other.
  • the metal layer is insulated.
  • the material of the passivation layer 170 is generally silicon nitride.
  • the planarization layer 180 is formed on the passivation layer 170 and covers the passivation layer 170.
  • the main function of the planarization layer 180 is to planarize the array substrate, and its material is generally polyimide (PI), polyethylene terephthalate (PET) or other organic materials.
  • the thickness of the active layer 141 located in the GOA area is greater than the thickness of the active layer 222 located in the AA area, it is very easy to cause the overall thickness of the array substrate in the GOA area to be greater than that of the array substrate in the AA area.
  • the overall thickness To ensure that the overall thickness of the array substrate in the GOA area is the same as the overall thickness of the array substrate in the AA area, the thickness of other functional film layers needs to be adjusted.
  • the thickness of the passivation layer located in the AA area is smaller than the thickness of the passivation layer located in the GOA area.
  • the sum of the thickness of the active layer and the passivation layer in the AA area is equal to the sum of the thickness of the active layer and the passivation layer in the GOA area; this compensates for the active area in the AA area and the GOA area
  • the difference in thickness affects the overall thickness of the array substrate.
  • the thickness of the planarization layer located in the AA area is smaller than the thickness of the planarization layer located in the GOA area.
  • the sum of the thickness of the active layer and the planarization layer located in the AA area is equal to the sum of the thickness of the active layer and the planarization layer located in the GOA area; this compensates for the active area in the AA area and the GOA area
  • the difference in thickness affects the overall thickness of the array substrate.
  • the array substrate provided by the present application has a top gate structure, and the array substrate includes:
  • the substrate 210 is a glass substrate or a flexible substrate.
  • the glass substrate is composed of aluminosilicate and other components, and the requirements are low alkali, high flatness, high temperature resistance and low thermal expansion coefficient.
  • the flexible substrate generally includes a first flexible substrate, a second flexible substrate, and an inorganic layer located between the first flexible substrate and the second flexible substrate; the materials of the first flexible substrate and the second flexible substrate Polyacetamide or polyethylene terephthalate is used to ensure the flexibility of the flexible substrate; the material of the inorganic layer is silicon nitride or silicon oxide, which is used to block water or oxygen outside the array substrate from entering the thin film transistor.
  • the active layer 220 is formed on the substrate 210 and is patterned to form an active region.
  • the active region is doped to form a doped region and a channel region.
  • the material of the active layer is indium gallium zinc oxide or amorphous silicon; the doped region is high-concentration phosphorous ion implantation and doping to form the source and drain of the N-type thin film transistor Region, or high-concentration boron ion implantation doping to form the source and drain regions of the P-type thin film transistor.
  • the active layer includes an active area 221 located in the GOA area and an active area 222 located in the AA area.
  • the thickness of the active area 221 is smaller than the thickness of the active area 222.
  • the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the fast response requirements of the thin film transistors in the GOA area; the active layer in the AA area
  • the thickness of the layer is set to be larger, which can alleviate the diffusion of photons in the active layer, thereby reducing the influence of the negative bias of the thin film transistor in the AA area; this way, the different thickness of the active layer in the GOA area and the AA area is set, and at the same time
  • the different feature requirements of the array substrate in the display area and the GOA area are met, and the quality of the display panel is improved.
  • the gate insulating layer 230 is formed on the active layer 220 and covers the active layer 220 and the substrate 210.
  • the gate insulating layer is generally a stacked structure formed by silicon oxide/silicon nitride. Silicon nitride has a higher breakdown voltage and can be used as a good gate insulating material. The surface of silicon oxide and polysilicon has good grain boundary matching and stress Matching, while silicon oxide has good step coverage.
  • the gate layer 240 is formed on the gate insulating layer 230 to form gates and scan signal lines by patterning.
  • the material of the gate layer 240 is generally metal molybdenum, metal aluminum or aluminum alloy.
  • the interlayer insulating layer 250 is formed on the gate layer 240 and covers the gate layer 240 and the gate insulating layer 230.
  • the material of the interlayer insulating layer is silicon oxide, or silicon nitride, or a stacked structure of silicon oxide and silicon nitride.
  • the source and drain layer 260 is formed on the interlayer insulating layer 250, and the source electrode, the drain electrode, the data signal line, the power signal line, etc. are formed by patterning.
  • the source electrode and the drain electrode are respectively connected to the doped regions located on both sides of the active region. Connected.
  • the material of the source and drain layer 260 is a stacked structure of titanium/aluminum/titanium or a stacked structure of molybdenum/aluminum/molybdenum.
  • the passivation layer 270 is formed on the source and drain layer 260 to cover the source and drain layer 260 and the interlayer insulating layer 250.
  • the passivation layer 270 is mainly used to isolate the source, drain, data signal line, power signal line, etc. in the open source drain layer to avoid shorting between them. At the same time, it is used to keep the source and drain layer from being connected to each other.
  • the metal layer is insulated.
  • the material of the passivation layer 270 is generally silicon nitride.
  • the planarization layer 280 is formed on the passivation layer 270 and covers the passivation layer 270.
  • the main function of the planarization layer 280 is to planarize the array substrate, and its material is generally polyimide (PI), polyethylene terephthalate (PET) or other organic materials.
  • the thickness of the active layer 221 located in the GOA area is greater than that of the active layer 222 located in the AA area, it is very easy to cause the overall thickness of the array substrate in the GOA area to be greater than that of the array substrate in the AA area.
  • the overall thickness To ensure that the overall thickness of the array substrate in the GOA area is the same as the overall thickness of the array substrate in the AA area, the thickness of other functional film layers needs to be adjusted.
  • the thickness of the interlayer insulating layer in the AA area is smaller than the thickness of the interlayer insulating layer in the GOA area.
  • the sum of the thickness of the active layer and the interlayer insulating layer located in the AA area is equal to the sum of the thickness of the active layer and the interlayer insulating layer located in the GOA area; The difference in the thickness of the source region has an impact on the overall thickness of the array substrate.
  • the thickness of the passivation layer located in the AA area is smaller than the thickness of the passivation layer located in the GOA area.
  • the sum of the thickness of the active layer and the passivation layer in the AA area is equal to the sum of the thickness of the active layer and the passivation layer in the GOA area; this compensates for the active area in the AA area and the GOA area
  • the difference in thickness affects the overall thickness of the array substrate.
  • the thickness of the planarization layer located in the AA area is smaller than the thickness of the planarization layer located in the GOA area.
  • the sum of the thickness of the active layer and the planarization layer located in the AA area is equal to the sum of the thickness of the active layer and the planarization layer located in the GOA area; this compensates for the active area in the AA area and the GOA area
  • the difference in thickness affects the overall thickness of the array substrate.
  • the present application provides a method for manufacturing an array substrate, which includes:
  • the semiconductor active layer is patterned to obtain an active area.
  • the thickness of the active area in the display area is greater than the thickness of the active area in the GOA area.
  • This embodiment provides a method for preparing an array substrate.
  • the preparation method uses patterning processing to set the active layer of the array substrate in the GOA area and the display area to different thicknesses.
  • the thickness of the active layer in the GOA area is set Smaller, it helps to achieve the fast response requirements of the thin film transistor in the GOA area; the larger the thickness of the active layer in the display area can alleviate the diffusion of photons in the active layer, so as to reduce the thin film transistor in the display area The influence of negative bias; in this way, the different thickness settings of the active layer in the GOA area and the display area meet the different feature requirements of the array substrate in the display area and the GOA area, and improve the quality of the display panel.
  • the semiconductor active layer is obtained by patterning using a half-mask mask technology.
  • the semi-illuminated mask 410 includes an opaque area 411, a semi-transmissive area 412, and a fully transparent area 413.
  • the light intensity of the light 420 through the translucent mask 410 is as shown by the curve 450.
  • the exposure illumination light 420 irradiates the fully transparent area 413, the exposure illumination light is not blocked in any way, and all passes through the semi-transparent mask and reaches the photoresist. At this time, the exposure illumination light received by the photoresist in the corresponding area The intensity of the photoresist is the strongest, and the photoresist in the corresponding area is exposed and developed, and almost all of the photoresist is removed by the polymerization reaction.
  • the exposure irradiated light 420 hits the opaque area 411, all the exposure irradiated light is blocked by the opaque area 411.
  • the exposure irradiated light cannot penetrate the semi-transparent mask and cannot reach the photoresist.
  • the corresponding area The intensity of the exposure irradiated light received by the photoresist is almost zero, and the photoresist in the corresponding area is exposed and developed, and almost all the photoresist is retained.
  • the exposure illumination light 420 irradiates the semi-transmissive area 412, only part of the exposure illumination light smoothly passes through the semi-transmissive area 412 to reach the photoresist. At this time, the photoresist in the corresponding area receives a significant amount of the exposure illumination light. The intensity is weakened, but part of the energy remains. The photoresist in the corresponding area is exposed and developed, the photoresist part undergoes polymerization and is removed, and the remaining part of the photoresist is retained.
  • the photoresist can be exposed and developed by using the semi-mask mask technology to obtain two photoresist patterns with different post-degrees, and further can realize the preparation of active layers of different thicknesses in the GOA area and the display area of the array substrate.
  • the magnetron sputtering method is used to sputter a layer of metal film on the substrate.
  • the metal film can be metal molybdenum, metal aluminum, or a composite material of metal molybdenum and metal aluminum.
  • the gate and the gate line are prepared.
  • a photoresist layer is deposited on the metal molybdenum film, a set of gate mask is used to expose the photoresist layer, and then the exposed photoresist is developed with a developer to obtain a gate Layer pattern; then wet etch the exposed metal molybdenum of the gate layer to remove the metal molybdenum that is not protected by the photoresist; then remove the remaining photoresist, and the remaining metal layer is the patterned gate Polar layer.
  • Ion chemical vapor deposition is used to deposit insulating material on the gate layer.
  • the insulating material can be a single-layer silicon nitride film, a single-layer silicon oxide film, or a silicon oxide/silicon nitride laminated film .
  • the gate insulating layer needs to have a higher dielectric constant, so that the capacitance of the gate oxide layer (the capacitance between the gate and the channel region of the active layer) is larger, and it is easier to produce the inversion layer of the channel.
  • a plasma chemical vapor deposition method is used to deposit a semiconductor active layer on the gate insulating layer.
  • the active layer may be an oxide active layer or an amorphous silicon active layer.
  • the active layer is patterned.
  • the translucent area of the translucent mask corresponds to the active area in the display area
  • the opaque area of the semi-transmissive mask corresponds to the active area in the GOA area
  • the exposed photoresist is developed, and the photoresist that is completely illuminated is removed, leaving a photoresist that has not been irradiated by light and is irradiated by semi-transmissive light, where the thickness of the photoresist that has not been irradiated by light, Greater than the thickness of the photoresist irradiated by translucent light;
  • the first etching process is used to etch the active layer without photoresist protection, and the remaining active layer is the active area protected by the photoresist;
  • Plasma ashing is performed on the photoresist to remove the photoresist irradiated by translucent light, and the photoresist that is not irradiated by light is thinned and retained;
  • the second etching process is used to etch the active layer without photoresist protection, and the etching process is controlled so that the active area is thinned and retained;
  • Plasma ashing is performed on the remaining photoresist, and the remaining photoresist is stripped off;
  • the patterning of the active layer is completed, and the thinned active area in the GOA area and the active area in the display area that are not thinned are obtained.
  • the patterned active region is doped, and the predetermined position of the active region is doped by ion bath or ion implantation through a self-aligned process.
  • the doped ions can be high
  • the concentration of phosphorus ions is used to form the source and drain regions of the N-type thin film transistor, and it can also be a high concentration of boron ions to form the source and drain regions of the P-type thin film transistor.
  • Plasma chemical vapor deposition is used to deposit a layer of silicon oxide film on the active layer as an etching stop layer.
  • the etching stop layer covers the active area of the active layer and can also cover part of the active layer. Miscellaneous area.
  • via holes need to be prepared at predetermined positions of the array substrate for connecting the active layer, the gate layer and the source and drain layers through the via holes in the process of depositing the source and drain metals.
  • the method used is dry etching, including reactive ion etching and inductively coupled plasma etching.
  • a magnetron sputtering method is used to sputter a layer of indium tin oxide film on the etching barrier layer. Under the action of a strong magnetic field, the indium tin oxide film is deposited. This is mainly because the sputtering of the indium tin oxide film is not suitable for high-power sputtering.
  • the target material will cause indium oxide on the surface of the indium tin oxide target, and the conductivity of indium oxide is not good, which affects the self-sustained discharge; and the temperature of the magnetron sputtering substrate should be lower than 100 degrees, and the indium tin oxide film formed at this time It is amorphous, the etching rate is high, and there is no residue.
  • the indium tin oxide film is patterned to form a source electrode, a drain electrode, a data signal line, and a power signal line.
  • Ion chemical vapor deposition is used to deposit an insulating material on the source and drain layers to form a passivation layer.
  • the insulating material can be a single layer of silicon nitride film, a single layer of silicon oxide film, or silicon oxide/nitrogen. Laminated film of silicon dioxide.
  • the passivation layer covers the source and drain layers and the interlayer insulating layer.
  • a layer of organic material is coated on the passivation layer to planarize the array substrate, and the organic material is generally polyimide, polyethylene terephthalate or other organic materials.
  • the semiconductor active layer is obtained by patterning using gray tone mask technology.
  • FIG. 5 it is a schematic diagram of the principle of the gray-tone mask technology.
  • the gray-tone mask technology uses the grating effect to achieve the half-illumination effect of the mask, thereby allowing the photoresist to be selectively exposed and developed.
  • the gray tone mask 510 includes an opaque area 511, a grating area 512, and a fully transparent area 513.
  • the light intensity of the light 520 through the translucent mask 510 is as shown by the curve 550.
  • the exposure radiation light 520 irradiates the fully transparent area 513
  • the exposure radiation light is not blocked by any means, and all passes through the semi-transparent mask and reaches the photoresist.
  • the exposure radiation light received by the photoresist in the corresponding area The intensity of the photoresist is the strongest, the photoresist in the corresponding area is exposed and developed, and almost all of the photoresist is removed by polymerization reaction.
  • the exposure irradiation light 520 irradiates the opaque area 511, all the exposure irradiation light is blocked by the opaque area 511.
  • the exposure irradiation light cannot penetrate the semi-transparent mask and cannot reach the photoresist.
  • the corresponding area The intensity of the exposure irradiated light received by the photoresist is almost zero, and the photoresist in the corresponding area is exposed and developed, and almost all the photoresist is retained.
  • the exposure light 520 irradiates the grating area 512, as shown in FIG. 6, only part of the exposure light passes through the hollow area of the grating to reach the photoresist, and the remaining part of the light is blocked by the grating. At this time, the corresponding area The intensity of the exposure irradiated light received by the photoresist inside is reduced, but there is still part of the energy reserved.
  • the photoresist in the corresponding area is exposed and developed. The photoresist part undergoes polymerization and is removed, and the rest of the light The resistance is retained.
  • using the gray tone mask technology to expose and develop the photoresist can also obtain two photoresist patterns with different post-degrees, and further can realize the preparation of active layers of different thicknesses in the GOA area and the display area of the array substrate.
  • the specific preparation method can refer to the preparation method of the semi-illuminated mask technology in the above-mentioned embodiment, which will not be described in detail here.
  • the present application also provides a display panel, including an array substrate, the array substrate includes a display area and a GOA area, and the array substrate includes:
  • the active layer is formed on the substrate and patterned to form the active area
  • the source and drain layers are formed on the active layer
  • the thickness of the active area located in the display area is greater than the thickness of the active area located in the GOA area.
  • This embodiment provides a display panel that includes an array substrate, the array substrate includes a display area and a GOA area, and the thickness of the active layer of the array substrate in the AA area is greater than the thickness of the active layer in the GOA area;
  • the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the fast response requirements of the thin film transistors in the GOA area;
  • the thickness of the inner active layer is set to be larger, which can alleviate the diffusion of photons in the active layer, so as to reduce the influence of the negative bias of the thin film transistor in the display area; this affects the different thickness of the active layer in the GOA area and the display area.
  • the setting meets the different feature requirements of the array substrate in the display area and the GOA area at the same time, and improves the quality of the display panel.
  • the array substrate further includes a substrate, a gate layer, a gate insulating layer, an etching stop layer, a source and drain layer, a passivation layer, and a planarization layer.
  • the active layer is located on the gate insulating layer. ⁇ etch barrier layer.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the thickness of the passivation layer located in the display area is smaller than the thickness of the passivation layer located in the GOA area.
  • the thickness of the planarization layer located in the display area is smaller than the thickness of the planarization layer located in the GOA area.
  • the array substrate further includes a substrate, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, a passivation layer, and a planarization layer.
  • the active layer is located on the substrate and the gate. Between extremely insulating layers.
  • the thickness of the array substrate in the display area is the same as the thickness in the GOA area.
  • the thickness of the interlayer insulating layer in the display area is smaller than the thickness of the interlayer insulating layer in the GOA area.
  • the thickness of the passivation layer located in the display area is smaller than the thickness of the passivation layer located in the GOA area.
  • the thickness of the planarization layer located in the display area is smaller than the thickness of the planarization layer located in the GOA area.
  • the embodiments of the present application provide an array substrate and a preparation method thereof, and a display panel.
  • the substrate includes a display area and a GOA area.
  • the thickness of the active layer of the array substrate in the AA area is greater than the thickness of the active layer in the GOA area.
  • the thickness of the active layer in the GOA area is set to be smaller, which helps to achieve the fast response requirements of the thin film transistors in the GOA area;
  • the thickness of the active layer in the area is set to be larger, which can alleviate the diffusion of photons in the active layer, thereby reducing the influence of the negative bias of the thin film transistor in the display area; this has a difference between the active layer in the GOA area and the display area.
  • the thickness setting meets the different feature requirements of the array substrate in the display area and the GOA area at the same time, and improves the quality of the display panel.

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Abstract

本申请提供一种阵列基板及其制备方法、显示面板，该基板GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，减小显示区内薄膜晶体管负偏的影响；同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。

Description

阵列基板及其制备方法、显示面板
本申请要求于2019年10月28日提交中国专利局、申请号为201911031657.3、发明名称为“阵列基板及其制备方法、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，尤其涉及一种阵列基板及其制备方法、显示面板。
 背景技术
GOA（Gate Driver On Array，栅极驱动集成在阵列基板上）技术由于具备可以节省栅极驱动集成电路、实现窄边框等优势，目前已经广泛的运用于面板设计当中。
在面板的显示区内，由于受到开口率的限制，黑矩阵的宽度设定在一定的范围内，无法增大，这样就导致了射入到黑矩阵边缘的光线会通过漫反射、折射等原因照射到阵列基板上；显示区内阵列基板的栅极端长时间受到负向电压，阵列基板经常受到光照，会加速薄膜晶体管的负偏。在GOA区域内，由于黑矩阵大面积遮挡，存在漏光的可能性很小；而GOA区的阵列基板为了达到快速响应的目的，通常对其有源区的厚度进行细部追究。所以，如何减小显示区内阵列基板的负偏，提高GOA 区内阵列基板的响应速度，从而提高显示质量，显得尤为重要。
因此，现有显示面板存在显示区内阵列基板的负偏需要避免，GOA 区内阵列基板的响应速度需要提高。
 技术问题
本申请提供一种阵列基板及其制备方法、显示面板，以缓解现有显示面板存在显示区内阵列基板的负偏需要避免，GOA 区内阵列基板的响应速度需要提高的问题。
 技术解决方案
为解决以上问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，其包括显示区和GOA区，所述阵列基板包括：
衬底；
有源层，形成于所述衬底上，图案化形成有源区；
源漏极层，形成于所述有源层上；
其中，位于所述显示区内的有源区的厚度，大于位于所述GOA区内的有源区的厚度。
在本申请提供的阵列基板中，所述阵列基板还包括在所述衬底上层叠设置的栅极层、栅极绝缘层、刻蚀阻挡层、钝化层、以及平坦化层，所述有源层位于所述栅极绝缘层和所述刻蚀阻挡层之间，所述源漏极层位于所述刻蚀阻挡层和所述钝化层之间。
在本申请提供的阵列基板中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
在本申请提供的阵列基板中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
在本申请提供的阵列基板中，位于所述显示区内的平坦化层的厚度，小于位于所述GOA区内的平坦化层的厚度。
在本申请提供的阵列基板中，所述阵列基板还包括在所述衬底上层叠设置的栅极绝缘层、栅极层、层间绝缘层、钝化层、以及平坦化层，所述有源层位于所述衬底和所述栅极绝缘层之间，所述源漏极层位于所述层间绝缘层和所述钝化层之间。
在本申请提供的阵列基板中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
在本申请提供的阵列基板中，位于所述显示区内的层间绝缘层的厚度，小于位于所述GOA区内的层间绝缘层的厚度。
在本申请提供的阵列基板中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
在本申请提供的阵列基板中，位于所述显示区内的平坦化层的厚度，小于位于所述GOA区内的平坦化层的厚度。
在本申请提供的阵列基板中，在所述GOA区内，所述阵列基板的有源层的材料为非晶硅或铟镓锌氧化合物。
同时，本申请还提供一种阵列基板的制备方法，其包括：
提供基板；
在所述基板上沉积一层半导体有源层；
图案化处理所述半导体有源层，得到有源区，位于显示区内的有源区的厚度，大于位于GOA区内的有源区的厚度。
在本申请提供的制备方法中，所述图案化处理所述半导体有源层的具体步骤包括：
采用半光罩掩膜技术，图案化处理所述半导体有源层。
在本申请提供的制备方法中，所述图案化处理所述半导体有源层的具体步骤包括：
采用灰色调掩膜技术，图案化处理所述半导体有源层。
同时，本申请还提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括显示区和GOA区，位于所述显示区内的有源层的厚度，大于位于所述GOA区内的有源层的厚度。
在本申请提供的显示面板中，所述阵列基板还包括在所述衬底上层叠设置的栅极层、栅极绝缘层、刻蚀阻挡层、钝化层、以及平坦化层，所述有源层位于所述栅极绝缘层和所述刻蚀阻挡层之间，所述源漏极层位于所述刻蚀阻挡层和所述钝化层之间。
在本申请提供的显示面板中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
在本申请提供的显示面板中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
在本申请提供的显示面板中，所述阵列基板还包括在所述衬底上层叠设置的栅极绝缘层、栅极层、层间绝缘层、钝化层、以及平坦化层，所述有源层位于所述衬底和所述栅极绝缘层之间，所述源漏极层位于所述层间绝缘层和所述钝化层之间。
在本申请提供的显示面板中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
 有益效果
本申请提供一种阵列基板及其制备方法、显示面板，该基板包括显示区和GOA区，阵列基板位于AA区内的有源层的厚度，大于位于GOA区内的有源层的厚度；通过将GOA区和显示区内阵列基板的有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，从而达到减小显示区内薄膜晶体管负偏的影响；这样对GOA区和显示区内有源层的不同厚度设置，同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。
 附图说明
图1为本申请实施例提供的阵列基板的第一种结构示意简图。
图2为本申请实施例提供的阵列基板的第一种结构示意简图。
图3为本申请实施例提供的阵列基板的制备流程图。
图4为本申请实施例提供的半光罩掩膜技术的原理示意简图。
图5为本申请实施例提供的灰色度掩膜技术的原理示意简图。
图6为图5中501区域的局部放大图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
针对现有Micro LED显示器存在驱动TFT功耗严重的问题，本申请提供一种Micro-LED芯片可以缓解这个问题。
在一种实施例中，如图1所示，本申请提供的Micro-LED芯片10包括由上到下依次层叠设置的：
缓冲层101，在一种实施例中，缓冲层101为较厚的氮化镓本征层，其厚度大于2um，该实施例仅为示例性说明，并非限定。
第一半导体层102、有源层103和第二半导体层104，在一种实施例中，第一半导体层102为N型氮化镓层，有源层103为氮化镓多量子阱层，第二半导体层104为P型氮化镓层，P型氮化镓层可为镁(Mg)掺杂的氮化镓层，N型氮化镓层可为硅(Si)掺杂的氮化镓层，氮化镓量子阱层可为依次重复排列的氮化铟镓/氮化镓(InGaN/GaN)层，该实施例仅为示例性说明，并非限定，在其他实施例中，第一半导体层102、有源层103和第二半导体层104的材料可根据Micro-LED芯片的实际需求设置。
绝缘层105，用于将第一半导体层102、有源层103和第二半导体层104分隔为至少两个独立的子芯片；在一种实施例中，绝缘层105的材料为氧化硅、氮化硅、氮氧化硅、氮化铝、涂布玻璃、聚酰亚胺中的一种或几种，优选透光性能良好的氧化硅。
电流扩散层106，用于将每一子芯片内的第二半导体层104，与下一子芯片内的第一半导体层102连接，形成欧姆接触，使P型半导体层中产生的空穴和/或N型半导体层中产生的电子能有效地注入有源层中，从而增加Micro-LED显示面板的发光效率。同时，电流扩散层106还起到反射光的作用。在一种实施例中，电流扩散层106的材料为石墨烯、氧化铟锡、氧化锌、镍、银、铝、金、铂、钯、镁、钨等导电性和反射性能都较好的材料，电流扩散层106可以是单层结构，也可以是多层结构。
保护层107，用于覆盖和隔绝电流扩散层106，同时隔绝水氧和导热，减缓Micro-LED芯片10中各膜层性能的衰减，从而延长Micro-LED芯片的使用寿命。在一中实施例中，保护层107的材料为氧化硅、氮化硅、氮氧化硅、氮化铝中的任一种，优选导热性良好的氮化硅、氮氧化硅、氮化铝等材料。
第一电极108和第二电极109，第一电极108电连接第一子芯片的第一半导体层102，第二电极109电连接最末子芯片的第二半导体层104。正在一种实施例中，第一电极108为N型电极，第二电极109为P型电极，其材料为铟、锡、锌、镍、银、铝、金、铂、钯、镁、钨等金属或合金中的一种或几种，可以采用单层金属结构，也可以采用多层金属结构。
在每一子芯片内，N型半导体层102、有源层103和P型半导体层104构成发光PN结，当将所述发光PN结连接到外电路中，实现通过外电路给发光PN结施加电压时，N型半导体层102和P型半导体层104内分别产生电子和针对现有显示面板存在显示区内阵列基板的负偏需要避免，GOA 区内阵列基板的响应速度需要提高的问题，本申请提供一种阵列基板及其制备方法可以缓解这个问题。
在一种实施例中，如图1和图2所示，本申请提供的阵列基板包括显示区AA和GOA区，阵列基板包括：
衬底；
有源层，形成于衬底上，图案化形成有源区；
源漏极层，形成于有源层上；
其中，位于显示区内的有源区的厚度，大于位于GOA区内的有源区的厚度。
本实施例提供一种阵列基板，该基板包括显示区和GOA区，阵列基板位于AA区内的有源层的厚度，大于位于GOA区内的有源层的厚度；通过将GOA区和显示区内阵列基板的有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，从而达到减小显示区内薄膜晶体管负偏的影响；这样对GOA区和显示区内有源层的不同厚度设置，同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。
在一种实施例中，如图1所示，本申请提供的阵列基板为底栅结构，所述阵列基板包括：
衬底110，衬底110为玻璃衬底或柔性衬底。玻璃衬底由铝硅酸盐和其他成分构成，要求是低碱、平整度高、耐高温和热膨胀系数低等。柔性衬底一般包括第一柔性衬底、第二柔性衬底、以及位于第一柔性衬底和第二柔性衬底之间的无机层；其中第一柔性衬底和第二柔性衬底的材料为聚乙酰胺或聚对苯二甲酸乙二醇酯，用于保证柔性衬底的柔性；无机层的材料为氮化硅或氧化硅，用于阻隔阵列基板外的水或氧气进入薄膜晶体管。
栅极层120，形成于衬底110上，图案化形成栅极以及扫描信号线，栅极层120的材料一般为金属钼、金属铝或铝合金。
栅极绝缘层130，形成于栅极层120上，覆盖栅极层120和衬底110。栅极绝缘层一般为氧化硅/氮化硅形成的堆叠结构，氮化硅具有较高的击穿电压，可作为良好的栅极绝缘材料，氧化硅与多晶硅表面具有良好的晶界匹配和应力匹配，同时氧化硅具有良好的台阶覆盖性。
有源层140，形成于栅极绝缘层130上，图案化形成有源区，有源区通过掺杂，形成掺杂区和沟道区。在本申请实施例中，所述有源层的材料为铟镓锌氧化物或非晶硅；所述掺杂区，为高浓度磷离子注入掺杂，以形成N型薄膜晶体管的源漏极区，或为高浓度硼离子注入掺杂，以形成P型薄膜晶体管的源漏极区。
有源层包括位于GOA区内的有源区141和位于AA区内的有源区142，有源区141的厚度小于有源区142的厚度。通过将GOA区和AA区内有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；AA区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，进而达到减小AA区内薄膜晶体管负偏的影响；这样对GOA区和AA区内有源层不同的厚度设置，同时满足了显示区和GOA区域内，阵列基板不同的特征需求，提高了显示面板的质量。
刻蚀阻挡层150，形成于有源层140上，覆盖有源层140的沟道区，也可以同时覆盖沟道区和掺杂区。刻蚀阻挡层的材料为氧化硅，或氮化硅，或氧化硅和氮化硅的叠层结构。刻蚀阻挡层150用于保护有源层140的沟道区在后续源漏极层的制备过程中，免遭刻蚀液的侵蚀。
源漏极层160，形成于刻蚀阻挡层150上，图案化形成源极、漏极、数据信号线、电源信号线等，源极和漏极分别与位于有源区两侧的掺杂区相连。源漏极层160的材料为钛/铝/钛的叠层结构，或是钼/铝/钼的叠层结构。
钝化层170，形成于源漏极层160上，覆盖源漏极层160、刻蚀阻挡层150和栅极绝缘层130。钝化层170主要用于隔开源漏极层内的源极、漏极、数据信号线、电源信号线等，避免其相互之间短接，同时用于使源漏极层与位于其上的金属层绝缘。钝化层170的材料一般为氮化硅。
平坦化层180，形成于钝化层170上，覆盖钝化层170。平坦化层180的主要作用是使阵列基板平坦化，其材料一般为聚酰亚胺（PI）、聚对苯二甲酸乙二醇酯（PET）或其他有机材料。
由于位于GOA区内的有源层141的厚度，比位于AA区内的有源层222的厚度大，因此，极易造成GOA区内的阵列基板的整体厚度，比AA区内的阵列基板的整体厚度。要保证GOA区内的阵列基板的整体厚度，与AA区内的阵列基板的整体厚度相同，就需要调节其他功能膜层的厚度。
在一种是实施例中，位于AA区内的钝化层的厚度，小于位于GOA区内的钝化层的厚度。且位于AA区内的有源层和钝化层的厚度之和，与位于GOA区内的有源层和钝化层的厚度之和相等；如此弥补了由于AA区和GOA区内有源区厚度的不同，对阵列基板整体厚度的影响。
在另一种实施例中，位于AA区内的平坦化层的厚度，小于位于GOA区内的平坦化层的厚度。且位于AA区内的有源层和平坦化层的厚度之和，与位于GOA区内的有源层和平坦化层的厚度之和相等；如此弥补了由于AA区和GOA区内有源区厚度的不同，对阵列基板整体厚度的影响。
在另一种实施例中，如图2所示，本申请提供的阵列基板为顶栅结构，所述阵列基板包括：
衬底210，衬底210为玻璃衬底或柔性衬底。玻璃衬底由铝硅酸盐和其他成分构成，要求是低碱、平整度高、耐高温和热膨胀系数低等。柔性衬底一般包括第一柔性衬底、第二柔性衬底、以及位于第一柔性衬底和第二柔性衬底之间的无机层；其中第一柔性衬底和第二柔性衬底的材料为聚乙酰胺或聚对苯二甲酸乙二醇酯，用于保证柔性衬底的柔性；无机层的材料为氮化硅或氧化硅，用于阻隔阵列基板外的水或氧气进入薄膜晶体管。
有源层220，形成于衬底210上，图案化形成有源区，有源区通过掺杂，形成掺杂区和沟道区。在本申请实施例中，所述有源层的材料为铟镓锌氧化物或非晶硅；所述掺杂区，为高浓度磷离子注入掺杂，以形成N型薄膜晶体管的源漏极区，或为高浓度硼离子注入掺杂，以形成P型薄膜晶体管的源漏极区。
有源层包括位于GOA区内的有源区221和位于AA区内的有源区222，有源区221的厚度小于有源区222的厚度。通过将GOA区和AA区内有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；AA区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，进而达到减小AA区内薄膜晶体管负偏的影响；这样对GOA区和AA区内有源层不同的厚度设置，同时满足了显示区和GOA区域内，阵列基板不同的特征需求，提高了显示面板的质量。
栅极绝缘层230，形成于有源层220上，覆盖有源层220和衬底210。栅极绝缘层一般为氧化硅/氮化硅形成的堆叠结构，氮化硅具有较高的击穿电压，可作为良好的栅极绝缘材料，氧化硅与多晶硅表面具有良好的晶界匹配和应力匹配，同时氧化硅具有良好的台阶覆盖性。
栅极层240，形成于栅极绝缘层230上，图案化形成栅极以及扫描信号线，栅极层240的材料一般为金属钼、金属铝或铝合金。
层间绝缘层250，形成于栅极层240上，覆盖栅极层240和栅极绝缘层230。层间绝缘层的材料为氧化硅，或氮化硅，或氧化硅和氮化硅的叠层结构。
源漏极层260，形成于层间绝缘层250上，图案化形成源极、漏极、数据信号线、电源信号线等，源极和漏极分别与位于有源区两侧的掺杂区相连。源漏极层260的材料为钛/铝/钛的叠层结构，或是钼/铝/钼的叠层结构。
钝化层270，形成于源漏极层260上，覆盖源漏极层260和层间绝缘层250。钝化层270主要用于隔开源漏极层内的源极、漏极、数据信号线、电源信号线等，避免其相互之间短接，同时用于使源漏极层与位于其上的金属层绝缘。钝化层270的材料一般为氮化硅。
平坦化层280，形成于钝化层270上，覆盖钝化层270。平坦化层280的主要作用是使阵列基板平坦化，其材料一般为聚酰亚胺（PI）、聚对苯二甲酸乙二醇酯（PET）或其他有机材料。
由于位于GOA区内的有源层221的厚度，比位于AA区内的有源层222的厚度大，因此，极易造成GOA区内的阵列基板的整体厚度，比AA区内的阵列基板的整体厚度。要保证GOA区内的阵列基板的整体厚度，与AA区内的阵列基板的整体厚度相同，就需要调节其他功能膜层的厚度。
在一种是实施例中，位于AA区内的层间绝缘层的厚度，小于位于GOA区内的层间绝缘层的厚度。且位于AA区内的有源层和层间绝缘层的厚度之和，与位于GOA区内的有源层和层间绝缘层的厚度之和相等；如此弥补了由于AA区和GOA区内有源区厚度的不同，对阵列基板整体厚度的影响。
在另一种是实施例中，位于AA区内的钝化层的厚度，小于位于GOA区内的钝化层的厚度。且位于AA区内的有源层和钝化层的厚度之和，与位于GOA区内的有源层和钝化层的厚度之和相等；如此弥补了由于AA区和GOA区内有源区厚度的不同，对阵列基板整体厚度的影响。
在又一种实施例中，位于AA区内的平坦化层的厚度，小于位于GOA区内的平坦化层的厚度。且位于AA区内的有源层和平坦化层的厚度之和，与位于GOA区内的有源层和平坦化层的厚度之和相等；如此弥补了由于AA区和GOA区内有源区厚度的不同，对阵列基板整体厚度的影响。
在一种实施例中，如图3所示，本申请提供一种阵列基板的制备方法，其包括：
S1、提供基板；
S2、在基板上沉积一层半导体有源层；
S3、图案化处理半导体有源层，得到有源区，位于显示区内的有源区的厚度，大于位于GOA区内的有源区的厚度。
本实施例提供一种阵列基板的制备方法，该制备方法通过图案化处理，将GOA区和显示区内阵列基板的有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，从而达到减小显示区内薄膜晶体管负偏的影响；这样对GOA区和显示区内有源层的不同厚度设置，同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。
在一种实施例中，半导体有源层采用半光罩掩膜技术，图案化处理得到。
如图4所示，为半光罩掩膜技术的原理示意图，半光照掩膜版410包括不透光区域411、半透光区域412、以及全透光区域413。当光线420透过半透光掩膜版410，对基板430上的光阻440进行光照的时候，光线420透过半透光掩膜版410的光照强度如曲线450所示。
当曝光照射光线420照射到全透光区域413时，曝光照射光线不受任何阻挡，全部穿过半透光掩膜版，到达光阻，此时该对应区域内的光阻接收到的曝光照射光线的强度最强，对该对应区域内的光阻曝光显影，所述光阻几乎全部发生聚合反应被去除掉。
当曝光照射光线420照射到不透光区域411时，曝光照射光线全部被不透光区域411阻挡，曝光照射光线无法穿透半透光掩膜版，无法到达光阻，此时该对应区域内的光阻接收到的曝光照射光线的强度几乎为零，对该对应区域内的光阻曝光显影，所述光阻几乎全部得到保留。
当曝光照射光线420照射到半透光区域412时，只有部分的曝光照射光线顺利穿过所述半透光区域412到达光阻，此时该对应区域内的光阻接收到的曝光照射光线的强度得到减弱，但仍然有部分能量保留，对该对应区域内的光阻进行曝光显影，所述光阻部分发生聚合反应被去除掉，其余部分的光阻得到保留。
即采用半光罩掩膜技术对光阻进行曝光显影可以得到两种不同后度的光阻图案，进而可以实现阵列基板GOA区和显示区不同厚度有源层的制备。
下面将结合半光罩掩膜技术对本申请提供的阵列基板的制备方法进行详细说明。
S401、提供衬底。
为了防止有害物质，如碱金属离子及其他杂质对多晶硅薄膜层性能的影响，需要对提供的衬底进行清洁。
S402、在衬底上制备栅极层。
采用磁控溅射法，在衬底上溅射一层金属薄膜，该金属薄膜可以为金属钼、金属铝、或金属钼和金属铝的复合材料。
经过一道光刻工艺，制备出栅极和栅极线。在金属钼的薄膜上沉积一层光刻胶层，采用一套栅极掩膜版，对所述光刻胶层进行曝光，然后用显影液对曝光过后的光刻胶进行显影，得到栅极层图案；然后对裸露在外的栅极层金属钼进行湿法刻蚀，去除没有光刻胶保护的金属钼；再对剩余的光刻胶进行去除，保留下来的金属层即为图案化的栅极层。
S403、在栅极层上制备栅极绝缘层。
采用离子化学气相沉积法在栅极层上沉积绝缘材料，该绝缘材料可以是单层的氮化硅薄膜，可以是单层的氧化硅薄膜，也可以是氧化硅/氮化硅的叠层薄膜。栅极绝缘层需要有较高的介电常数，这样栅极氧化层电容（栅极与有源层沟道区之间的电容）更大，更容易产生沟道的反型层。
S404、在栅极绝缘层上制备有源层。
采用等离子化学气相沉积法在栅极绝缘层上沉积一层半导体有源层，所述有源层可以是氧化物有源层，也可以是非晶硅有源层。
对有源层进行图案化处理。
在有源层上涂覆一层光刻胶，并用半透光掩膜版对所述光刻胶进行曝光处理，半透光掩膜版的半透光区域对应于显示区内的有源区，半透光掩膜版的不透光区域对应于GOA区内的有源区；
对曝光后的光刻胶进行显影，去除被完全光照的光刻胶，留下具有没有被光照射和被半透光照射的光刻胶，其中，没有被光照射的光刻胶的厚度，大于被半透光照射的光刻胶的厚度；
采用第一次刻蚀工艺，对没有光刻胶保护的有源层进行刻蚀，得到保留的有源层即为被光刻胶保护的有源区；
对光刻胶进行等离子体灰化处理，将半透光照射的光刻胶去除掉，没有被光照射的光刻胶被减薄并得到保留；
采用第二次刻蚀工艺，对没有光刻胶保护的有源层进行刻蚀，控制刻蚀工艺，使所述有源区得到减薄并保留；
对剩余的光刻胶进行等离子体灰化处理，剥离掉剩余的光刻胶；
至此完成对有源层的图案化处理，得到位于GOA区内减薄的有源区，和位于显示区内没有被减薄的有源区。
对图案化的有源区进行掺杂处理，通过自对准工艺方法，采用离子浴或者离子注入的方式，对所述有源区的预定位置进行离子掺杂，所述掺杂离子可以是高浓度磷离子，以形成N型薄膜晶体管的源漏极区，也可以是高浓度硼离子，以形成P型薄膜晶体管的源漏极区。
S405、在有源层上制备刻蚀阻挡层。
采用等离子体化学气相沉积法，在有源层上沉积一层氧化硅薄膜，作为刻蚀阻挡层，所述刻蚀阻挡层覆盖有源层的有源区，还可以覆盖有源层的部分掺杂区。
S406、在刻蚀阻挡层上制备源漏极层。
在制备源漏极层前，需在阵列基板的预定位置制备过孔，用于在沉积源漏极金属的过程中，将有源层、栅极层与源漏极层通过过孔连接。所采用的方法为干法刻蚀，包括反应性离子刻蚀和感应耦合等离子体刻蚀。
在完后过孔制备后，采用磁控溅射方式，在刻蚀阻挡层上溅射一层氧化铟锡薄膜。在强磁场作用下，沉积氧化铟锡薄膜薄膜，这主要是因为氧化铟锡薄膜的溅射不适于采用高功率的方式溅射，在高功率的情况下，高能量的氩离子轰击氧化铟锡靶材，会引起氧化铟锡靶材表面氧化铟化，而氧化铟导电性不好，影响自持放电；且磁控溅射衬底的温度应低于100度，此时形成的氧化铟锡薄膜为非晶态，刻蚀速率高，不会有残留。
采用一次光刻工艺，对氧化铟锡薄膜进行图案化处理，形成源极、漏极、数据信号线、以及电源信号线。
S407、在源漏极层上制备钝化层。
采用离子化学气相沉积法在源漏极层上沉积绝缘材料以形成钝化层，该绝缘材料可以是单层的氮化硅薄膜，可以是单层的氧化硅薄膜，也可以是氧化硅/氮化硅的叠层薄膜。钝化层覆盖源漏极层和层间绝缘层。
S408、在钝化层上制备平坦化层。
在钝化层上涂覆一层有机材料以使阵列基板平坦化，该有机材料一般为聚酰亚胺、聚对苯二甲酸乙二醇酯或其他有机材料。
在另一种实施例中，半导体有源层采用灰色调掩膜技术，图案化处理得到。
如图5所示，为灰色调掩膜技术的原理示意图，灰色调掩膜技术是利用光栅效应，实现掩膜版的半光照效果，进而使得光刻胶选择性曝光显影。灰色调掩膜版510包括不透光区域511、光栅区域512、以及全透光区域513。当光线520透过半透光掩膜版510，对基板530上的光阻540进行光照的时候，光线520透过半透光掩膜版510的光照强度如曲线550所示。
当曝光照射光线520照射到全透光区域513时，曝光照射光线不受任何阻挡，全部穿过半透光掩膜版，到达光阻，此时该对应区域内的光阻接收到的曝光照射光线的强度最强，对该对应区域内的光阻曝光显影，所述光阻几乎全部发生聚合反应被去除掉。
当曝光照射光线520照射到不透光区域511时，曝光照射光线全部被不透光区域511阻挡，曝光照射光线无法穿透半透光掩膜版，无法到达光阻，此时该对应区域内的光阻接收到的曝光照射光线的强度几乎为零，对该对应区域内的光阻曝光显影，所述光阻几乎全部得到保留。
当曝光照射光线520照射到光栅区域512时，如图6所示，只有部分的曝光照射光线顺利穿过所述光栅的镂空区到达光阻，剩余部分的光线被光栅阻挡，此时该对应区域内的光阻接收到的曝光照射光线的强度得到减弱，但仍然有部分能量保留，对该对应区域内的光阻进行曝光显影，所述光阻部分发生聚合反应被去除掉，其余部分的光阻得到保留。
即采用灰色调掩膜技术对光阻进行曝光显影同样可以得到两种不同后度的光阻图案，进而可以实现阵列基板GOA区和显示区不同厚度有源层的制备。其具体制备方法可参照上述实施例中，半光照掩膜技术的制备方法，在此不再详细赘述。
同时，本申请还提供一种显示面板，包括阵列基板，所述阵列基板包括显示区和GOA区，阵列基板包括：
衬底；
有源层，形成于衬底上，图案化形成有源区；
源漏极层，形成于有源层上；
其中，位于显示区内的有源区的厚度，大于位于GOA区内的有源区的厚度。
本实施例提供一种显示面板，该显示面板包括阵列基板，阵列基板包括显示区和GOA区，阵列基板位于AA区内的有源层的厚度，大于位于GOA区内的有源层的厚度；通过将GOA区和显示区内阵列基板的有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，从而达到减小显示区内薄膜晶体管负偏的影响；这样对GOA区和显示区内有源层的不同厚度设置，同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。
在一种实施例中，阵列基板还包括衬底、栅极层、栅极绝缘层、刻蚀阻挡层、源漏极层、钝化层、以及平坦化层，有源层位于栅极绝缘层和刻蚀阻挡层之间。
在一种实施例中，阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
在一种实施例中，位于显示区内的钝化层的厚度，小于位于GOA区内的钝化层的厚度。
在一种实施例中，位于显示区内的平坦化层的厚度，小于位于GOA区内的平坦化层的厚度。
在一种实施例中，阵列基板还包括衬底、栅极绝缘层、栅极层、层间绝缘层、源漏极层、钝化层、以及平坦化层，有源层位于衬底和栅极绝缘层之间。
在一种实施例中，阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
在一种实施例中，位于显示区内的层间绝缘层的厚度，小于位于GOA区内的层间绝缘层的厚度。
在一种实施例中，位于显示区内的钝化层的厚度，小于位于GOA区内的钝化层的厚度。
在一种实施例中，位于显示区内的平坦化层的厚度，小于位于GOA区内的平坦化层的厚度。
根据上述实施例可知：
本申请实施例提供一种阵列基板及其制备方法、显示面板，该基板包括显示区和GOA区，阵列基板位于AA区内的有源层的厚度，大于位于GOA区内的有源层的厚度；通过将GOA区和显示区内阵列基板的有源层设置成不同的厚度，GOA区内的有源层的厚度设置的较小，有助于实现GOA区域内薄膜晶体管快速响应的需求；显示区内有源层的厚度设置的较大，可以缓解光子在有源层内的扩散，从而达到减小显示区内薄膜晶体管负偏的影响；这样对GOA区和显示区内有源层的不同厚度设置，同时满足了显示区和GOA区域内，阵列基板的不同特征需求，提高了显示面板的质量。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种阵列基板，其包括显示区和GOA区，所述阵列基板包括：
    衬底；
    有源层，形成于所述衬底上，图案化形成有源区；
    源漏极层，形成于所述有源层上；
    其中，位于所述显示区内的有源区的厚度，大于位于所述GOA区内的有源区的厚度。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括在所述衬底上层叠设置的栅极层、栅极绝缘层、刻蚀阻挡层、钝化层、以及平坦化层，所述有源层位于所述栅极绝缘层和所述刻蚀阻挡层之间，所述源漏极层位于所述刻蚀阻挡层和所述钝化层之间。
  3. 如权利要求2所述的阵列基板，其中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
  4. 如权利要求3所述的阵列基板，其中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
  5. 如权利要求3所述的阵列基板，其中，位于所述显示区内的平坦化层的厚度，小于位于所述GOA区内的平坦化层的厚度。
  6. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括在所述衬底上层叠设置的栅极绝缘层、栅极层、层间绝缘层、钝化层、以及平坦化层，所述有源层位于所述衬底和所述栅极绝缘层之间，所述源漏极层位于所述层间绝缘层和所述钝化层之间。
  7. 如权利要求6所述的阵列基板，其中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
  8. 如权利要求7所述的阵列基板，其中，位于所述显示区内的层间绝缘层的厚度，小于位于所述GOA区内的层间绝缘层的厚度。
  9. 如权利要求7所述的阵列基板，其中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
  10. 如权利要求7所述的阵列基板，其中，位于所述显示区内的平坦化层的厚度，小于位于所述GOA区内的平坦化层的厚度。
  11. 如权利要求1所述的阵列基板，其中，在所述GOA区内，所述阵列基板的有源层的材料为非晶硅或铟镓锌氧化合物。
  12. 一种阵列基板的制备方法，其包括：
    提供基板；
    在所述基板上沉积一层半导体有源层；
    图案化处理所述半导体有源层，得到有源区，位于显示区内的有源区的厚度，大于位于GOA区内的有源区的厚度。
  13. 如权利要求12所述的制备方法，其中，所述图案化处理所述半导体有源层的具体步骤包括：
    采用半光罩掩膜技术，图案化处理所述半导体有源层。
  14. 如权利要求12所述的制备方法，其中，所述图案化处理所述半导体有源层的具体步骤包括：
    采用灰色调掩膜技术，图案化处理所述半导体有源层。
  15. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括显示区和GOA区，位于所述显示区内的有源层的厚度，大于位于所述GOA区内的有源层的厚度。
  16. 如权利要求15所述的显示面板，其中，所述阵列基板还包括在所述衬底上层叠设置的栅极层、栅极绝缘层、刻蚀阻挡层、钝化层、以及平坦化层，所述有源层位于所述栅极绝缘层和所述刻蚀阻挡层之间，所述源漏极层位于所述刻蚀阻挡层和所述钝化层之间。
  17. 如权利要求16所述的显示面板，其中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
  18. 如权利要求17所述的显示面板，其中，位于所述显示区内的钝化层的厚度，小于位于所述GOA区内的钝化层的厚度。
  19. 如权利要求15所述的显示面板，其中，所述阵列基板还包括在所述衬底上层叠设置的栅极绝缘层、栅极层、层间绝缘层、钝化层、以及平坦化层，所述有源层位于所述衬底和所述栅极绝缘层之间，所述源漏极层位于所述层间绝缘层和所述钝化层之间。
  20. 如权利要求19所述的显示面板，其中，所述阵列基板在显示区内的厚度，和在GOA区内的厚度相同。
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