WO2021073134A1 - 半导体封装方法、半导体封装结构及封装体 - Google Patents

半导体封装方法、半导体封装结构及封装体 Download PDF

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Publication number
WO2021073134A1
WO2021073134A1 PCT/CN2020/096255 CN2020096255W WO2021073134A1 WO 2021073134 A1 WO2021073134 A1 WO 2021073134A1 CN 2020096255 W CN2020096255 W CN 2020096255W WO 2021073134 A1 WO2021073134 A1 WO 2021073134A1
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Prior art keywords
semiconductor
semiconductor die
groove
die stack
conductive
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PCT/CN2020/096255
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English (en)
French (fr)
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刘杰
应战
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长鑫存储技术有限公司
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Priority to EP20876451.4A priority Critical patent/EP4047637A4/en
Publication of WO2021073134A1 publication Critical patent/WO2021073134A1/zh
Priority to US17/372,541 priority patent/US11854941B2/en

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the invention relates to the field of semiconductor packaging, in particular to a semiconductor packaging method, a semiconductor packaging structure and a packaging body.
  • Stacked packaging technology also known as 3D or three-dimensional packaging technology
  • 3D or three-dimensional packaging technology is one of the current mainstream multi-chip packaging technologies. It can assemble at least two semiconductor chips (Die, also known as a die, which is a piece cut from a wafer). Blocks with complete functions are superimposed in the vertical direction, and are commonly used to manufacture electronic components such as memory chips, logic chips, and processor chips.
  • Die also known as a die, which is a piece cut from a wafer
  • Blocks with complete functions are superimposed in the vertical direction, and are commonly used to manufacture electronic components such as memory chips, logic chips, and processor chips.
  • With the development of the electronics industry there is an increasing need for high capacity, high functionality, high speed and small size of electronic components. In order to meet this demand, it is necessary to incorporate more chips in a single package, which will cause the package height of electronic components to become higher. , The reliability becomes lower, which affects the performance of the package structure.
  • the technical problem to be solved by the present invention is to provide a semiconductor packaging method, a semiconductor packaging structure and a packaging body, which can have the characteristics of low packaging height, high reliability and low warpage.
  • the present invention provides a semiconductor packaging method, which includes the following steps: providing a substrate wafer, the substrate wafer having a first surface and a second surface opposed to each other, on the first surface Having a plurality of grooves, a plurality of conductive pillars at the bottom of the groove, the conductive pillars penetrating the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; The stack is placed in the groove, the upper surface of the semiconductor die stack is lower than or flush with the upper edge of the groove, and the bottom of the semiconductor die stack is electrically connected to the conductive pillar ; Cover the cover wafer on the first surface of the substrate wafer to seal the groove to form a semiconductor packaging structure, the substrate wafer, the semiconductor die stack and the cover The gaps between the wafers are not filled with filler.
  • conductive blocks there are a plurality of conductive blocks on the second surface of the substrate wafer, and the conductive blocks are electrically connected to the conductive pillars.
  • the method of forming a groove on the substrate wafer includes the following steps: flattening the first surface of the substrate wafer; removing part of the substrate wafer from the first surface, Until the conductive pillar is exposed, the groove is formed.
  • the substrate wafer has a dicing lane, and the dicing lane is used as an alignment mark for forming the groove.
  • the semiconductor die stack is formed by stacking a plurality of semiconductor dies, and the semiconductor dies are electrically connected to each other, and are electrically connected to the conductive pillars through the bottom of the semiconductor die stack.
  • the semiconductor dies are electrically connected through conductive pillars penetrating each of the semiconductor dies and conductive blocks between adjacent semiconductor dies.
  • the bottom of the semiconductor die stack is electrically connected to the conductive pillar penetrating the bottom of the groove through a conductive block.
  • the surface of the cover wafer facing the substrate wafer has a plurality of conductive pillars, and the conductive pillars are electrically connected to the upper surface of the semiconductor die stack.
  • the method further includes a cutting step: cutting the semiconductor package structure along the gap between the grooves to form a plurality of independent packages.
  • the present invention also provides a semiconductor package structure, which includes: a substrate wafer having a first surface and a second surface opposed to each other, a plurality of grooves on the first surface, and A plurality of conductive pillars are provided at the bottom of the groove, and the conductive pillars penetrate through the bottom of the groove to the second surface; a plurality of stacked semiconductor dies are placed in the groove, and the semiconductor dies are stacked The upper surface of the body is lower than or flush with the upper edge of the groove, and the bottom of the semiconductor die stack is electrically connected to the conductive pillar; a cover wafer covers the first wafer of the substrate A surface to seal the groove, and the gap between the substrate wafer, the semiconductor die stack and the cover wafer is not filled with filler.
  • conductive blocks there are a plurality of conductive blocks on the second surface of the substrate wafer, and the conductive blocks are electrically connected to the conductive pillars.
  • the semiconductor die stack is formed by stacking a plurality of semiconductor dies, and the semiconductor dies are electrically connected to each other, and are electrically connected to the conductive pillars through the bottom of the semiconductor die stack.
  • the semiconductor dies are electrically connected through conductive pillars penetrating each of the semiconductor dies and conductive blocks between adjacent semiconductor dies.
  • the bottom of the semiconductor die stack is electrically connected to the conductive pillar penetrating the bottom of the groove through a conductive block.
  • the surface of the cover wafer facing the substrate wafer has a plurality of conductive pillars, and the conductive pillars are electrically connected to the upper surface of the semiconductor die stack.
  • the present invention also provides a package, which includes: a substrate having a first surface and a second surface opposed to each other, at least one groove on the first surface, and a bottom of the groove A plurality of conductive pillars, the conductive pillars penetrate through the bottom of the groove to the second surface; at least one semiconductor die stack is placed in the groove, and the upper surface of the semiconductor die stack is lower than Or flush with the upper edge of the groove, the bottom of the semiconductor die stack is electrically connected to the conductive column; a cover plate covering the first surface of the substrate to seal the groove, The gap between the substrate, the semiconductor die stack, and the cover plate is not filled with filler.
  • the advantage of the present invention is that grooves are formed on the substrate wafer to accommodate the semiconductor die stack, and sealed by the cover wafer, which can greatly reduce the cost of the semiconductor packaging structure while packaging the same number of semiconductor die. Height, realize ultra-thin package.
  • the gaps between the substrate wafer, the semiconductor die stack, and the cover wafer are not filled with fillers, and only the cover wafer is used to seal the groove, thereby sealing the Semiconductor die stack, which can avoid the mismatch of the expansion coefficient of the filler and the substrate wafer, the semiconductor die stack, and the cover wafer from causing deformation of the semiconductor package structure, which in turn causes reliability problems and warpage problems
  • the semiconductor packaging structure formed by the semiconductor packaging method of the present invention has good reliability and low warpage.
  • FIG. 1 is a schematic diagram of the steps of a specific embodiment of the semiconductor packaging method of the present invention.
  • FIGS. 2A to 2G are schematic flowcharts of a specific embodiment of the semiconductor packaging method of the present invention.
  • FIG. 3 is a schematic structural diagram of a specific embodiment of the semiconductor package structure of the present invention.
  • FIG. 4 is a schematic structural diagram of a specific embodiment of the package of the present invention.
  • FIG. 1 is a schematic diagram of the steps of a specific embodiment of the semiconductor packaging method of the present invention.
  • the semiconductor packaging method includes the following steps: step S10, a substrate wafer is provided, the substrate wafer has a first surface and a second surface opposed to each other, and the first surface has a plurality of The groove has a plurality of conductive pillars at the bottom of the groove, and the conductive pillars penetrate the bottom of the groove to the second surface; step S11, provide a plurality of semiconductor die stacks; step S12, add the The semiconductor die stack is placed in the groove, the upper surface of the semiconductor die stack is lower than or flush with the upper edge of the groove, and the bottom of the semiconductor die stack is connected to the conductive The column is electrically connected; step S13, cover the cover wafer on the first surface of the substrate wafer to seal the groove to form a semiconductor package structure, the substrate wafer and the semiconductor die are stacked The gap between the body and the cover wafer is not filled with filler; in step S14, the semiconductor
  • FIGS. 2A to 2G are schematic flowcharts of a specific embodiment of the semiconductor packaging method of the present invention.
  • a substrate wafer 200 is provided, and the substrate wafer 200 has a first surface 200A and a second surface 200B disposed opposite to each other. There are a plurality of grooves 201 on the first surface 200A, and a plurality of conductive pillars 202 at the bottom of the groove 201, and the conductive pillars 202 penetrate the bottom of the groove 201 to the second surface 200B.
  • the substrate wafer 200 has a first surface 200A and a second surface 200B opposite to each other.
  • the first surface 200A is the back surface of the substrate wafer 200
  • the second surface 200B is the front surface of the substrate wafer 200, that is, on the second surface 200B
  • the circle 200 has a functional layer 200C.
  • the conductive pillar 202 extends from the second surface 200B to the inside of the substrate wafer 200, and the surface of the conductive pillar 202 is exposed to the second surface 200B.
  • the conductive pillar 202 can not only play a role of conducting electricity, but also play a role of conducting heat.
  • the first surface 200A of the substrate wafer 200 is planarized to facilitate subsequent processes. Further, the first surface 200A of the substrate wafer 200 can be planarized by a chemical mechanical polishing method. In this step, the substrate wafer 200 is thinned. It should be noted that after this step is performed, the distance H from the first surface 200A of the substrate wafer 200 to the functional layer 200C of the second surface 200B is greater than or equal to the height of the semiconductor die stack 210 , In order to provide enough operating space for the follow-up process.
  • a part of the substrate wafer 200 is removed from the first surface 200A until the conductive pillar 202 is exposed to form the groove 201.
  • a photolithography and etching process can be used to remove part of the substrate wafer 200, and the etching is stopped when the conductive pillar 202 is exposed at the bottom of the groove 201.
  • the etching conditions can be adjusted so that the etching rate of the edge of the groove 201 is lower than the etching rate of the middle of the groove 201, so that the bottom corners of the groove 201 are arc-shaped, which can enhance the concave The stability of the side wall of the groove 201.
  • the substrate wafer 200 has a dicing lane 203.
  • the dicing lane 203 passes through the gap between two adjacent grooves 201, and then the groove 201 is formed.
  • the cutting track 203 can be used as the alignment mark for forming the groove 201, thereby improving the accuracy of forming the groove 201, and there is no need to make additional alignment marks, which saves process steps and improves production efficiency. .
  • the foregoing is a specific embodiment of forming the groove 201 on the first surface 200A of the substrate wafer 200. In other specific embodiments of the present invention, other methods may also be used to form the first surface 200A of the substrate wafer 200.
  • the surface 200A forms a groove 201.
  • the width of the cutting path 203 is the same as the distance between the two grooves 201.
  • the groove 201 may occupy part of the space of the cutting path 203, so that two adjacent The distance between the grooves 201 is smaller than the width of the scribe line 203, which facilitates the subsequent placement of the semiconductor die stack 210 in the groove 201; in addition, it can also avoid the side surface of the semiconductor die stack 210 and the recess.
  • the sidewalls of the trench 201 are in contact with each other to avoid affecting the performance of the semiconductor die stack 210.
  • the conductive blocks 204 are electrically connected to the conductive pillars 202 to electrically connect the conductive pillars 202. Connect to external devices, such as printed circuit boards.
  • the conductive block 204 may be formed on the second surface 200B of the substrate wafer 200 before the groove 201 is formed.
  • a plurality of semiconductor die stacks 210 are provided.
  • the number of the semiconductor die stack 210 may be the same as the number of the grooves 201, or the number of the semiconductor die stack 210 may be more than the number of the grooves 201. Specifically, if the number of the semiconductor die stack 210 is the same as the number of the grooves 201, in the subsequent process, one semiconductor die stack 210 is placed in one groove 201; The number of die stacks 210 is more than the number of the grooves 201, so two or more semiconductor die stacks 210 can be placed in one groove 201 in parallel.
  • the semiconductor die stack 210 is formed by stacking a plurality of semiconductor die 210A.
  • three semiconductor die 210A are schematically shown.
  • Three semiconductor die 210A are sequentially stacked to form the semiconductor die stack 210.
  • the semiconductor die 210A are electrically connected to each other, so that the electrical signal of the semiconductor die 210A can be transmitted to an external structure.
  • the semiconductor dies 210A are electrically connected to each other through a conductive pillar 211 that penetrates each semiconductor dies and a conductive block 212 between adjacent semiconductor dies.
  • the method of forming conductive pillars on the semiconductor die 210A includes but is not limited to a through silicon via (TSV) process known in the art.
  • TSV through silicon via
  • the surface of the conductive pillar is exposed on the bottom of the semiconductor die stack 210, and the surface of the conductive pillar is also exposed on the top of the semiconductor die stack 210.
  • the semiconductor die stack 210 is placed in the groove 201.
  • one semiconductor die stack 210 can be placed in one of the grooves 201, or multiple semiconductor die stacks 210 can be placed.
  • a semiconductor die stack 210 is placed in a groove 201.
  • the bottom of the semiconductor die stack 210 is electrically connected to the conductive pillar 202 passing through the bottom of the groove 201.
  • the conductive pillars 211 exposed at the bottom of the semiconductor die stack 210 are electrically connected to the conductive pillars 202 exposed at the bottom of the groove 201.
  • the two can be electrically connected through the conductive block 213.
  • the upper surface of the semiconductor die stack 210 is lower than or flush with the upper edge of the groove 201 to facilitate subsequent processes.
  • the upper surface of the semiconductor die stack 210 is lower than the upper edge of the groove 201.
  • the cover wafer 220 is covered on the first surface 200A of the substrate wafer 200 to seal the groove 201 to form a semiconductor package structure.
  • the internal space of the groove 201 is a closed space.
  • the cover wafer 220 and the substrate wafer 200 can be combined by a bonding process, so that the groove 201 is sealed.
  • the semiconductor packaging method of the present invention forms a groove on the substrate wafer to accommodate the semiconductor die stack, and seals the semiconductor die stack by the cover wafer, which can greatly reduce the height of the semiconductor packaging structure while packaging the same number of semiconductor die , Achieve ultra-thin packaging.
  • the gap between the substrate wafer 200, the semiconductor die stack 210, and the cover wafer 220 is not filled with fillers, and only the cover wafer 220 is used to seal the groove 201 , And further seal the semiconductor die stack 210, which can avoid the mismatch of the expansion coefficients of the filler and the substrate wafer, the semiconductor die stack, and the cover wafer to cause deformation of the semiconductor package structure, thereby causing reliability
  • the problem is that the semiconductor packaging structure formed by the semiconductor packaging method of the present invention has good reliability.
  • the surface of the cover wafer 220 facing the substrate wafer 200 has a plurality of conductive pillars 221, and the conductive pillars 221 are electrically connected to the upper surface of the semiconductor die stack 210, that is, the The conductive pillars 221 on the surface of the cover wafer 220 are electrically connected to the conductive pillars 211 exposed on the upper surface of the semiconductor die stack 210.
  • the cover wafer 220 can provide heat conduction to the semiconductor die stack 210 through the conductive pillars 221 and further fix the position of the semiconductor die stack 210.
  • other wafers may also be stacked on the cover wafer 220, and the conductive pillars 221 may function as electrical connections.
  • a cutting step is further included.
  • the semiconductor package structure is cut along the gap between the grooves 201 to form a plurality of independent packages.
  • the cutting method includes, but is not limited to, mechanical cutting, laser cutting, and the like.
  • FIG. 3 is a schematic structural diagram of a specific embodiment of the semiconductor package structure of the present invention. Please refer to FIG. 3, the semiconductor package structure includes a substrate wafer 300, a plurality of semiconductor die stacks 310 and a cover wafer 320.
  • the substrate wafer 300 has a first surface 300A and a second surface 300B opposite to each other, a plurality of grooves 301 are provided on the first surface 300A, and a plurality of conductive pillars 302 are provided at the bottom of the grooves 301, so The conductive pillar 302 penetrates the bottom of the groove 301 to the second surface 300B.
  • a plurality of conductive blocks 304 are provided on the second surface 300B of the substrate wafer 300, and the conductive blocks 304 are electrically connected to the conductive pillars 302.
  • the semiconductor die stack 310 is placed in the groove 301, and the upper surface of the semiconductor die stack 310 is lower than or flush with the upper edge of the groove 301. In this embodiment, The upper surface of the semiconductor die stack 310 is lower than the upper edge of the groove 301.
  • the bottom of the semiconductor die stack 310 is electrically connected to the conductive pillar 302.
  • the semiconductor die stack is formed by stacking a plurality of semiconductor dies 310A at 310, and conductive pillars 311 passing through each semiconductor die 310A and adjacent semiconductor dies 310A can pass between the semiconductor dies 310A.
  • the conductive blocks 312 therebetween are electrically connected, and are electrically connected to the conductive pillars 302 through the bottom of the semiconductor die stack 310. Wherein, the bottom of the semiconductor die stack 310 and the conductive pillar 302 can be electrically connected by a conductive block 313.
  • the cover wafer 320 covers the first surface 300A of the substrate wafer 300 to seal the groove 301. If the gap between the substrate wafer 300, the semiconductor die stack 310, and the cover wafer 320 is not filled with filler, then. Further, the surface of the cover wafer 320 facing the substrate wafer 300 has a plurality of conductive pillars 321, and the conductive pillars 321 are electrically connected to the upper surface of the semiconductor die stack 310. Specifically, the conductive pillars 321 are electrically connected to the conductive pillars 311 exposed on the upper surface of the semiconductor die stack 310.
  • the cover wafer 300 can provide heat conduction to the semiconductor die stack 310 through the conductive pillars 321 and further fix the position of the semiconductor die stack 310. In addition, in semiconductor packaging, other wafers can also be stacked on the cover wafer 300, and the conductive pillars 321 can function as electrical connections.
  • the semiconductor packaging structure of the present invention forms a groove on the substrate wafer to accommodate the semiconductor bare chip stack, and seals the semiconductor die stack by the cover wafer, thereby greatly reducing the height of the semiconductor packaging structure and realizing ultra-thin packaging.
  • the gaps between the substrate wafer, the semiconductor die stack, and the cover wafer are not filled with fillers, and only the cover wafer is used to seal the groove, thereby sealing the
  • the semiconductor die stack can avoid the mismatch of the expansion coefficients of the filler and the substrate wafer, the semiconductor die stack, and the cover wafer from causing the reliability problem of the semiconductor package structure.
  • the semiconductor package structure of the present invention has good reliability Sex.
  • FIG. 4 is a schematic structural diagram of a specific embodiment of the package of the present invention. Please refer to FIG. 4, the package body is formed by cutting the above-mentioned semiconductor package structure along the cutting line between the grooves.
  • the package includes a substrate 400, at least one semiconductor die stack 410, and a cover 420.
  • the substrate 400 has a first surface 400A and a second surface 400B disposed opposite to each other.
  • the first surface 400A has at least one groove 401, and the bottom of the groove 401 has a plurality of conductive pillars 402.
  • the pillar 402 penetrates the bottom of the groove 401 to the second surface 400B.
  • the semiconductor die stack 410 is placed in the groove 401, and the upper surface of the semiconductor die stack 410 is lower than or flush with the upper edge of the groove 401, and the semiconductor die stack The bottom of the 410 is electrically connected to the conductive pillar 402.
  • the cover plate 420 covers the first surface 400A of the substrate 400 to seal the groove 401, the gap between the substrate 400, the semiconductor die stack 410, and the cover plate 420 Not filled with filler.
  • the packaging body of the invention has a small packaging thickness, meets the requirement of ultra-thin packaging, does not hesitate to deform the substrate due to different thermal expansion coefficients, and has high reliability.

Abstract

一种半导体封装方法、半导体封装结构及封装体，所述方法包括如下步骤：提供衬底晶圆（200），衬底晶圆（200）具有相对设置的第一表面（200A）及第二表面（200B），在第一表面（200A）具有多个凹槽（201），在凹槽（201）底部具有多个导电柱（202），导电柱（202）贯穿衬底晶圆（200）（S10）；提供多个半导体裸片堆叠体（210）（S11）；将半导体裸片堆叠体（210）置于凹槽（201）中，半导体裸片堆叠体（210）的上表面低于或者平齐于凹槽（201）的上边缘，半导体裸片堆叠体（210）的底部与导电柱（202）电连接（S12）；将盖板晶圆（220）覆盖在衬底晶圆（200）的第一表面（200A），以密封凹槽（201），形成半导体封装结构，衬底晶圆（200）、半导体裸片堆叠体（210）及盖板晶圆（220）之间的间隙未被填充物填充（S13）。形成的半导体结构具有封装高度低、可靠性高及翘曲度低的特点。

Description

半导体封装方法、半导体封装结构及封装体
相关申请引用说明
本申请要求于2019年10月16日递交的中国专利申请号201910982066.8，申请名为“半导体封装方法、半导体封装结构及封装体”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体封装领域，尤其涉及一种半导体封装方法、半导体封装结构及封装体。
背景技术
堆叠式封装技术，也称为3D或三维封装技术，是目前主流的多芯片封装技术之一，能够将至少两个半导体晶片(Die，也称为裸片，即从晶圆上切割出来的一块具有完整功能的块)在垂直方向叠加起来，常用来制造存储器芯片、逻辑芯片、处理器芯片等电子元件。随着电子产业的发展，日益需要电子元件的高容量、高功能、高速和小尺寸，为了满足该需求，需要在单个封装中并入更多晶片，而这会造成电子元件的封装高度变高，可靠性变低，影响封装体结构的性能。
因此，如何降低封装体的封装高度，提高封装体的可靠性成为目前亟需解决的技术问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体封装方法、半导体封装结构及封装体，其能够具有封装高度低、可靠性高及翘曲度低的特点。
为了解决上述问题，本发明提供了一种半导体封装方法，其包括如下步骤：提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第 一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；提供多个半导体裸片堆叠体；将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；将盖板晶圆覆盖在所述衬底晶圆的第一表面，以密封所述凹槽，形成半导体封装结构，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充。
进一步，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
进一步，在所述衬底晶圆上形成凹槽的方法包括如下步骤：对所述衬底晶圆的第一表面进行平坦化处理；自所述第一表面去除部分所述衬底晶圆，至暴露出所述导电柱，形成所述凹槽。
进一步，所述衬底晶圆具有切割道，以所述切割道作为形成所述凹槽的对准标记。
进一步，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
进一步，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
进一步，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
进一步，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱与所述半导体裸片堆叠体的上表面电连接。
进一步，在密封所述凹槽的步骤后，还包括切割步骤：沿凹槽之间的间隙 切割所述半导体封装结构，形成多个彼此独立的封装体。
本发明还提供一种半导体封装结构，其包括：衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；多个半导体裸片堆叠体，放置在所述凹槽内，且所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；盖板晶圆，覆盖在所述衬底晶圆的第一表面，以密封所述凹槽，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充。
进一步，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
进一步，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
进一步，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
进一步，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
进一步，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱与所述半导体裸片堆叠体的上表面电连接。
本发明还提供一种封装体，其包括：衬底，所述衬底具有相对设置的第一表面及第二表面，在所述第一表面具有至少一凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；至少一半导体裸片堆叠体，放置在所述凹槽内，所述半导体裸片堆叠体的上表面低于或者平齐于所 述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；盖板，覆盖在所述衬底的第一表面，以密封所述凹槽，所述衬底、所述半导体裸片堆叠体及所述盖板之间的间隙未被填充物填充。
本发明的优点在于，在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过盖板晶圆进行密封，能够在封装相同数量的半导体裸片的同时，大大降低半导体封装结构的高度，实现超薄封装。另外，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充，仅是采用盖板晶圆密封所述凹槽，进而密封所述半导体裸片堆叠体，其能够避免填充物与衬底晶圆、半导体裸片堆叠体及盖板晶圆的膨胀系数不匹配而引起半导体封装结构变形，进而引起的可靠性问题及翘曲度问题，本发明半导体封装方法形成的半导体封装结构具有良好的可靠性及较低的翘曲度。
附图说明
图1是本发明半导体封装方法的一具体实施方式的步骤示意图；
图2A～图2G是本发明半导体封装方法的一具体实施方式的流程示意图；
图3是本发明半导体封装结构的一具体实施方式的结构示意图。
图4是本发明封装体的一具体实施方式的结构示意图。
具体实施方式
下面结合附图对本发明提供的半导体封装方法、半导体封装结构及封装体的具体实施方式做详细说明。
图1是本发明半导体封装方法的一具体实施方式的步骤示意图。请参阅图1，所述半导体封装方法包括如下步骤：步骤S10，提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表 面；步骤S11，提供多个半导体裸片堆叠体；步骤S12，将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；步骤S13，将盖板晶圆覆盖在所述衬底晶圆的第一表面，以密封所述凹槽，形成半导体封装结构，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充；步骤S14，沿凹槽之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。
图2A～图2G是本发明半导体封装方法的一具体实施方式的流程示意图。
请参阅步骤S10及图2C，提供衬底晶圆200，所述衬底晶圆200具有相对设置的第一表面200A及第二表面200B。在所述第一表面200A具有多个凹槽201，在所述凹槽201底部具有多个导电柱202，所述导电柱202贯穿所述凹槽201底部至所述第二表面200B。
下面举例说明形成所述凹槽201的一具体实施方式。
请参阅图2A，所述衬底晶圆200具有相对设置的第一表面200A及第二表面200B。其中，所述第一表面200A为所述衬底晶圆200的背面，所述第二表面200B为所述衬底晶圆200的正面，即在所述第二表面200B，所述衬底晶圆200具有功能层200C。所述导电柱202自所述第二表面200B向所述衬底晶圆200内部延伸，且所述导电柱202的表面暴露于所述第二表面200B。所述导电柱202不仅可起到导电的作用，还可起到导热的作用。
请参阅图2B，对所述衬底晶圆200的第一表面200A进行平坦化处理，以便于后续工艺的进行。进一步，可采用化学机械研磨的方法对所述衬底晶圆200的第一表面200A进行平坦化处理。在该步骤中，所述衬底晶圆200被减薄。需要说明的是，在该步骤执行完毕后，所述衬底晶圆200的第一表面200A至 所述第二表面200B的功能层200C的距离H要大于或者等于半导体裸片堆叠体210的高度，以为后续工艺提供足够的操作空间。
请参阅图2C，自所述第一表面200A去除部分所述衬底晶圆200，至暴露出所述导电柱202，形成所述凹槽201。在该步骤中，可采用光刻与刻蚀工艺去除部分所述衬底晶圆200，当在所述凹槽201的底部暴露出所述导电柱202时停止刻蚀。进一步，在临近停止刻蚀时，可以通过调整刻蚀条件，使得凹槽201边缘刻蚀速率小于凹槽201中部刻蚀速率，从而使凹槽201底部边角处呈圆弧状，可以增强凹槽201侧壁的稳定性。
进一步，在该步骤中，所述衬底晶圆200具有切割道203，如图2C所示，切割道203经过相邻的两个凹槽201之间的间隙，则在形成所述凹槽201时，可将所述切割道203作为形成所述凹槽201的对准标记，从而提高形成所述凹槽201的精确度，且不需要额外制作对准标记，节省了工艺步骤，提高生产效率。
上述为在所述衬底晶圆200的第一表面200A形成凹槽201的一具体实施方式，在本发明其他具体实施方式中，也可采用其他方法在所述衬底晶圆200的第一表面200A形成凹槽201。
在本具体实施方式中，所述切割道203的宽度与两凹槽201之间的距离相同，在本发明其他具体实施方式中，凹槽201可占用部分切割道203的空间，使得两相邻凹槽201之间的距离小于切割道203的宽度，进而便于后续半导体裸片堆叠体210置于所述凹槽201内；另外还能够避免所述半导体裸片堆叠体210的侧面与所述凹槽201的侧壁接触，避免影响所述半导体裸片堆叠体210的性能。
进一步，请继续参阅图2A，在所述衬底晶圆200的第二表面200B具有多 个导电块204，所述导电块204与所述导电柱202电连接，以将所述导电柱202电连接至外部器件，例如，印刷电路板。其中，所述导电块204可在形成所述凹槽201之前形成在所述衬底晶圆200的第二表面200B。
请参阅步骤S11及图2D，提供多个半导体裸片堆叠体210。所述半导体裸片堆叠体210的数量可与所述凹槽201的数量相同，或者所述半导体裸片堆叠体210的数量多于所述凹槽201的数量。具体地说，若所述半导体裸片堆叠体210的数量与所述凹槽201的数量相同，则在后续工艺中，在一个凹槽201内放置一个半导体裸片堆叠体210；若所述半导体裸片堆叠体210的数量多于所述凹槽201的数量，则在一个凹槽201内可并行放置两个及两个以上半导体裸片堆叠体210。
所述半导体裸片堆叠体210由多个半导体裸片210A堆叠形成，在本具体实施方式中，示意性地绘示三个半导体裸片210A。三个半导体裸片210A依次叠放，形成所述半导体裸片堆叠体210。在半导体裸片堆叠体210中，所述半导体裸片210A之间电连接，以使得所述半导体裸片210A的电信号能够被传递至外部结构。在本具体实施方式中，所述半导体裸片210A之间通过贯穿各所述半导体裸片的导电柱211及相邻所述半导体裸片间的导电块212电连接。其中，在所述半导体裸片210A上形成导电柱的方法包括但不限于本领域公知的硅通孔(TSV)工艺。
其中，在该步骤实施完毕后，所述半导体裸片堆叠体210的底部暴露有导电柱的表面，所述半导体裸片堆叠体210的顶部也暴露有导电柱的表面。
请参阅步骤S12及图2E，将所述半导体裸片堆叠体210置于所述凹槽201中。在该步骤中，在一个所述凹槽201内可放置一个半导体裸片堆叠体210，也可放置多个半导体裸片堆叠体210。在本具体实施方式中，在一个凹槽201 内放置一个半导体裸片堆叠体210。
所述半导体裸片堆叠体210的底部与贯穿所述凹槽201底部的所述导电柱202电连接。也就是说，在所述半导体裸片堆叠体210的底部暴露的导电柱211与所述凹槽201底部暴露的导电柱202电连接。具体地说，两者可通过导电块213电连接。
所述半导体裸片堆叠体210的上表面低于或者平齐于所述凹槽201的上边缘，以便于后续工艺的进行。在本具体实施方式中，所述半导体裸片堆叠体210的上表面低于所述凹槽201的上边缘。
请参阅步骤S13及图2F，将盖板晶圆220覆盖在所述衬底晶圆200的第一表面200A，以密封所述凹槽201，形成半导体封装结构。该步骤执行完毕，所述凹槽201的内部空间为密闭空间。其中，所述盖板晶圆220与所述衬底晶圆200可通过键合工艺结合，以使所述凹槽201被密封。
本发明半导体封装方法在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过盖板晶圆进行密封，能够在封装相同数量的半导体裸片的同时，大大降低半导体封装结构的高度，实现超薄封装。另外，所述衬底晶圆200、所述半导体裸片堆叠体210及所述盖板晶圆220之间的间隙未被填充物填充，仅是采用盖板晶圆220密封所述凹槽201，进而密封所述半导体裸片堆叠体210，其能够避免填充物与衬底晶圆、半导体裸片堆叠体及盖板晶圆的膨胀系数不匹配而引起半导体封装结构变形，进而引起的可靠性问题，本发明半导体封装方法形成的半导体封装结构具有良好的可靠性。
进一步，所述盖板晶圆220朝向所述衬底晶圆200的表面具有多个导电柱221，所述导电柱221与所述半导体裸片堆叠体210的上表面电连接，即，所述盖板晶圆220表面的所述导电柱221与所述半导体裸片堆叠体210的上表面 暴露的导电柱211电连接。所述盖板晶圆220可通过所述导电柱221向所述半导体裸片堆叠体210提供热传导，并进一步固定所述半导体裸片堆叠体210的位置。另外，在半导体封装中，还可以在所述盖板晶圆220上堆叠其他晶圆，所述导电柱221可起到电连接的作用。
可选地，在本具体实施方式中，在步骤S13之后，还包括一切割步骤。请参阅步骤S14及图2G，沿凹槽201之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。具体地说，沿凹槽201之间的切割道203切割，以形成多个彼此独立的封装体。所述切割方法包括但不限于机械切割、激光切割等。
本发明还提供一种采用上述半导体封装方法形成的半导体封装结构。图3是本发明半导体封装结构的一具体实施方式的结构示意图。请参阅图3，所述半导体封装结构包括衬底晶圆300、多个半导体裸片堆叠体310及盖板晶圆320。
所述衬底晶圆300具有相对设置的第一表面300A及第二表面300B，在所述第一表面300A具有多个凹槽301，在所述凹槽301底部具有多个导电柱302，所述导电柱302贯穿所述凹槽301底部至所述第二表面300B。在所述衬底晶圆300的第二表面300B具有多个导电块304，所述导电块304与所述导电柱302电连接。
所述半导体裸片堆叠体310放置在所述凹槽301内，且所述半导体裸片堆叠体310的上表面低于或者平齐于所述凹槽301的上边缘，在本具体实施方式中，所述半导体裸片堆叠体310的上表面低于所述凹槽301的上边缘。所述半导体裸片堆叠体310的底部与所述导电柱302电连接。所述半导体裸片堆叠体由310由多个半导体裸片310A堆叠形成，所述半导体裸片310A之间可通过 贯穿各所述半导体裸片310A的导电柱311及相邻所述半导体裸片310A间的导电块312电连接，并通过所述半导体裸片堆叠体310的底部与所述导电柱302电连接。其中，所述半导体裸片堆叠体310的底部与所述导电柱302之间可通过导电块313电连接。
所述盖板晶圆320覆盖在所述衬底晶圆300的第一表面300A，以密封所述凹槽301。所述衬底晶圆300、所述半导体裸片堆叠体310及所述盖板晶圆320之间的间隙未被填充物填充，则。进一步，所述盖板晶圆320朝向所述衬底晶圆300的表面具有多个导电柱321，所述导电柱321与所述半导体裸片堆叠体310的上表面电连接。具体地说，所述导电柱321与所述半导体裸片堆叠体310的上表面暴露的导电柱311电连接。所述盖板晶圆300可通过所述导电柱321向所述半导体裸片堆叠体310提供热传导，并进一步固定所述半导体裸片堆叠体310的位置。另外，在半导体封装中，还可以在所述盖板晶圆300上堆叠其他晶圆，所述导电柱321可起到电连接的作用。
本发明半导体封装结构在衬底晶圆上形成凹槽来容纳半导体裸片堆叠体，并通过盖板晶圆进行密封，大大降低半导体封装结构的高度，实现超薄封装。另外，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充，仅是采用盖板晶圆密封所述凹槽，进而密封所述半导体裸片堆叠体，其能够避免填充物与衬底晶圆、半导体裸片堆叠体及盖板晶圆的膨胀系数不匹配而引起半导体封装结构可靠性问题，本发明半导体封装结构具有良好的可靠性。
本发明还提供一种封装体。图4是本发明封装体的一具体实施方式的结构示意图。请参阅图4，所述封装体为上述的半导体封装结构沿凹槽之间的切割道切割而成。所述封装体包括衬底400、至少一半导体裸片堆叠体410及盖板 420。
所述衬底400具有相对设置的第一表面400A及第二表面400B，在所述第一表面400A具有至少一凹槽401，在所述凹槽401底部具有多个导电柱402，所述导电柱402贯穿所述凹槽401底部至所述第二表面400B。
所述半导体裸片堆叠体410放置在所述凹槽401内，所述半导体裸片堆叠体410的上表面低于或者平齐于所述凹槽401的上边缘，所述半导体裸片堆叠体410的底部与所述导电柱402电连接。
所述盖板420覆盖在所述衬底400的第一表面400A，以密封所述凹槽401，所述衬底400、所述半导体裸片堆叠体410及所述盖板420之间的间隙未被填充物填充。本发明封装体封装厚度小，满足封装体超薄的需求，且不会犹豫热膨胀系数不同而导致衬底变形，可靠性高。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种半导体封装方法，其特征在于，包括如下步骤：
    提供衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
    提供多个半导体裸片堆叠体；
    将所述半导体裸片堆叠体置于所述凹槽中，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
    将盖板晶圆覆盖在所述衬底晶圆的第一表面，以密封所述凹槽，形成半导体封装结构，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充。
  2. 根据权利要求1所述的半导体封装方法，其特征在于，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
  3. 根据权利要求1所述的半导体封装方法，其特征在于，在所述衬底晶圆上形成凹槽的方法包括如下步骤：
    对所述衬底晶圆的第一表面进行平坦化处理；
    自所述第一表面去除部分所述衬底晶圆，至暴露出所述导电柱，形成所述凹槽。
  4. 根据权利要求3所述的半导体封装方法，其特征在于，所述衬底晶圆具有切割道，以所述切割道作为形成所述凹槽的对准标记。
  5. 根据权利要求1所述的半导体封装方法，其特征在于，所述半导体裸片堆叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
  6. 根据权利要求5所述的半导体封装方法，其特征在于，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
  7. 根据权利要求1所述的半导体封装方法，其特征在于，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
  8. 根据权利要求1所述的半导体封装方法，其特征在于，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱与所述半导体裸片堆叠体的上表面电连接。
  9. 根据权利要求1所述的半导体封装方法，其特征在于，在密封所述凹槽的步骤后，还包括切割步骤：沿凹槽之间的间隙切割所述半导体封装结构，形成多个彼此独立的封装体。
  10. 一种半导体封装结构，其特征在于，包括：
    衬底晶圆，所述衬底晶圆具有相对设置的第一表面及第二表面，在所述第一表面具有多个凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
    多个半导体裸片堆叠体，放置在所述凹槽内，且所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
    盖板晶圆，覆盖在所述衬底晶圆的第一表面，以密封所述凹槽，所述衬底晶圆、所述半导体裸片堆叠体及所述盖板晶圆之间的间隙未被填充物填充。
  11. 根据权利要求10所述的半导体封装结构，其特征在于，在所述衬底晶圆的第二表面具有多个导电块，所述导电块与所述导电柱电连接。
  12. 根据权利要求10所述的半导体封装结构，其特征在于，所述半导体裸片堆 叠体由多个半导体裸片堆叠形成，所述半导体裸片之间电连接，并通过所述半导体裸片堆叠体的底部与所述导电柱电连接。
  13. 根据权利要求12所述的半导体封装结构，其特征在于，所述半导体裸片之间通过贯穿各所述半导体裸片的导电柱及相邻所述半导体裸片间的导电块电连接。
  14. 根据权利要求10所述的半导体封装结构，其特征在于，所述半导体裸片堆叠体的底部与贯穿所述凹槽底部的导电柱之间通过导电块电连接。
  15. 根据权利要求10所述的半导体封装结构，其特征在于，所述盖板晶圆朝向所述衬底晶圆的表面具有多个导电柱，所述导电柱与所述半导体裸片堆叠体的上表面电连接。
  16. 一种封装体，其特征在于，包括：
    衬底，所述衬底具有相对设置的第一表面及第二表面，在所述第一表面具有至少一凹槽，在所述凹槽底部具有多个导电柱，所述导电柱贯穿所述凹槽底部至所述第二表面；
    至少一半导体裸片堆叠体，放置在所述凹槽内，所述半导体裸片堆叠体的上表面低于或者平齐于所述凹槽的上边缘，所述半导体裸片堆叠体的底部与所述导电柱电连接；
    盖板，覆盖在所述衬底的第一表面，以密封所述凹槽，所述衬底、所述半导体裸片堆叠体及所述盖板之间的间隙未被填充物填充。
PCT/CN2020/096255 2019-10-16 2020-06-16 半导体封装方法、半导体封装结构及封装体 WO2021073134A1 (zh)

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