WO2021062799A1 - 一种磊晶结构及其制备方法、led - Google Patents

一种磊晶结构及其制备方法、led Download PDF

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WO2021062799A1
WO2021062799A1 PCT/CN2019/109724 CN2019109724W WO2021062799A1 WO 2021062799 A1 WO2021062799 A1 WO 2021062799A1 CN 2019109724 W CN2019109724 W CN 2019109724W WO 2021062799 A1 WO2021062799 A1 WO 2021062799A1
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layer
gan
defect
epitaxial structure
growing
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杨顺贵
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重庆康佳光电技术研究院有限公司
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Priority to US17/055,887 priority Critical patent/US11621371B2/en
Priority to CN201980002001.0A priority patent/CN111316452B/zh
Priority to PCT/CN2019/109724 priority patent/WO2021062799A1/zh
Publication of WO2021062799A1 publication Critical patent/WO2021062799A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/025—Physical imperfections, e.g. particular concentration or distribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

Definitions

  • the invention relates to the technical field of epitaxial structures, in particular to an epitaxial structure, a preparation method thereof, and LEDs.
  • LED Light-emitting diode
  • the material is InGaN, but the current InGaN-based blue-green LED is grown on the sapphire substrate (sapphire) through the MOCVD machine, but because of the stacking of different materials (heterogeneous epitaxy), many defects are caused (10 -9 ⁇ 10 -10 cm -2 ) further affect the recombination efficiency of electrons and holes and reduce the luminous efficiency of the overall device.
  • the epitaxial process is roughly divided into homoepitaxial (A material grows on the A material substrate) and heteroepitaxial (A material grows on the B material substrate).
  • the current GaN-based LED manufacturing process It is the GaN material that grows on the sapphire substrate, because the lattice constants of GaN and the sapphire substrate do not match up to 14%. Therefore, GaN growing on the sapphire substrate will cause stress, which will cause material defects. These defects will have floating bonds. It will affect the capture of electrons or holes, which will make the electron-hole coincidence efficiency worse, and the luminous efficiency of the overall device will worsen.
  • the technical problem to be solved by the present invention is to provide an epitaxial structure and a preparation method thereof, and an LED in view of the above-mentioned defects in the prior art, aiming to solve the problem of defects caused by GaN growing on a sapphire substrate in the prior art.
  • An epitaxial structure which includes: a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer arranged in sequence.
  • the defect exposure layer is a low temperature undoped GaN layer or a low temperature undoped InGaN layer
  • the defect termination layer is an island-shaped doped GaN layer. Hybrid GaN layer.
  • the island-shaped doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer, and the doping concentration of the island-shaped doped GaN layer is greater than 10 19 cm -3 .
  • the epitaxial structure further includes: an n-type GaN layer, a light-emitting layer, an EBL layer, and a p-type GaN layer sequentially arranged on the defect stop layer.
  • An LED including: the epitaxial structure as described in any one of the above.
  • a defect stop layer is grown on the defect exposure layer.
  • the method for preparing the epitaxial structure, wherein the growing a GaN layer on the sapphire substrate includes:
  • a GaN layer is obtained by growing the single crystal GaN as a seed crystal.
  • the method for preparing the epitaxial structure, wherein the growing a defect exposure layer on the GaN layer includes:
  • the growing a defect termination layer on the defect exposure layer includes:
  • Doped GaN is grown on the defect exposure layer to obtain a defect termination layer; wherein the growth temperature of the doped GaN is 1000-1100° C., and the V-III ratio is 4500-7500.
  • the growth of doped GaN is doped with silicon or magnesium, and the doping concentration is greater than 10 19 cm -3 .
  • the method for preparing the epitaxial structure wherein the method further includes:
  • n-type GaN layer, a light-emitting layer, an EBL layer, and a p-type GaN layer are sequentially grown on the defect stop layer.
  • the present invention expands and exposes the defects in the buffer layer through the defect exposure layer, and then changes the direction of the defect through the defect stop layer to stop the defect from continuing to expand . Therefore, when the subsequent layer is continuously prepared on the defect stop layer, the subsequent layer will not form larger defects on the basis of the defects of the buffer layer.
  • Fig. 1 is a schematic diagram of a defect in the prior art.
  • Fig. 2 is a schematic diagram of an epitaxial structure in the prior art.
  • Fig. 3 is a schematic diagram of the epitaxial structure in the present invention.
  • Fig. 4 is an AFM (atomic force microscope) image of an epitaxial structure in the prior art.
  • Figure 5 is an AFM diagram of the epitaxial structure in the present invention.
  • Fig. 6 is a schematic diagram of the structure of the GaN unit cell of the present invention.
  • Fig. 7 is a flow chart of the method for preparing an epitaxial structure in the present invention.
  • the present invention provides some embodiments of an epitaxial structure.
  • the epitaxial structure usually includes: a sapphire substrate 1, an undoped GaN layer (ie, a buffer layer 2), an N-type GaN layer 3, and a stress relief layer 4 arranged in sequence.
  • the light-emitting layer 5 multi-quantum well layer, MQWs may be used
  • the EBL layer 6 that is, the electron blocking layer, such as a p-type AlGaN layer
  • the GaN of the buffer layer 2 does not match the lattice constant of the sapphire substrate 1, when GaN is grown on the sapphire substrate 1, there is stress, which results in many defects (ie V-pits), and the defect density is usually 10 9- 10 10 cm -2 (There are 9 10 ⁇ 10 10 defects in an area of one square centimeter).
  • the subsequent layer will continue to grow according to the lattice with V-pits, so the V- The pits will extend to the outermost P-GaN layer, and the V-pits will become larger and larger.
  • an epitaxial structure of the present invention includes: a sapphire substrate 1, a GaN layer, a defect exposure layer 21, and a defect termination layer 22 arranged in sequence.
  • the present invention expands and exposes the defects in the buffer layer 2 through the defect exposure layer 21, and then changes the defects through the defect stop layer 22 The direction of termination of the defect continues to expand. Therefore, when the subsequent layers (for example, the N-type GaN layer 3, the stress relief layer 4, the multiple quantum well layer, the electron blocking layer, the p-type AlGaN layer, and the p-type GaN layer 7) continue to be prepared on the defect stop layer 22, the subsequent layers No larger V-pits will be formed on the basis of the V-pits of the buffer layer 2.
  • the subsequent layers for example, the N-type GaN layer 3, the stress relief layer 4, the multiple quantum well layer, the electron blocking layer, the p-type AlGaN layer, and the p-type GaN layer
  • FIG. 4 there are multiple V-pits in the AFM diagram of the epitaxial structure (including the subsequent layer) in the prior art, and as shown in FIG. 5, the AFM of the epitaxial structure (including the subsequent layer) in the present invention There is no V-pits in the picture.
  • the GaN layer is a high temperature undoped GaN layer
  • the defect exposure layer 21 is a low temperature undoped GaN layer or a low temperature undoped InGaN layer
  • the defect stop layer 22 It is an island-shaped doped GaN layer.
  • the "high temperature” and “low temperature” here are relative terms, that is to say, relative to the GaN or InGaN in the defect exposure layer 21, the GaN in the buffer layer 2 is prepared at a high temperature, and the specific temperature is 950 -1050°C. Compared with the GaN in the buffer layer 2, the GaN or InGaN in the defect exposure layer 21 is prepared at a low temperature, and the specific temperature is 600-800°C.
  • the specific temperature is 600-800°C.
  • it is beneficial to enlarge the V-pits in the buffer layer 2 that is to say, the opening of the V-pits can be made larger, and the V-pits can be exposed in advance to facilitate termination by defects Layer 22 terminates the exposed V-pits.
  • GaN is a hexagonal crystal system (the unit cell is hexagonal prism shape), the growth rate of GaN on the c-axis and a-axis is fixed, and the defect stop layer 22 adopts doped GaN to form an island structure, that is The island-shaped doped GaN layer, because the GaN here is doped, the growth rate of GaN on the c-axis and the a-axis is different. With the increase of the doping concentration, the growth rate of the a-axis gradually increases, and the growth rate of the c-axis The growth rate gradually decreases.
  • the c-axis is perpendicular to the sapphire substrate 1, and the a-axis is parallel to the sapphire substrate 1.
  • the growth rate of the a-axis of doped GaN increases, the growth rate of the c-axis decreases, and the doped GaN tends to side It is long and expands in the horizontal direction.
  • the V-pits pit turns as the doped GaN tends to grow longer, so it will not extend to the subsequent layers and will not form a larger V-pits pit.
  • the island-shaped doped GaN layer is an island-shaped silicon-doped GaN layer or an island-shaped magnesium-doped GaN layer, and the doping concentration of the island-shaped doped GaN layer is greater than 10 19 cm -3 .
  • the silicon source may be silane (SiH 4 ), and the magnesium source may be magnesium ocene (Cp 2 Mg).
  • the doping concentration of silicon or magnesium is greater than 10 19 cm -3 , that is, within a cubic centimeter volume,
  • the number of Si atoms substituted for Ga atoms is more than 10 20 , because the number of electrons in the periphery of Si is one more electron than the number of Ga atoms. Therefore, doped GaN provides material for the main electrons.
  • the epitaxial structure further includes: an N-type GaN layer 3, a light-emitting layer 5, an EBL layer 6, and p-type GaN layer 7.
  • a stress relief layer 4 can also be provided between the N-type GaN layer 3 and the light-emitting layer 5.
  • the present invention also provides a preferred embodiment of the LED:
  • An LED according to an embodiment of the present invention includes the epitaxial structure as described in any of the above embodiments.
  • the present invention also provides a preferred embodiment of a method for preparing an epitaxial structure:
  • the method for preparing an epitaxial structure according to an embodiment of the present invention includes the following steps:
  • step S100 a sapphire substrate 1 is provided, and a GaN layer is grown on the sapphire substrate 1.
  • step S100 includes:
  • Step S110 a sapphire substrate 1 is provided.
  • Step S120 growing amorphous GaN on the sapphire substrate 1.
  • Step S130 heating the amorphous GaN to obtain single crystal GaN; wherein the temperature of the heating treatment is 950-1050°C.
  • Step S140 using the single crystal GaN as a seed crystal to grow to obtain a GaN layer.
  • step S200 a defect exposure layer 21 is grown on the GaN layer.
  • step S200 includes:
  • Step S210 growing GaN or InGaN on the GaN layer to obtain the defect exposure layer 21; wherein the temperature for growing GaN or InGaN is 600-800°C, and the V-III ratio (the molar ratio of the N source and the Ga+In source ) Is 1000-2500, and the growth pressure is 300-400torr.
  • the N source here uses ammonia gas
  • the Ga source uses trimethylgallium or triethylgallium
  • the In source uses trimethylindium.
  • the defect exposure layer 21 is a low temperature undoped GaN layer or a low temperature undoped InGaN layer, and the specific composition of the low temperature undoped InGaN layer is In x Ga 1-x N (0.2 ⁇ x ⁇ 0.35).
  • the thickness of the defect exposure layer 21 is 0.5-1 ⁇ m.
  • step S300 a defect stop layer 22 is grown on the defect exposure layer 21.
  • step S300 includes:
  • Step S310 growing doped GaN on the defect exposure layer 21 to obtain the defect termination layer 22; wherein the temperature of growing the doped GaN is 1000-1100° C., and the V-III ratio is 4500-7500.
  • the thickness of the defect exposure layer 21 is 1-1.5 ⁇ m.
  • the grown doped GaN is doped with silicon or magnesium, and the doping concentration is greater than 10 19 cm -3 .
  • the doping concentration can be increased according to the extension of time, that is, as the defect exposure layer 21 grows, the concentration of the doping source is increased.
  • step S400 an N-type GaN layer 3, a light-emitting layer 5, an EBL layer 6, and a p-type GaN layer 7 are sequentially grown on the defect stop layer 22.
  • the stress relief layer 4 may also be grown between the N-type GaN layer 3 and the light-emitting layer 5.
  • the present invention provides an epitaxial structure and a manufacturing method thereof, and an LED.
  • the epitaxial structure includes: a sapphire substrate, a GaN layer, a defect exposure layer, and a defect termination layer arranged in sequence.
  • the buffer layer GaN layer
  • the present invention expands and exposes the defects in the buffer layer through the defect exposure layer, and then changes the direction of the defects through the defect termination layer to stop the defects from continuing to expand. Therefore, when the subsequent layer is continuously prepared on the defect stop layer, the subsequent layer will not form larger defects on the basis of the defects of the buffer layer.

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Abstract

一种磊晶结构及其制备方法、LED，所述磊晶结构包括：依次设置的蓝宝石衬底（1）、GaN层（2）、缺陷暴露层（21）、缺陷终止层（22）。在蓝宝石衬底（1）上制备缓冲层（2）之后，通过缺陷暴露层（21），将缓冲层（2）中的缺陷扩大，并暴露出来，然后通过缺陷终止层（22）改变缺陷的方向，终止缺陷继续扩大。因此，在缺陷终止层（22）上继续制备后续层时，后续层不会在缓冲层（2）的缺陷的基础上形成更大的缺陷。

Description

一种磊晶结构及其制备方法、LED 技术领域
本发明涉及磊晶结构技术领域，尤其涉及的是一种磊晶结构及其制备方法、LED。
背景技术
发光二极管(Light-emittingdiode，LED)是一种能发光的半导体电子组件，透过三价与五价元素所组成的复合光源，可应用在照明，广告广告牌，手机背光等，目前所使用的材料为InGaN，但目前是在蓝宝石基板(sapphire)透过MOCVD机台成长InGaN为主的蓝绿光LED，但因是不同材料所堆栈(异质磊晶)进而造成许多缺陷(10 -9～10 -10cm -2)进而影响电子及空穴复合效率而降低整体组件发光效率。即是说，在磊晶制程中大致分为同质磊晶(A材料长在A材料基板上)以及异质磊晶(A材料长在B材料基板上)，目前在GaN基LED制程上目前是GaN材料长在蓝宝石基板上，因为GaN和蓝宝石基板的晶格常数不匹配达14％，因此，GaN长在蓝宝石基板上会产生应力，进而产生材料缺陷，这些缺陷将会存在悬浮键，这将会导致影响捕捉电子或空穴，使得电子电洞符合效率变差，而使整体组件发光效率变差。
因此，现有技术还有待于改进和发展。
发明内容
本发明要解决的技术问题在于，针对现有技术的上述缺陷，提供一种磊晶结构及其制备方法、LED，旨在解决现有技术中GaN长在蓝宝石基板上时产生缺陷的问题。
本发明解决技术问题所采用的技术方案如下：
一种磊晶结构，其中，包括：依次设置的蓝宝石衬底、GaN层、缺陷暴露层、缺陷终止层。
所述的磊晶结构，其中，所述GaN层为高温无掺杂GaN层，所述缺陷暴露层为低温无掺杂GaN层或低温无掺杂InGaN层，所述缺陷终止层为岛状掺杂GaN层。
所述的磊晶结构，其中，所述岛状掺杂GaN层为岛状硅掺杂GaN层或岛状镁掺杂GaN层，所述岛状掺杂GaN层的掺杂浓度大于10 19cm -3。
所述的磊晶结构，其中，所述磊晶结构还包括：依次设置在所述缺陷终止层上的n型GaN层、发光层、EBL层、p型GaN层。
一种LED，其中，包括：如上述任意一项所述的磊晶结构。
一种如上述任意一项所述的磊晶结构的制备方法，其中，所述方法包括以下步骤：
提供一蓝宝石衬底，并在所述蓝宝石衬底上生长GaN层；
在所述GaN层上生长缺陷暴露层；
在所述缺陷暴露层上生长缺陷终止层。
所述的磊晶结构的制备方法，其中，所述在所述蓝宝石衬底上生长GaN层，包括：
在所述蓝宝石衬底上生长非晶GaN；
对所述非晶GaN进行加热处理得到单晶GaN；其中，所述加热处理的温度为950-1050℃；
以所述单晶GaN为晶种生长得到GaN层。
所述的磊晶结构的制备方法，其中，所述在所述GaN层上生长缺陷暴露层，包括：
在所述GaN层上生长GaN或InGaN得到缺陷暴露层；其中，所述生长GaN或InGaN的温度为600-800℃，V-III比为1000-2500；
所述在所述缺陷暴露层上生长缺陷终止层，包括：
在所述缺陷暴露层上生长掺杂GaN得到缺陷终止层；其中，所述生长掺杂GaN的温度为1000-1100℃，V-III比为4500-7500。
所述的磊晶结构的制备方法，其中，所述生长掺杂GaN中采用硅或镁掺杂，掺杂浓度大于10 19cm -3。
所述的磊晶结构的制备方法，其中，所述方法还包括：
在所述缺陷终止层上依次生长n型GaN层、发光层、EBL层、p型GaN层。
有益效果：在蓝宝石衬底上制备缓冲层(GaN层)之后，本发明通过缺陷暴露层，将缓冲层中的缺陷扩大，并暴露出来，然后通过缺陷终止层改变缺陷的方向，终止缺陷 继续扩大。因此，在缺陷终止层上继续制备后续层时，后续层不会在缓冲层的缺陷的基础上形成更大的缺陷。
附图说明
图1是现有技术中缺陷的结构示意图。
图2是现有技术中磊晶结构的示意图。
图3是本发明中磊晶结构的示意图。
图4是现有技术中磊晶结构的AFM(原子力显微镜)图。
图5是本发明中磊晶结构的AFM图。
图6是本发明中GaN的晶胞的结构示意图。
图7是本发明中磊晶结构的制备方法的流程图。
具体实施方式
为使本发明的目的、技术方案及优点更加清楚、明确，以下参照附图并举实施例对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
请同时参阅图3-图6，本发明提供了一种磊晶结构的一些实施例。
需要说明的是，如图1和图2所示，磊晶结构通常包括：依次设置的蓝宝石衬底1、无掺杂GaN层(即缓冲层2)、N型GaN层3、应力释放层4、发光层5(可以采用多量子阱层，MQWs)、EBL层6(即电子阻挡层，如p型AlGaN层)以及p型GaN层7。由于缓冲层2的GaN与蓝宝石衬底1晶格常数不匹配达，在蓝宝石衬底1上生长GaN时，存在应力，因而产生许多缺陷(即V-pits坑)，缺陷密度通常为10 9-10 10cm -2(一平方公分的面积内有9 10～10 10个缺陷)，在后续层的生长过程中，后续层会照着有V-pits坑的晶格继续成长，因此该V-pits坑将会一直延伸到最外层P-GaN层，且V-pits坑会越变越大。一旦磊晶结构中有缺陷存在，电子及空穴将会走最短路径，即缺陷路径(或者说漏电路径)，将不会经过发光层5，而使得磊晶结构不会发光，也会使得起始电压异常 偏低，造成组件无法正常操作。
如图3所示，本发明的一种磊晶结构，包括：依次设置的蓝宝石衬底1、GaN层、缺陷暴露层21、缺陷终止层22。
值得说明的是，在蓝宝石衬底1上制备缓冲层2(GaN层)之后，本发明通过缺陷暴露层21，将缓冲层2中的缺陷扩大，并暴露出来，然后通过缺陷终止层22改变缺陷的方向，终止缺陷继续扩大。因此，在缺陷终止层22上继续制备后续层(例如，N型GaN层3、应力释放层4、多量子阱层、电子阻挡层、p型AlGaN层、p型GaN层7)时，后续层不会在缓冲层2的V-pits坑的基础上形成更大的V-pits坑。
如图4所示，现有技术中磊晶结构(包括后续层)的AFM图中有多个V-pits坑，而如图5所示，本发明中磊晶结构(包括后续层)的AFM图中没有V-pits坑。
在本发明的一个较佳实施例中，所述GaN层为高温无掺杂GaN层，所述缺陷暴露层21为低温无掺杂GaN层或低温无掺杂InGaN层，所述缺陷终止层22为岛状掺杂GaN层。
具体地，这里的“高温”和“低温”是相对而言的，也就是说，相对于缺陷暴露层21中的GaN或InGaN来说，缓冲层2中的GaN采用高温制备，具体温度为950-1050℃。相对于缓冲层2中的GaN来说，缺陷暴露层21中的GaN或InGaN采用低温制备，具体温度为600-800℃。采用低温制备GaN或InGaN时，有利于将缓冲层2中的V-pits坑放大，也就是说，可以使V-pits坑的开口更大，将V-pits坑提前暴露出来，便于通过缺陷终止层22将暴露出来的V-pits坑终止。
如图6所示，GaN为六方晶系(晶胞呈六棱柱状)，GaN在c轴和a轴上的生长速率是既定的，缺陷终止层22采用掺杂GaN形成岛状结构，也即岛状掺杂GaN层，由于这里的GaN进行了掺杂，GaN在c轴和a轴上的生长速率不相同，随着掺杂浓度的提高，a轴的生长速率逐渐升高，c轴的生长速率逐渐降低。在磊晶结构中，c轴垂直与蓝宝石衬底1，a轴平行于蓝宝石衬底1，由于掺杂的GaN的a轴的生长速率提高，c轴的生长速率降低，掺杂的GaN倾向侧长，向水平方向扩展，V-pits坑随着掺杂的GaN倾向侧长而转弯，因此不会延伸到后续层中，不会形成更大的V-pits坑。
在本发明的一个较佳实施例中，所述岛状掺杂GaN层为岛状硅掺杂GaN层或岛状镁掺杂GaN层，所述岛状掺杂GaN层的掺杂浓度大于10 19cm -3。
具体地，硅源可以采用硅烷(SiH 4)，镁源采用二茂镁(Cp 2Mg)，硅或镁的掺杂浓度大于10 19cm -3，也就是说，在一立方公分体积内，Si原子取代Ga原子数目大于10 20个，因Si外围电子数目比Ga原子数目多一个电子，因此，掺杂GaN为主要电子提供材料。
在本发明的一个较佳实施例中，如图3所示，所述磊晶结构还包括：依次设置在所述缺陷终止层22上的N型GaN层3、发光层5、EBL层6、p型GaN层7。当然在N型GaN层3和发光层5之间还可以设置应力释放层4。
基于上述磊晶结构，本发明还提供了一种LED的较佳实施例：
本发明实施例所述一种LED，包括如上述任意一实施例所述的磊晶结构。
基于上述磊晶结构，本发明还提供了一种磊晶结构的制备方法的较佳实施例：
如图7所示，本发明实施例所述一种磊晶结构的制备方法，包括以下步骤：
步骤S100、提供一蓝宝石衬底1，并在所述蓝宝石衬底1上生长GaN层。
具体地，步骤S100包括：
步骤S110、提供一蓝宝石衬底1。
步骤S120、在所述蓝宝石衬底1上生长非晶GaN。
步骤S130、对所述非晶GaN进行加热处理得到单晶GaN；其中，所述加热处理的温度为950-1050℃。
步骤S140、以所述单晶GaN为晶种生长得到GaN层。
步骤S200、在所述GaN层上生长缺陷暴露层21。
具体地，步骤S200包括：
步骤S210、在所述GaN层上生长GaN或InGaN得到缺陷暴露层21；其中，所述生长GaN或InGaN的温度为600-800℃，V-III比(N源和Ga+In源的摩尔比)为1000-2500，生长压力为300-400torr。这里的N源采用氨气，Ga源采用三甲基镓或三乙基镓，In源采用三甲基铟。
具体地，缺陷暴露层21为低温无掺杂GaN层或低温无掺杂InGaN层，低温无掺杂InGaN层具体成分为In xGa 1-xN(0.2≤x≤0.35)。缺陷暴露层21的厚度为0.5-1μm。
步骤S300、在所述缺陷暴露层21上生长缺陷终止层22。
具体地，步骤S300包括：
步骤S310、在所述缺陷暴露层21上生长掺杂GaN得到缺陷终止层22；其中，所述生长掺杂GaN的温度为1000-1100℃，V-III比为4500-7500。
具体地，缺陷暴露层21的厚度为1-1.5μm。所述生长掺杂GaN中采用硅或镁掺杂，掺杂浓度大于10 19cm -3。掺杂浓度可以根据时间的延长增大，也就是说，随着缺陷暴露层21的生长，提高掺杂源的浓度。
步骤S400、在所述缺陷终止层22上依次生长N型GaN层3、发光层5、EBL层6、p型GaN层7。
具体地，也可以在N型GaN层3与发光层5之间生长应力释放层4。
综上所述，本发明所提供的一种磊晶结构及其制备方法、LED，所述磊晶结构包括：依次设置的蓝宝石衬底、GaN层、缺陷暴露层、缺陷终止层。在蓝宝石衬底上制备缓冲层(GaN层)之后，本发明通过缺陷暴露层，将缓冲层中的缺陷扩大，并暴露出来，然后通过缺陷终止层改变缺陷的方向，终止缺陷继续扩大。因此，在缺陷终止层上继续制备后续层时，后续层不会在缓冲层的缺陷的基础上形成更大的缺陷。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (10)

  1. 一种磊晶结构，其特征在于，包括：依次设置的蓝宝石衬底、GaN层、缺陷暴露层、缺陷终止层。
  2. 根据权利要求1所述的磊晶结构，其特征在于，所述GaN层为高温无掺杂GaN层，所述缺陷暴露层为低温无掺杂GaN层或低温无掺杂InGaN层，所述缺陷终止层为岛状掺杂GaN层。
  3. 根据权利要求2所述的磊晶结构，其特征在于，所述岛状掺杂GaN层为岛状硅掺杂GaN层或岛状镁掺杂GaN层，所述岛状掺杂GaN层的掺杂浓度大于10 19cm -3。
  4. 根据权利要求1所述的磊晶结构，其特征在于，所述磊晶结构还包括：依次设置在所述缺陷终止层上的n型GaN层、发光层、EBL层、p型GaN层。
  5. 一种LED，其特征在于，包括：如权利要求1-4任意一项所述的磊晶结构。
  6. 一种如权利要求1-4任意一项所述的磊晶结构的制备方法，其特征在于，所述方法包括以下步骤：
    提供一蓝宝石衬底，并在所述蓝宝石衬底上生长GaN层；
    在所述GaN层上生长缺陷暴露层；
    在所述缺陷暴露层上生长缺陷终止层。
  7. 根据权利要求6所述的磊晶结构的制备方法，其特征在于，所述在所述蓝宝石衬底上生长GaN层，包括：
    在所述蓝宝石衬底上生长非晶GaN；
    对所述非晶GaN进行加热处理得到单晶GaN；其中，所述加热处理的温度为950-1050℃；
    以所述单晶GaN为晶种生长得到GaN层。
  8. 根据权利要求6所述的磊晶结构的制备方法，其特征在于，所述在所述GaN层上生长缺陷暴露层，包括：
    在所述GaN层上生长GaN或InGaN得到缺陷暴露层；其中，所述生长GaN或InGaN的温度为600-800℃，V-III比为1000-2500；
    所述在所述缺陷暴露层上生长缺陷终止层，包括：
    在所述缺陷暴露层上生长掺杂GaN得到缺陷终止层；其中，所述生长掺杂GaN的温度为1000-1100℃，V-III比为4500-7500。
  9. 根据权利要求8所述的磊晶结构的制备方法，其特征在于，所述生长掺杂GaN中采用硅或镁掺杂，掺杂浓度大于10 19cm -3。
  10. 根据权利要求6所述的磊晶结构的制备方法，其特征在于，所述方法还包括：
    在所述缺陷终止层上依次生长n型GaN层、发光层、EBL层、p型GaN层。
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