WO2021062588A1 - 显示基板、显示面板和显示装置 - Google Patents

显示基板、显示面板和显示装置 Download PDF

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Publication number
WO2021062588A1
WO2021062588A1 PCT/CN2019/109326 CN2019109326W WO2021062588A1 WO 2021062588 A1 WO2021062588 A1 WO 2021062588A1 CN 2019109326 W CN2019109326 W CN 2019109326W WO 2021062588 A1 WO2021062588 A1 WO 2021062588A1
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WO
WIPO (PCT)
Prior art keywords
layer
retaining wall
base substrate
supply voltage
power supply
Prior art date
Application number
PCT/CN2019/109326
Other languages
English (en)
French (fr)
Inventor
青海刚
肖云升
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2019/109326 priority Critical patent/WO2021062588A1/zh
Priority to US17/055,110 priority patent/US20210367023A1/en
Priority to EP19945447.1A priority patent/EP4040496A4/en
Priority to CN201980001894.7A priority patent/CN113574676A/zh
Publication of WO2021062588A1 publication Critical patent/WO2021062588A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/814—Anodes combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a display panel, and a display device.
  • AMOLED Active-matrix organic light-emitting diode
  • an embodiment of the present disclosure provides a display substrate, including a base substrate, and a source and drain metal layer and a common electrode layer sequentially disposed on the base substrate;
  • the pattern of the source/drain metal layer includes a power supply voltage line; the power supply voltage line includes an inlet portion; the display substrate includes an effective display area and a binding area;
  • the display substrate further includes a retaining wall arranged on the base substrate and surrounding the effective display area; the orthographic projection of the retaining wall on the base substrate and the effective display area on the base substrate There is a gap between the orthographic projections on the substrate;
  • the inlet portion includes a first part and a second part; the orthographic projection of the first part on the base substrate and the orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at the stop
  • the wall is far from the side of the effective display area, and is located between the retaining wall and the binding area, and is used for receiving a power supply voltage signal;
  • the common electrode layer is in direct contact with the power supply voltage line.
  • the display substrate further includes a conductive connection layer disposed between the power supply voltage line and the common electrode layer;
  • the power supply voltage line further includes a main body, and the main body is overlapped with the common electrode layer through the conductive connection layer.
  • the display substrate according to at least one embodiment of the present disclosure further includes an anode disposed in the effective display area;
  • the conductive connection layer and the anode are arranged in the same layer.
  • the display substrate according to at least one embodiment of the present disclosure further includes a first insulating layer disposed between the power supply voltage line and the conductive connection layer, and a first insulating layer disposed between the conductive connection layer and the common connection layer.
  • the common electrode layer overlaps with the first portion across a first opening penetrating the first insulating layer and a second opening penetrating the first organic layer.
  • the first insulating layer is a flat layer
  • the first organic layer is a pixel defining layer.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the wire inlet portion on the base substrate do not overlap.
  • the orthographic projection on the base substrate of the lead-in portion included in the power supply voltage line overlaps with the orthographic projection of the retaining wall on the base substrate.
  • the retaining wall includes a first retaining wall and a second retaining wall
  • the first retaining wall includes a first retaining wall portion and a second retaining wall portion that are stacked, and the first retaining wall portion and the first organic layer are provided in the same layer;
  • the second retaining wall includes a third retaining wall portion, a fourth retaining wall portion, and a fifth retaining wall portion that are stacked;
  • the third retaining wall portion is provided on the same layer as the first insulating layer, the fourth retaining wall portion is provided on the same layer as the first organic layer, and the fifth retaining wall portion is provided with the second retaining wall Department on the same floor.
  • the common electrode layer is a cathode layer
  • the cathode voltage line is a power supply voltage line.
  • an embodiment of the present disclosure also provides a display substrate, including a base substrate, and a source and drain metal layer and a common electrode layer sequentially disposed on the base substrate;
  • the pattern of the source/drain metal layer includes a power supply voltage line; the power supply voltage line includes an inlet portion; the display substrate includes an effective display area and a binding area;
  • the display substrate further includes a retaining wall arranged on the base substrate and surrounding the effective display area; the orthographic projection of the retaining wall on the base substrate and the effective display area on the base substrate There is a gap between the orthographic projections on the substrate;
  • the inlet portion includes a first part and a second part; the orthographic projection of the first part on the base substrate and the orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at the stop
  • the wall is far from the side of the effective display area, and is located between the retaining wall and the binding area, and is used for receiving a power supply voltage signal;
  • the display substrate further includes a conductive connection layer and a first organic layer;
  • the conductive connection layer includes a first side surface and a second side surface; the first side surface is covered by the first organic layer, and the second side surface is at least partially covered by the first organic layer;
  • the retaining wall includes a straight side portion and a corner portion, and the minimum distance between the second side surface and the corner portion is smaller than the minimum distance between the corner portion and the second portion.
  • the second side surface includes a portion not covered by the first organic layer.
  • the second side surface is completely covered by the first organic layer.
  • the power supply voltage line further includes a main body, and the main body is overlapped with the common electrode layer through the conductive connection layer.
  • the display substrate according to at least one embodiment of the present disclosure further includes a first insulating layer disposed between the power supply voltage line and the conductive connection layer;
  • the common electrode layer directly overlaps the first portion across the first opening that penetrates the first insulating layer and the second opening that penetrates the first organic layer.
  • the first insulating layer is a flat layer
  • the first organic layer is a pixel defining layer.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the wire inlet portion on the base substrate do not overlap.
  • the orthographic projection on the base substrate of the lead-in portion included in the power supply voltage line overlaps with the orthographic projection of the retaining wall on the base substrate.
  • the retaining wall includes a first retaining wall and a second retaining wall
  • the first retaining wall includes a first retaining wall portion and a second retaining wall portion that are stacked, and the first retaining wall portion and the first organic layer are provided in the same layer;
  • the second retaining wall includes a third retaining wall portion, a fourth retaining wall portion, and a fifth retaining wall portion that are stacked;
  • the third retaining wall portion is provided on the same layer as the first insulating layer, the fourth retaining wall portion is provided on the same layer as the first organic layer, and the fifth retaining wall portion is provided with the second retaining wall Department on the same floor.
  • an embodiment of the present disclosure also provides a display panel, including the above-mentioned display substrate.
  • the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • the display substrate, the display panel, and the display device make the common electrode layer and the common electrode layer overlapped by the first part of the lead-in portion included in the power supply voltage line and the overlap area of the common electrode layer.
  • the power supply voltage line is in direct contact, instead of the common electrode layer being overlapped with the power supply voltage line through the conductive connection layer, so as to prevent water and oxygen from invading the effective display area through the side of the conductive connection layer.
  • FIG. 1 is a top view of a display substrate according to at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram showing the first wire-in part 111 and the second wire-in part 112 included in the power supply voltage line in at least one embodiment of the display substrate shown in FIG. 1;
  • FIG. 3A shows, in at least one embodiment of the display substrate, a first portion S1 included in the first wire inlet portion, a second portion S2 included in the first wire inlet portion, and the second wire inlet
  • 3B is a schematic diagram of adding a binding area Ba in at least one embodiment of the display substrate shown in FIG. 3A;
  • the overlap area A1 between the first portion included in the first wire inlet portion and the common electrode layer 12 and the first portion included in the second wire inlet portion and the common electrode layer 12 A schematic diagram of the overlapping area A2 of the common electrode layer 12;
  • FIG. 5 is a schematic diagram of a first wire-in part 111, a second wire-in part 112, and a main body part 113 included in the power supply voltage line in the display substrate according to at least one embodiment of the present disclosure
  • Fig. 6A is a cross-sectional view of AA' in Fig. 1;
  • 6B is a cross-sectional view of the display substrate according to at least one embodiment of the present disclosure.
  • Fig. 7A is a cross-sectional view of BB' in Fig. 1;
  • FIG. 7B is a schematic diagram showing the first opening H1 in FIG. 7A;
  • FIG. 7C is a schematic diagram showing the second opening H2 in FIG. 7A;
  • FIG. 8A is a schematic diagram of the positional relationship between the anode layer 13 and the first portion S1 of the first inlet portion included in the power supply voltage line on the lower side of the display substrate according to at least one embodiment of the present disclosure
  • FIG. 8B is a top view of the power supply voltage line 11 on the lower side of the display substrate according to at least one embodiment of the present disclosure
  • 8C is a schematic diagram of the positional relationship between the direct contact area S0, the power supply voltage line 11 and the common electrode layer 12 on the lower side of the display substrate according to at least one embodiment of the present disclosure
  • FIG. 8D is a first part of the first inlet portion included in the first retaining wall D1, the second retaining wall D2, the anode layer 13 and the power supply voltage line on the lower side of the display substrate according to at least one embodiment of the present disclosure Schematic diagram of the positional relationship between S1;
  • FIG. 8E is a schematic diagram showing the first side surface portion B21 and the second side surface portion B22 on the basis of FIG. 8D;
  • FIG. 8F is a schematic diagram of adding a main body 113 on the basis of FIG. 8D;
  • Figure 8G is a top view of the first retaining wall D1 and the second retaining wall D2 in Figure 8D;
  • 9A is a top view of a part of the anode layer 13 and the first part 81 in the display substrate according to at least one embodiment of the present disclosure
  • 9B is a top view of a part of the anode layer 13 and the first part 81 in the display substrate according to at least one embodiment of the present disclosure
  • Figure 10 is a top view of a related display substrate
  • FIG. 11 is a schematic diagram of a first wire-in part 111, a second wire-in part 112, and a main body part 113 included in the power supply voltage line in the related display substrate.
  • the display substrate includes a base substrate, and a source/drain metal layer and a common electrode layer sequentially disposed on the base substrate; the pattern of the source/drain metal layer includes a power supply voltage line; The power supply voltage line includes an inlet portion; the display substrate includes an effective display area and a binding area;
  • the display substrate further includes a retaining wall arranged on the base substrate and surrounding the effective display area; the orthographic projection of the retaining wall on the base substrate and the effective display area on the base substrate There is a gap between the orthographic projections on the substrate;
  • the inlet portion includes a first part and a second part; the orthographic projection of the first part on the base substrate and the orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at the stop A wall away from the side of the effective display area and located between the retaining wall and the binding area, for receiving a power supply voltage signal;
  • the common electrode layer is in direct contact with the power supply voltage line.
  • the common electrode layer is in direct contact with the power supply voltage line instead of the power supply voltage line through the overlap area between the first part of the power supply voltage line and the common electrode layer.
  • the common electrode layer is overlapped with the power supply voltage line through the conductive connection layer, thereby preventing water and oxygen from invading the effective display area through the side of the conductive connection layer.
  • the common electrode layer may be a cathode layer
  • the power supply voltage line may be a cathode voltage line, but it is not limited thereto.
  • the line labeled 11 is the power supply voltage line
  • the line labeled 12 is the common electrode layer
  • the diagonal line labeled 13 is the anode layer.
  • the label A0 is the effective display area.
  • the power supply voltage line includes a first line-in part 111 and a second line-in part 112.
  • the first part included in the first wire inlet is labeled S1, and the second part included in the first wire inlet is labeled S2;
  • the first part included in the second line-in part is marked S3, and the second part included in the second line-in part is marked S4.
  • the area labeled Ba is the bonding area, and COF (Chip On Flex, chip on film) and IC (Integrated Circuit, integrated circuit), etc. may be bonded in the bonding area.
  • COF Chip On Flex, chip on film
  • IC Integrated Circuit, integrated circuit
  • the common electrode layer 12 and the common electrode layer 12 are overlapped with each other.
  • the power supply voltage line 11 is in direct contact;
  • the common electrode layer 12 is in direct contact with the power supply voltage line 11.
  • the overlapping area between the first part and the common electrode layer refers to: in the overlapping area, the orthographic projection of the first part on the base substrate is the same as the common electrode layer.
  • the orthographic projections on the base substrate overlap each other.
  • the power supply voltage line includes a first incoming line part 111, a second incoming line part 112 and a main body part 113.
  • the display substrate according to at least one embodiment of the present disclosure further includes a first insulating layer disposed between the power supply voltage line and the conductive connection layer, and a first insulating layer disposed between the conductive connection layer and the common electrode The first organic layer between layers;
  • the common electrode layer overlaps with the first portion across a first opening penetrating the first insulating layer and a second opening penetrating the first organic layer.
  • Fig. 6A is a cross-sectional view of AA' in Fig. 1.
  • the display substrate includes a base substrate 20, and the power supply voltage line provided on the base substrate 20 includes The second wire entry portion 112 of the second wire entry portion 112, and the first insulating layer 21, the first organic layer 22, and the common electrode layer 12 that are sequentially disposed on the side of the second wire entry portion 112 away from the base substrate 20;
  • the common electrode layer 12 straddles the first opening that penetrates the first insulating layer 21 and penetrates the first organic layer.
  • the second opening of 22 overlaps with the first part of the second inlet 112 included in the power supply voltage line;
  • the display substrate further includes a first retaining wall and a second retaining wall;
  • the first retaining wall includes a first retaining wall portion D11 and a second retaining wall portion D12 that are stacked, and the first retaining wall portion D11 and the first organic layer 22 are provided on the same layer;
  • the second retaining wall includes a third retaining wall portion D21, a fourth retaining wall portion D22, and a fifth retaining wall portion D23 that are stacked;
  • the third retaining wall portion D21 is arranged on the same layer as the first insulating layer 21, the fourth retaining wall portion D22 is arranged on the same layer as the first organic layer 22, and the fifth retaining wall portion D23 is arranged on the same layer as the first insulating layer 21.
  • the second retaining wall D12 is arranged on the same floor;
  • the first retaining wall and the second retaining wall are arranged on a side of the power supply voltage line 11 away from the base substrate 20.
  • the first insulating layer 21 may be a flat layer
  • the first organic layer 22 may be a pixel defining layer
  • the second wall portion D12 and the fifth wall portion D23 may be partitions. Pillars, but not limited to this.
  • the display substrate may further include a conductive connection layer disposed between the power supply voltage line and the common electrode layer;
  • the power supply voltage line further includes a main body, and the main body is overlapped with the common electrode layer through the conductive connection layer.
  • the display substrate according to at least one embodiment of the present disclosure is not provided with an anode layer 13 in the lower left corner and the lower right corner to prevent water and oxygen from invading the effective display area A0 through the side of the conductive connection layer; however, in FIG.
  • the left side, right side, and upper side of the display substrate shown are still provided with an anode layer 13, and the main body part of the power supply voltage line 11 is overlapped with the common electrode layer 12 through the anode layer 13 .
  • the conductive connection layer may be an anode layer, but is not limited to this.
  • the display substrate according to at least one embodiment of the present disclosure may further include an anode disposed in the effective display area;
  • the conductive connection layer and the anode are arranged in the same layer.
  • the display substrate may include a base substrate 20, a common electrode layer 12, an anode layer 13, an organic light-emitting layer 61, a pixel defining layer 62, a flat layer 63, an inorganic layer 64,
  • the source/drain metal layer 64 is directly connected to the anode layer 60 through a via hole.
  • the conductive connection layer may be the anode layer 60, but it is not limited thereto.
  • the pixel defining layer 62 can be provided with the same layer and the same material as the first organic layer, and the source and drain electrode layer 65 can be provided with the same layer and the same material as the power supply voltage line, so The anode layer 13 and the conductive connection layer may be provided with the same layer and the same material, but it is not limited to this.
  • Fig. 7A is a cross-sectional view of BB' in Fig. 1.
  • the display substrate includes a base substrate 20 and a power supply voltage line provided on the base substrate 20 It includes a main body portion 113, and a first insulating layer 21, an anode layer 13, a first organic layer 22, and a common electrode layer 12 that are sequentially disposed on a side of the main body portion 113 away from the base substrate 20;
  • the common electrode layer 12 is overlapped with the main body portion 113 included in the power supply voltage line through the anode layer 13;
  • the first retaining wall is labeled D1
  • the second retaining wall is labeled D2.
  • the one marked H1 is the first opening
  • the one marked H2 is the second opening.
  • FIG. 7B only the base substrate 20, the main body portion 113, and the first insulating layer 21 are shown.
  • FIG. 7C only the base substrate 20, the main body portion 113, the anode layer 13, the first insulating layer 21, and the first organic layer 22 are shown.
  • the first insulating layer may be a flat layer, and the first organic layer may be a pixel defining layer.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the wire inlet on the base substrate do not overlap.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the inlet portion on the base substrate do not overlap, so that the side surface of the conductive connection layer and the inlet portion include The distance of the second part is relatively far, so as to prevent water and oxygen from invading the effective display area through the side of the conductive connection layer.
  • the orthographic projection of the lead-in portion included in the power supply voltage line on the base substrate overlaps the orthographic projection of the retaining wall on the base substrate.
  • the retaining wall may include a first retaining wall and a second retaining wall
  • the first retaining wall includes a first retaining wall portion and a second retaining wall portion that are stacked, and the first retaining wall portion and the first organic layer are provided in the same layer;
  • the second retaining wall includes a third retaining wall portion, a fourth retaining wall portion, and a fifth retaining wall portion that are stacked;
  • the third retaining wall portion is provided on the same layer as the first insulating layer, the fourth retaining wall portion is provided on the same layer as the first organic layer, and the fifth retaining wall portion is provided with the second retaining wall Department on the same floor.
  • the retaining wall may include a first retaining wall and a second retaining wall, the first retaining wall and the second retaining wall may be a multi-layer laminated structure, and the first retaining wall includes a first retaining wall.
  • a retaining wall portion is arranged on the same layer as the first organic layer, and a fourth retaining wall portion included in the second retaining wall is arranged on the same layer as the first organic layer.
  • S1 is the first part of the first inlet part included in the power supply voltage line
  • 13 is the anode layer.
  • the portion covered by the anode layer 13 may be the main body portion 113 included in the power supply voltage line.
  • the reference number 11 is the power supply voltage line
  • the reference number 12 is the common electrode layer.
  • the common electrode layer 12 is in direct contact with the power supply voltage line 11.
  • the first retaining wall labeled D1 is the first retaining wall
  • the second retaining wall labeled D2 is the second retaining wall
  • the one labeled S1 is the first part of the first inlet part of the power supply voltage line
  • the one labeled 13 is Anode layer.
  • the anode layer 13 includes a first side B1 and a second side B2;
  • the first side surface B1 is the outer boundary surface of the anode layer 13, and the first side surface B1 is shown by a thicker line in FIG. 8D;
  • the first side B1 may be covered by an organic layer, and the second side B2 may be partially covered by an organic layer;
  • the first side surface B1 is covered by the second retaining wall D2, but it is not limited to this. In specific implementation, the first side surface B1 may also be covered by the first retaining wall D1.
  • the first retaining wall D1 and the second retaining wall D2 may be made of organic materials.
  • the second side surface B2 may include a first side surface portion B21 and a second side surface portion B22;
  • B21 is set between D1 and D2, B21 is not covered by the organic layer; B22 is set above D1, and B22 is also not covered by the organic layer; the second side surface B2 includes parts other than B21 and B22 that can be covered by the organic layer Cover; At this time, B21 and B22 are used to isolate water vapor.
  • B21 and/or B22 can also be covered by an organic layer to protect the boundary of the anode layer.
  • the organic layer may be a first organic layer or a retaining wall, but it is not limited to this.
  • the portion of the second side surface that is not covered by the organic layer is in the corner area of the second retaining wall (that is, closer to the corner of the second retaining wall D2), and Keep away from the effective display area, and away from the second part of the incoming line of the power supply voltage line to avoid the formation of water and oxygen intrusion channels near the effective display area.
  • the second side surface may also be located in the corner area of the second retaining wall.
  • a main body portion 113 is added to the figure shown in FIG. 8D, and the outer boundary surface of the main body portion 113 may be below the second retaining wall D2, but is not limited to this.
  • the outer boundary surface on the left side of the main body 113 may also be on the left of the second retaining wall D2, that is, it may slightly exceed the second retaining wall D2 to reduce electrical resistance.
  • D1 includes a first corner portion D11 and a first straight edge portion (the first straight edge portion may be included in D1 Except for the corner portion), D2 includes a second corner portion D21 and a second straight side portion (the second straight side portion may be a portion other than the corner portion included in D2);
  • the minimum distance between the second side surface B2 and the second corner portion D21 is smaller than the minimum distance between the second corner portion D21 and the second portion, so that the second side surface B2 is far away from the effective display Zone and the second part.
  • Figures 8A to 9B are top views.
  • the number 13 is the anode layer, and the number 81 is the first part; in the embodiment of FIG. 9A, the orthographic projection of the anode layer 13 on the base substrate is on the The main body 113 of the power supply voltage line is within the orthographic projection of the base substrate.
  • the portion covered by the anode layer 13 may be the main body portion 113 of the power supply voltage line.
  • the orthographic projection of the anode layer 13 on the base substrate may not be completely within the orthographic projection of the main body portion 113 on the base substrate.
  • 60 is the source and drain metal layer, 12 is the common electrode layer, 13 is the anode layer, and A0 is the effective display area;
  • the smallest area in the middle is the effective display area A0
  • the common electrode layer 12 covering the entire effective display area A0 is a layer of semi-transparent metal conductive Film layer
  • the area of the common electrode layer 12 is larger than the area of the effective display area A0
  • the portion of the common electrode layer 12 that exceeds the effective display area A0 is in contact with the anode layer 13
  • the anode layer 13 is a layer An opaque conductive layer
  • the anode layer 13 is generally in full contact with the common electrode layer 12 on the left, right and upper sides of the display substrate; and on the lower left corner of the display substrate and the display substrate In the lower right corner, the anode layer 13 is in partial contact with the common electrode layer 12; the anode layer 13 is not directly input signals, and the anode layer 13 is connected to the source and drain metal layers located under the anode layer 13 60 is connected to access a signal
  • the source-drain metal layer 60 is a conductive metal layer
  • the source-drain metal layer 60 is a
  • the source and drain metal layers include power supply voltage lines, and the power supply voltage lines may include a first incoming line part 111, a second incoming line part 112, and a main body part 113;
  • the main body portion 113 is arranged around the effective display area A0, and the main body portion 113 is arranged on the left side, right side and upper side of the effective display area A0; In the lower left corner of the effective display area A0, the second line entry 112 is located at the lower right corner of the effective display area A0.
  • a driving integrated circuit may be provided on the lower side of the effective display area A0, and the driving integrated circuit is used to provide the cathode voltage ELVSS for the power supply voltage line.
  • At least one embodiment of the present disclosure removes the anode layer at the left and right lower corners of the display substrate, so that the edge of the anode layer is away from the position a-b in FIG. 10 to prevent water and oxygen from invading the effective display area.
  • the display substrate includes a base substrate, and a source/drain metal layer and a common electrode layer sequentially disposed on the base substrate;
  • the pattern of the source/drain metal layer includes a power supply voltage line; the power supply voltage line includes an inlet portion; the display substrate includes an effective display area and a binding area;
  • the display substrate further includes a retaining wall arranged on the base substrate and surrounding the effective display area; the orthographic projection of the retaining wall on the base substrate and the effective display area on the base substrate There is a gap between the orthographic projections on the substrate;
  • the inlet portion includes a first part and a second part; the orthographic projection of the first part on the base substrate and the orthographic projection of the gap on the base substrate at least partially overlap; the second part is located at the stop A wall away from the side of the effective display area and located between the retaining wall and the binding area, for receiving a power supply voltage signal;
  • the display substrate further includes a conductive connection layer and a first organic layer;
  • the conductive connection layer includes a first side surface and a second side surface; the first side surface is covered by the first organic layer, and the second side surface is at least partially covered by the first organic layer;
  • the retaining wall includes a straight side portion and a corner portion, and the minimum distance between the second side surface and the corner portion is smaller than the minimum distance between the corner portion and the second portion.
  • the first side surface of the conductive layer is set to be covered by the first organic layer, which can prevent water and oxygen from invading the effective display area through the side surface of the conductive connection layer;
  • the second side surface included in the conductive connection layer is arranged farther from the second part, so as to avoid the formation of a water and oxygen intrusion channel close to the effective display area.
  • the second side surface may include a portion not covered by the first organic layer.
  • the second side surface may also be completely covered by the first organic layer.
  • the first organic layer borders the retaining wall, that is, the part of the first organic layer covering the second side and the retaining wall are an integral structure.
  • the power supply voltage line further includes a main body, and the main body is overlapped with the common electrode layer through the conductive connection layer.
  • the display substrate of the present disclosure may further include a first insulating layer disposed between the power supply voltage line and the conductive connection layer;
  • the common electrode layer overlaps with the main body part across a first opening penetrating the first insulating layer and a second opening penetrating the first organic layer.
  • the first insulating layer may be a flat layer, and the first organic layer may be a pixel defining layer.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the wire inlet portion on the base substrate do not overlap.
  • the orthographic projection of the conductive connection layer on the base substrate and the orthographic projection of the inlet portion on the base substrate do not overlap, so that the side surface of the conductive connection layer and the inlet portion include The distance of the second part is relatively far, so as to prevent water and oxygen from invading the effective display area through the side of the conductive connection layer.
  • the orthographic projection of the lead-in portion included in the power supply voltage line on the base substrate overlaps the orthographic projection of the retaining wall on the base substrate.
  • the retaining wall may include a first retaining wall and a second retaining wall
  • the first retaining wall includes a first retaining wall portion and a second retaining wall portion that are stacked, and the first retaining wall portion and the first organic layer are provided in the same layer;
  • the second retaining wall includes a third retaining wall portion, a fourth retaining wall portion, and a fifth retaining wall portion that are stacked;
  • the third retaining wall portion is provided on the same layer as the first insulating layer, the fourth retaining wall portion is provided on the same layer as the first organic layer, and the fifth retaining wall portion is provided with the second retaining wall Department on the same floor.
  • the display panel according to at least one embodiment of the present disclosure may include the above-mentioned display substrate.
  • the display device described in at least one embodiment of the present disclosure may include the above-mentioned display panel.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种显示基板、显示面板和显示装置。显示基板包括源漏金属层（65）和公用电极层（12）；源漏金属层的图形（65）包括电源电压线（11）；电源电压线（11）包括进线部；显示基板还包括挡墙；挡墙在衬底基板（20）上的正投影和有效显示区域（A0）在衬底基板（20）上的正投影之间存在间隙；进线部包括第一部分（S1）和第二部分（S2）；第一部分（S1）在衬底基板（20）上的正投影和所述间隙在衬底基板（20）上的正投影至少部分重叠；第二部分（S2）位于挡墙远离所述有效显示区（A0）域的一侧，且位于所述挡墙和所述绑定区（Ba）之间，用于接收电源电压信号；在第一部分（S1）与公用电极层（12）的重叠区域，公用电极层（12）与所述电源电压线（11）直接接触。能够避免水氧通过导电连接层的侧面入侵有效显示区域。

Description

显示基板、显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示面板和显示装置。
背景技术
随着AMOLED(Active-matrix organic light-emitting diode，有源矩阵有机发光二极管)技术的成熟，AMOLED在移动终端的使用也越来越普遍。作为构成AMOLED面板核心的发光元器件的小分子发光材料非常怕水氧的入侵，一旦水氧侵蚀，该发光元器件就会失效，从而在显示上产生暗点不良。
发明内容
在一个方面中，本公开实施例提供了一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的源漏金属层和公用电极层；
所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域以及绑定区域；
所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区之间，用于接收电源电压信号；
在所述第一部分与所述公用电极层的重叠区域，所述公用电极层与所述电源电压线直接接触。
可选的，所述显示基板还包括设置于所述电源电压线和所述公用电极层之间的导电连接层；
所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
可选的，本公开至少一实施例所述的显示基板还包括设置于所述有效显示区域中的阳极；
所述导电连接层与所述阳极同层设置。
可选的，本公开至少一实施例所述的显示基板还包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层，以及设置于所述导电连接层与所述公用电极层之间的第一有机层；
所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口与所述第一部分搭接。
可选的，所述第一绝缘层为平坦层，所述第一有机层为像素界定层。
可选的，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
可选的，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
可选的，所述挡墙包括第一挡墙和第二挡墙；
所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
可选的，所述公用电极层为阴极层，所述阴极电压线为电源电压线。
在第二个方面中，本公开实施例还提供了一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的源漏金属层和公用电极层；
所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域以及绑定区域；
所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区之间，用于接收电源电压信号；
所述显示基板还包括导电连接层和第一有机层；
所述导电连接层包括第一侧面和第二侧面；所述第一侧面被所述第一有机层覆盖，所述第二侧面至少部分被所述第一有机层覆盖；
所述挡墙包括直边部分和拐角部分，所述第二侧面与所述拐角部分之间的最小距离小于所述拐角部分与所述第二部分之间的最小距离。
可选的，所述第二侧面包括未被所述第一有机层覆盖的部分。
可选的，所述第二侧面全部被所述第一有机层覆盖。
可选的，所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
可选的，本公开至少一实施例所述的显示基板还包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层；
所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口直接与所述第一部分搭接。
可选的，所述第一绝缘层为平坦层，所述第一有机层为像素界定层。
可选的，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
可选的，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
可选的，所述挡墙包括第一挡墙和第二挡墙；
所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
在第三个方面中，本公开实施例还提供了一种显示面板，包括上述的显 示基板。
本公开实施例还提供了一种显示装置，包括上述的显示面板。
与相关技术相比，本公开实施例所述的显示基板、显示面板和显示装置通过在电源电压线包括的进线部中的第一部分与公用电极层的重叠区域，使得所述公用电极层与电源电压线直接接触，而不是所述公用电极层通过导电连接层与电源电压线搭接，从而能够避免水氧通过导电连接层的侧面入侵有效显示区域。
附图说明
图1是本公开至少一实施例所述的显示基板的俯视图；
图2是在图1所示的显示基板的至少一实施例中示出所述电源电压线包括的第一进线部111和第二进线部112的示意图；
图3A是在所述显示基板的至少一实施例中，示出所述第一进线部包括的第一部分S1、所述第一进线部包括的第二部分S2、所述第二进线部包括的第一部分S3和所述第二进线部包括的第二部分S4的示意图；
图3B是在图3A所示的显示基板的至少一实施例中增加绑定区域Ba的示意图；
图4是在所述显示基板的至少一实施例中，所述第一进线部包括的第一部分与所述公用电极层12的重叠区域A1和所述第二进线部包括的第一部分与所述公用电极层12的重叠区域A2的示意图；
图5是在本公开至少一实施例所述的显示基板中，电源电压线包括的第一进线部111、第二进线部112和主体部113的示意图；
图6A是图1中的AA’截面图；
图6B是本公开至少一实施例所述的显示基板的截面图；
图7A是图1中的BB’截面图；
图7B是在图7A中标示第一开口H1的示意图；
图7C是在图7A中标示第二开口H2的示意图；
图8A是在本公开至少一实施例所述的显示基板的下侧边，阳极层13与电源电压线包括的第一进线部中的第一部分S1之间的位置关系示意图；
图8B是在本公开至少一实施例所述的显示基板的下侧边，电源电压线11的俯视图；
图8C是在本公开至少一实施例所述的显示基板的下侧边，直接接触区域S0、电源电压线11和公用电极层12之间的位置关系示意图；
图8D是在本公开至少一实施例所述的显示基板的下侧边，第一挡墙D1、第二挡墙D2、阳极层13与电源电压线包括的第一进线部中的第一部分S1之间的位置关系示意图；
图8E是在图8D的基础上示出第一侧面部B21和第二侧面部B22的示意图；
图8F是在图8D的基础上增加主体部113的示意图；
图8G是图8D中的第一挡墙D1和第二挡墙D2的俯视图；
图9A是在本公开至少一实施例所述的显示基板中，阳极层13的一部分与第一部分81的俯视图；
图9B是在本公开至少一实施例所述的显示基板中，阳极层13的一部分与第一部分81的俯视图；
图10是相关的显示基板的俯视图；
图11是在相关的显示基板中，电源电压线包括的第一进线部111、第二进线部112和主体部113的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开至少一实施例所述的显示基板包括衬底基板、以及依次设置于所述衬底基板上的源漏金属层和公用电极层；所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域和绑定区域；
所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的 挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区域之间，用于接收电源电压信号；
在所述第一部分与所述公用电极层的重叠区域，所述公用电极层与所述电源电压线直接接触。
本公开至少一实施例所述的显示基板通过在电源电压线包括的进线部中的第一部分与公用电极层的重叠区域，使得所述公用电极层与电源电压线直接接触，而不是所述公用电极层通过导电连接层与电源电压线搭接，从而能够避免水氧通过导电连接层的侧面入侵有效显示区域。
在本公开至少一实施例中，所述公用电极层可以为阴极层，所述电源电压线可以为阴极电压线，但不以此为限。
如图1所示，在本公开至少一实施例所述的显示基板中，标号为11的为电源电压线，标号为12的为公用电极层，标号为13的斜线所示的为阳极层，标号为A0的为有效显示区域。
如图2所示，在图1所示的显示基板的至少一实施例中，所述电源电压线包括第一进线部111和第二进线部112。
如图3A所示，在所述显示基板的至少一实施例中，所述第一进线部包括的第一部分标号为S1，所述第一进线部包括的第二部分标号为S2；所述第二进线部包括的第一部分标号为S3，所述第二进线部包括的第二部分标号为S4。
在图3B中，标号为Ba的为绑定区域，在所述绑定区域可以绑定有COF(Chip On Flex，覆晶薄膜)和IC(Integrated Circuit，集成电路)等。
如图4所示，在所述显示基板的至少一实施例中，在所述第一进线部包括的第一部分与所述公用电极层12的重叠区域A1，所述公用电极层12与所述电源电压线11直接接触；
在所述第二进线部包括的第一部分与所述公用电极层12的重叠区域A2， 所述公用电极层12与所述电源电压线11直接接触。
在本公开至少一实施例中，所述第一部分与所述公用电极层的重叠区域指的是：在所述重叠区域，所述第一部分在衬底基板上的正投影与所述公用电极层在衬底基板上的正投影相互交叠。
在图5中，仅示出有效显示区域A0和电源电压线，所述电源电压线包括第一进线部111、第二进线部112和主体部113。
具体的，本公开至少一实施例所述的显示基板还包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层，以及设置于所述导电连接层与所述公用电极层之间的第一有机层；
所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口与所述第一部分搭接。
图6A是图1中的AA’截面图。
如图6A所示，在本公开如图1所示的显示基板的实施例的右下侧边，所述显示基板包括衬底基板20、设置于所述衬底基板20上的电源电压线包括的第二进线部112，以及依次设置于所述第二进线部112远离所述衬底基板20的一侧的第一绝缘层21、第一有机层22和公用电极层12；
如图6A所示，在所述显示基板的至少一实施例的右下侧边，所述公用电极层12跨过贯穿所述第一绝缘层21的第一开口和贯穿所述第一有机层22的第二开口与所述电源电压线包括的第二进线部112中的第一部分搭接；
并如图6A所示，所述显示基板还包括第一挡墙和第二挡墙；
所述第一挡墙包括层叠设置的第一挡墙部D11和第二挡墙部D12，所述第一挡墙部D11与所述第一有机层22同层设置；
所述第二挡墙包括层叠设置的第三挡墙部D21、第四挡墙部D22和第五挡墙部D23；
所述第三挡墙部D21与所述第一绝缘层21同层设置，所述第四挡墙部D22与所述第一有机层22同层设置，所述第五挡墙部D23与所述第二挡墙部D12同层设置；
所述第一挡墙和所述第二挡墙设置于所述电源电压线11远离所述衬底基板20的一侧。在图6A中，所述第一绝缘层21可以为平坦层，所述第一 有机层22可以为像素界定层，所述第二挡墙部D12和所述第五挡墙部D23可以为隔垫柱，但不以此为限。
具体的，所述显示基板还可以包括设置于所述电源电压线和所述公用电极层之间的导电连接层；
所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
如图1所示，本公开至少一实施例所述的显示基板在左下角和右下角不设置有阳极层13，以避免水氧通过导电连接层的侧面入侵有效显示区域A0；然而在图1所示的显示基板的左侧边、右侧边和上侧边，依然设置有阳极层13，所述电源电压线11包括的主体部通过所述阳极层13与所述公用电极层12搭接。
在具体实施时，所述导电连接层可以为阳极层，但不以此为限。
具体的，本公开至少一实施例所述的显示基板还可以包括设置于所述有效显示区域中的阳极；
所述导电连接层与所述阳极同层设置。
图6B所示，本公开至少一实施例所述的显示基板可以包括衬底基板20、公用电极层12、阳极层13、有机发光层61、像素界定层62、平坦层63、无机层64、源漏金属层65、栅金属层66、有源层67、层间介质层68、栅绝缘层69和缓冲层610；在图6B中，标号为611的为封装基板。
如图6B所示，在本公开至少一实施例所述的显示基板中，所述源漏金属层64直接与所述阳极层60通过过孔连接。在本公开至少一实施例中，所述导电连接层可以为所述阳极层60，但不以此为限。
在图6B所示的显示基板的至少一实施例中，像素界定层62可以与所述第一有机层同层同材料设置，源漏电极层65可以与电源电压线同层同材料设置，所述阳极层13可以与所述导电连接层同层同材料设置，但不以此为限。
图7A是图1中的BB’截面图。
如图7A所示，在本公开如图1所示的显示基板的至少一实施例的左侧边，所述显示基板包括衬底基板20、设置于所述衬底基板20上的电源电压线包括的主体部113，以及依次设置于所述主体部113远离所述衬底基板20 的一侧的第一绝缘层21、阳极层13、第一有机层22和公用电极层12；
在所述显示基板的至少一实施例的左侧边，所述公用电极层12通过所述阳极层13与所述电源电压线包括的主体部113搭接；
在图7A中，标号为D1的为第一挡墙，标号为D2的为第二挡墙。在图7B中，标号为H1的为所述第一开口，在图7C中，标号为H2的为所述第二开口。在图7B中，仅示出衬底基板20、主体部113和第一绝缘层21。在图7C中，仅示出衬底基板20、主体部113、阳极层13、第一绝缘层21和第一有机层22。
在本公开至少一实施例中，所述第一绝缘层可以为平坦层，所述第一有机层可以为像素界定层。
优选的，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
在优选情况下，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠，以使得导电连接层的侧面与进线部包括的第二部分的距离较远，从而避免水氧通过导电连接层的侧面入侵有效显示区域。
具体的，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
具体的，所述挡墙可以包括第一挡墙和第二挡墙；
所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
在具体实施时，所述挡墙可以包括第一挡墙和第二挡墙，所述第一挡墙和所述第二挡墙可以为多层层叠结构，所述第一挡墙包括的第一挡墙部与所述第一有机层同层设置，所述第二挡墙包括的第四挡墙部与所述第一有机层同层设置。
如图8A所示，标号为S1的为电源电压线包括的第一进线部中的第一部 分，标号为13的为阳极层。在图8A中，被阳极层13覆盖的部分可以为电源电压线包括的主体部113。
在图8B中，标号为11的为电源电压线，在图8C中，标号为12的为公用电极层，在直接接触区域S0，所述公用电极层12与所述电源电压线11直接接触。
在图8D中，标号为D1的为第一挡墙，标号为D2的为第二挡墙,标号为S1的为电源电压线包括的第一进线部中的第一部分，标号为13的为阳极层。
在图8D中，所述阳极层13包括第一侧面B1和第二侧面B2；
所述第一侧面B1为所述阳极层13的外边界面，在图8D中以较粗的线示出第一侧面B1；
所述第一侧面B1可以被有机层覆盖，所述第二侧面B2可以部分被有机层覆盖；
在图8D所示的至少一实施例中，所述第一侧面B1被第二挡墙D2覆盖，但不以此为限。在具体实施时，所述第一侧面B1也可以被第一挡墙D1覆盖。
在本公开至少一实施例中，所述第一挡墙D1和所述第二挡墙D2可以为有机材料制成。
如图8E所示，所述第二侧面B2可以包括第一侧面部B21和第二侧面部B22；
B21设置于D1和D2之间，B21不被有机层覆盖；B22设置于D1上方，B22也不被有机层覆盖；所述第二侧面B2包括的除了B21和B22之外的部分可以被有机层覆盖；此时，B21和B22用于隔绝水汽。
但是在实际操作时，B21和/或B22也可以被有机层覆盖，以保护阳极层边界。
在本公开至少一实施例中，所述有机层可以为第一有机层或挡墙，但不以此为限。
在本公开至少一实施例中，所述第二侧面未被所述有机层覆盖的部分处于所述第二挡墙的拐角区域(也即距离第二挡墙D2的拐角部较近)，并远离有效显示区，远离电源电压线的进线部的第二部分，以避免形成离有效显示 区域近的水氧入侵的通道。
并且，无论所述第二侧面是否被有机层覆盖，所述第二侧面也可以处于第二挡墙的拐角区域。
在图8A、图8D和图8E中，标号为113的为主体部。
如图8F所示，在图8D所示的图中增加主体部113，所述主体部113的外边界面可以在所述第二挡墙D2下方，但不以此为限。在实际操作时，所述主体部113的左侧的外边界面也可以在所述第二挡墙D2左方，也即可以稍超过所述第二挡墙D2，以减小电阻。
在图8G中，仅示出图8D中的第一挡墙D1和第二挡墙D2，D1包括第一拐角部分D11和第一直边部分(所述第一直边部分可以为D1包括的除了拐角部分之外的部分)，D2包括第二拐角部分D21和第二直边部分(所述第二直边部分可以为D2包括的除了拐角部分之外的部分)；
所述第二侧面B2与所述第二拐角部分D21之间的最小距离小于所述第二拐角部分D21与所述第二部分之间的最小距离，以使得所述第二侧面B2远离有效显示区和第二部分。
图8A至图9B为俯视图。
由图9A所示，标号为13的为阳极层，标号为81的为所述第一部分；在图9A的实施例中，所述阳极层13在所述衬底基板上的正投影在所述电源电压线的主体部113在所述衬底基板的正投影之内。
在图9A中，被所述阳极层13覆盖的部分可以为电源电压线的主体部113。
可选的，如图9B所示，所述阳极层13在衬底基板上的正投影也可以不完全在所述主体部113在所述衬底基板上的正投影内，此时增大阳极层13的面积，以减小电阻。
如图10所示，在相关的显示基板中，标号为60的为源漏金属层，标号为12的为公用电极层，标号为13的为阳极层，标号为A0的为有效显示区域；
在图10所示的相关的显示基板中，中间最小的区域为有效显示区域A0，覆盖在整个有效显示区域A0之上的为公用电极层12，公用电极层12为一层半透明的金属导电膜层，通常所述公用电极层12的面积比所述有效显示区域 A0的面积大，所述公用电极层12超过所述有效显示区域A0的部分与阳极层13接触，阳极层13为一层不透光的导电层，所述阳极层13一般会在显示基板的左侧边、右侧边和上侧边与所述与公用电极层12完全接触；而在显示基板的左下角和显示基板的右下角，所述阳极层13与所述公用电极层12存在部分接触；所述阳极层13并不被直接输入信号，阳极层13是通过与位于所述阳极层13下方的源漏金属层60连接以接入信号，所述源漏金属层60为导电金属层，所述源漏金属层60包括电源电压线，以接入阴极电压ELVSS。
在相关技术中，如图11所示，源漏金属层包括电源电压线，所述电源电压线可以包括第一进线部111、第二进线部112和主体部113；
所述主体部113围绕着所述有效显示区域A0设置，所述主体部113设置于所述有效显示区域A0的左侧边、右侧边和上侧边；所述第一进线部111位于所述有效显示区域A0的左下角，所述第二进线部112位于所述有效显示区域A0的右下角。
在图11中，仅示出有效显示区域A0和电源电压线。
在相关技术和本公开至少一实施例中，在所述有效显示区域A0的下侧边可以设置有驱动集成电路，所述驱动集成电路用于为所述电源电压线提供阴极电压ELVSS。
如图10所示，在相关的显示基板中，水氧容易从图10中的a-b位置沿着阳极层13的边界入侵进入有效显示区域A0，而该位置距离有效显示区域AA0非常近，该阳极层13的边界非常容易形成水氧入侵的通道，该通道离有效区域A0很近，水氧一旦入侵，靠近该通道的发光材料容易氧化，最终导致发光材料变性失效，因此会导致该位置附近的发光像素点失效，从而形成暗点。
基于此，本公开至少一实施例去除显示基板左右下角的阳极层，从而使得阳极层边沿远离图10中的a-b位置，以避免水氧入侵有效显示区域。
本公开至少一实施例所述的显示基板包括衬底基板，以及依次设置于所述衬底基板上的源漏金属层和公用电极层；
所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域和绑定区域；
所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区域之间，用于接收电源电压信号；
所述显示基板还包括导电连接层和第一有机层；
所述导电连接层包括第一侧面和第二侧面；所述第一侧面被所述第一有机层覆盖，所述第二侧面至少部分被所述第一有机层覆盖；
所述挡墙包括直边部分和拐角部分，所述第二侧面与所述拐角部分之间的最小距离小于所述拐角部分与所述第二部分之间的最小距离。
本公开至少一实施例所述的显示显示基板通过将导电层的第一侧面设置为被第一有机层覆盖，能够避免水氧通过导电连接层的侧面入侵有效显示区域；并且，本公开至少一实施例所述的显示基板通过将所述导电连接层包括的第二侧面设置为距离所述第二部分较远，从而避免形成离有效显示区域近的水氧入侵的通道。
可选的，所述第二侧面可以包括未被所述第一有机层覆盖的部分。
可选的，所述第二侧面也可以全部被所述第一有机层覆盖。此时，第一有机层与挡墙会接壤，也即包覆所述第二侧边的第一有机层的部分和所述挡墙为一体结构。
具体的，所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
具体的，本公开所述的显示基板还可以包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层；
所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口与所述主体部搭接。
在本公开至少一实施例中，所述第一绝缘层可以为平坦层，所述第一有机层可以为像素界定层。
在优选情况下，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
在优选情况下，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠，以使得导电连接层的侧面与进线部包括的第二部分的距离较远，从而避免水氧通过导电连接层的侧面入侵有效显示区域。
具体的，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
在具体实施时，所述挡墙可以包括第一挡墙和第二挡墙；
所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
本公开至少一实施例所述的显示面板可以包括上述的显示基板。
本公开至少一实施例所述的显示装置可以包括上述的显示面板。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (20)

  1. 一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的源漏金属层和公用电极层；
    所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域以及绑定区域；
    所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
    所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区之间，用于接收电源电压信号；
    在所述第一部分与所述公用电极层的重叠区域，所述公用电极层与所述电源电压线直接接触。
  2. 如权利要求1所述的显示基板，其中，所述显示基板还包括设置于所述电源电压线和所述公用电极层之间的导电连接层；
    所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
  3. 如权利要求2所述的显示基板，其中，还包括设置于所述有效显示区域中的阳极；
    所述导电连接层与所述阳极同层设置。
  4. 如权利要求2所述的显示基板，其中，还包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层，以及设置于所述导电连接层与所述公用电极层之间的第一有机层；
    所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口与所述第一部分搭接。
  5. 如权利要求4所述的显示基板，其中，所述第一绝缘层为平坦层，所述第一有机层为像素界定层。
  6. 如权利要求4所述的显示基板，其中，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
  7. 如权利要求1所述的显示基板，其中，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
  8. 如权利要求4所述的显示基板，其中，所述挡墙包括第一挡墙和第二挡墙；
    所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
    所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
    所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
  9. 如权利要求1至8中任一权利要求所述的显示基板，其中，所述公用电极层为阴极层，所述阴极电压线为电源电压线。
  10. 一种显示基板，包括衬底基板以及依次设置于所述衬底基板上的源漏金属层和公用电极层；
    所述源漏金属层的图形包括电源电压线；所述电源电压线包括进线部；所述显示基板包括有效显示区域以及绑定区域；
    所述显示基板还包括设置于所述衬底基板上的围绕所述有效显示区域的挡墙；所述挡墙在所述衬底基板上的正投影和所述有效显示区域在所述衬底基板上的正投影之间存在间隙；
    所述进线部包括第一部分和第二部分；所述第一部分在衬底基板上的正投影和所述间隙在衬底基板上的正投影至少部分重叠；所述第二部分位于所述挡墙远离所述有效显示区域的一侧，且位于所述挡墙和所述绑定区之间，用于接收电源电压信号；
    所述显示基板还包括导电连接层和第一有机层；
    所述导电连接层包括第一侧面和第二侧面；所述第一侧面被所述第一有机层覆盖，所述第二侧面至少部分被所述第一有机层覆盖；
    所述挡墙包括直边部分和拐角部分，所述第二侧面与所述拐角部分之间的最小距离小于所述拐角部分与所述第二部分之间的最小距离。
  11. 如权利要求10所述的显示基板，其中，所述第二侧面包括未被所述第一有机层覆盖的部分。
  12. 如权利要求10所述的显示基板，其中，所述第二侧面全部被所述第一有机层覆盖。
  13. 如权利要求10所述的显示基板，其中，所述电源电压线还包括主体部，所述主体部通过所述导电连接层与所述公用电极层搭接。
  14. 如权利要求13所述的显示基板，其中，还包括设置于所述电源电压线和所述导电连接层之间的第一绝缘层；
    所述公用电极层跨过贯穿所述第一绝缘层的第一开口和贯穿所述第一有机层的第二开口直接与所述第一部分搭接。
  15. 如权利要求14所述的显示基板，其中，所述第一绝缘层为平坦层，所述第一有机层为像素界定层。
  16. 如权利要求10所述的显示基板，其中，所述导电连接层在衬底基板上的正投影与所述进线部在所述衬底基板上的正投影不交叠。
  17. 如权利要求10所述的显示基板，其中，所述电源电压线包括的进线部在所述衬底基板上的正投影与所述挡墙在所述衬底基板上的正投影交叠。
  18. 如权利要求14所述的显示基板，其中，所述挡墙包括第一挡墙和第二挡墙；
    所述第一挡墙包括层叠设置的第一挡墙部和第二挡墙部，所述第一挡墙部与所述第一有机层同层设置；
    所述第二挡墙包括层叠设置的第三挡墙部、第四挡墙部和第五挡墙部；
    所述第三挡墙部与所述第一绝缘层同层设置，所述第四挡墙部与所述第一有机层同层设置，所述第五挡墙部与所述第二挡墙部同层设置。
  19. 一种显示面板，包括如权利要求1至18中任一权利要求所述的显示基板。
  20. 一种显示装置，包括如权利要求19所述的显示面板。
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