WO2021057883A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021057883A1
WO2021057883A1 PCT/CN2020/117632 CN2020117632W WO2021057883A1 WO 2021057883 A1 WO2021057883 A1 WO 2021057883A1 CN 2020117632 W CN2020117632 W CN 2020117632W WO 2021057883 A1 WO2021057883 A1 WO 2021057883A1
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Prior art keywords
wire
substrate
array substrate
layer
oxide semiconductor
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PCT/CN2020/117632
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English (en)
French (fr)
Inventor
林滨
曾勇
霍亚洲
李梁梁
陈周煜
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
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Priority to US17/298,493 priority Critical patent/US12021091B2/en
Publication of WO2021057883A1 publication Critical patent/WO2021057883A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • the oxide thin film transistor uses an oxide semiconductor material as an active layer, which has good uniformity, and is especially suitable for large-area display requirements.
  • a method for manufacturing an array substrate includes: providing a substrate; forming a plurality of wires on one side of the substrate; forming an oxide semiconductor film on the side of the plurality of wires away from the substrate, and the oxide
  • the semiconductor thin film covers the plurality of wires and directly contacts with at least one wire; the at least one wire is configured to extract static electricity generated in the oxide semiconductor thin film; and the oxide semiconductor thin film is processed by a photolithography process.
  • the patterning process removes the part directly in contact with the at least one wire to form an oxide semiconductor layer including an active layer of a plurality of oxide thin film transistors.
  • the manufacturing method of the array substrate further includes: before forming the oxide semiconductor film, forming a gate conductive layer including the gates of a plurality of oxide thin film transistors; The multiple wires are located on the same side of the substrate.
  • a gate insulating film is formed on the side of the plurality of wires and the gate conductive layer away from the substrate; the gate insulating film covers the plurality of wires and the gate conductive layer.
  • the gate insulating film is patterned to form a gate insulating layer with at least one via; the at least one via exposes at least a part of the surface of the at least one wire, and the at least one via is in the substrate
  • the orthographic projection on the substrate at least partially overlaps the orthographic projection of the at least one wire on the substrate.
  • the oxide semiconductor film is in direct contact with the at least one wire through the at least one via hole.
  • a part of the boundary of the orthographic projection of the at least one wire on the substrate is connected to the at least one via on the substrate. Part of the boundary of the orthographic projection coincides.
  • the material of the plurality of wires includes a metal material; the plurality of wires and the gate conductive layer are formed in the same patterning process.
  • the method for preparing the array substrate further includes: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the substrate, and the source-drain conductive layer includes a conductive layer connected to each active layer.
  • the source electrode and the drain electrode in direct contact with the layer, and an auxiliary lead directly in contact with the at least one wire.
  • the array substrate has a display area and a frame area located beside the display area.
  • the auxiliary lead is located in the frame area.
  • the at least one wire is configured to transmit a common voltage signal to the display area or to protect the array substrate from static electricity.
  • the auxiliary lead is configured to be connected in parallel with the at least one wire to reduce the resistance of the at least one wire.
  • the material of the oxide semiconductor film includes zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide It is one of indium aluminum zinc oxide and indium aluminum zinc oxide.
  • the orthographic projection of the oxide semiconductor layer on the substrate and the orthographic projection of the at least one wire on the substrate overlap at most.
  • an array substrate in another aspect, includes: a substrate; a plurality of wires arranged on one side of the substrate; and a plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of wires are arranged on the substrate The same side of the bottom.
  • each oxide thin film transistor includes a gate, an active layer, a source and a drain; the active layers of the plurality of oxide thin film transistors are formed by patterning an oxide semiconductor thin film directly in contact with at least one wire. And the active layer and the at least one wire are insulated from each other.
  • the array substrate further includes a gate insulating layer disposed between the gate and the active layer.
  • the gate insulating layer has at least one via, the at least one via exposes at least a part of the surface of the at least one wire, and the orthographic projection of the at least one via on the substrate is in line with the at least one wire.
  • the orthographic projections on the substrate at least partially overlap.
  • the oxide semiconductor film directly contacts the at least one wire through the at least one via hole.
  • the array substrate further includes: auxiliary leads arranged on a side of the gate insulating layer away from the substrate.
  • the auxiliary lead directly contacts the at least one wire through the at least one via hole.
  • the array substrate further includes: auxiliary leads with the same material as the source electrode and the drain electrode and arranged in the same layer.
  • the auxiliary lead is in direct contact with the at least one wire.
  • the orthographic projection of the auxiliary lead on the substrate and the orthographic projection of the at least one wire on the substrate at least partially overlap.
  • the routing direction of the auxiliary lead is the same or substantially the same as the routing direction of the at least one wire.
  • the array substrate further includes a passivation layer disposed on a side of the source electrode and the drain electrode away from the substrate. A part of the passivation layer is located in the at least one via and is in direct contact with the at least one wire.
  • the array substrate has a display area and a frame area located beside the display area.
  • the at least one wire is located in the frame area.
  • the at least one wire includes a common electrode wire or an electrostatic protection wire.
  • the common electrode line is configured to transmit a common voltage signal to the display area; the electrostatic protection line is configured to perform electrostatic protection on the array substrate.
  • the gate electrode and the plurality of wires have the same material and are arranged in the same layer.
  • a display device in another aspect, includes: the array substrate as described in any of the above embodiments.
  • the display device further includes: a counter substrate disposed opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the counter substrate.
  • the display device further includes: a plurality of light-emitting devices arranged on a side of the array substrate away from the substrate of the array substrate with a plurality of oxide thin film transistors.
  • FIG. 1 is a structural diagram of static electricity accumulated in an oxide semiconductor film according to the related art
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure
  • FIG. 3 is a flowchart of another method for manufacturing an array substrate according to some embodiments of the present disclosure.
  • 4a to 4g are schematic diagrams of a manufacturing process of an array substrate according to some embodiments of the present disclosure.
  • 5a to 5l are schematic diagrams of a preparation process along the O-O' direction in the preparation process shown in Figs. 4a to 4g;
  • Fig. 6 is a structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 7 is a structural diagram of another array substrate according to some embodiments of the present disclosure.
  • FIG. 8 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 9 is a structural diagram of another display device according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • connection and its extensions may be used.
  • connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
  • the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
  • exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
  • a photolithography process can be used to prepare an active layer forming an oxide thin film transistor.
  • a layer of oxide semiconductor material film may be deposited first, and then a photoresist layer may be formed on one side surface of the oxide semiconductor material film.
  • the resist layer is exposed and developed to obtain a patterned photoresist layer, and the patterned photoresist layer can be used to pattern the oxide semiconductor material film to obtain an active layer.
  • the oxide semiconductor material film is prone to generate and accumulate static electricity in the exposure machine, and then electrostatic breakdown (Electro-Static Discharge, ESD) phenomenon may occur, which reduces the yield of array substrates including oxide thin film transistors.
  • ESD Electro-Static Discharge
  • an oxide thin film transistor is taken as an example of a bottom-gate thin film transistor.
  • a plurality of gates 1' may be formed first, and then On one side of the plurality of gates 1', a gate insulating layer 2'covering the plurality of gates 1'and an oxide semiconductor material film 3'covering the gate insulating layer 2'are sequentially formed, and then a photolithography process is used to The oxide semiconductor material film 3'is patterned.
  • the oxide semiconductor material is usually a substance with an amorphous structure, its conductivity is poor.
  • static electricity is easily generated in the oxide semiconductor material film 3'.
  • the oxide semiconductor material film 3' can also form a parasitic capacitance structure with other conductive structures.
  • the oxide semiconductor material film 3' can form a parasitic capacitance structure with the gate 1'and induce different gates.
  • a parasitic capacitance structure is formed between 1'. In the case where a large amount of static electricity generated in the oxide semiconductor material film 3'accumulates, the phenomenon of electrostatic breakdown is prone to occur.
  • some embodiments of the present disclosure provide a method for manufacturing an array substrate.
  • the preparation method of the array substrate includes: S100-S400.
  • a substrate 1 is provided.
  • the above-mentioned substrate 1 includes multiple materials, which can be selected and set according to actual needs.
  • the above-mentioned substrate 1 may be a substrate of inorganic material, or a substrate of organic material.
  • the material of the substrate 1 may be soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, or other materials.
  • the material of the substrate 1 may be polymethyl methacrylate (PMMA for short), polyvinyl alcohol (PVA for short), or polyvinyl phenol (PMMA for short).
  • PMMA polymethyl methacrylate
  • PVA polyvinyl alcohol
  • PMMA polyvinyl phenol
  • PVP polyethersulfone
  • PES Polyimide
  • polyamide polyacetal
  • PC Polycarbonate
  • PC Polyterephthalic acid Polyethylene terephthalate
  • PEN polyethylene naphthalate
  • the substrate 1 when the substrate 1 uses an inorganic material, the substrate 1 may be a rigid substrate; when the substrate 1 uses an organic material, the substrate 1 may be a flexible substrate.
  • a plurality of conductive lines 2 are formed on the substrate 1.
  • the material of the aforementioned wire 2 may include one conductive material or a combination of multiple conductive materials.
  • the material of the wire 2 may include a metal material, a conductive metal oxide material, a conductive metal nitride material, a conductive polymer material, a conductive composite material, or a combination of at least two of them.
  • the foregoing metal material may be, for example, platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination of at least two of them.
  • the aforementioned conductive metal oxide material may be, for example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO) metal oxide, or doped metal oxide.
  • ITO indium tin oxide
  • FTO fluorine-doped tin oxide
  • doped metal oxide doped metal oxide.
  • the aforementioned conductive metal nitride material may be titanium nitride or the like, for example.
  • the above-mentioned conductive polymer material can be, for example, polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/polystyrene sulfonic acid (PEDOT/PSS) or among them At least a combination of the two, or the above-mentioned materials doped with dopants; among them, the dopant can be, for example, acids such as hydrochloric acid, sulfuric acid, and sulfonic acid, or Lewis acids such as PF6, AsF5, and FeCl3, or halogens such as iodide ion. Ion, or metal ions such as sodium ion and potassium ion.
  • the dopant can be, for example, acids such as hydrochloric acid, sulfuric acid, and sulfonic acid, or Lewis acids such as PF6, AsF5, and FeCl3, or halogens such as iodide ion. Ion
  • the aforementioned conductive composite material may be, for example, a conductive composite material dispersed with carbon black, graphite powder, metal particles, or the like.
  • the above-mentioned wire 2 may be a single-layer structure composed of a layer of conductive material, or may be a multi-layer structure formed by sequentially stacking multiple layers of conductive materials.
  • the wire 2 in the present disclosure may be a single-layer structure formed by a layer of metal material.
  • the wire 2 in the present disclosure may have a three-layer structure formed by a first metal layer, a second metal layer, and a first metal layer that are sequentially stacked.
  • the first metal layer may be a single-layer structure formed of at least one metal material
  • the second metal layer may be a single-layer structure formed of at least one metal material
  • the metal material included in the first metal layer and the second metal layer is different.
  • an oxide semiconductor film 3 is formed on the side of the plurality of wires 2 away from the substrate 1.
  • the oxide semiconductor film 3 covers the plurality of wires 2 and directly contacts with at least one wire 2. That is, the oxide semiconductor thin film 3 may be in direct contact with one wire 2 or may be in direct contact with a plurality of wires 2.
  • the at least one wire 2 is configured to discharge static electricity generated in the oxide semiconductor thin film 3.
  • a process such as magnetron sputtering may be used to prepare and form the above-mentioned oxide semiconductor film 3.
  • the material of the above-mentioned oxide semiconductor thin film 3 may be an amorphous oxide semiconductor material.
  • the oxide semiconductor material may be zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), Aluminum zinc oxide (AZO), yttrium zinc oxide (YZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (Indium aluminum zinc oxide)
  • ZnO zinc oxide
  • IAZO indium gallium zinc oxide
  • IAZO indium aluminum zinc oxide
  • the above-mentioned oxide semiconductor material may be in an amorphous state, that is, the above-mentioned oxide semiconductor material may be an amorphous oxide semiconductor material.
  • the above-mentioned oxide semiconductor film 3 may be an amorphous indium gallium zinc oxide film.
  • the oxide semiconductor thin film 3 is patterned to remove the portion directly in contact with the at least one wire 2 to form an oxide layer 51 including a plurality of oxide thin film transistors 5.
  • the oxide semiconductor layer 3a and the above-mentioned at least one wire 2 are insulated from each other.
  • a photolithography process may be used to pattern the oxide semiconductor film 3.
  • the oxide semiconductor thin film 3 is patterned by a photolithography process, including: S410 to S450.
  • a photoresist layer PR is formed on the surface of the oxide semiconductor film 3 away from the substrate 1.
  • a coating process may be used to coat a photoresist on the surface of the oxide semiconductor film 3 away from the substrate 1 to form a photoresist layer PR.
  • the above-mentioned photoresist may be a positive photoresist, or the above-mentioned photoresist may be a negative photoresist.
  • the method for preparing the array substrate is schematically illustrated by taking the photoresist as a positive photoresist as an example.
  • the photoresist layer PR may be exposed in an exposure machine.
  • static electricity is generated in the oxide semiconductor film 3.
  • the static electricity generated in the oxide semiconductor film 3 can be discharged into the at least one wire 2, and the static electricity is discharged through the at least one wire 2 to reduce Even the accumulation of static electricity in the oxide semiconductor thin film 3 is avoided, thereby avoiding the phenomenon of electrostatic breakdown caused by a large amount of static electricity accumulated in the oxide semiconductor thin film 3.
  • the exposed photoresist layer PR is developed, and the exposed part of the photoresist layer PR is removed to obtain a patterned photoresist layer PR'.
  • the patterned photoresist layer PR' exposes a part of the surface of the oxide semiconductor film 3 away from the substrate 1 and covers the rest of the oxide semiconductor film 3.
  • the oxide semiconductor film 3 is patterned, and the unpatterned light in the oxide semiconductor film 3 is removed by etching.
  • the part covered by the resist layer PR' retains the part covered by the patterned photoresist layer PR' in the oxide semiconductor film 3, that is, the oxide semiconductor layer 3a.
  • the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 above overlap at most, and the oxide semiconductor layer 3a and the at least one wire 2 are insulated from each other. .
  • the effective electrical connection between the at least one wire 2 and the thin film formed in the subsequent preparation can be ensured, and the power supply caused by the oxide semiconductor layer 3a sandwiched between the at least one wire 2 and the thin film formed in the subsequent preparation can be avoided.
  • the manufacturing method of the array substrate is to form a plurality of wires 2 on one side of the substrate 1, and after the oxide semiconductor film 3 is formed, the oxide semiconductor film 3 and at least one wire are formed. 2 Direct contact, so that in the process of patterning the oxide semiconductor film 3, the static electricity generated in the oxide semiconductor film 3 can be discharged to at least one wire 2 with good conductivity, which is beneficial to reduce the
  • the accumulation of static electricity on the oxide semiconductor layer 3a of the multiple active layers 51 avoids the phenomenon of electrostatic breakdown and improves the yield of the prepared array substrate.
  • the oxide thin film transistor 5 in the formed array substrate may be a bottom-gate oxide thin film transistor. In other embodiments, the oxide thin film transistor 5 in the formed array substrate may be a top gate type oxide thin film transistor.
  • the preparation method of the array substrate may further include: S210 to S230.
  • a gate conductive layer Gate is formed.
  • the gate conductive layer Gate is located on the same side of the substrate 1 as the multiple wires 2 described above.
  • the aforementioned gate conductive layer Gate may include a plurality of gate lines and a plurality of gate electrodes 52 of the oxide thin film transistor 5.
  • Each gate 52 may be disposed opposite to the active layer 51 formed by subsequent preparation.
  • the material and hierarchical structure of the gate conductive layer Gate may be the same as or different from the plurality of conductive lines 2.
  • the gate conductive layer Gate and the plurality of wires 2 may be provided on the same surface, and have the same structure and material, that is, the gate conductive layer Gate and the plurality of wires 2 may be on the same surface. Preparation and formation in the sub-patterning process.
  • the gate conductive layer Gate and the plurality of wires 2 can be formed by the following method:
  • a gate conductive material film is formed on one side of the substrate 1; then the gate conductive material film is patterned to simultaneously form the plurality of wires 2 and the gate conductive layer Gate.
  • the above-mentioned gate conductive material film may be patterned through a photolithography process.
  • a gate insulating film GI' is formed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1.
  • the gate insulating film GI' covers the gate conductive layer Gate and the plurality of wires 2.
  • the material of the gate insulating film GI' may be silicon oxide, silicon oxynitride, silicon nitride, or other insulating materials.
  • the gate insulating film GI' can be prepared by, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process.
  • the gate insulating film GI' is patterned to form a gate insulating layer GI having at least one via hole K.
  • the at least one via K exposes at least a part of the surface of the at least one wire 2, and the orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap.
  • the oxide semiconductor film 3 directly contacts the at least one wire 2 through the at least one via K.
  • the gate insulating film GI' may be patterned through a photolithography process to obtain the gate insulating layer GI.
  • the gate insulating layer GI covers the gate conductive layer Gate.
  • the orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap, that is, the at least one via K exposes a part of the at least one wire 2.
  • the number of via holes K may be one or multiple.
  • the relationship between the at least one via K and the at least one wire 2 includes multiple types, which can be selected and set according to actual needs.
  • the at least one via K may correspond to the at least one wire 2 in a one-to-one correspondence, that is, one via K may expose a part of the wire 2.
  • one wire 2 may correspond to at least two vias K in the multiple vias K, that is, the at least two vias K In the hole K, each via K can expose a part of a corresponding wire 2.
  • one via K may correspond to at least two wires 2 of the multiple wires 2, that is, the via K simultaneously exposes the Part of at least two wires 2.
  • the formed oxide semiconductor film 3 can directly contact the at least one wire 2 through the at least one via K.
  • the static electricity generated in the oxide semiconductor film 3 can pass through the portion of the oxide semiconductor film 3 located in the at least one via hole K. Release to the at least one wire 2 and lead out through the at least one wire 2.
  • the oxide semiconductor layer 3a may expose the at least one via K, and further expose a part of the at least one wire 2.
  • the orthographic projection of the formed oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one via K on the substrate 1 can be disjoint. Stack, completely remove the oxide semiconductor material in the at least one via hole K.
  • a part of the boundary of the orthographic projection of the at least one wire 2 on the substrate 1 is different from the at least one wire 2 above.
  • the method for preparing the above-mentioned array substrate may further include preparing the source electrode 53 and the drain electrode 54 of the oxide thin film transistor 5.
  • the preparation method of the array substrate may further include: S500.
  • a source-drain conductive layer SD is formed on the side of the oxide semiconductor layer 3a away from the substrate 1.
  • the source-drain conductive layer SD may include a plurality of sources 52 and a plurality of drains 53, which are electrically connected to the plurality of active layers 51 in a one-to-one correspondence, and the plurality of drains 53 are connected to a plurality of The source layers 51 are electrically connected in a one-to-one correspondence.
  • an oxide thin film transistor 5 may include an active layer 51, a source 52 and a drain 53.
  • the source-drain conductive layer SD may further include auxiliary leads 6, and the auxiliary leads 6 are electrically connected to the at least one wire 2 described above.
  • the auxiliary lead 6 and the above-mentioned at least one wire 2 can be directly contacted in a one-to-one correspondence to form an electrical connection.
  • the auxiliary lead 6 can be used to reduce the resistance of the wire 2 electrically connected to the auxiliary lead 6 and improve the stability of the electrical signal transmitted in the wire 2. Not only that, because the auxiliary lead 6 can reduce the resistance of the wire 2 electrically connected to it, so that the line width of the wire 2 (that is, the size of the wire 2 in the direction perpendicular to its routing) can be reduced, thereby reducing The space ratio of the wire 2 in the array substrate is reduced.
  • the source-drain conductive layer SD may be formed by the following method.
  • a source-drain conductive material film SD' may be formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' covers the at least one conductive wire 2 described above. At least one exposed portion of the via hole K, a portion of the gate insulating layer GI not covered by the active layer 51, and the active layer 51.
  • the material of the source-drain conductive material film SD' can be titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), Tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta) or an alloy thereof or a combination of at least two of the foregoing materials.
  • the source-drain conductive material film SD' can be a single-layer structure formed by a layer of conductive material, or a multilayer structure formed by multiple layers of conductive materials stacked in sequence.
  • a sputtering process can be used to form the source-drain conductive material film SD'.
  • the source-drain conductive material film SD' may be patterned to form the source-drain conductive layer SD including the auxiliary lead 6, the source 53 and the drain 54.
  • the source-drain conductive material film SD' can be patterned through a photolithography process.
  • the source-drain conductive layer SD may also include source-drain layer leads, such as voltage leads and data lines.
  • the orthographic projections on the substrate 1 of the auxiliary lead 6 and the wire 2 electrically connected to the auxiliary lead 6 may be overlapped with each other or may be partially overlapped.
  • the formed array substrate 100 may have a display area A and a frame area B located beside the display area A.
  • the substrate 1 also has a frame area B and a display area A.
  • the orthographic projection of the frame area B of the array substrate 100 on the substrate 1 coincides with the frame area B of the substrate 1
  • the orthographic projection of the display area A of the array substrate 100 on the substrate 1 is the same as the display area A of the substrate 1. coincide.
  • the side refers to one side, two sides, three layers, or peripheral side of the display area A (as shown in FIG. 4g).
  • the frame area B can be located on one side, two sides, or three sides of the display area A, or the frame area B can surround the display area A.
  • At least one wire 2 directly in contact with the oxide semiconductor thin film 3 may be formed in the frame area B of the array substrate 100.
  • the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be an electrostatic protection line used to protect the array substrate 100 from static electricity.
  • the above-mentioned at least one wire 2 may have a larger size in the direction perpendicular to its routing direction, so as to ensure that it has a smaller impedance, thereby ensuring the stability of the electrical signal transmitted by it.
  • the resistance of the at least one wire 2 can be reduced, and the line width of the at least one wire 2 can be reduced, which is beneficial to reduce the size of the frame area B, so that The array substrate 100 can realize a narrow frame design.
  • At least one wire 2 directly in contact with the oxide semiconductor film 3 may be formed in the display area A of the array substrate 100.
  • the at least one wire 2 may be a second common electrode line that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate.
  • the manufacturing method of the array substrate of the present disclosure may further include: forming a passivation layer (PVX) 7 on the side of the oxide thin film transistor 5 away from the substrate 1.
  • PVX passivation layer
  • FIGS. 4g and 51 a plurality of pixel electrodes 8 are formed on the side of the passivation layer 7 away from the substrate 1, and the plurality of pixel electrodes 8 are connected to the source 53 or drain of the plurality of oxide thin film transistors 5, respectively.
  • the poles 54 are electrically connected in a one-to-one correspondence.
  • the method for preparing the array substrate of the present disclosure may further include: before forming the pixel electrode 8, forming a planarization layer covering the passivation layer 7 so as to provide a flat surface for the pixel electrode 8.
  • the pixel electrode 8 may be formed on the side surface of the planarization layer away from the substrate 1.
  • the prepared array substrate 100 can be applied to LCD (Liquid Crystal Display, liquid crystal display device).
  • the manufacturing method of the array substrate 100 may further include: forming a common electrode on the side of the pixel electrode 8 away from the substrate 1.
  • the manufacturing method of the array substrate of the present disclosure may further include: sequentially forming a light-emitting layer and a cathode layer on the side of the pixel electrode 8 away from the substrate 1, and the at least one wire 2 is the first
  • the cathode layer may be electrically connected to the above-mentioned at least one wire 2, or to the auxiliary lead 6, or to the at least one wire 2 and the auxiliary lead 6 at the same time.
  • the prepared array substrate can be applied to an OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display device.
  • OLED Organic Light Emitting Diode, Organic Light Emitting Diode
  • a substrate 1 is provided.
  • the substrate 1 is a glass substrate.
  • the substrate 1 has a display area A and a frame area B surrounding the display area A.
  • a gate conductive material film is formed on one side of the substrate 1, and the gate conductive material film covers the display area A and the frame area B of the substrate 1.
  • the above-mentioned gate conductive material film can be formed by a deposition method, for example, the gate conductive material film can be formed by a magnetron sputtering deposition method.
  • the gate conductive material film is patterned to form a gate conductive layer Gate located in the display area A and a plurality of wires 2 located in the frame area B.
  • the gate conductive layer Gate includes a plurality of gate lines and a plurality of gates 52 for forming an oxide thin film transistor 5;
  • the plurality of wires 2 includes at least one common electrode line for providing a common voltage signal for the display area and/ Or an electrostatic protection wire used for electrostatic protection of the array substrate 100.
  • a gate insulating film GI' covering the gate conductive layer Gate and the plurality of conductive lines 2 is formed on the side of the gate conductive layer Gate and the plurality of conductive lines 2 away from the substrate 1.
  • the gate insulating film GI' can be formed by a deposition method, for example, the gate insulating film GI' can be formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD) method.
  • the gate insulating film GI' is patterned with the help of a mask to form a gate insulating layer GI having at least one via K.
  • the at least one via K exposes a part of the at least one wire 2.
  • the mask may have a pattern for forming at least one via K in the frame area B.
  • an oxide semiconductor film 3 is formed on the side of the gate insulating layer GI away from the substrate 1.
  • the oxide semiconductor film 3 is located in the display area A and the frame area B at the same time.
  • the oxide semiconductor film 3 is in direct contact with the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI.
  • the oxide semiconductor thin film 3 may be formed by a deposition method, for example, the oxide semiconductor thin film 3 may be formed by a magnetron sputtering method.
  • the oxide semiconductor thin film 3 is patterned to form an oxide semiconductor layer 3a.
  • the oxide semiconductor layer 3a includes a plurality of active layers 51 for forming an oxide thin film transistor 5, and the oxide semiconductor layer 3a does not cover the at least one wire 2 described above.
  • the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 do not overlap at all.
  • the substrate containing the oxide semiconductor thin film 3 may be transported into an exposure machine for exposure. Since oxide semiconductor materials are usually amorphous materials, they have poor electrical conductivity and are prone to static electricity in the exposure machine. Since the oxide semiconductor film 3 is in direct contact with the at least one wire 2, the static electricity generated in the oxide semiconductor film 3 can be discharged to the at least one wire 2, and the at least one wire 2 is led out, reducing or even avoiding the accumulation of static electricity. , Effectively avoid the occurrence of electrostatic breakdown (ESD) phenomenon.
  • ESD electrostatic breakdown
  • the portion of the oxide semiconductor film 3 above and inside the at least one via K will be removed, exposing part of the surface of the at least one wire 2.
  • a source-drain conductive film material SD' is formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' is located in the display area A and the frame area B at the same time. That is, the source-drain conductive material film SD' covers the exposed at least one wire 2, the portion of the gate insulating layer GI that is not covered by the active layer 51, and the active layer 51.
  • the source and drain conductive material film SD' can be formed by a deposition method, for example, the source and drain conductive material film SD' can be formed by a magnetron sputtering method.
  • the source-drain conductive material film SD' is patterned to form a source-drain conductive layer SD.
  • the source-drain conductive layer SD includes auxiliary leads 6 located in the frame area B and directly contacting the at least one wire 2 through the via K, and multiple data lines and the source of each oxide thin film transistor 5 located in the display area A. Pole 53 and drain 54 and so on.
  • the auxiliary lead 6 can be connected in parallel with the at least one wire 2 to reduce the resistance of the at least one wire 2, which not only improves the stability of the electrical signal transmitted in the at least one wire 2, but also reduces the at least one wire 2.
  • the size in the direction perpendicular to the routing direction is beneficial to reduce the size of the frame area B, and is beneficial to realize the narrow frame design of the array substrate 100.
  • a passivation layer 7 (PVX) and a planarization layer are sequentially formed.
  • a plurality of pixel electrodes 8 are formed on the side of the planarization layer away from the substrate 1, wherein the plurality of pixel electrodes 8 are connected to the drains of the plurality of oxide thin film transistors 5, respectively.
  • Pole 54 is electrically connected.
  • the material of the pixel electrode 8 may be ITO, for example.
  • the preparation method of the exemplary array substrate may further include: forming a light-emitting layer and a cathode layer in sequence on the side of the pixel electrode 8 away from the substrate 1, wherein the cathode layer extends to the frame area B and is directly connected to the auxiliary lead 6
  • the contact forms an electrical connection.
  • the wire 2 electrically connected to the auxiliary lead may be a common electrode wire.
  • a protective layer is formed on the side of the cathode layer away from the substrate 1, a protective layer is formed.
  • the array substrate 100 may include a substrate 1, a plurality of wires 2 and a plurality of oxide thin film transistors 5.
  • the material of the substrate 1 can refer to the schematic descriptions in some of the above-mentioned embodiments, which will not be repeated here.
  • the plurality of oxide thin film transistors 5 and the plurality of wires 2 are arranged on the same side of the substrate 1.
  • each oxide thin film transistor 5 includes an active layer 51, a gate 52, a source 53 and a drain 54.
  • the active layer 51 of any oxide thin film transistor 5 is obtained by patterning the oxide semiconductor thin film 3 directly in contact with at least one wire 2 (for example, refer to the preparation of the array substrate provided in some of the above embodiments). Method), and the active layer 51 of any oxide thin film transistor 5 and the at least one wire 2 are insulated from each other.
  • the material of the above-mentioned active layer 51 includes multiple types.
  • the material of the active layer 51 may be an oxide semiconductor material.
  • the oxide semiconductor material may be an amorphous oxide semiconductor material.
  • the amorphous oxide semiconductor material may be zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium.
  • the array substrate 100 provided by some embodiments of the present disclosure can be prepared and formed by the preparation method of the array substrate provided in some of the above embodiments, because the active layer 51 of the plurality of oxide thin film transistors 5 is combined with the above at least one The oxide semiconductor film 3 directly in contact with the wire 2 is obtained by patterning, and the at least one wire 2 has good conductivity. Therefore, the static electricity generated in the oxide semiconductor film 3 can be released into the at least one wire 2 through the At least one wire 2 is led out to avoid the accumulation of static electricity in the oxide semiconductor layer 3a including multiple active layers 51, thereby avoiding electrostatic breakdown, and effectively improving the yield of the array substrate 100.
  • the oxide thin film transistor 5 is taken as an example of a bottom-gate oxide thin film transistor.
  • the multiple wires 2 and the gate 52 in each oxide thin film transistor 5 are located on the side of the active layer 51 close to the substrate 1.
  • the plurality of wires 2 and each gate 52 are made of the same material and arranged in the same layer.
  • the “same layer” mentioned in this article refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the above-mentioned multiple conductive lines 2 and each gate 52 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the manufacturing process of the array substrate 100.
  • the array substrate 100 further includes: a gate insulating layer GI disposed between the gate 52 and the active layer 51.
  • the gate 52 belongs to the gate conductive layer Gate
  • the active layer 51 belongs to the oxide semiconductor layer 3a, that is, the gate insulating layer GI is located between the gate conductive layer Gate and the oxide semiconductor layer 3a.
  • the gate conductive layer Gate may further include gate lines.
  • the gate insulating layer GI has at least one via K exposing a portion of the at least one wire 2, that is, the orthographic projection of the at least one via K on the substrate 1 and the at least one via K The orthographic projection of a wire 2 on the substrate 1 at least partially overlaps.
  • a part of the boundary of the orthographic projection of the at least one signal line 2 on the substrate 1 is different from the boundary of the orthographic projection of the at least one via K on the substrate 1 One part coincides.
  • the above-mentioned oxide semiconductor film 3 may be electrically connected to the above-mentioned at least one wire 2 through the at least one via K.
  • the static electricity can be discharged to the at least one wire 2 through the portion of the oxide semiconductor film 3 located in the at least one via K, and then the at least one wire 2 can pass through the at least one wire 2.
  • Export static electricity when static electricity is generated in the oxide semiconductor film 3, the static electricity can be discharged to the at least one wire 2 through the portion of the oxide semiconductor film 3 located in the at least one via K, and then the at least one wire 2 can pass through the at least one wire 2.
  • the array substrate further includes an auxiliary lead 6 directly in contact with the above-mentioned at least one wire 2.
  • auxiliary lead 6 can be set in multiple ways, which can be selected and set according to actual needs.
  • the auxiliary lead 6 may be arranged on the side of the gate insulating layer GI away from the substrate 1, and the auxiliary lead 6 directly contacts the at least one wire 2 through the at least one via K.
  • the auxiliary lead 6 can be used to reduce the resistance of the at least one wire 2, thereby reducing the size of the at least one wire 2 perpendicular to its routing direction, and reducing the space ratio of the at least one wire 2 in the array substrate 100 .
  • the auxiliary lead 6 may have the same material as the source 53 and the drain 54 of the oxide thin film transistor 5 and be arranged in the same layer. In this way, the auxiliary lead 6, the source electrode 53 and the drain electrode 54 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the array substrate 100.
  • the film including the auxiliary lead 6, the source electrode 53 and the drain electrode 54 may be referred to as a source-drain conductive layer SD.
  • the source-drain conductive layer SD may also include data lines, power lines, and the like.
  • the orthographic projection of the auxiliary lead 6 on the substrate 1 and the orthographic projection of the aforementioned at least one wire 2 on the substrate 1 at least partially overlap.
  • the auxiliary lead 6 corresponds to the above-mentioned at least one wire 2 in a one-to-one correspondence.
  • the orthographic projection of the auxiliary lead 6 on the substrate 1 and the corresponding orthographic projection of the wire 2 on the substrate 1 at least partially overlap, which may include: a partial misalignment between the auxiliary lead 6 and the wire 2 so that the auxiliary lead 6 is on the substrate 1 A part of the orthographic projection of the corresponding wire 2 overlaps with a part of the orthographic projection of the corresponding wire 2 on the substrate 1; or, the orthographic projection of the auxiliary lead 6 on the substrate 1 is located on the orthographic projection of the corresponding wire 2 on the substrate 1. Within the projection range.
  • the routing direction of the auxiliary lead 6 is the same or substantially the same as the routing direction of the at least one wire 2 described above. That is, the angle between the routing direction of the auxiliary lead 6 and the routing direction of the at least one wire 2 is 0° or close to 0°. This is beneficial to ensure the effect of reducing the resistance of the at least one wire 2.
  • the array substrate 100 may further include: a passivation layer 7 disposed on the side of the source electrode 53 and the drain electrode 54 away from the substrate 1 (that is, covering each oxide thin film transistor 5) .
  • a part of the passivation layer 7 may be located in at least one via K of the gate insulating layer GI. In this way, it is possible to prevent the subsequently formed conductive layer (for example, the pixel electrode 8) from forming an electrical connection with the above-mentioned at least one wire 2 and avoid signal crosstalk.
  • the array substrate 100 may further include: a pixel electrode 8 disposed on the side of the passivation layer 7 away from the substrate 1.
  • the pixel electrode 8 may be electrically connected to the drain 54 of the oxide thin film transistor 5, for example.
  • the array substrate 100 may further include a planarization layer provided between the passivation layer 7 and the pixel electrode 8.
  • the array substrate 100 has a display area A and a frame area B located beside the display area A.
  • the display area A For the "side”, reference may be made to the schematic description in some of the foregoing examples.
  • the oxide thin film transistor 5 in the array substrate 100 may be located in the display area A.
  • at least one wire 2 electrically connected to the oxide semiconductor thin film 3 may be located in the display area A, or may be located in the frame area B.
  • the at least one wire 2 may be a second common signal that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate.
  • Electrode wire In the case where the above-mentioned at least one wire 2 is located in the frame area B, the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be used to perform processing on the array substrate 100.
  • Electrostatic protection wire for electrostatic protection.
  • the array substrate 100 may include a substrate 1, a plurality of wires 2, a gate conductive layer Gate, a gate insulating layer GI, an oxide semiconductor layer 3a, source and drain conductive layers. Layer SD, passivation layer 7 and a plurality of pixel electrodes 8.
  • the substrate 1 may be a glass substrate.
  • the substrate 1 may have a display area A and a frame area B surrounding the display area A.
  • the above-mentioned multiple wires 2 may be located in the frame area B of the substrate 1.
  • the aforementioned gate conductive layer Gate may be located in the display area A of the substrate 1.
  • the gate conductive layer Gate and the plurality of wires 2 may be arranged on the same side of the substrate 1 and on the same surface, for example, the two materials are the same and arranged in the same layer.
  • the gate conductive layer Gate may include a plurality of gate lines and a plurality of gates 52 for forming the oxide thin film transistor 5.
  • the gate insulating layer GI may be disposed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1.
  • the gate insulating layer GI has at least one via K, and the at least one via K exposes at least one wire 2 of the plurality of wires 2, that is, the orthographic projection of the gate insulating layer GI on the substrate 1 and the at least one wire 2
  • the orthographic projections of the wires 2 on the substrate 1 partially overlap.
  • the oxide semiconductor layer 3a may be provided on the side of the gate conductive layer Gate away from the substrate 1.
  • the oxide semiconductor layer 3a includes a plurality of active layers 51 for forming oxide thin film transistors 5, and the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 is the same as the orthographic projection of the at least one wire 2 on the substrate 1.
  • the projections do not overlap at all.
  • the oxide semiconductor layer 3 a is obtained by patterning the oxide semiconductor thin film 3 a directly in contact with the at least one wire 2.
  • the source-drain conductive layer SD may be provided on the side of the oxide semiconductor layer 3a away from the substrate 1.
  • the source-drain conductive layer SD may include an auxiliary lead 6 electrically connected to the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI, a plurality of source and drain layer leads (such as data lines), and each oxide thin film transistor 5 The source 53 and drain 54 and so on.
  • the auxiliary lead 6 can be arranged in the frame area B, and the source and drain layer leads, the source electrode 53 and the drain electrode 54 are arranged in the display area A.
  • the passivation layer 7 may be formed on the side of the source and drain conductive layer SD away from the substrate 1.
  • the passivation layer 7 may, for example, cover the source-drain conductive layer SD and retain a part of the drain 54 in the source-drain conductive layer SD.
  • a plurality of pixel electrodes 8 may be arranged on the side of the passivation layer 7 away from the substrate 1.
  • the plurality of pixel electrodes 8 may be electrically connected to the plurality of drain electrodes 54 in a one-to-one correspondence.
  • the array substrate 100 of the present disclosure can be prepared by the preparation method of the array substrate provided in some of the above-mentioned embodiments, and the structure, principle and effect of the array substrate 100 have been compared with the preparation method of the array substrate provided in some of the above-mentioned embodiments It is described in detail in, so I won’t repeat it here.
  • Some embodiments of the present disclosure also provide a display device 1000. As shown in FIGS. 8 and 9, the display device 1000 further includes the array substrate 100 as described in some of the above embodiments.
  • the beneficial effects that can be achieved by the display device 1000 provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 100 provided in some of the foregoing embodiments, and will not be repeated here.
  • the display device 1000 may be an LCD. At this time, the display device 1000 may further include a counter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.
  • the above-mentioned counter substrate 200 may be a transparent substrate, or may also be a color filter substrate (as shown in FIG. 8).
  • the array substrate 100 may further include a color filter layer and/or a black matrix disposed on the side of the pixel electrode 8 close to the counter substrate 200.
  • the display device 1000 may be an OLED display device. At this time, the display device 1000 may further include: a plurality of light-emitting devices 400 arranged on a side of the array substrate 100 away from the substrate 1 with a plurality of oxide thin film transistors 5.
  • the pixel electrode 8 in the array substrate 100 may be referred to as the anode layer of the light emitting device 400.
  • the light-emitting device 400 may further include a light-emitting layer and a cathode layer that are sequentially stacked on the side of the anode layer away from the substrate 1.
  • the above-mentioned display device 1000 may be any device that displays whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (Personal Digital Assistants).
  • electronic devices such as (but not limited to) mobile phones, wireless devices, and personal data assistants (Personal Digital Assistants).
  • PDA Personal Digital Assistant
  • handheld or portable computer Global Positioning System (GPS) receiver/navigator
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Abstract

一种阵列基板的制备方法，包括：提供衬底。在所述衬底上形成多条导线。在所述多条导线远离所述衬底的一侧形成氧化物半导体薄膜；所述氧化物半导体薄膜覆盖所述多条导线并与至少一条信号线直接接触；所述至少一条导线被配置为，导出所述氧化物半导体薄膜中产生的静电。采用光刻工艺，对所述氧化物半导体薄膜进行图案化处理，去除与所述至少一条导线直接接触的部分，形成包括多个氧化物薄膜晶体管的有源层的氧化物半导体层。

Description

阵列基板及其制备方法、显示装置
本申请要求于2019年09月25日提交的、申请号为201910913692.1的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示装置。
背景技术
氧化物薄膜晶体管使用氧化物半导体材料作为有源层，其具有良好的均一性，尤其适用于大面积显示的需求。
发明内容
一方面，提供一种阵列基板的制备方法。所述阵列基板的制备方法包括：提供衬底；在所述衬底的一侧形成多条导线；在所述多条导线远离所述衬底的一侧形成氧化物半导体薄膜，所述氧化物半导体薄膜覆盖所述多条导线并与至少一条导线直接接触；所述至少一条导线被配置为，导出所述氧化物半导体薄膜中产生的静电；采用光刻工艺，对所述氧化物半导体薄膜进行图案化处理，去除与所述至少一条导线直接接触的部分，形成包括多个氧化物薄膜晶体管的有源层的氧化物半导体层。
在一些实施例中，所述阵列基板的制备方法，还包括：在形成所述氧化物半导体薄膜之前，形成包括多个氧化物薄膜晶体管的栅极的栅导电层；所述栅导电层与所述多条导线位于所述衬底的同一侧。在所述多条导线和所述栅导电层远离所述衬底的一侧形成栅绝缘薄膜；所述栅绝缘薄膜覆盖所述多条导线和所述栅导电层。对所述栅绝缘薄膜进行图案化处理，形成具有至少一个过孔的栅绝缘层；所述至少一个过孔暴露所述至少一条导线的至少一部分表面，所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠。其中，所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。
在一些实施例中，沿垂直于所述至少一条导线的走线方向，所述至少一条导线在所述衬底上的正投影边界的一部分，与所述至少一个过孔在所述衬底上的正投影边界的一部分重合。
在一些实施例中，所述多条导线的材料包括金属材料；所述多条导线和所述栅导电层在同一次构图工艺中形成。
在一些实施例中，所述阵列基板的制备方法，还包括：在所述氧化物半 导体层远离所述衬底的一侧形成源漏导电层，所述源漏导电层包括与每个有源层直接接触的源极和漏极，以及与所述至少一条导线直接接触的辅助引线。
在一些实施例中，所述阵列基板具有显示区和位于所述显示区旁侧的边框区。所述辅助引线位于所述边框区。所述至少一条导线被配置为，向所述显示区传输公共电压信号，或对所述阵列基板进行静电防护。所述辅助引线被配置为，与所述至少一条导线形成并联，降低所述至少一条导线的电阻。
在一些实施例中，所述氧化物半导体薄膜的材料包括氧化锌、氧化铟、氧化锡、铟锌氧化物、氧化锌锡、氧化铝锌、氧化钇锌、氧化铟锡锌、铟镓锌氧化物和铟铝锌氧中的一种。
在一些实施例中，所述氧化物半导体层在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至多部分重叠。
另一方面，提供一种阵列基板。所述阵列基板包括：衬底；设置在所述衬底一侧的多条导线；以及，多个氧化物薄膜晶体管，所述多个氧化物薄膜晶体管与所述多条导线设置在所述衬底的同一侧。其中，每个氧化物薄膜晶体管包括栅极、有源层、源极和漏极；所述多个氧化物薄膜晶体管的有源层为通过对与至少一条导线直接接触的氧化物半导体薄膜进行图案化处理而获得的，且所述有源层与所述至少一条导线相互绝缘。
在一些实施例中，所述阵列基板，还包括：设置在所述栅极与所述有源层之间的栅绝缘层。所述栅绝缘层具有至少一个过孔，所述至少一个过孔暴露所述至少一条导线的至少一部分表面，所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠。所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。
在一些实施例中，所述阵列基板，还包括：设置在所述栅绝缘层远离所述衬底一侧的辅助引线。所述辅助引线通过所述至少一个过孔与所述至少一条导线直接接触。
在一些实施例中，所述阵列基板，还包括：与所述源极和所述漏极材料相同且同层设置的辅助引线。所述辅助引线与所述至少一条导线直接接触。
在一些实施例中，所述辅助引线在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠。
在一些实施例中，所述辅助引线的走线方向与所述至少一条导线的走线方向相同或大致相同。
在一些实施例中，所述阵列基板，还包括：设置在所述源极和所述漏极远离所述衬底一侧的钝化层。所述钝化层中的一部分位于所述至少一个过孔 内，并与所述至少一条导线直接接触。
在一些实施例中，所述阵列基板具有显示区和位于所述显示区旁侧的边框区。所述至少一条导线位于所述边框区。所述至少一条导线包括公共电极线或静电防护线。所述公共电极线被配置为，向所述显示区传输公共电压信号；所述静电防护线被配置为，对所述阵列基板进行静电防护。
在一些实施例中，所述栅极和所述多条导线材料相同且同层设置。
又一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的阵列基板。
在一些实施例中，所述显示装置，还包括：与所述阵列基板相对设置的对置基板；以及，设置在所述阵列基板和所述对置基板之间的液晶层。
在一些实施例中，所述显示装置，还包括：设置在所述阵列基板的多个氧化物薄膜晶体管远离所述阵列基板的衬底一侧的多个发光器件。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术中的一种氧化物半导体薄膜中累积静电的结构图；
图2为根据本公开的一些实施例中的一种阵列基板的制备方法的流程图；
图3为根据本公开的一些实施例中的另一种阵列基板的制备方法的流程图；
图4a～图4g为根据本公开一些实施例中的一种阵列基板的制备流程的示意图；
图5a～图5l为图4a～图4g所示制备流程中沿O-O＇向的一种制备流程的示意图；
图6为根据本公开一些实施例中的一种阵列基板的结构图；
图7为根据本公开一些实施例中的另一种阵列基板的结构图；
图8为根据本公开一些实施例中的一种显示装置的结构图；
图9为根据本公开一些实施例中的另一种显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地 描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通 技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，例如可以采用光刻工艺制备形成氧化物薄膜晶体管的有源层。
也即，在形成氧化物薄膜晶体管的有源层的过程中，可以先沉积一层氧化物半导体材料薄膜，然后在氧化物半导体材料薄膜的一侧表面上形成光刻胶层，通过对该光刻胶层进行曝光、显影，得到图案化后的光刻胶层，便可以利用该图案化后的光刻胶层对氧化物半导体材料薄膜进行图案化处理，得到有源层。
然而，氧化物半导体材料薄膜在曝光机内容易产生并累积静电，进而可能出现静电击穿(Electro-Static discharge，简称ESD)现象，降低包括氧化物薄膜晶体管的阵列基板的良率。
在一种实现方式中，以氧化物薄膜晶体管为底栅型薄膜晶体管为例，如图1所示，在制备氧化物薄膜晶体管的过程中，例如可以先形成多个栅极1＇，然后在该多个栅极1＇的一侧依次形成覆盖该多个栅极1＇的栅绝缘层2＇以及覆盖该栅绝缘层2＇的氧化物半导体材料薄膜3＇，然后再采用光刻工艺对该氧化物半导体材料薄膜3＇进行图案化处理。
由于氧化物半导体材料通常为非晶结构的物质，其导电性能较差，在曝光机内对光刻胶层进行曝光的过程中，氧化物半导体材料薄膜3＇内容易产生静电。不仅如此，氧化物半导体材料薄膜3＇还可以与其他导电结构之间形成寄生电容结构，例如氧化物半导体材料薄膜3＇可以与栅极1＇之间形成寄生电容结构，并诱导不同的栅极1＇之间形成寄生电容结构。在氧化物半导体材料薄膜3＇中产生的静电大量累积的情况下，容易出现静电击穿现象。
基于此，本公开的一些实施例提供了一种阵列基板的制备方法。如图2所示，该阵列基板的制备方法包括：S100～S400。
S100，提供衬底1。
上述衬底1的材料包括多种，可以根据实际需要选择设置。
在一些示例中，上述衬底1可以为无机材料的衬底，也可以为有机材料的衬底。
举例而言，在本公开的一种实施方式中，衬底1的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等材料，或者可以为不锈钢、铝、镍等材料。在本公开的另一种实施方式中，衬底1的材料可以为聚甲基丙烯酸甲酯(Polymethyl methacrylate，简称PMMA)、聚乙烯醇(Polyvinyl alcohol，简称PVA)、聚乙烯基苯酚(Polyvinyl phenol，简称PVP)、聚醚砜(Polyether sulfone，简称PES)、聚酰亚胺(Polyimide，简称PI)、聚酰胺、聚缩醛、聚碳酸酯(Poly carbonate，简称PC)、聚对苯二甲酸乙二酯(Polyethylene terephthalate，简称PET)、聚萘二甲酸乙二酯(Polyethylene naphthalate，简称PEN)或其中至少两者的组合等。
此处，在衬底1采用无机材料的情况下，衬底1可以为刚性衬底；在衬底1采用有机材料的情况下，衬底1可以为柔性衬底。
S200，如图4a和图5a所示，在衬底1上形成多条导线2。
在一些示例中，上述导线2的材料可以包括一种导电材料或者多种导电材料的组合。
示例性的，导线2的材料可以包括金属材料、导电金属氧化物材料、导电金属氮化物材料、导电高分子材料、导电复合材料或者其中至少两者的组合等。
可选的，上述金属材料例如可以为铂、金、银、铝、铬、镍、铜、钼、钛、镁、钙、钡、钠、钯、铁、锰或其中至少两者的组合等。
可选的，上述导电金属氧化物材料例如可以为铟锡氧化物(Indium tin oxide，简称ITO)、掺氟的氧化锡(Fluorine tin oxide，简称FTO)金属氧化物或者掺杂的金属氧化物。
可选的，上述导电金属氮化物材料例如可以为氮化钛等。
可选的，上述导电高分子材料例如可以是聚苯胺、聚吡咯、聚噻吩、聚乙炔、聚(3,4-伸乙基二氧噻吩)/聚苯乙烯磺酸(PEDOT/PSS)或其中至少两者的组合等，或者掺杂有掺杂剂的上述材料；其中，掺杂剂例如可以为盐酸、硫酸、磺酸等酸，或PF6、AsF5、FeCl3等路易斯酸，或碘离子等卤素离子，或钠离子、钾离子等金属离子。
可选的，上述导电复合材料例如可以是分散有碳黑、石墨粉或金属微粒子等的导电复合材料。
在一些示例中，上述导线2可以为由一层导电材料组成的单层结构，也可以为由多层导电材料依次层叠而形成的多层结构。
例如，本公开中的导线2可以为由一层金属材料形成的单层结构。
又如，本公开中的导线2可以为由依次层叠的第一金属层、第二金属层和第一金属层所形成的三层结构。其中，第一金属层可以为由至少一种金属材料形成的单层结构，第二金属层可以为由至少一种金属材料形成的单层结构，第一金属层所包括的金属材料和第二金属层所包括的金属材料不同。
S300，如图4d和图5d所示，在上述多条导线2远离衬底1的一侧形成氧化物半导体薄膜3。该氧化物半导体薄膜3覆盖该多条导线2并与至少一条导线2直接接触。也即，氧化物半导体薄膜3可以与一条导线2直接接触，也可以与多条导线2直接接触。该至少一条导线2被配置为，导出氧化物半导体薄膜3中产生的静电。
在一些示例中，例如可以采用磁控溅射等工艺制备形成上述氧化物半导体薄膜3。
在一些示例中，上述氧化物半导体薄膜3的材料可以为非晶态氧化物半导体材料。
举例而言，该氧化物半导体材料例如可以为氧化锌(ZnO)、氧化铟(InO)、氧化锡(SnO)、铟锌氧化物(Indium zinc oxide，简称IZO)、氧化锌锡(ZTO)、氧化铝锌(AZO)、氧化钇锌(YZO)、氧化铟锡锌(Indium tin zinc oxide，简称ITZO)、铟镓锌氧化物(Indium gallium zinc oxide，简称IGZO)、铟铝锌氧(Indium aluminum zinc oxide，简称IAZO)中的一种。可选的，上述氧化物半导体材料可以呈非晶态，也即上述氧化物半导体材料可以为非晶态氧化物半导体材料。
示例性的，上述氧化物半导体薄膜3可以为非晶态铟镓锌氧化物薄膜。
S400，如图4e和图5i所示，对氧化物半导体薄膜3进行图案化处理，去除与上述至少一条导线2直接接触的部分，形成包括多个氧化物薄膜晶体管5的有源层51的氧化物半导体层3a。该氧化物半导体层3a与上述至少一条导线2相互绝缘。
在一些示例中，在上述S400中，例如可以采用光刻工艺对氧化物半 导体薄膜3进行图案化处理。
示例性的，如图5e～图5i所示，采用光刻工艺对氧化物半导体薄膜3进行图案化处理，包括：S410～S450。
S410，如图5e所示，在氧化物半导体薄膜3远离衬底1的一侧表面形成一光刻胶层PR。
示例性的，可以采用涂覆工艺将光刻胶涂覆在氧化物半导体薄膜3远离衬底1的一侧表面上，形成光刻胶层PR。
上述光刻胶的类型包括多种，例如，上述光刻胶可以为正性光刻胶，或者，上述光刻胶可以为负性光刻胶。
下面，以光刻胶为正性光刻胶为例对阵列基板的制备方法进行示意性说明。
S420，如图5f所示，对上述光刻胶层PR进行曝光。
示例性的，可以在曝光机中对光刻胶层PR进行曝光。
示例性的，在对光刻胶层PR进行曝光的过程中，氧化物半导体薄膜3中会产生静电。在该氧化物半导体薄膜3与至少一条导线2电连接的情况下，氧化物半导体薄膜3中所产生的静电可以释放至该至少一条导线2中，通过该至少一条导线2对静电进行导出，减少甚至避免出现氧化物半导体薄膜3中静电累积的情况，进而避免出现因氧化物半导体薄膜3中大量累积的静电而导致的静电击穿现象。
S430，如图5g所示，对曝光后的光刻胶层PR进行显影，去除上述光刻胶层PR中被曝光的部分，得到图案化后的光刻胶层PR＇。图案化后的光刻胶层PR＇暴露部分氧化物半导体薄膜3远离衬底1的一侧表面，并覆盖其余部分氧化物半导体薄膜3。
S440，如图5h所示，以图案化后的光刻胶层PR＇为掩膜，对氧化物半导体薄膜3进行图案化处理，刻蚀去除氧化物半导体薄膜3中未被图案化后的光刻胶层PR＇覆盖的部分，保留氧化物半导体薄膜3中被图案化后的光刻胶层PR＇覆盖的部分，也即为氧化物半导体层3a。
可以理解的是，氧化物半导体层3a在衬底1上的正投影与上述至少一条导线2在衬底1上的正投影至多部分重叠，且氧化物半导体层3a与该至少一条导线2相互绝缘。如此，可以保证该至少一条导线2与后续制备形成的薄膜之间的有效电连接，避免了因氧化物半导体层3a夹设于该至少一条导线2与后续制备形成的薄膜之间而导致的供电不良情况，又可以避免增加额外的工序以去除覆盖该至少一条导线2的氧化物半导 体层3a的部分。
S450，如图5i所示，去除图案化后的光刻胶层PR＇。
本公开的一些实施例所提供的阵列基板的制备方法，通过在衬底1的一侧形成多条导线2，并在形成氧化物半导体薄膜3之后，使得该氧化物半导体薄膜3与至少一条导线2直接接触，这样在对氧化物半导体薄膜3进行图案化处理的过程中，氧化物半导体薄膜3中产生的静电便可以释放至具有良好的导电性的至少一条导线2中，进而有利于降低包括多个有源层51的氧化物半导体层3a上的静电累积，避免产生静电击穿的现象，提高所制备的阵列基板的良率。
需要说明的是，所形成的阵列基板中的薄膜晶体管5的类型包括多种，可以根据实际需要选择设置。
在一些实施方式中，所形成的阵列基板中的氧化物薄膜晶体管5可以为底栅型氧化物薄膜晶体管。在其他实施方式中，所形成的阵列基板中的氧化物薄膜晶体管5可以为顶栅型的氧化物薄膜晶体管。
下面，以所形成的阵列基板中的氧化物薄膜晶体管5为底栅型氧化物薄膜晶体管为例，对阵列基板的制备方法进行示意性说明。如图4a～图4c以及图5a～图5c所示，阵列基板的制备方法还可以包括：S210～S230。
S210，如图4a和图5a所示，在上述S300之前，形成栅导电层Gate。该栅导电层Gate与上述多条导线2位于衬底1的同一侧。
示例性的，上述栅导电层Gate可以包括多条栅极线和多个氧化物薄膜晶体管5的栅极52。每个栅极52可以与后续制备形成的有源层51相对设置。
在一些示例中，上述栅导电层Gate的材料以及层级结构，可以与该多条导线2相同，也可以不相同。
在本公开的一种实施方式中，栅导电层Gate和该多条导线2可以设于同一表面、且具有同样的结构和材料，也即，栅导电层Gate和该多条导线2可以在同一次构图工艺中制备形成。
举例而言，可以通过如下方法形成栅导电层Gate和多条导线2：
在衬底1的一侧形成一栅导电材料薄膜；然后对该栅导电材料薄膜进行图案化处理，同时形成该多条导线2和栅导电层Gate。
可选的，可以通过光刻工艺对上述栅导电材料薄膜进行图案化处理。
S220，如图4b和图5b所示，在上述多条导线2和栅导电层Gate远离衬底1的一侧形成栅绝缘薄膜GI＇。该栅绝缘薄膜GI＇覆盖栅导电层 Gate和多条导线2。
可选的，栅绝缘薄膜GI＇的材料可以为氧化硅、氮氧化硅、氮化硅或者其他绝缘材料等。栅绝缘薄膜GI＇例如可以采用PECVD(Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积)工艺制备形成。
S230，如图4c和图5c所示，对栅绝缘薄膜GI＇进行图案化处理，形成具有至少一个过孔K的栅绝缘层GI。该至少一个过孔K暴露上述至少一条导线2的至少一部分表面，该至少一个过孔K在衬底1上的正投影与上述至少一条导线2在衬底1上的正投影至少部分重叠。其中，氧化物半导体薄膜3通过该至少一个过孔K与该至少一条导线2直接接触。
示例性的，可以通过光刻工艺对栅绝缘薄膜GI＇进行图案化处理，得到栅绝缘层GI。
可选的，栅绝缘层GI覆盖栅导电层Gate。上述至少一个过孔K在衬底1上的正投影与上述至少一条导线2在衬底1上的正投影至少部分重叠，也即，该至少一个过孔K暴露该至少一条导线2的一部分。其中，过孔K的数量可以为一个，也可以为多个。
此处，上述至少一个过孔K与上述至少一条导线2之间的关系包括多种，可以根据实际需要选择设置。
示例性的，上述至少一个过孔K与上述至少一条导线2可以一一对应，也即，一个过孔K可以暴露一条导线2的一部分。
示例性的，在该至少一个过孔K的数量为多个的情况下，一条导线2可以与该多个过孔K中的至少两个过孔K相对应，也即，该至少两个过孔K中，每个过孔K均可以暴露相应的一条导线2的一部分。
示例性的，在该至少一条导线2的数量为多条的情况下，一个过孔K可以与该多条导线2中的至少两条导线2相对应，也即，该过孔K同时暴露该至少两条导线2的一部分。
相应的，在上述S300中，所形成的氧化物半导体薄膜3便可以通过该至少一个过孔K与该至少一条导线2直接接触。在上述S400中，在对氧化物半导体薄膜3进行图案化处理的过程中，氧化物半导体薄膜3中所产生的静电，便可以通过该氧化物半导体薄膜3位于该至少一个过孔K内的部分释放至该至少一条导线2，通过该至少一条导线2导出。
此外，在上述S400中，在形成氧化物半导体层3a后，可以使得氧化物半导体层3a暴露该至少一个过孔K，进而暴露该至少一条导线2的 一部分。换言之，在对氧化物半导体薄膜3进行图案化处理后，可以使得所形成的氧化物半导体层3a在衬底1上的正投影与该至少一个过孔K在衬底1上的正投影不交叠，完全去除该至少一个过孔K中的氧化物半导体材料。
在本公开的一种实施方式中，如图5c所示，沿垂直于上述至少一条导线2的走线方向，该至少一条导线2在衬底1上的正投影边界的一部分，与上述至少一个过孔K在衬底1上的正投影边界的一部分重合，也即，沿垂直于该至少一条导线2的走线方向，该至少一个过孔K完全暴露该至少一条导线2，这样可以使得该至少一条导线2能够与氧化物半导体薄膜3之间具有较大的接触面积，提高氧化物半导体薄膜3中的静电电荷的扩散效率。
在一些实施例中，上述阵列基板的制备方法还可以包括制备氧化物薄膜晶体管5的源极53和漏极54。举例而言，阵列基板的制备方法还可以包括：S500。
S500，如图4f和图5k所示，在氧化物半导体层3a远离衬底1的一侧形成源漏导电层SD。其中，该源漏导电层SD可以包括多个源极52和多个漏极53，多个源极52与多个有源层51一一对应的电连接，多个漏极53与多个有源层51一一对应的电连接。
可以理解的是，一个氧化物薄膜晶体管5中，可以包含有一个有源层51、一个源极52和一个漏极53。
可选的，如图4f和图5k所示，源漏导电层SD中，还可以包括辅助引线6，辅助引线6与上述至少一条导线2电连接。例如，辅助引线6与上述至少一条导线2可以一一对应地直接接触，形成电连接。
通过将辅助引线6和上述至少一条导线2电连接，可以利用辅助引线6降低与其电连接的导线2的电阻，提高该导线2中所传输的电信号的稳定性。不仅如此，由于利用辅助引线6可以降低与其电连接的导线2的电阻，这样可以减小该导线2的线宽(也即该导线2在垂直于其走线方向上的尺寸)，进而可以减小该导线2在阵列基板中的空间占比。
在本公开的一种实施方式中，可以通过如下方法形成源漏导电层SD。
示例性的，如图5j所示，可以在氧化物半导体层3a远离衬底1的一侧形成一源漏导电材料薄膜SD＇，该源漏导电材料薄膜SD＇覆盖上述至少一条导线2中被至少一个过孔K暴露的部分、栅绝缘层GI未被 有源层51覆盖的部分、以及有源层51。
可选的，源漏导电材料薄膜SD＇的材料可以为钛(Ti)、铂(Pt)、钌(Ru)、金(Au)、银(Ag)、钼(Mo)、铝(Al)、钨(W)、铜(Cu)、钕(Nd)、铬(Cr)、钽(Ta)或其合金或上述至少两种材料的组合。源漏导电材料薄膜SD＇可以为由一层导电材料形成的单层结构，也可以为由多层依次层叠的导电材料所形成的多层结构。
可选的，可以采用溅射工艺形成源漏导电材料薄膜SD＇。
示例性的，如图5k所示，可以对源漏导电材料薄膜SD＇进行图案化处理，形成包括辅助引线6、源极53和漏极54的源漏导电层SD。
可选的，可以通过光刻工艺对源漏导电材料薄膜SD＇进行图案化处理。
可选的，源漏导电层SD还可以包括源漏层引线，例如包括电压引线和数据线等。
可选的，辅助引线6和与其电连接的导线2在衬底1上的正投影，可以相互重合或者可以部分重叠。
在一些实施例中，如图4g和图5l所示，所形成的阵列基板100可以具有显示区A和位于该显示区A旁侧的边框区B。相应的，衬底1也具有边框区B和显示区A。其中，阵列基板100的边框区B在衬底1上的正投影与衬底1的边框区B重合，阵列基板100的显示区A在衬底1上的正投影与衬底1的显示区A重合。
示例性的，旁侧指的是，显示区A的一侧、两侧、三层或者周侧(如图4g所示)等。这也就意味着，边框区B可以位于显示区A的一侧、两侧或三侧，或者，边框区B可以围绕显示区A。
在一些示例中，如图4g和图5l所示，与氧化物半导体薄膜3直接接触的至少一条导线2可以形成于阵列基板100的边框区B。此时，该至少一条导线2可以为用于向显示区A提供公共电压信号的第一公共电极线，或者，也可以为用于对阵列基板100进行静电防护的静电防护线。
上述至少一条导线2在垂直于其走线方向上，可以具有较大的尺寸以，以保证其具有较小的阻抗，进而确保其所传输的电信号的稳定性。，通过将上述至少一条导线2与辅助引线6电连接，可以降低该至少一条导线2的电阻，进而可以减小该至少一条导线2的线宽，这样有利于减小边框区B的尺寸，使得阵列基板100能够实现窄边框设计。
在另一些示例中，与氧化物半导体薄膜3直接接触的至少一条导线 2可以形成于阵列基板100的显示区A。此时，该至少一条导线2可以为向阵列基板中的电极层(例如公共电极层或阴极层)传输公共电压信号的第二公共电极线。
在一些实施例中，如图5l所示，本公开的阵列基板的制备方法还可以包括：在氧化物薄膜晶体管5远离衬底1的一侧形成钝化层(PVX)7。如图4g和图5l所示，在钝化层7远离衬底1的一侧形成多个像素电极8，且该多个像素电极8分别与多个氧化物薄膜晶体管5的源极53或漏极54一一对应的电连接。
进一步地，如图5l所示本公开的阵列基板的制备方法还可以包括：在形成像素电极8之前，形成覆盖钝化层7的平坦化层，以能够为像素电极8提供平坦的表面。此处，像素电极8可以形成于平坦化层远离衬底1的一侧表面上。
基于此，制备形成的阵列基板100可以应用于LCD(Liquid Crystal Display，液晶显示装置)。此时，阵列基板100的制备方法还可以包括：在像素电极8远离衬底1的一侧形成公共电极。
在本公开的一种实施方式中，本公开的阵列基板的制备方法还可以包括：在上述像素电极8远离衬底1的一侧依次形成发光层和阴极层，在上述至少一条导线2为第一公共电极线或第二公共电极线的情况下，阴极层可以与上述至少一条导线2电连接，或者与辅助引线6电连接，或者同时与该至少一条导线2和辅助引线6电连接。
基于此，制备形成的阵列基板可以应用于OLED(Organic Light Emitting Diode，有机发光二极管)显示装置。
下面，示例性地介绍本公开的阵列基板的制备方法的一种实现方式，以便进一步解释和说明本公开的阵列基板的制备方法的原理和效果。该示例性的阵列基板的制备方法如下所示。
示例性的，提供一衬底1。该衬底1为玻璃衬底。其中，衬底1具有显示区A和围绕该显示区A的边框区B。
在衬底1的一侧形成栅导电材料薄膜，该栅导电材料薄膜覆盖衬底1的显示区A和边框区B。可以通过沉积的方法形成上述栅导电材料薄膜，例如可以通过磁控溅射沉积的方法形成栅导电材料薄膜。
示例性的，如图4a和图5a所示，对栅导电材料薄膜进行图案化处理，形成位于显示区A的栅导电层Gate和位于边框区B的多条导线2。其中，栅导电层Gate包括多条栅极线和用于形成氧化物薄膜晶体管5的 多个栅极52；多条导线2包括至少一条用于为显示区提供公共电压信号的公共电极线和/或用于对阵列基板100进行静电防护的静电防护线。
示例性的，如图4b和图5b所示，在上述栅导电层Gate和多条导线2远离衬底1的一侧形成覆盖该栅导电层Gate和多条导线2的栅绝缘薄膜GI＇。可以通过沉积的方法形成栅绝缘薄膜GI＇，例如可以通过化学气相沉积(Chemical Vapor Deposition，简称CVD)的方法形成栅绝缘薄膜GI＇。
示例性的，如图4c和图5c所示，借助掩膜板，对栅绝缘薄膜GI＇进行图案化处理，形成具有至少一个过孔K的栅绝缘层GI。该至少一个过孔K暴露至少一条导线2的一部分。可选的，沿垂直于该至少一条导线2的走线方向，该至少一条导线2在衬底1上的正投影边界的一部分，与该至少一个过孔K在衬底1上的正投影边界的一部分重合。可以理解的是，掩膜板可以具有用于在边框区B形成至少一个过孔K的图案。
示例性的，如图4d和图5d所示，在栅绝缘层GI远离衬底1的一侧形成氧化物半导体薄膜3。该氧化物半导体薄膜3同时位于显示区A和边框区B。其中，氧化物半导体薄膜3通过栅绝缘层GI中的至少一个过孔K与上述至少一条导线2直接接触。此处，可以通过沉积的方法形成氧化物半导体薄膜3，例如可以通过磁控溅射的方法形成氧化物半导体薄膜3。
示例性的，如图4e和图5e～图5i所示，对氧化物半导体薄膜3进行图案化处理，形成氧化物半导体层3a。其中，氧化物半导体层3a包含有用于形成氧化物薄膜晶体管5的多个有源层51，且氧化物半导体层3a不覆盖上述至少一条导线2。换言之，氧化物半导体层3a在衬底1上的正投影与该至少一条导线2在衬底1上的正投影完全不重叠。
此处，在对氧化物半导体薄膜3进行图案化处理的过程中，可以将包含有氧化物半导体薄膜3的基板传送入曝光机内进行曝光。由于氧化物半导体材料通常为非晶结构的物质，因此其导电性能较差，在曝光机内容易产生静电。由于氧化物半导体薄膜3与上述至少一条导线2直接接触，因此氧化物半导体薄膜3中产生的静电可以释放至上述至少一条导线2上，通过该至少一条导线2导出，降低甚至避免了静电的累积，有效避免了静电击穿(ESD)现象的发生。
在对氧化物半导体薄膜3进行图案化处理后，氧化物半导体薄膜3中位于上述至少一个过孔K上方及内部的部分会被去除，暴露出该上述 至少一条导线2的部分表面。
示例性的，如图5j所示，在氧化物半导体层3a远离衬底1的一侧形成源漏导电薄膜材料SD＇，该源漏导电材料薄膜SD＇同时位于显示区A和边框区B。也即，该源漏导电材料薄膜SD＇覆盖暴露的至少一条导线2、栅绝缘层GI未被有源层51覆盖的部分、以及有源层51。可以通过沉积的方法形成源漏导电材料薄膜SD＇，例如可以通过磁控溅射的方法形成源漏导电材料薄膜SD＇。
示例性的，如图4f和图5k所示，对源漏导电材料薄膜SD＇进行图案化处理，形成源漏导电层SD。其中，源漏导电层SD包括位于边框区B且与上述至少一条导线2通过过孔K直接接触的辅助引线6，以及位于显示区A的、多条数据线和各个氧化物薄膜晶体管5的源极53和漏极54等。
上述辅助引线6可以与上述至少一条导线2并联，降低该至少一条导线2的电阻，这样不仅可以提高该至少一条导线2中所传输的电信号的稳定性，还可以减小该至少一条导线2在垂直于其走线方向上的尺寸，进而有利于减小边框区B的尺寸，有利于实现阵列基板100的窄边框设计。
示例性的，如图5l所示，在源漏导电层SD远离衬底1的一侧，依次形成钝化层7(PVX)和平坦化层。
示例性的，如图4g和图5l所示，在平坦化层远离衬底1的一侧形成多个像素电极8，其中，该多个像素电极8分别与多个氧化物薄膜晶体管5的漏极54电连接。其中，像素电极8的材料例如可以为ITO。
更进一步的，示例性的阵列基板的制备方法还可以包括：在像素电极8远离衬底1的一侧，依次形成发光层和阴极层，其中阴极层延伸至边框区B并与辅助引线6直接接触形成电连接。此处，与辅助引线电连接的导线2可以为公共电极线。在阴极层远离衬底1的一侧，形成保护层。
需要说明的是，尽管在附图中以特定顺序描述了本公开中方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等，均应视为本公开的一部分。
本公开的一些实施例还提供了一种阵列基板100。如图6所示，该 阵列基板100可以包括衬底1、多条导线2和多个氧化物薄膜晶体管5。
在一些示例中，衬底1的材料可以参考上述一些实施例中的示意性说明，此处不再赘述。
在一些示例中，如图6所示，上述多个氧化物薄膜晶体管5与多条导线2设置于衬底1的同一侧。
示例性的，每个氧化物薄膜晶体管5包括有源层51、栅极52、源极53和漏极54。任一氧化物薄膜晶体管5的有源层51为通过对与至少一条导线2直接接触的氧化物半导体薄膜3进行图案化处理而获得的(例如可以参照上述一些实施例中提供的阵列基板的制备方法)，且任一氧化物薄膜晶体管5的有源层51与该至少一条导线2相互绝缘。
上述有源层51的材料包括多种。示例性的，有源层51的材料可以为氧化物半导体材料。可选的，该氧化物半导体材料可以为非晶态氧化物半导体材料。例如，该非晶态氧化物半导体材料可以为氧化锌、氧化铟、氧化锡、铟锌氧化物、氧化锌锡、氧化铝锌、氧化钇锌、氧化铟锡锌、铟镓锌氧化物和铟铝锌氧中的一种。
本公开的一些实施例所提供的阵列基板100，可以通过上述一些实施例中提供的阵列基板的制备方法制备形成，由于上述多个氧化物薄膜晶体管5的有源层51为通过与上述至少一条导线2直接接触的氧化物半导体薄膜3进行图案化获得的，且该至少一条导线2具有良好的导电性，因此氧化物半导体薄膜3中产生的静电可以释放至该至少一条导线2中，通过该至少一条导线2导出，避免包括有多个有源层51的氧化物半导体层3a中形成静电累积，进而可以避免产生静电击穿现象，可以有效提高阵列基板100的良率。
下面结合附图对本公开的一些实施例中所提供的阵列基板100的结构进行示意性说明。
此处，如图6所示，以氧化物薄膜晶体管5为底栅型氧化物薄膜晶体管为例。
基于此，上述多条导线2和每个氧化物薄膜晶体管5中的栅极52，位于有源层51靠近衬底1的一侧。
在一些示例中，上述多条导线2和各栅极52的材料相同且同层设置。
需要说明的是，本文中提及的“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、 显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以在一次构图工艺中，同时制备形成上述多条导线2和各栅极52，有利于简化阵列基板100的制备工艺。
在一些实施例中，阵列基板100还包括：设置在栅极52和有源层51之间的栅绝缘层GI。此处，栅极52属于栅导电层Gate，有源层51属于氧化物半导体层3a，也就是说，栅绝缘层GI位于栅导电层Gate与氧化物半导体层3a之间。示例性的，栅导电层Gate还可以包括栅极线。
在一些示例中，如图6所示，栅绝缘层GI具有暴露至少一条导线2的一部分的至少一个过孔K，也即，该至少一个过孔K在衬底1上的正投影与该至少一条导线2在衬底1上的正投影至少部分重叠。
示例性的，沿上述至少一条导线2的走线方向，该至少一条信号线2在衬底1上的正投影边界的一部分，与上述至少一个过孔K在衬底1上的正投影边界的一部分重合。
其中，上述氧化物半导体薄膜3可以通过该至少一个过孔K与上述至少一条导线2电连接。这样在氧化物半导体薄膜3中产生静电的情况下，便可以通过氧化物半导体薄膜3的位于该至少一个过孔K内的部分，将静电释放至该至少一条导线2，通过该至少一条导线2导出静电。
在一些示例中，如图6所示，阵列基板还包括与上述至少一条导线2直接接触的辅助引线6。
上述辅助引线6的设置方式包括多种，可以根据实际需要选择设置。
示例性的，如图6所示，辅助引线6可以设置在栅绝缘层GI远离衬底1的一侧，该辅助引线6通过上述至少一个过孔K与上述至少一条导线2直接接触。这样可以利用辅助引线6降低该至少一条导线2的电阻，进而可以降低该至少一条导线2在垂直于其走线方向上的尺寸，减小该至少一条导线2在阵列基板100中的空间占比。
示例性的，如图6所示，辅助引线6可以与氧化物薄膜晶体管5的源极53和漏极54材料相同且同层设置。这样可以在一次构图工艺中，同时制备形成辅助引线6、源极53和漏极54，有利于简化阵列基板100的制备工艺。
此处，例如可以把包括辅助引线6、源极53和漏极54的薄膜称为源漏导电层SD。可选的，该源漏导电层SD还可以包括数据线和电源线等。
在一些示例中，如图6所示，辅助引线6在衬底1上的正投影与上述至少一条导线2在衬底1上的正投影至少部分重叠。
示例性的，辅助引线6与上述至少一条导线2一一对应。辅助引线6在衬底1上的正投影与相应的导线2在衬底1上的正投影至少部分重叠，可以包括：辅助引线6和导线2之间局部错位，使得辅助引线6在衬底1上的正投影的一部分，与相应的导线2在衬底1上的正投影的一部分相重叠；或者，辅助引线6在衬底1上的正投影位于相应的导线2在衬底1上的正投影范围内。
在一些示例中，如图4g所示，辅助引线6的走线方向与上述至少一条导线2的走线方向相同或大致相同。也即，辅助引线6的走线方向与上述至少一条导线2的走线方向之间的夹角为0°或者接近于0°。这样有利于确保对该至少一条导线2的电阻的降低效果。
在一些实施例中，如图6所示，阵列基板100还可以包括：设置在源极53和漏极54远离衬底1一侧(也即覆盖各个氧化物薄膜晶体管5)的钝化层7。
在一些示例中，如图7所示，在阵列基板100未包括辅助引线6的情况下，上述钝化层7以一部分可以位于栅绝缘层GI的至少一个过孔K内。这样可以避免后续形成的导电层(例如像素电极8)与上述至少一条导线2形成电连接，避免出现信号串扰的情况。
在一些实施例中，如图6所示，阵列基板100还可以包括：设置在钝化层7远离衬底1一侧的像素电极8。该像素电极8例如可以与氧化物薄膜晶体管5的漏极54电连接。
可选的，阵列基板100还可以包括：设置在钝化层7和像素电极8之间的平坦化层。
在一些实施例中，如图6所示，阵列基板100具有显示区A和位于该显示区A旁侧的边框区B。其中，关于“旁侧”，可以参照上述一些示例中的示意性说明。
在一些示例中，阵列基板100中的氧化物薄膜晶体管5可以位于显示区A内。上述多条信号线2中，与氧化物半导体薄膜3电连接的至少一条导线2可以位于显示区A，也可以位于边框区B。
此处，在上述至少一条信号线2位于显示区A内的情况下，该至少一条导线2可以为向阵列基板中的电极层(例如公共电极层或阴极层)传输公共电压信号的第二公共电极线。在上述至少一条导线2位于边框 区B的情况下，该至少一条导线2可以为用于向显示区A提供公共电压信号的第一公共电极线，或者，也可以为用于对阵列基板100进行静电防护的静电防护线。
下面，示例性地介绍本公开的阵列基板的一种实现方式，以便进一步解释和说明本公开的阵列基板的结构和原理。
在该示例性地阵列基板100中，如图6所示，该阵列基板100可以包括衬底1、多条导线2、栅导电层Gate、栅绝缘层GI、氧化物半导体层3a、源漏导电层SD、钝化层7和多个像素电极8。
示例性的，衬底1可以为玻璃基板。该衬底1可以具有显示区A和围绕该显示区A的边框区B。
示例性的，上述多条导线2可以位于衬底1的边框区B。上述栅导电层Gate可以位于衬底1的显示区A。栅导电层Gate与该多条导线2可以设置在衬底1的同一侧且位于同一表面，例如，两者材料相同且同层设置。其中，栅导电层Gate可以包括多条栅极线和用于形成氧化物薄膜晶体管5的多个栅极52。
示例性的，栅绝缘层GI可以设置在上述多条导线2和栅导电层Gate远离衬底1的一侧。栅绝缘层GI中具有至少一个过孔K，该至少一个过孔K暴露该多条导线2中的至少一条导线2，也即，栅绝缘层GI在衬底1上的正投影与该至少一条导线2在衬底1上的正投影部分重叠。
示例性的，氧化物半导体层3a可以设置在栅导电层Gate远离衬底1的一侧。该氧化物半导体层3a包括用于形成氧化物薄膜晶体管5的多个有源层51，且氧化物半导体层3a在衬底1上的正投影与上述至少一条导线2在衬底1上的正投影完全不重合。其中，氧化物半导体层3a为通过对与该至少一条导线2直接接触的氧化物半导体薄膜3a进行图案化处理而获得的。
示例性的，源漏导电层SD可以设置在氧化物半导体层3a远离衬底1的一侧。源漏导电层SD可以包括与上述至少一条导线2通过栅绝缘层GI中的至少一个过孔K电连接的辅助引线6、多条源漏层引线(例如数据线)、各个氧化物薄膜晶体管5的源极53和漏极54等。其中，辅助引线6可以设置在边框区B内，源漏层引线、源极53和漏极54设置在显示区A。
示例性的，钝化层7可以形成在源漏导电层SD远离衬底1的一侧。该钝化层7例如可以覆盖源漏导电层SD，并保留该源漏导电层SD中漏 极54的一部分。
示例性的，多个像素电极8可以设置在钝化层7远离衬底1的一侧。该多个像素电极8可以分别与多个漏极54一一对应地电连接。
由于本公开的阵列基板100可以通过上述一些实施例中所提供的阵列基板的制备方法进行制备，且阵列基板100的结构、原理和效果已经在上述一些实施例中所提供的阵列基板的制备方法中进行了详细描述，在此不再赘述。
本公开的一些实施例还提供了一种显示装置1000。如图8和图9所示，该显示装置1000还包括如上述一些实施例中所述的阵列基板100。
本公开的一些实施例所提供的显示装置1000所能实现的有益效果，与上述一些实施例中所提供的阵列基板100所能实现的有益效果相同，此处不再赘述。
上述显示装置1000的类型包括多种，可以根据实际需要选择设置。
在一些示例中，如图8所示，显示装置1000可以为LCD。此时，显示装置1000还可以包括：与阵列基板100相对设置的对置基板200，以及设置在阵列基板100和对置基板200之间的液晶层300。
示例性的，上述对置基板200可以为透明的基板，或者也可以为彩膜基板(如图8所示)。在对置基板200为透明的基板的情况下，阵列基板100还可以包括设置在像素电极8靠近对置基板200一侧的彩膜层和/或黑矩阵。
在另一些示例中，如图9所示，显示装置1000可以为OLED显示装置。此时，显示装置1000还可以包括：设置在阵列基板100的多个氧化物薄膜晶体管5远离衬底1一侧的多个发光器件400。
示例性的，阵列基板100中的像素电极8可以称为发光器件400的阳极层。在此基础上，发光器件400还可以包括依次层叠设置在阳极层远离衬底1一侧的发光层和阴极层。
在一些实施例中，上述显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(Personal Digital Assistant，简称PDA)、手持式或便携式计算机、全球定位系统(Global Positioning System，简称GPS)接收器/导航器、相机、动态图像专家组(Moving Picture Experts Group 4，简称 MP4)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板的制备方法，包括：
    提供衬底；
    在所述衬底上形成多条导线；
    在所述多条导线远离所述衬底的一侧形成氧化物半导体薄膜；所述氧化物半导体薄膜覆盖所述多条导线并与至少一条导线直接接触；所述至少一条导线被配置为，导出所述氧化物半导体薄膜中产生的静电；
    采用光刻工艺，对所述氧化物半导体薄膜进行图案化处理，去除与所述至少一条导线直接接触的部分，形成包括多个氧化物薄膜晶体管的有源层的氧化物半导体层。
  2. 根据权利要求1所述的阵列基板的制备方法，还包括：
    在形成所述氧化物半导体薄膜之前，形成包括多个氧化物薄膜晶体管的栅极的栅导电层；所述栅导电层与所述多条导线位于所述衬底的同一侧；
    在所述多条导线和所述栅导电层远离所述衬底的一侧形成栅绝缘薄膜；所述栅绝缘薄膜覆盖所述多条导线和所述栅导电层；
    对所述栅绝缘薄膜进行图案化处理，形成具有至少一个过孔的栅绝缘层；所述至少一个过孔暴露所述至少一条导线的至少一部分表面，所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠；
    其中，所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。
  3. 根据权利要求2所述的阵列基板的制备方法，其中，沿垂直于所述至少一条导线的走线方向，所述至少一条导线在所述衬底上的正投影边界的一部分，与所述至少一个过孔在所述衬底上的正投影边界的一部分重合。
  4. 根据权利要求2或3所述的阵列基板的制备方法，其中，所述多条导线的材料包括金属材料；
    所述多条导线和所述栅导电层在同一次构图工艺中形成。
  5. 根据权利要求1～4中任一项所述的阵列基板的制备方法，还包括：
    在所述氧化物半导体层远离所述衬底的一侧形成源漏导电层，所述源漏导电层包括与每个有源层直接接触的源极和漏极，以及与所述至少一条导线直接接触的辅助引线。
  6. 根据权利要求5所述的阵列基板的制备方法，其中，所述阵列基板具有显示区和位于所述显示区旁侧的边框区；
    所述至少一条导线和所述辅助引线位于所述边框区；
    所述至少一条导线被配置为，向所述显示区传输公共电压信号，或对所述阵列基板进行静电防护；
    所述辅助引线被配置为，与所述至少一条导线形成并联，降低所述至少一条导线的电阻。
  7. 根据权利要求1～6中任一项所述的阵列基板的制备方法，其中，所述氧化物半导体薄膜的材料包括氧化锌、氧化铟、氧化锡、铟锌氧化物、氧化锌锡、氧化铝锌、氧化钇锌、氧化铟锡锌、铟镓锌氧化物和铟铝锌氧中的一种。
  8. 根据权利要求1～7中任一项所述的阵列基板的制备方法，其中，所述氧化物半导体层在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至多部分重叠。
  9. 一种阵列基板，包括：
    衬底；
    设置在所述衬底一侧的多条导线；以及，
    多个氧化物薄膜晶体管，所述多个氧化物薄膜晶体管与所述多条导线设置在所述衬底的同一侧；
    其中，每个氧化物薄膜晶体管包括栅极、有源层、源极和漏极；所述多个氧化物薄膜晶体管的有源层为通过对与至少一条导线直接接触的氧化物半导体薄膜进行图案化处理而获得的，且所述有源层与所述至少一条导线相互绝缘。
  10. 根据权利要求9所述的阵列基板，还包括：设置在所述栅极与所述有源层之间的栅绝缘层；
    所述栅绝缘层具有至少一个过孔，所述至少一个过孔暴露所述至少一条导线的至少一部分表面，所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠；
    所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。
  11. 根据权利要求10所述的阵列基板，还包括：设置在所述栅绝缘层远离所述衬底一侧的辅助引线；
    所述辅助引线通过所述至少一个过孔与所述至少一条导线直接接触。
  12. 根据权利要求9所述的阵列基板，还包括：与所述源极和所述漏极材料相同且同层设置的辅助引线；
    所述辅助引线与所述至少一条导线直接接触。
  13. 根据权利要求11或12所述的阵列基板，其中，所述辅助引线在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠。
  14. 根据权利要求11～13中任一项所述的阵列基板，其中，所述辅助引线的走线方向与所述至少一条导线的走线方向相同或大致相同。
  15. 根据权利要求10所述的阵列基板，还包括：设置在所述源极和所述漏极远离所述衬底一侧的钝化层；
    所述钝化层中的一部分位于所述至少一个过孔内，并与所述至少一条导线直接接触。
  16. 根据权利要求9～15中任一项所述的阵列基板，其中，所述阵列基板具有显示区和位于所述显示区旁侧的边框区；
    所述至少一条导线位于所述边框区；
    所述至少一条导线包括公共电极线或静电防护线；
    所述公共电极线被配置为，向所述显示区传输公共电压信号；
    所述静电防护线被配置为，对所述阵列基板进行静电防护。
  17. 根据权利要求9～16中任一项所述的阵列基板，其中，所述栅极和所述多条导线材料相同且同层设置。
  18. 一种显示装置，包括：如权利要求9～17中任一项所述的阵列基板。
  19. 根据权利要求18所述的显示装置，还包括：
    与所述阵列基板相对设置的对置基板；以及，
    设置在所述阵列基板和所述对置基板之间的液晶层。
  20. 根据权利要求19所述的显示装置，还包括：
    设置在所述阵列基板的多个氧化物薄膜晶体管远离所述阵列基板的衬底一侧的多个发光器件。
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CN110518023B (zh) * 2019-09-25 2021-12-24 福州京东方光电科技有限公司 阵列基板及其制备方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766868A (zh) * 2015-03-24 2015-07-08 深圳市华星光电技术有限公司 阵列基板及显示面板
JP2016157263A (ja) * 2015-02-24 2016-09-01 京セラディスプレイ株式会社 タッチパネル付液晶表示装置
CN106847826A (zh) * 2017-02-09 2017-06-13 京东方科技集团股份有限公司 一种阵列基板、显示装置以及阵列基板的制备方法
CN109952532A (zh) * 2017-08-08 2019-06-28 京东方科技集团股份有限公司 阵列基板、显示装置和制造阵列基板的方法
CN110518023A (zh) * 2019-09-25 2019-11-29 福州京东方光电科技有限公司 阵列基板及其制备方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5604477B2 (ja) * 2012-07-10 2014-10-08 株式会社半導体エネルギー研究所 表示装置
US9147676B2 (en) * 2013-10-02 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. SCRs with checker board layouts
CN103681773A (zh) * 2013-12-27 2014-03-26 京东方科技集团股份有限公司 一种有机电致发光显示器件、其制备方法及显示装置
KR102224457B1 (ko) * 2014-08-06 2021-03-09 엘지디스플레이 주식회사 표시장치와 그 제조 방법
CN104392990B (zh) * 2014-11-25 2018-07-13 合肥鑫晟光电科技有限公司 一种阵列基板及显示装置
JP6832624B2 (ja) * 2015-12-22 2021-02-24 三菱電機株式会社 液晶表示装置およびその製造方法
CN106684070B (zh) * 2017-01-22 2019-03-29 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及薄膜晶体管的制作方法
CN107589606A (zh) * 2017-09-05 2018-01-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN108987445B (zh) * 2018-07-16 2020-07-07 京东方科技集团股份有限公司 一种阵列基板、电致发光显示面板及显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016157263A (ja) * 2015-02-24 2016-09-01 京セラディスプレイ株式会社 タッチパネル付液晶表示装置
CN104766868A (zh) * 2015-03-24 2015-07-08 深圳市华星光电技术有限公司 阵列基板及显示面板
CN106847826A (zh) * 2017-02-09 2017-06-13 京东方科技集团股份有限公司 一种阵列基板、显示装置以及阵列基板的制备方法
CN109952532A (zh) * 2017-08-08 2019-06-28 京东方科技集团股份有限公司 阵列基板、显示装置和制造阵列基板的方法
CN110518023A (zh) * 2019-09-25 2019-11-29 福州京东方光电科技有限公司 阵列基板及其制备方法

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