US20220278134A2 - Array substrate and method of manufacturing the same, and display apparatus - Google Patents
Array substrate and method of manufacturing the same, and display apparatus Download PDFInfo
- Publication number
- US20220278134A2 US20220278134A2 US17/298,493 US202017298493A US2022278134A2 US 20220278134 A2 US20220278134 A2 US 20220278134A2 US 202017298493 A US202017298493 A US 202017298493A US 2022278134 A2 US2022278134 A2 US 2022278134A2
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- Prior art keywords
- array substrate
- base
- conductive
- conductive line
- oxide semiconductor
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- 239000000758 substrate Substances 0.000 title claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 144
- 239000010408 film Substances 0.000 claims abstract description 139
- 239000010409 thin film Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 40
- 230000008569 process Effects 0.000 claims abstract description 35
- 238000000059 patterning Methods 0.000 claims abstract description 21
- 230000003068 static effect Effects 0.000 claims abstract description 20
- 230000005611 electricity Effects 0.000 claims abstract description 19
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims description 51
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 17
- 238000002161 passivation Methods 0.000 claims description 16
- 239000007769 metal material Substances 0.000 claims description 9
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 8
- 239000011787 zinc oxide Substances 0.000 claims description 8
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 5
- JAONJTDQXUSBGG-UHFFFAOYSA-N dialuminum;dizinc;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Al+3].[Al+3].[Zn+2].[Zn+2] JAONJTDQXUSBGG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052733 gallium Inorganic materials 0.000 claims description 5
- 229910052738 indium Inorganic materials 0.000 claims description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 5
- 239000004973 liquid crystal related substance Substances 0.000 claims description 5
- DZLPZFLXRVRDAE-UHFFFAOYSA-N [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] Chemical compound [O--].[O--].[O--].[O--].[Al+3].[Zn++].[In+3] DZLPZFLXRVRDAE-UHFFFAOYSA-N 0.000 claims description 4
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 4
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 4
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 claims description 4
- UTGMRVNJUMTNIU-UHFFFAOYSA-N zinc oxygen(2-) yttrium(3+) Chemical compound [O-2].[Zn+2].[Y+3] UTGMRVNJUMTNIU-UHFFFAOYSA-N 0.000 claims description 4
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 221
- 239000004020 conductor Substances 0.000 description 27
- 229920002120 photoresistant polymer Polymers 0.000 description 26
- 238000010586 diagram Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- -1 polyethylene terephthalate Polymers 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 239000002356 single layer Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229920001609 Poly(3,4-ethylenedioxythiophene) Polymers 0.000 description 2
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004372 Polyvinyl alcohol Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 229920001940 conductive polymer Polymers 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 239000004926 polymethyl methacrylate Substances 0.000 description 2
- 229920002451 polyvinyl alcohol Polymers 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910017049 AsF5 Inorganic materials 0.000 description 1
- LSNNMFCWUKXFEE-UHFFFAOYSA-M Bisulfite Chemical compound OS([O-])=O LSNNMFCWUKXFEE-UHFFFAOYSA-M 0.000 description 1
- OYPRJOBELJOOCE-UHFFFAOYSA-N Calcium Chemical compound [Ca] OYPRJOBELJOOCE-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000002841 Lewis acid Substances 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910021188 PF6 Inorganic materials 0.000 description 1
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 1
- 229930182556 Polyacetal Natural products 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- NPYPAHLBTDXSSS-UHFFFAOYSA-N Potassium ion Chemical compound [K+] NPYPAHLBTDXSSS-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- FKNQFGJONOIPTF-UHFFFAOYSA-N Sodium cation Chemical compound [Na+] FKNQFGJONOIPTF-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- YBGKQGSCGDNZIB-UHFFFAOYSA-N arsenic pentafluoride Chemical compound F[As](F)(F)(F)F YBGKQGSCGDNZIB-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052791 calcium Inorganic materials 0.000 description 1
- 239000011575 calcium Substances 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- XMBWDFGMSWQBCA-UHFFFAOYSA-M iodide Chemical compound [I-] XMBWDFGMSWQBCA-UHFFFAOYSA-M 0.000 description 1
- 229940006461 iodide ion Drugs 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 150000007517 lewis acids Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- NQBRDZOHGALQCB-UHFFFAOYSA-N oxoindium Chemical compound [O].[In] NQBRDZOHGALQCB-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001197 polyacetylene Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000767 polyaniline Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 229920006324 polyoxymethylene Polymers 0.000 description 1
- 229920000128 polypyrrole Polymers 0.000 description 1
- 229920000123 polythiophene Polymers 0.000 description 1
- 229910052700 potassium Inorganic materials 0.000 description 1
- 229910001414 potassium ion Inorganic materials 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000005361 soda-lime glass Substances 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 229910001415 sodium ion Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method of manufacturing the same, and a display apparatus.
- An oxide semiconductor material is used as active layers in oxide thin film transistors, which has good uniformity, and is especially suitable for large-area displays.
- a method of manufacturing an array substrate includes: providing a base; forming a plurality of conductive lines on a side of the base; forming an oxide semiconductor film on a side of the plurality of conductive lines away from the base, the oxide semiconductor film covering the plurality of conductive lines and being in direct contact with at least one conductive line, and the at least one conductive line being configured to discharge static electricity generated in the oxide semiconductor film; and patterning the oxide semiconductor film by using a photoetching process to remove a portion of the oxide semiconductor film that is in direct contact with the at least one conductive line, and form an oxide semiconductor layer including active layers of a plurality of oxide thin film transistors, the oxide semiconductor layer and the at least one conductive line being insulated from each other.
- the method of manufacturing the array substrate further includes: before forming the oxide semiconductor film, forming a gate conductive layer including gates of the plurality of oxide thin film transistors, the gate conductive layer and the plurality of conductive lines being located on the same side of the base; forming a gate insulating film on a side of both the plurality of conductive lines and the gate conductive layer away from the base, the gate insulating film covering the plurality of conductive lines and the gate conductive layer; and patterning the gate insulating film to form a gate insulating layer with at least one via hole, an orthogonal projection of the at least one via hole on the base being at least partially overlapped with an orthogonal projection of the at least one conductive line on the base.
- the oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole.
- a portion of a boundary of the orthogonal projection of the at least one conductive line on the base coincides with a portion of a boundary of the orthogonal projection of the at least one via hole on the base.
- a material of the plurality of conductive lines includes a metal material.
- the plurality of conductive lines and the gate conductive layer are formed in a same patterning process.
- the method of manufacturing the array substrate further includes: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the base.
- the source-drain conductive layer includes sources and drains of the plurality of oxide thin film transistors that are in direct contact with respective active layers.
- the array substrate has a display area and a bezel area located beside the display area.
- the source-drain conductive layer further includes at least one auxiliary lead that is in direct contact with the at least one conductive line.
- the at least one auxiliary lead and the at least one conductive line are located in the bezel area.
- the at least one conductive line is configured to transmit a common voltage signal to the display area, or to perform an electrostatic protection on the array substrate.
- the at least one auxiliary lead is configured to be connected in parallel with the at least one conductive line, so as to reduce a resistance of the at least one conductive line.
- a material of the oxide semiconductor film includes one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide.
- an orthogonal projection of the oxide semiconductor layer on the base is at most partially overlapped with an orthogonal projection of the at least one conductive line on the base.
- an array substrate in another aspect, includes: a base; a plurality of conductive lines disposed on a side of the base; and a plurality of oxide thin film transistors.
- the plurality of oxide thin film transistors and the plurality of conductive lines are disposed on the same side of the base.
- Each oxide thin film transistor includes a gate, an active layer, a source, and a drain. Active layers of the plurality of oxide thin film transistors are obtained by patterning an oxide semiconductor film that is in direct contact with at least one of the plurality of conductive lines, and the active layers and the at least one conductive line are insulated from each other.
- the array substrate further includes a gate insulating layer disposed between gates and active layers of the plurality of oxide thin film transistors.
- the gate insulating layer has at least one via hole.
- An orthogonal projection of the at least one via hole on the base is at least partially overlapped with an orthogonal projection of the at least one conductive line on the base.
- the oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole.
- the array substrate further includes at least one auxiliary lead disposed on a side of the gate insulating layer away from the base.
- the at least one auxiliary lead is in direct contact with the at least one conductive line through the at least one via hole.
- the array substrate further includes at least one auxiliary lead made of a same material and arranged in a same layer as the source and the drain.
- the at least one auxiliary lead is in direct contact with the at least one conductive line.
- an orthogonal projection of the at least one auxiliary lead on the base is at least partially overlapped with the orthogonal projection of the at least one conductive line on the base.
- a routing direction of the at least one auxiliary lead is same as a routing direction of the at least one conductive line.
- the array substrate further includes a passivation layer disposed on a side of both sources and drains of the plurality of oxide thin film transistors away from the base. A portion of the passivation layer is located in the at least one via hole, and is in direct contact with the at least one conductive line.
- the array substrate has a display area and a bezel area located beside the display area.
- the at least one conductive line is located in the bezel area.
- the at least one conductive line includes a common electrode line or an electrostatic protection line.
- the common electrode line is configured to transmit a common voltage signal to the display area.
- the electrostatic protection line is configured to perform an electrostatic protection on the array substrate.
- the gate and the plurality of conductive lines are made of a same material and arranged in a same layer.
- a display apparatus includes the array substrate as described in any of the above embodiments.
- the display apparatus further includes an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate.
- the display apparatus further includes a plurality of light-emitting devices disposed on a side of the plurality of oxide thin film transistors in the array substrate away from the base in the array substrate.
- FIG. 1 is a structural diagram showing an electrostatic accumulation in an oxide semiconductor film, in accordance with the related art
- FIG. 2 is a flow diagram of a method of manufacturing an array substrate, in accordance with some embodiments of the present disclosure
- FIG. 3 is a flow diagram of a method of manufacturing another array substrate, in accordance with some embodiments of the present disclosure.
- FIGS. 4 a to 4 g are schematic diagrams showing a manufacturing process of an array substrate, in accordance with some embodiments of the present disclosure
- FIGS. 5 a to 5 l are schematic diagrams showing a manufacturing process taken along the 0 - 0 ′ direction in the manufacturing process shown in FIGS. 4 a to 4 g;
- FIG. 6 is a structural diagram of an array substrate, in accordance with some embodiments of the present disclosure.
- FIG. 7 is a structural diagram of another array substrate, in accordance with some embodiments of the present disclosure.
- FIG. 8 is a structural diagram of a display apparatus, in accordance with some embodiments of the present disclosure.
- FIG. 9 is a structural diagram of another display apparatus, in accordance with some embodiments of the present disclosure.
- the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as an open and inclusive meaning, i.e., “including, but not limited to”.
- the terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “an example,” “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s).
- the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.
- first and second are only used for descriptive purposes, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features.
- a feature defined with “first” or “second” may explicitly or implicitly include one or more of the features.
- “a/the plurality of” means two or more unless otherwise specified.
- connection and derivatives thereof may be used.
- the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electric contact with each other.
- the embodiments disclosed herein are not necessarily limited to the contents herein.
- a and/or B includes following three combinations: only A, only B, and a combination of A and B.
- the term “if” is, optionally, construed to mean “when” or “in a case where” or “in response to determining” or “in response to detecting”, depending on the context.
- the phrase “if it is determined” or “if [a stated condition or event] is detected” is, optionally, construed to mean “in a case where it is determined” or “in response to determining” or “in a case where [the stated condition or event] is determined ” or “in response to detecting [the stated condition or event]”, depending on the context.
- Exemplary embodiments are described herein with reference to sectional views and/or plan views as idealized exemplary drawings.
- thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shapes with respect to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include the deviations in shapes due to, for example, manufacturing.
- an etched region that is shown to have a rectangular shape generally has a curved feature. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show actual shapes of the regions in a device, and are not intended to limit the scope of the exemplary embodiments.
- An active layer of an oxide thin film transistor may be, for example, manufactured by using a photoetching process.
- a layer of an oxide semiconductor material film may be deposited first, and then a photoresist layer may be formed on a surface of the oxide semiconductor material film.
- the photoresist layer is exposed and developed to obtain a patterned photoresist layer, and the patterned photoresist layer may be used to pattern the oxide semiconductor material film, so as to obtain the active layer.
- the oxide semiconductor material film is easy to generate and accumulate static electricity in an exposure machine, and thus an electrostatic breakdown (i.e., electrostatic discharge (ESD)) may occur, which reduces a yield of an array substrate including the oxide thin film transistor.
- ESD electrostatic discharge
- a plurality of gates 1 ′ may be formed first, and then a gate insulating layer 2 ′ covering the plurality of gates 1 ′ and an oxide semiconductor material film 3 ′ covering the gate insulating layer 2 ′ are sequentially formed on a side of the plurality of gates 1 ′. Then, the oxide semiconductor material film 3 ′ is patterned by using the photoetching process.
- an oxide semiconductor material is usually a substance with an amorphous structure, and is poor in conductivity, in a process of exposing the photoresist layer in the exposure machine, the static electricity is easily generated in the oxide semiconductor material film 3 ′.
- the oxide semiconductor material film 3 ′ may also form parasitic capacitance structures with other conductive structures.
- the oxide semiconductor material film 3 ′ may form parasitic capacitance structures with the gates 1 ′, and induce different gates 1 ′ to form parasitic capacitance structures. In a case where a large amount of static electricity generated in the oxide semiconductor material film 3 ′ accumulates, the electrostatic breakdown is easy to occur.
- some embodiments of the present disclosure provide a method of manufacturing an array substrate. As shown in FIG. 2 , the method of manufacturing the array substrate includes S 100 to S 400 .
- a base 1 is provided.
- a category of the base 1 is various, which may be selectively set according to actual needs.
- the base 1 may be an inorganic material base, or may be an organic material base.
- the material of the base 1 may be soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, etc.
- the material of the base 1 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide (PI), polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination of at least two of the foregoing.
- the base 1 may be a rigid base. In a case of using the organic material for the base 1 , the base 1 may be a flexible base.
- a plurality of conductive lines 2 are formed on the base 1 .
- a material of the conductive lines 2 may include a conductive material or a combination of a plurality of conductive materials.
- the material of the conductive lines 2 may include a metal material, a conductive metal oxide material, a conductive metal nitride material, a conductive polymer material, a conductive composite material, or a combination of at least two of the foregoing.
- the metal material may be, for example, platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination of at least two of the foregoing.
- the conductive metal oxide material may be, for example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), or doped metal oxide.
- ITO indium tin oxide
- FTO fluorine-doped tin oxide
- doped metal oxide doped metal oxide.
- the conductive metal nitride material may be, for example, titanium nitride.
- the conductive polymer material may be, for example, polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/poly(sodium-p-styrenesulfonate) (PEDOT/PSS) or a combination of at least two of the foregoing, or the above material doped with a dopant.
- the dopant may be an acid such as hydrochloric acid, sulfuric acid, or sulfonic acid, or a Lewis acid such as PF 6 , AsF 5 , or FeCl 3 , or a halogen ion such as iodide ion, or a metal ion such as sodium ion or potassium ion.
- the conductive composite material may be, for example, a conductive composite material dispersed with carbon black, graphite powders, or metal particles.
- the conductive line 2 may be of a single-layer structure composed of a layer of conductive material, or may be of a multi-layer structure formed by sequentially stacking a plurality of layers of conductive materials.
- the conductive line 2 may be of a single-layer structure formed by a layer of metal material.
- the conductive line 2 may be of a three-layer structure formed by a first metal layer, a second metal layer, and the first metal layer that are sequentially stacked.
- the first metal layer may be a single-layer structure formed by at least one metal material
- the second metal layer may be a single-layer structure formed by at least one metal material
- the metal material(s) included in the first metal layer are different from the metal material(s) included in the second metal layer.
- an oxide semiconductor film 3 is formed on a side of the plurality of conductive lines 2 away from the base 1 .
- the oxide semiconductor film 3 covers the plurality of conductive lines 2 , and is in direct contact with at least one conductive line 2 . That is, the oxide semiconductor film 3 may be in direct contact with one conductive line 2 , or may be in direct contact with a plurality of conductive lines 2 .
- the at least one conductive line 2 is configured to discharge static electricity generated in the oxide semiconductor film 3 .
- a magnetron sputtering process may be used to manufacture the oxide semiconductor film 3 .
- the oxide semiconductor film 3 may be made of an amorphous oxide semiconductor material.
- the oxide semiconductor material may be one of zinc oxide (ZnO), indium oxide (InO), stannic oxide (SnO 2 ), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), yttrium zinc oxide (YZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or indium aluminum zinc oxide (IAZO).
- the oxide semiconductor material may be in an amorphous state. That is, the oxide semiconductor material may be the amorphous oxide semiconductor material.
- the oxide semiconductor film 3 may be an amorphous indium gallium zinc oxide film.
- the oxide semiconductor film 3 is patterned to remove a portion of the oxide semiconductor film 3 that is in direct contact with the at least one conductive line 2 , and form an oxide semiconductor layer 3 a including active layers 51 of a plurality of oxide thin film transistors 5 .
- the oxide semiconductor layer 3 a and the at least one conductive line 2 are insulated from each other.
- a photoetching process may be used to pattern the oxide semiconductor film 3 .
- patterning the oxide semiconductor film 3 by using the photoetching process includes S 410 to S 450 .
- a photoresist layer PR is formed on a surface of the oxide semiconductor film 3 away from the base 1 .
- a coating process may be used to coat a photoresist on the surface of the oxide semiconductor film 3 away from the base 1 , so as to form the photoresist layer PR.
- the photoresist may be a positive photoresist.
- the photoresist may be a negative photoresist.
- the method of manufacturing the array substrate will be schematically described below in an example where the photoresist is the positive photoresist.
- the photoresist layer PR may be exposed in an exposure machine.
- the static electricity is generated in the oxide semiconductor film 3 .
- the static electricity generated in the oxide semiconductor film 3 may be discharged into the at least one conductive line 2 , and the static electricity is discharged through the at least one conductive line 2 , which reduces or even avoids the electrostatic accumulation in the oxide semiconductor film 3 , thereby avoiding the electrostatic breakdown caused by a large amount of static electricity accumulated in the oxide semiconductor film 3 .
- the exposed photoresist layer PR is developed to remove an exposed portion of the photoresist layer PR, so as to obtain a patterned photoresist layer PR′.
- the patterned photoresist layer PR′ exposes a portion of the surface of the oxide semiconductor film 3 away from the base 1 , and covers the remaining portion of the oxide semiconductor film 3 .
- the oxide semiconductor film 3 is patterned by using the patterned photoresist layer PR′ as a mask. A portion of the oxide semiconductor film 3 that is not covered by the patterned photoresist layer PR′ is removed by etching, and a portion (i.e., the oxide semiconductor layer 3 a ) of the oxide semiconductor film 3 that is covered by the patterned photoresist layer PR′ is remained.
- an orthogonal projection of the oxide semiconductor layer 3 a on the base 1 is at most partially overlapped with an orthogonal projection of the at least one conductive line 2 on the base 1 , and the oxide semiconductor layer 3 a and the at least one conductive line 2 are insulated from each other.
- the plurality of conductive lines 2 are formed on the side of the base 1 , and after the oxide semiconductor film 3 is formed, the oxide semiconductor film 3 is in direct contact with the at least one conductive line 2 .
- the static electricity generated in the oxide semiconductor film 3 may be discharged into the at least one conductive line 2 with good conductivity, which is beneficial to reducing the electrostatic accumulation in the oxide semiconductor layer 3 a including a plurality of active layers 51 , avoiding the electrostatic breakdown, and improving a yield of the manufactured array substrate.
- a category of the thin film transistor 5 formed in the array substrate is various, which may be selectively set according to actual needs.
- the oxide thin film transistor 5 formed in the array substrate may be a bottom-gate oxide thin film transistor. In some other embodiments, the oxide thin film transistor 5 formed in the array substrate may be a top-gate oxide thin film transistor.
- the method of manufacturing the array substrate will be schematically described below in an example where the oxide thin film transistor 5 formed in the array substrate is the bottom-gate oxide thin film transistor. As shown in FIGS. 4 a to 4 c and 5 a to 5 c , the method of manufacturing the array substrate may further include S 210 to S 230 .
- a gate conductive layer Gate is formed.
- the gate conductive layer Gate and the plurality of conductive lines 2 are located on the same side of the base 1 .
- the gate conductive layer Gate may include a plurality of gate lines GL and gates 52 of the plurality of oxide thin film transistors 5 .
- Each gate 52 may be arranged opposite to the active layer 51 formed by subsequent manufacturing.
- a material and a layer structure of the gate conductive layer Gate may be the same as or different from those of the plurality of conductive lines 2 .
- the gate conductive layer Gate and the plurality of conductive lines 2 may be disposed on the same surface, and be of the same structure and the same material. That is, the gate conductive layer Gate and the plurality of conductive lines 2 may be manufactured in a same patterning process.
- the gate conductive layer Gate and the plurality of conductive lines 2 may be formed by a following method.
- a gate conductive material film is formed on a side of the base 1 , and then the gate conductive material film is patterned to form the plurality of conductive lines 2 and the gate conductive layer Gate synchronously.
- the gate conductive material film may be patterned through a photoetching process.
- a gate insulating film GI′ is formed on a side of both the plurality of conductive lines 2 and the gate conductive layer Gate away from the base 1 .
- the gate insulating film GI′ covers the gate conductive layer Gate and the plurality of conductive lines 2 .
- the gate insulating film GI′ may be made of silicon oxide, silicon oxynitride, silicon nitride, or other insulating materials.
- the gate insulating film GI′ may be manufactured by using a plasma enhanced chemical vapor deposition (PECVD) process.
- PECVD plasma enhanced chemical vapor deposition
- the gate insulating film GI′ is patterned to form a gate insulating layer GI with at least one via hole K.
- the at least one via hole K exposes at least one portion of a surface of the at least one conductive line 2 .
- An orthogonal projection of the at least one via hole K on the base 1 is at least partially overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 .
- the oxide semiconductor film 3 is in direct contact with the at least one conductive line 2 through the at least one via hole K.
- the gate insulating film GI′ may be patterned through a photoetching process to obtain the gate insulating layer GI.
- the gate insulating layer GI covers the gate conductive layer Gate.
- the orthogonal projection of the at least one via hole K on the base 1 is at least partially overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 . That is, the at least one via hole K exposes at least one portion of the at least one conductive line 2 .
- the via hole(s) K may be one or more.
- a relationship between the at least one via hole K and the at least one conductive line 2 is various, which may be selectively set according to actual needs.
- the at least one via hole K may be in one-to-one correspondence with the at least one conductive line 2 . That is, one via hole K may expose a portion of one conductive line 2 .
- one conductive line 2 may correspond to at least two of the multiple via holes K. That is, in the at least two via holes K, each via hole K may expose a portion of the corresponding conductive line 2 .
- one via hole K may correspond to at least two of the multiple conductive lines 2 . That is, the via hole K exposes portions of the at least two conductive lines 2 synchronously.
- the formed oxide semiconductor film 3 may be in direct contact with the at least one conductive line 2 through the at least one via hole K.
- the static electricity generated in the oxide semiconductor film 3 may be discharged into the at least one conductive line 2 through a portion of the oxide semiconductor film 3 located in the at least one via hole K, and be discharged through the at least one conductive line 2 .
- the oxide semiconductor layer 3 a may expose the at least one via hole K, and thus expose the at least one portion of the at least one conductive line 2 .
- the orthogonal projection of the formed oxide semiconductor layer 3 a on the base 1 may not be overlapped with the orthogonal projection of the at least one via hole K on the base 1 , so as to completely remove the oxide semiconductor material in the at least one via hole K.
- a portion of a boundary of the orthogonal projection of the at least one conductive line 2 on the base 1 coincides with a portion of a boundary of the orthogonal projection of the at least one via hole K on the base 1 .
- the at least one via hole K completely exposes the portion of the at least one conductive line 2 , so that the at least one conductive line 2 and the oxide semiconductor film 3 have a large contact area therebetween, so as to improve a diffusion efficiency of electrostatic charges in the oxide semiconductor film 3 .
- the method of manufacturing the array substrate may further include: manufacturing sources 53 and drains 54 of the oxide thin film transistors 5 .
- the method of manufacturing the array substrate may further include S 500 .
- a source-drain conductive layer SD is formed on a side of the oxide semiconductor layer 3 a away from the base 1 .
- the source-drain conductive layer SD may include a plurality of sources 53 and a plurality of drains 54 .
- the plurality of sources 53 are electrically connected to the plurality of active layers 51 in one-to-one correspondence
- the plurality of drains 54 are electrically connected to the plurality of active layers 51 in one-to-one correspondence.
- the oxide thin film transistor 5 may include the active layer 51 , the source 53 and the drain 54 .
- the source-drain conductive layer SD may further include auxiliary lead(s) 6 , and the auxiliary lead(s) 6 are electrically connected to the at least one conductive line 2 .
- the auxiliary lead(s) 6 may be in direct contact with the at least one conductive line 2 in one-to-one correspondence, so as to form electrical connection(s).
- the auxiliary lead 6 may be used to reduce a resistance of the conductive line 2 electrically connected to the auxiliary lead 6 , which improves stability of an electrical signal transmitted in the conductive line 2 .
- the auxiliary lead 6 may be used to reduce the resistance of the conductive line 2 electrically connected to the auxiliary lead 6 , a line width (i.e., a dimension of the conductive line 2 in the direction perpendicular to the routing direction of the conductive line 2 ) of the conductive line 2 may be reduced, thereby reducing a space ratio of the conductive line 2 in the array substrate.
- the source-drain conductive layer SD may be formed by a following method.
- a source-drain conductive material film SD′ may be formed on the side of the oxide semiconductor layer 3 a away from the base 1 , and the source-drain conductive material film SD′ covers the portion of the at least one conductive line 2 that is exposed through the at least one via hole K, a portion of the gate insulating layer GI that is not covered by the active layers 51 , and the active layers 51 .
- the source-drain conductive material film SD′ may be made of titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta), or an alloy thereof, or a combination of at least two of the foregoing materials.
- the source-drain conductive material film SD′ may be of a single-layer structure formed by a layer of conductive material, or may be of a multi-layer structure formed by a plurality of layers of conductive materials that are sequentially stacked.
- a sputtering process may be used to form the source-drain conductive material film SD′.
- the source-drain conductive material film SD′ may be patterned to form the source-drain conductive layer SD including the auxiliary lead(s) 6 , the sources 53 and the drains 54 .
- the source-drain conductive material film SD′ may be patterned through a photoetching process.
- the source-drain conductive layer SD may further include source-drain layer leads, for example, include voltage lead(s) and data lines DL.
- orthogonal projections of the auxiliary lead 6 and the conductive line 2 electrically connected to the auxiliary lead 6 on the base 1 may coincide with each other or may partially overlap.
- the formed array substrate 100 may have a display area A and a bezel area B located beside the display area A. Accordingly, the base 1 also has a bezel area and a display area. An orthogonal projection of the bezel area B of the array substrate 100 on a plane parallel to the base 1 coincides with an orthogonal projection of the bezel area of the base 1 on the plane parallel to the base 1 , and an orthogonal projection of the display area A of the array substrate 100 on the plane parallel to the base 1 coincides with an orthogonal projection of the display area of the base 1 on the plane parallel to the base 1 .
- the bezel area B may be located at one, two or three sides of the display area A, or the bezel area B may be arranged around the display area A.
- the at least one conductive line 2 that is in direct contact with the oxide semiconductor film 3 may be formed in the bezel area B of the array substrate 100 .
- the at least one conductive line 2 may be first common electrode line(s) used to provide a common voltage signal to the display area A, or may be electrostatic protection line(s) used to perform an electrostatic protection on the array substrate 100 .
- the at least one conductive line 2 may have a large dimension in the direction perpendicular to the routing direction of the at least one conductive line 2 , so as to ensure that the at least one conductive line 2 has a small impedance, thereby ensuring the stability of the electrical signal transmitted by the at least one conductive line 2 .
- the resistance of the at least one conductive line 2 may be reduced, thereby reducing the line width of the at least one conductive line 2 , which is beneficial to reducing a size of the bezel area B, so as to realize a narrow bezel design for the array substrate 100 .
- the at least one conductive line 2 that is in direct contact with the oxide semiconductor film 3 may be formed in the display area A of the array substrate 100 .
- the at least one conductive line 2 may be second common electrode line(s) that transmit a common voltage signal to an electrode layer (e.g., a common electrode layer or a cathode layer) in the array substrate.
- the method of manufacturing the array substrate may further include: forming a passivation layer (PVX) 7 on a side of the oxide thin film transistors 5 away from the base 1 .
- PVX passivation layer
- FIGS. 4 g and 5 l a plurality of pixel electrodes 8 are formed on a side of the passivation layer 7 away from the base 1 , and the plurality of pixel electrodes 8 are electrically connected to the sources 53 or the drains 54 of the plurality of oxide thin film transistors 5 in one-to-one correspondence.
- the method of manufacturing the array substrate may further include: before forming the pixel electrodes 8 , forming a planarization layer covering the passivation layer 7 , so as to provide a planar surface for the pixel electrodes 8 .
- the pixel electrodes 8 may be formed on a surface of the planarization layer away from the base 1 .
- the manufactured array substrate 100 may be applied to a liquid crystal display (LCD) apparatus.
- the method of manufacturing the array substrate 100 may further include: forming a common electrode at a side of the pixel electrodes 8 away from the base 1 .
- the method of manufacturing the array substrate may further include: sequentially forming a light-emitting layer and the cathode layer on the side of the pixel electrode 8 away from the base 1 .
- the cathode layer may be electrically connected to the at least one conductive line 2 , or electrically connected to the auxiliary lead(s) 6 , or electrically connected to both the at least one conductive line 2 and the auxiliary lead(s) 6 .
- the manufactured array substrate may be applied to an organic light-emitting diode (OLED) display apparatus.
- OLED organic light-emitting diode
- the method of manufacturing the array substrate is exemplarily as follows.
- the base 1 is provided.
- the base 1 is a glass base.
- the base 1 has the display area and the bezel area around the display area.
- the gate conductive material film is formed on the side of the base 1 , and the gate conductive material film covers the display area and the bezel area of the base 1 .
- the gate conductive material film may be formed through a deposition process.
- the gate conductive material film may be formed through a magnetron sputtering deposition process.
- the gate conductive material film is patterned to form the gate conductive layer Gate located in the display area A and the plurality of conductive lines 2 located in the bezel area B.
- the gate conductive layer Gate includes the plurality of gate lines GL and the plurality of gates 52 used to form the oxide thin film transistors 5 .
- the plurality of conductive lines 2 include at least one common electrode line used to provide the common voltage signal to the display area and/or at least one electrostatic protection line used to perform the electrostatic protection on the array substrate 100 .
- the gate insulating film GI′ covering the gate conductive layer Gate and the plurality of conductive lines 2 is formed on the side of both the gate conductive layer Gate and the plurality of conductive lines 2 away from the base 1 .
- the gate insulating film GI′ may be formed through a deposition process.
- the gate insulating film GI′ may be formed through a chemical vapor deposition (CVD) process.
- the gate insulating film GI′ is patterned with a mask to form the gate insulating layer GI with the at least one via hole K.
- the at least one via hole K exposes the portion of the at least one conductive line 2 .
- the portion of the boundary of the orthogonal projection of the at least one conductive line 2 on the base 1 coincides with the portion of the boundary of the orthogonal projection of the at least one via hole K on the base 1 .
- the mask may have a pattern used to form the at least one via hole K in the bezel area B.
- the oxide semiconductor film 3 is formed on a side of the gate insulating layer GI away from the base 1 .
- the oxide semiconductor film 3 is located both in the display area A and the bezel area B.
- the oxide semiconductor film 3 is in direct contact with the at least one conductive line 2 through the at least one via hole K in the gate insulating layer GI.
- the oxide semiconductor film 3 may be formed through a deposition process.
- the oxide semiconductor film 3 may be formed through a magnetron sputtering process.
- the oxide semiconductor film 3 is patterned to form the oxide semiconductor layer 3 a .
- the oxide semiconductor layer 3 a includes the plurality of active layers 51 used to form the oxide thin film transistors 5 , and the oxide semiconductor layer 3 a does not cover the at least one conductive line 2 .
- the orthogonal projection of the oxide semiconductor layer 3 a on the base 1 is completely non-overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 .
- a substrate including the oxide semiconductor film 3 may be transported into the exposure machine for exposure. Since the oxide semiconductor material is usually the substance with the amorphous structure, and is poor in conductivity, the static electricity is easily generated in the oxide semiconductor film 3 in the exposure machine. Since the oxide semiconductor film 3 is in direct contact with the at least one conductive line 2 , the static electricity generated in the oxide semiconductor film 3 may be discharged into the at least one conductive line 2 , and be discharged through the at least one conductive line 2 , which reduces or even avoids the electrostatic accumulation, and effectively avoids the electrostatic breakdown.
- the portion of the oxide semiconductor film 3 located above and inside the at least one via hole K is removed to expose the portion of the surface of the at least one conductive line 2 .
- the source-drain conductive material film SD′ is formed on the side of the oxide semiconductor layer 3 a away from the base 1 , and the source-drain conductive material film SD′ is located both in the display area A and the bezel area B. That is, the source-drain conductive material film SD′ covers the exposed at least one conductive line 2 , the portion of the gate insulating layer GI that is not covered by the active layers 51 , and the active layers 51 .
- the source-drain conductive material film SD′ may be formed through a deposition process.
- the source-drain conductive material film SD′ may be formed through a magnetron sputtering process.
- the source-drain conductive material film SD′ is patterned to form the source-drain conductive layer SD.
- the source-drain conductive layer SD includes the auxiliary lead(s) 6 located in the bezel area B and in direct contact with the at least one conductive line 2 through the via hole(s) K, and both a plurality of data lines DL and the sources 53 and the drains 54 of the oxide thin film transistors 5 located in the display area A.
- the auxiliary lead 6 may be connected in parallel with the conductive line 2 to reduce the resistance of the conductive line 2 , which not only improves the stability of the electrical signal transmitted in the at least one conductive line 2 , but also reduces the dimension of the at least one conductive line 2 in the direction perpendicular to the routing direction of the at least one conductive line 2 , thereby facilitating reduction in the size of the bezel area B, and facilitating realization of the narrow frame design for the array substrate 100 .
- the passivation layer (PVX) 7 and the planarization layer 9 are sequentially formed on a side of the source-drain conductive layer SD away from the base 1 .
- the plurality of pixel electrodes 8 are formed on a side of the planarization layer away from the base 1 .
- the plurality of pixel electrodes 8 are electrically connected to the drains 54 of the plurality of oxide thin film transistors 5 , respectively.
- a material of the pixel electrodes 8 may be, for example, ITO.
- the method of manufacturing the array substrate may exemplarily further include: sequentially forming the light-emitting layer and the cathode layer on the side of the pixel electrodes 8 away from the base 1 , the cathode layer extending to the bezel area B and being in direct contact with the auxiliary lead(s) 6 to form electrical connections; forming a protective layer on a side of the cathode layer away from the base 1 .
- the conductive line 2 electrically connected to the auxiliary lead may be the common electrode line.
- the array substrate 100 may include a base 1 , a plurality of conductive lines 2 and a plurality of oxide thin film transistors 5 .
- a material of the base 1 may refer to the schematic descriptions in some of the above embodiments, which will not be repeated here.
- the plurality of oxide thin film transistors 5 and the plurality of conductive lines 2 are disposed on the same side of the base 1 .
- each oxide thin film transistor 5 includes an active layer 51 , a gate 52 , a source 53 and a drain 54 .
- the active layer 51 of any oxide thin film transistor 5 is obtained by patterning an oxide semiconductor film 3 that is in direct contact with at least one conductive line 2 (e.g., reference may be made to the method of manufacturing the array substrate provided in some of the above embodiments).
- the active layer 51 of any oxide thin film transistor 5 and the at least one conductive line 2 are insulated from each other.
- the material of the active layers 51 may be an oxide semiconductor material.
- the oxide semiconductor material may be an amorphous oxide semiconductor material.
- the amorphous oxide semiconductor material may be one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide or indium aluminum zinc oxide.
- the array substrate 100 provided by some embodiments of the present disclosure may be manufactured through the method of manufacturing the array substrate in some of the above embodiments. Since the active layers 51 of the plurality of oxide thin film transistors 5 are obtained by patterning the oxide semiconductor film 3 that is in direct contact with the at least one conductive line 2 , and the at least one conductive line 2 has a good conductivity, static electricity generated in the oxide semiconductor film 3 may be discharged into the at least one conductive line 2 , and be discharged through the at least one conductive line 2 , which avoids an electrostatic accumulation in an oxide semiconductor layer 3 a including a plurality of active layers 51 , thereby avoiding an electrostatic breakdown, and effectively improving a yield of the array substrate 100 .
- a structure of the array substrate 100 in some embodiments of the present disclosure will be schematically described below with reference to the accompanying drawings.
- the oxide thin film transistor 5 is a bottom-gate oxide thin film transistor, which is taken as an example.
- the plurality of conductive lines 2 and the gates 52 of respective oxide thin film transistors 5 are located at a side of the active layers 51 proximate to the base 1 .
- the plurality of conductive lines 2 and the gates 52 are made of the same material and arranged in the same layer.
- the “same layer” mentioned herein means that a film for forming a specific pattern is formed by using the same film-forming process, and then is patterned by a same patterning process by using the same mask to form a layer structure.
- the same patterning process may include several exposure, development or etching processes, the specific patterns formed in the layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
- the plurality of conductive lines 2 and the gates 52 may be manufactured in a same patterning process, which is beneficial to simplify a manufacturing process of the array substrate 100 .
- the array substrate 100 further includes a gate insulating layer GI disposed between the gates 52 and the active layers 51 .
- the gates 52 belong to a gate conductive layer Gate
- the active layers 51 belong to the oxide semiconductor layer 3 a . That is, the gate insulating layer GI is located between the gate conductive layer Gate and the oxide semiconductor layer 3 a .
- the gate conductive layer Gate may further include gate lines GL.
- the gate insulating layer GI has at least one via hole K that exposes at least one portion of the at least one conductive line 2 . That is, an orthogonal projection of the at least one via hole K on the base 1 is at least partially overlapped with an orthogonal projection of the at least one conductive line 2 on the base 1 .
- a portion of a boundary of the orthogonal projection of the at least one conductive line 2 on the base 1 coincides with a portion of a boundary of the orthogonal projection of the at least one via hole K on the base 1 .
- the oxide semiconductor film 3 may be electrically connected to the at least one conductive line 2 through the at least one via hole K. In this way, in a case where the static electricity is generated in the oxide semiconductor film 3 , the static electricity may be discharged into the at least one conductive line 2 through a portion of the oxide semiconductor film 3 located in the at least one via hole K, and then the static electricity is discharged through the at least one conductive line 2 .
- the array substrate further includes auxiliary lead(s) 6 that are in direct contact with the at least one conductive line 2 .
- the auxiliary lead(s) 6 can be set in various ways, which may be selectively set according to actual needs.
- the auxiliary lead(s) 6 may be disposed on a side of the gate insulating layer GI away from the base 1 , and the auxiliary lead(s) 6 are in direct contact with the at least one conductive line 2 through the at least one via hole K.
- the auxiliary lead(s) 6 may be used to reduce a resistance of the at least one conductive line 2 , thereby reducing a dimension of the at least one conductive line 2 in the direction perpendicular to the routing direction of the at least one conductive line 2 , and reducing a space ratio of the at least one conductive line 2 in the array substrate 100 .
- the auxiliary lead(s) 6 and the sources 53 and the drains 54 of the oxide thin film transistors 5 may be made of the same material and arranged in the same layer.
- the auxiliary lead(s) 6 , the sources 53 , and the drains 54 may be manufactured in a same patterning process, which is beneficial to simplify the manufacturing process of the array substrate 100 .
- a film including the auxiliary lead(s) 6 , the sources 53 and the drains 54 may be referred to as a source-drain conductive layer SD.
- the source-drain conductive layer SD may further include data lines DL and power lines.
- orthogonal projection(s) of the auxiliary lead(s) 6 on the base 1 are at least partially overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 .
- the auxiliary lead(s) 6 are in one-to-one correspondence with the at least one conductive line 2 .
- the orthogonal projection of the auxiliary lead 6 on the base 1 is at least partially overlapped with the orthogonal projection of a corresponding conductive line 2 on the base 1 , which may include: a partial misalignment being present between the auxiliary lead 6 and the conductive line 2 , so that a portion of the orthogonal projection of the auxiliary lead 6 on the base 1 is overlapped with a portion of the orthogonal projection of the corresponding conductive line 2 on the base 1 ; or, the orthogonal projection of the auxiliary lead 6 on the base 1 being located within the orthogonal projection of the corresponding conductive line 2 on the base 1 .
- a routing direction of the auxiliary lead 6 is the same or substantially the same as the routing direction of the at least one conductive line 2 . That is, an angle between a routing direction of a portion of the auxiliary lead 6 and a routing direction of a portion of the conductive line 2 that is overlapped with the portion of the auxiliary lead 6 is 0° or approximately 0°. This is beneficial to ensure the reduction in the resistance of the at least one conductive line 2 .
- the array substrate 100 may further include a passivation layer 7 disposed on a side of both the sources 53 and the drains 54 away from the base 1 (i.e., covering the oxide thin film transistors 5 ).
- a portion of the passivation layer 7 may be located in the at least one via hole K in the gate insulating layer GI. In this way, it is possible to prevent a conductive layer (e.g., pixel electrodes 8 ) subsequently formed from forming electrical connection(s) with the at least one conductive line 2 , so as to avoid signal crosstalk.
- a conductive layer e.g., pixel electrodes 8
- the array substrate 100 may further include the pixel electrodes 8 disposed at a side of the passivation layer 7 away from the base 1 .
- the pixel electrodes 8 may be, for example, electrically connected to the drains 54 of the oxide thin film transistors 5 .
- the array substrate 100 may further include a planarization layer disposed between the passivation layer 7 and the pixel electrodes 8 .
- the array substrate 100 has a display area A and a bezel area B located beside the display area A.
- a display area A For “beside the display area A”, reference may be made to the schematic descriptions in some of the above examples.
- the oxide thin film transistors 5 in the array substrate 100 may be located in the display area A.
- the at least one conductive line 2 electrically connected to the oxide semiconductor film 3 may be located in the display area A, or may be located in the bezel area B.
- the at least one conductive line 2 may be second common electrode line(s) that transmit a common voltage signal to an electrode layer (e.g., a common electrode layer or a cathode layer) in the array substrate.
- the at least one conductive line 2 may be first common electrode line(s) used to provide a common voltage signal to the display area A, or may be electrostatic protection line(s) used to perform an electrostatic protection on the array substrate 100 .
- the array substrate 100 may include the base 1 , the plurality of conductive lines 2 , the gate conductive layer Gate, the gate insulating layer GI, the oxide semiconductor layer 3 a , the source-drain conductive layer SD, the passivation layer 7 and the plurality of pixel electrodes 8 .
- the base 1 may be a glass base.
- the base 1 may have a display area and a bezel area around the display area.
- the plurality of conductive lines 2 may be located in the bezel area of the base 1 .
- the gate conductive layer Gate may be located in the display area of the base 1 .
- the gate conductive layer Gate and the plurality of conductive lines 2 may be disposed on the same side and located on the same surface of the base 1 .
- the gate conductive layer Gate and the plurality of conductive lines 2 are made of the same material and arranged in the same layer.
- the gate conductive layer Gate may include the plurality of gate lines GL and the plurality of gates 52 used to form the oxide thin film transistors 5 .
- the gate insulating layer GI may be disposed on a side of both the plurality of conductive lines 2 and the gate conductive layer Gate away from the base 1 .
- the gate insulating layer GI has the at least one via hole K, and the at least one via hole K exposes a portion of the at least one of the plurality of conductive lines 2 . That is, the orthogonal projection of the at least one via hole K on the base 1 is partially overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 .
- the oxide semiconductor layer 3 a may be disposed at the side of the gate conductive layer Gate away from the base 1 .
- the oxide semiconductor layer 3 a includes the plurality of active layers 51 used to form the oxide thin film transistors 5 , and an orthogonal projection of the oxide semiconductor layer 3 a on the base 1 is completely non-overlapped with the orthogonal projection of the at least one conductive line 2 on the base 1 .
- the oxide semiconductor layer 3 a is obtained by patterning the oxide semiconductor film 3 that is in direct contact with the at least one conductive line 2 .
- the source-drain conductive layer SD may be disposed on a side of the oxide semiconductor layer 3 a away from the base 1 .
- the source-drain conductive layer SD may include the auxiliary lead(s) 6 electrically connected to the at least one conductive line 2 through the at least one via hole K in the gate insulating layer GI, a plurality of source-drain layer leads (e.g., data lines DL), and the sources 53 and the drains 54 of the oxide thin film transistors 5 .
- the auxiliary lead(s) 6 may be disposed in the bezel area B, and the source-drain layer leads, the sources 53 , and the drains 54 are disposed in the display area A.
- the passivation layer 7 may be formed on a side of the source-drain conductive layer SD away from the base 1 .
- the passivation layer 7 may expose portions of the drains 54 in the source-drain conductive layer SD.
- the plurality of pixel electrodes 8 may be disposed at the side of the passivation layer 7 away from the base 1 .
- the plurality of pixel electrodes 8 may be electrically connected to the plurality of drains 54 in one-to-one correspondence.
- the array substrate 100 may be manufactured through the method of manufacturing the array substrate in some of the above embodiments, and the structure, principle and effects of the array substrate 100 have been described in detail in the method of manufacturing the array substrate in some of the above embodiments, which will not be repeated here.
- Some embodiments of the present disclosure further provide a display apparatus 1000 .
- the display apparatus 1000 includes the array substrate 100 as described in some of the above embodiments.
- Beneficial effects that may be achieved by the display apparatus 1000 in some embodiments of the present disclosure are the same as the beneficial effects that may be achieved by the array substrate 100 in some of the above embodiments, which will not be repeated here.
- a category of the display apparatus 1000 is various, which may be selectively set according to actual needs.
- the display apparatus 1000 may be a liquid crystal display (LCD) apparatus.
- the display apparatus 1000 may further include an opposite substrate 200 arranged opposite to the array substrate 100 , and a liquid crystal layer 300 disposed between the array substrate 100 and the opposite substrate 200 .
- the opposite substrate 200 may be a transparent substrate, or may be a color film substrate (as shown in FIG. 8 ).
- the array substrate 100 may further include a color film layer and/or black matrixes disposed on a side of the pixel electrodes 8 proximate to the opposite substrate 200 .
- the display apparatus 1000 may be an organic light-emitting diode (OLED) display apparatus.
- the display apparatus 1000 may further include a plurality of light-emitting devices 400 disposed on a side of the plurality of oxide thin film transistors 5 in the array substrate 100 away from the base 1 .
- the pixel electrode 8 in the array substrate 100 may be referred to as an anode layer of the light-emitting device 400 .
- the light-emitting device 400 may further include a light-emitting layer and a cathode layer that are sequentially stacked on a side of the anode layer away from the base 1 .
- the display apparatus 100 may be any apparatus that displays images whether in motion (e.g., a video) or stationary (e.g., a static image), and whether literal or graphical. It is anticipated that the described embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDA), handheld or portable computers, global positioning system (GPS) receivers/navigators, cameras, moving picture experts group 4 (MP4) video players, video cameras, game consoles, watches, clocks, calculators, television monitors, computer monitors, car displays (e.g., odometer displays), navigators, cockpit controllers and/or displays, camera view displays (e.g., rear-view camera displays in vehicles), electronic photographs, electronic billboards or direction boards, projectors, building structures, packaging and aesthetic structures (e.g., a display for an image of a piece of jewelry).
- PDA personal digital assistants
- GPS global positioning system
- MP4 moving picture experts group 4
- video cameras
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Abstract
Description
- This application is a national phase entry under 35 USC 371 of International Patent Application No. PCT/CN 2020/117632, filed on Sep. 25, 2020, which claims priority to Chinese Patent Application No. 201910913692.1, filed on Sep. 25, 2019, which are incorporated herein by reference in their entirety.
- The present disclosure relates to the field of display technologies, and in particular, to an array substrate and a method of manufacturing the same, and a display apparatus.
- An oxide semiconductor material is used as active layers in oxide thin film transistors, which has good uniformity, and is especially suitable for large-area displays.
- In an aspect, a method of manufacturing an array substrate is provided. The method of manufacturing the array substrate includes: providing a base; forming a plurality of conductive lines on a side of the base; forming an oxide semiconductor film on a side of the plurality of conductive lines away from the base, the oxide semiconductor film covering the plurality of conductive lines and being in direct contact with at least one conductive line, and the at least one conductive line being configured to discharge static electricity generated in the oxide semiconductor film; and patterning the oxide semiconductor film by using a photoetching process to remove a portion of the oxide semiconductor film that is in direct contact with the at least one conductive line, and form an oxide semiconductor layer including active layers of a plurality of oxide thin film transistors, the oxide semiconductor layer and the at least one conductive line being insulated from each other.
- In some embodiments, the method of manufacturing the array substrate further includes: before forming the oxide semiconductor film, forming a gate conductive layer including gates of the plurality of oxide thin film transistors, the gate conductive layer and the plurality of conductive lines being located on the same side of the base; forming a gate insulating film on a side of both the plurality of conductive lines and the gate conductive layer away from the base, the gate insulating film covering the plurality of conductive lines and the gate conductive layer; and patterning the gate insulating film to form a gate insulating layer with at least one via hole, an orthogonal projection of the at least one via hole on the base being at least partially overlapped with an orthogonal projection of the at least one conductive line on the base. The oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole.
- In some embodiments, a portion of a boundary of the orthogonal projection of the at least one conductive line on the base coincides with a portion of a boundary of the orthogonal projection of the at least one via hole on the base.
- In some embodiments, a material of the plurality of conductive lines includes a metal material. The plurality of conductive lines and the gate conductive layer are formed in a same patterning process.
- In some embodiments, the method of manufacturing the array substrate further includes: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the base. The source-drain conductive layer includes sources and drains of the plurality of oxide thin film transistors that are in direct contact with respective active layers.
- In some embodiments, the array substrate has a display area and a bezel area located beside the display area. The source-drain conductive layer further includes at least one auxiliary lead that is in direct contact with the at least one conductive line. The at least one auxiliary lead and the at least one conductive line are located in the bezel area. The at least one conductive line is configured to transmit a common voltage signal to the display area, or to perform an electrostatic protection on the array substrate. The at least one auxiliary lead is configured to be connected in parallel with the at least one conductive line, so as to reduce a resistance of the at least one conductive line.
- In some embodiments, a material of the oxide semiconductor film includes one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide.
- In some embodiments, an orthogonal projection of the oxide semiconductor layer on the base is at most partially overlapped with an orthogonal projection of the at least one conductive line on the base.
- In another aspect, an array substrate is provided. The array substrate includes: a base; a plurality of conductive lines disposed on a side of the base; and a plurality of oxide thin film transistors. The plurality of oxide thin film transistors and the plurality of conductive lines are disposed on the same side of the base. Each oxide thin film transistor includes a gate, an active layer, a source, and a drain. Active layers of the plurality of oxide thin film transistors are obtained by patterning an oxide semiconductor film that is in direct contact with at least one of the plurality of conductive lines, and the active layers and the at least one conductive line are insulated from each other.
- In some embodiments, the array substrate further includes a gate insulating layer disposed between gates and active layers of the plurality of oxide thin film transistors. The gate insulating layer has at least one via hole. An orthogonal projection of the at least one via hole on the base is at least partially overlapped with an orthogonal projection of the at least one conductive line on the base. The oxide semiconductor film is in direct contact with the at least one conductive line through the at least one via hole.
- In some embodiments, the array substrate further includes at least one auxiliary lead disposed on a side of the gate insulating layer away from the base. The at least one auxiliary lead is in direct contact with the at least one conductive line through the at least one via hole.
- In some embodiments, the array substrate further includes at least one auxiliary lead made of a same material and arranged in a same layer as the source and the drain. The at least one auxiliary lead is in direct contact with the at least one conductive line.
- In some embodiments, an orthogonal projection of the at least one auxiliary lead on the base is at least partially overlapped with the orthogonal projection of the at least one conductive line on the base.
- In some embodiments, a routing direction of the at least one auxiliary lead is same as a routing direction of the at least one conductive line.
- In some embodiments, the array substrate further includes a passivation layer disposed on a side of both sources and drains of the plurality of oxide thin film transistors away from the base. A portion of the passivation layer is located in the at least one via hole, and is in direct contact with the at least one conductive line.
- In some embodiments, the array substrate has a display area and a bezel area located beside the display area. The at least one conductive line is located in the bezel area. The at least one conductive line includes a common electrode line or an electrostatic protection line. The common electrode line is configured to transmit a common voltage signal to the display area. The electrostatic protection line is configured to perform an electrostatic protection on the array substrate.
- In some embodiments, the gate and the plurality of conductive lines are made of a same material and arranged in a same layer.
- In yet another aspect, a display apparatus is provided. The display apparatus includes the array substrate as described in any of the above embodiments.
- In some embodiments, the display apparatus further includes an opposite substrate arranged opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the opposite substrate.
- In some embodiments, the display apparatus further includes a plurality of light-emitting devices disposed on a side of the plurality of oxide thin film transistors in the array substrate away from the base in the array substrate.
- In order to describe technical solutions in the present disclosure more clearly, accompanying drawings to be used in some embodiments of the present disclosure will be introduced below briefly. Obviously, the accompanying drawings to be described below are merely accompanying drawings of some embodiments of the present disclosure, and a person of ordinary skill in the art may obtain other drawings according to those drawings. In addition, the accompanying drawings in the following description may be regarded as schematic diagrams, and are not limitations on an actual size of a product, an actual process of a method, and an actual timing of a signal involved in the embodiments of the present disclosure.
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FIG. 1 is a structural diagram showing an electrostatic accumulation in an oxide semiconductor film, in accordance with the related art; -
FIG. 2 is a flow diagram of a method of manufacturing an array substrate, in accordance with some embodiments of the present disclosure; -
FIG. 3 is a flow diagram of a method of manufacturing another array substrate, in accordance with some embodiments of the present disclosure; -
FIGS. 4a to 4g are schematic diagrams showing a manufacturing process of an array substrate, in accordance with some embodiments of the present disclosure; -
FIGS. 5a to 5l are schematic diagrams showing a manufacturing process taken along the 0-0′ direction in the manufacturing process shown inFIGS. 4a to 4 g; -
FIG. 6 is a structural diagram of an array substrate, in accordance with some embodiments of the present disclosure; -
FIG. 7 is a structural diagram of another array substrate, in accordance with some embodiments of the present disclosure; -
FIG. 8 is a structural diagram of a display apparatus, in accordance with some embodiments of the present disclosure; and -
FIG. 9 is a structural diagram of another display apparatus, in accordance with some embodiments of the present disclosure. - The technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings below. Obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure shall be included in the protection scope of the present disclosure.
- Unless the context requires otherwise, throughout the description and the claims, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as an open and inclusive meaning, i.e., “including, but not limited to”. In the description of the specification, the terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “an example,” “specific example” or “some examples” are intended to indicate that specific features, structures, materials or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.
- Below, the terms such as “first” and “second” are only used for descriptive purposes, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with “first” or “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, “a/the plurality of” means two or more unless otherwise specified.
- In the description of some embodiments, the term “connected” and derivatives thereof may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electric contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
- The phrase “A and/or B” includes following three combinations: only A, only B, and a combination of A and B.
- As used herein, the term “if” is, optionally, construed to mean “when” or “in a case where” or “in response to determining” or “in response to detecting”, depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” is, optionally, construed to mean “in a case where it is determined” or “in response to determining” or “in a case where [the stated condition or event] is determined ” or “in response to detecting [the stated condition or event]”, depending on the context.
- The use of “applicable to” or “configured to” herein is means an open and inclusive expression, which does not exclude devices applicable to or configured to perform additional tasks or steps.
- Additionally, the use of “based on” is meant to be open and inclusive, in that a process, step, calculation, or other actions “based on” one or more recited conditions or values may, in practice, be based on additional conditions or values beyond those recited.
- As used herein, “about” or “approximately” is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).
- Exemplary embodiments are described herein with reference to sectional views and/or plan views as idealized exemplary drawings. In the drawings, thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shapes with respect to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include the deviations in shapes due to, for example, manufacturing. For example, an etched region that is shown to have a rectangular shape generally has a curved feature. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show actual shapes of the regions in a device, and are not intended to limit the scope of the exemplary embodiments.
- An active layer of an oxide thin film transistor may be, for example, manufactured by using a photoetching process.
- That is, in a process of forming the active layer of the oxide thin film transistor, a layer of an oxide semiconductor material film may be deposited first, and then a photoresist layer may be formed on a surface of the oxide semiconductor material film. The photoresist layer is exposed and developed to obtain a patterned photoresist layer, and the patterned photoresist layer may be used to pattern the oxide semiconductor material film, so as to obtain the active layer.
- However, the oxide semiconductor material film is easy to generate and accumulate static electricity in an exposure machine, and thus an electrostatic breakdown (i.e., electrostatic discharge (ESD)) may occur, which reduces a yield of an array substrate including the oxide thin film transistor.
- In an implementation manner, in an example where the oxide thin film transistor is a bottom-gate thin film transistor, as shown in
FIG. 1 , in a process of manufacturing the oxide thin film transistors, for example, a plurality ofgates 1′ may be formed first, and then agate insulating layer 2′ covering the plurality ofgates 1′ and an oxidesemiconductor material film 3′ covering thegate insulating layer 2′ are sequentially formed on a side of the plurality ofgates 1′. Then, the oxidesemiconductor material film 3′ is patterned by using the photoetching process. - Since an oxide semiconductor material is usually a substance with an amorphous structure, and is poor in conductivity, in a process of exposing the photoresist layer in the exposure machine, the static electricity is easily generated in the oxide
semiconductor material film 3′. In addition, the oxidesemiconductor material film 3′ may also form parasitic capacitance structures with other conductive structures. For example, the oxidesemiconductor material film 3′ may form parasitic capacitance structures with thegates 1′, and inducedifferent gates 1′ to form parasitic capacitance structures. In a case where a large amount of static electricity generated in the oxidesemiconductor material film 3′ accumulates, the electrostatic breakdown is easy to occur. - Based on this, some embodiments of the present disclosure provide a method of manufacturing an array substrate. As shown in
FIG. 2 , the method of manufacturing the array substrate includes S100 to S400. - In S100, a
base 1 is provided. - A category of the
base 1 is various, which may be selectively set according to actual needs. - In some examples, the
base 1 may be an inorganic material base, or may be an organic material base. - For example, in an implementation manner of the present disclosure, the material of the
base 1 may be soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, etc. In another implementation manner of the present disclosure, the material of thebase 1 may be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide (PI), polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination of at least two of the foregoing. - Here, in a case of using the inorganic material for the
base 1, thebase 1 may be a rigid base. In a case of using the organic material for thebase 1, thebase 1 may be a flexible base. - In S200, as shown in
FIGS. 4a and 5a , a plurality ofconductive lines 2 are formed on thebase 1. - In some examples, a material of the
conductive lines 2 may include a conductive material or a combination of a plurality of conductive materials. - For example, the material of the
conductive lines 2 may include a metal material, a conductive metal oxide material, a conductive metal nitride material, a conductive polymer material, a conductive composite material, or a combination of at least two of the foregoing. - The metal material may be, for example, platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination of at least two of the foregoing.
- The conductive metal oxide material may be, for example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), or doped metal oxide.
- The conductive metal nitride material may be, for example, titanium nitride.
- The conductive polymer material may be, for example, polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/poly(sodium-p-styrenesulfonate) (PEDOT/PSS) or a combination of at least two of the foregoing, or the above material doped with a dopant. The dopant may be an acid such as hydrochloric acid, sulfuric acid, or sulfonic acid, or a Lewis acid such as PF6, AsF5, or FeCl3, or a halogen ion such as iodide ion, or a metal ion such as sodium ion or potassium ion.
- The conductive composite material may be, for example, a conductive composite material dispersed with carbon black, graphite powders, or metal particles.
- In some examples, the
conductive line 2 may be of a single-layer structure composed of a layer of conductive material, or may be of a multi-layer structure formed by sequentially stacking a plurality of layers of conductive materials. - For example, the
conductive line 2 may be of a single-layer structure formed by a layer of metal material. - For another example, the
conductive line 2 may be of a three-layer structure formed by a first metal layer, a second metal layer, and the first metal layer that are sequentially stacked. The first metal layer may be a single-layer structure formed by at least one metal material, the second metal layer may be a single-layer structure formed by at least one metal material, and the metal material(s) included in the first metal layer are different from the metal material(s) included in the second metal layer. - In S300, as shown in
FIGS. 4d and 5d , anoxide semiconductor film 3 is formed on a side of the plurality ofconductive lines 2 away from thebase 1. Theoxide semiconductor film 3 covers the plurality ofconductive lines 2, and is in direct contact with at least oneconductive line 2. That is, theoxide semiconductor film 3 may be in direct contact with oneconductive line 2, or may be in direct contact with a plurality ofconductive lines 2. The at least oneconductive line 2 is configured to discharge static electricity generated in theoxide semiconductor film 3. - In some examples, a magnetron sputtering process may be used to manufacture the
oxide semiconductor film 3. - In some examples, the
oxide semiconductor film 3 may be made of an amorphous oxide semiconductor material. - For example, the oxide semiconductor material may be one of zinc oxide (ZnO), indium oxide (InO), stannic oxide (SnO2), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), yttrium zinc oxide (YZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), or indium aluminum zinc oxide (IAZO). Optionally, the oxide semiconductor material may be in an amorphous state. That is, the oxide semiconductor material may be the amorphous oxide semiconductor material.
- For example, the
oxide semiconductor film 3 may be an amorphous indium gallium zinc oxide film. - In S400, as shown in
FIGS. 4e and 5i , theoxide semiconductor film 3 is patterned to remove a portion of theoxide semiconductor film 3 that is in direct contact with the at least oneconductive line 2, and form anoxide semiconductor layer 3 a includingactive layers 51 of a plurality of oxidethin film transistors 5. Theoxide semiconductor layer 3 a and the at least oneconductive line 2 are insulated from each other. - In some examples, in S400 described above, a photoetching process may be used to pattern the
oxide semiconductor film 3. - For example, as shown in
FIGS. 5e to 5i , patterning theoxide semiconductor film 3 by using the photoetching process, includes S410 to S450. - In S410, as shown in
FIG. 5e , a photoresist layer PR is formed on a surface of theoxide semiconductor film 3 away from thebase 1. - For example, a coating process may be used to coat a photoresist on the surface of the
oxide semiconductor film 3 away from thebase 1, so as to form the photoresist layer PR. - A type of the photoresist is various. For example, the photoresist may be a positive photoresist. Or the photoresist may be a negative photoresist.
- The method of manufacturing the array substrate will be schematically described below in an example where the photoresist is the positive photoresist.
- In S420, as shown in
FIG. 5f , the photoresist layer PR is exposed. - For example, the photoresist layer PR may be exposed in an exposure machine.
- For example, in a process of exposing the photoresist layer PR, the static electricity is generated in the
oxide semiconductor film 3. In a case where theoxide semiconductor film 3 is electrically connected to the at least oneconductive line 2, the static electricity generated in theoxide semiconductor film 3 may be discharged into the at least oneconductive line 2, and the static electricity is discharged through the at least oneconductive line 2, which reduces or even avoids the electrostatic accumulation in theoxide semiconductor film 3, thereby avoiding the electrostatic breakdown caused by a large amount of static electricity accumulated in theoxide semiconductor film 3. - In S430, as shown in
FIG. 5g , the exposed photoresist layer PR is developed to remove an exposed portion of the photoresist layer PR, so as to obtain a patterned photoresist layer PR′. The patterned photoresist layer PR′ exposes a portion of the surface of theoxide semiconductor film 3 away from thebase 1, and covers the remaining portion of theoxide semiconductor film 3. - In S440, as shown in
FIG. 5h , theoxide semiconductor film 3 is patterned by using the patterned photoresist layer PR′ as a mask. A portion of theoxide semiconductor film 3 that is not covered by the patterned photoresist layer PR′ is removed by etching, and a portion (i.e., theoxide semiconductor layer 3 a) of theoxide semiconductor film 3 that is covered by the patterned photoresist layer PR′ is remained. - It can be understood that an orthogonal projection of the
oxide semiconductor layer 3 a on thebase 1 is at most partially overlapped with an orthogonal projection of the at least oneconductive line 2 on thebase 1, and theoxide semiconductor layer 3 a and the at least oneconductive line 2 are insulated from each other. In this way, it is possible to ensure an effective electrical connection between the at least oneconductive line 2 and a film formed by subsequent manufacturing, which avoids a poor power supply caused by theoxide semiconductor layer 3 a sandwiched between the at least oneconductive line 2 and the film formed by subsequent manufacturing, and also avoids adding an additional process to remove the portion of theoxide semiconductor film 3 that is in direct contact with the at least oneconductive line 2. - In S450, as shown in
FIG. 5i , the patterned photoresist layer PR′ is removed. - In the method of manufacturing the array substrate provided by some embodiments of the present disclosure, the plurality of
conductive lines 2 are formed on the side of thebase 1, and after theoxide semiconductor film 3 is formed, theoxide semiconductor film 3 is in direct contact with the at least oneconductive line 2. In this way, in the process of patterning theoxide semiconductor film 3, the static electricity generated in theoxide semiconductor film 3 may be discharged into the at least oneconductive line 2 with good conductivity, which is beneficial to reducing the electrostatic accumulation in theoxide semiconductor layer 3 a including a plurality ofactive layers 51, avoiding the electrostatic breakdown, and improving a yield of the manufactured array substrate. - It will be noted that a category of the
thin film transistor 5 formed in the array substrate is various, which may be selectively set according to actual needs. - In some embodiments, the oxide
thin film transistor 5 formed in the array substrate may be a bottom-gate oxide thin film transistor. In some other embodiments, the oxidethin film transistor 5 formed in the array substrate may be a top-gate oxide thin film transistor. - The method of manufacturing the array substrate will be schematically described below in an example where the oxide
thin film transistor 5 formed in the array substrate is the bottom-gate oxide thin film transistor. As shown inFIGS. 4a to 4c and 5a to 5c , the method of manufacturing the array substrate may further include S210 to S230. - In S210, as shown in
FIGS. 4a and 5a , before S300 described above, a gate conductive layer Gate is formed. The gate conductive layer Gate and the plurality ofconductive lines 2 are located on the same side of thebase 1. - For example, the gate conductive layer Gate may include a plurality of gate lines GL and
gates 52 of the plurality of oxidethin film transistors 5. Eachgate 52 may be arranged opposite to theactive layer 51 formed by subsequent manufacturing. - In some examples, a material and a layer structure of the gate conductive layer Gate may be the same as or different from those of the plurality of
conductive lines 2. - In an implementation of the present disclosure, the gate conductive layer Gate and the plurality of
conductive lines 2 may be disposed on the same surface, and be of the same structure and the same material. That is, the gate conductive layer Gate and the plurality ofconductive lines 2 may be manufactured in a same patterning process. - For example, the gate conductive layer Gate and the plurality of
conductive lines 2 may be formed by a following method. - A gate conductive material film is formed on a side of the
base 1, and then the gate conductive material film is patterned to form the plurality ofconductive lines 2 and the gate conductive layer Gate synchronously. - Optionally, the gate conductive material film may be patterned through a photoetching process.
- In S220, as shown in
FIGS. 4b and 5b , a gate insulating film GI′ is formed on a side of both the plurality ofconductive lines 2 and the gate conductive layer Gate away from thebase 1. The gate insulating film GI′ covers the gate conductive layer Gate and the plurality ofconductive lines 2. - Optionally, the gate insulating film GI′ may be made of silicon oxide, silicon oxynitride, silicon nitride, or other insulating materials. For example, the gate insulating film GI′ may be manufactured by using a plasma enhanced chemical vapor deposition (PECVD) process.
- In S230, as shown in
FIGS. 4c and 5c , the gate insulating film GI′ is patterned to form a gate insulating layer GI with at least one via hole K. The at least one via hole K exposes at least one portion of a surface of the at least oneconductive line 2. An orthogonal projection of the at least one via hole K on thebase 1 is at least partially overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. Theoxide semiconductor film 3 is in direct contact with the at least oneconductive line 2 through the at least one via hole K. - For example, the gate insulating film GI′ may be patterned through a photoetching process to obtain the gate insulating layer GI.
- Optionally, the gate insulating layer GI covers the gate conductive layer Gate. The orthogonal projection of the at least one via hole K on the
base 1 is at least partially overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. That is, the at least one via hole K exposes at least one portion of the at least oneconductive line 2. The via hole(s) K may be one or more. - Here, a relationship between the at least one via hole K and the at least one
conductive line 2 is various, which may be selectively set according to actual needs. - For example, the at least one via hole K may be in one-to-one correspondence with the at least one
conductive line 2. That is, one via hole K may expose a portion of oneconductive line 2. - For example, in a case where the number of the at least one via hole K is multiple, one
conductive line 2 may correspond to at least two of the multiple via holes K. That is, in the at least two via holes K, each via hole K may expose a portion of the correspondingconductive line 2. - For example, in a case where the number of the at least one
conductive line 2 is multiple, one via hole K may correspond to at least two of the multipleconductive lines 2. That is, the via hole K exposes portions of the at least twoconductive lines 2 synchronously. - Accordingly, in S300 described above, the formed
oxide semiconductor film 3 may be in direct contact with the at least oneconductive line 2 through the at least one via hole K. In S400 described above, in the process of patterning theoxide semiconductor film 3, the static electricity generated in theoxide semiconductor film 3 may be discharged into the at least oneconductive line 2 through a portion of theoxide semiconductor film 3 located in the at least one via hole K, and be discharged through the at least oneconductive line 2. - In addition, in S400 described above, after the
oxide semiconductor layer 3 a is formed, theoxide semiconductor layer 3 a may expose the at least one via hole K, and thus expose the at least one portion of the at least oneconductive line 2. In other words, after theoxide semiconductor film 3 is patterned, the orthogonal projection of the formedoxide semiconductor layer 3 a on thebase 1 may not be overlapped with the orthogonal projection of the at least one via hole K on thebase 1, so as to completely remove the oxide semiconductor material in the at least one via hole K. - In an implementation of the present disclosure, as shown in
FIG. 5c , in a direction (the 0-0′ direction) perpendicular to a routing direction of the at least oneconductive line 2, a portion of a boundary of the orthogonal projection of the at least oneconductive line 2 on thebase 1 coincides with a portion of a boundary of the orthogonal projection of the at least one via hole K on thebase 1. That is, in the direction (the 0-0′ direction) perpendicular to the routing direction of the at least oneconductive line 2, the at least one via hole K completely exposes the portion of the at least oneconductive line 2, so that the at least oneconductive line 2 and theoxide semiconductor film 3 have a large contact area therebetween, so as to improve a diffusion efficiency of electrostatic charges in theoxide semiconductor film 3. - In some embodiments, the method of manufacturing the array substrate may further include:
manufacturing sources 53 and drains 54 of the oxidethin film transistors 5. For example, the method of manufacturing the array substrate may further include S500. - In S500, as shown in
FIGS. 4f and 5k , a source-drain conductive layer SD is formed on a side of theoxide semiconductor layer 3 a away from thebase 1. The source-drain conductive layer SD may include a plurality ofsources 53 and a plurality ofdrains 54. The plurality ofsources 53 are electrically connected to the plurality ofactive layers 51 in one-to-one correspondence, and the plurality ofdrains 54 are electrically connected to the plurality ofactive layers 51 in one-to-one correspondence. - It can be understood that the oxide
thin film transistor 5 may include theactive layer 51, thesource 53 and thedrain 54. - Optionally, as shown in
FIGS. 4f and 5k , the source-drain conductive layer SD may further include auxiliary lead(s) 6, and the auxiliary lead(s) 6 are electrically connected to the at least oneconductive line 2. For example, the auxiliary lead(s) 6 may be in direct contact with the at least oneconductive line 2 in one-to-one correspondence, so as to form electrical connection(s). - By electrically connecting the auxiliary lead(s) 6 and the at least one
conductive line 2, theauxiliary lead 6 may be used to reduce a resistance of theconductive line 2 electrically connected to theauxiliary lead 6, which improves stability of an electrical signal transmitted in theconductive line 2. In addition, since theauxiliary lead 6 may be used to reduce the resistance of theconductive line 2 electrically connected to theauxiliary lead 6, a line width (i.e., a dimension of theconductive line 2 in the direction perpendicular to the routing direction of the conductive line 2) of theconductive line 2 may be reduced, thereby reducing a space ratio of theconductive line 2 in the array substrate. - In an implementation of the present disclosure, the source-drain conductive layer SD may be formed by a following method.
- For example, as shown in
FIG. 5j , a source-drain conductive material film SD′ may be formed on the side of theoxide semiconductor layer 3 a away from thebase 1, and the source-drain conductive material film SD′ covers the portion of the at least oneconductive line 2 that is exposed through the at least one via hole K, a portion of the gate insulating layer GI that is not covered by theactive layers 51, and theactive layers 51. - Optionally, the source-drain conductive material film SD′ may be made of titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta), or an alloy thereof, or a combination of at least two of the foregoing materials. The source-drain conductive material film SD′ may be of a single-layer structure formed by a layer of conductive material, or may be of a multi-layer structure formed by a plurality of layers of conductive materials that are sequentially stacked.
- Optionally, a sputtering process may be used to form the source-drain conductive material film SD′.
- For example, as shown in
FIG. 5k , the source-drain conductive material film SD′ may be patterned to form the source-drain conductive layer SD including the auxiliary lead(s) 6, thesources 53 and thedrains 54. - Optionally, the source-drain conductive material film SD′ may be patterned through a photoetching process.
- Optionally, the source-drain conductive layer SD may further include source-drain layer leads, for example, include voltage lead(s) and data lines DL.
- Optionally, orthogonal projections of the
auxiliary lead 6 and theconductive line 2 electrically connected to theauxiliary lead 6 on thebase 1 may coincide with each other or may partially overlap. - In some embodiments, as shown in
FIGS. 4g and 5l , the formedarray substrate 100 may have a display area A and a bezel area B located beside the display area A. Accordingly, thebase 1 also has a bezel area and a display area. An orthogonal projection of the bezel area B of thearray substrate 100 on a plane parallel to thebase 1 coincides with an orthogonal projection of the bezel area of thebase 1 on the plane parallel to thebase 1, and an orthogonal projection of the display area A of thearray substrate 100 on the plane parallel to thebase 1 coincides with an orthogonal projection of the display area of thebase 1 on the plane parallel to thebase 1. - For example, beside the display area A refer to a side, two sides, three sides, or peripheral sides of the display area A (as shown in
FIG. 4g ), which means that the bezel area B may be located at one, two or three sides of the display area A, or the bezel area B may be arranged around the display area A. - In some examples, as shown in
FIGS. 4g and 5l , the at least oneconductive line 2 that is in direct contact with theoxide semiconductor film 3 may be formed in the bezel area B of thearray substrate 100. In this case, the at least oneconductive line 2 may be first common electrode line(s) used to provide a common voltage signal to the display area A, or may be electrostatic protection line(s) used to perform an electrostatic protection on thearray substrate 100. - The at least one
conductive line 2 may have a large dimension in the direction perpendicular to the routing direction of the at least oneconductive line 2, so as to ensure that the at least oneconductive line 2 has a small impedance, thereby ensuring the stability of the electrical signal transmitted by the at least oneconductive line 2. By electrically connecting the at least oneconductive line 2 and the auxiliary lead(s) 6, the resistance of the at least oneconductive line 2 may be reduced, thereby reducing the line width of the at least oneconductive line 2, which is beneficial to reducing a size of the bezel area B, so as to realize a narrow bezel design for thearray substrate 100. - In some other examples, the at least one
conductive line 2 that is in direct contact with theoxide semiconductor film 3 may be formed in the display area A of thearray substrate 100. In this case, the at least oneconductive line 2 may be second common electrode line(s) that transmit a common voltage signal to an electrode layer (e.g., a common electrode layer or a cathode layer) in the array substrate. - In some embodiments, as shown in
FIG. 5l , the method of manufacturing the array substrate may further include: forming a passivation layer (PVX) 7 on a side of the oxidethin film transistors 5 away from thebase 1. As shown inFIGS. 4g and 5l , a plurality ofpixel electrodes 8 are formed on a side of thepassivation layer 7 away from thebase 1, and the plurality ofpixel electrodes 8 are electrically connected to thesources 53 or thedrains 54 of the plurality of oxidethin film transistors 5 in one-to-one correspondence. - Further, as shown in
FIG. 5l , the method of manufacturing the array substrate may further include: before forming thepixel electrodes 8, forming a planarization layer covering thepassivation layer 7, so as to provide a planar surface for thepixel electrodes 8. Here, thepixel electrodes 8 may be formed on a surface of the planarization layer away from thebase 1. - Based on this, the manufactured
array substrate 100 may be applied to a liquid crystal display (LCD) apparatus. In this case, the method of manufacturing thearray substrate 100 may further include: forming a common electrode at a side of thepixel electrodes 8 away from thebase 1. - In an implementation of the present disclosure, the method of manufacturing the array substrate may further include: sequentially forming a light-emitting layer and the cathode layer on the side of the
pixel electrode 8 away from thebase 1. In a case where the at least oneconductive line 2 is the first common electrode line(s) or the second common electrode line(s), the cathode layer may be electrically connected to the at least oneconductive line 2, or electrically connected to the auxiliary lead(s) 6, or electrically connected to both the at least oneconductive line 2 and the auxiliary lead(s) 6. - Based on this, the manufactured array substrate may be applied to an organic light-emitting diode (OLED) display apparatus.
- An implementation manner of the method of manufacturing the array substrate will be exemplarily introduced below, so as to further explain and describe the principle and the effects of the method of manufacturing the array substrate. The method of manufacturing the array substrate is exemplarily as follows.
- For example, the
base 1 is provided. Thebase 1 is a glass base. Thebase 1 has the display area and the bezel area around the display area. - The gate conductive material film is formed on the side of the
base 1, and the gate conductive material film covers the display area and the bezel area of thebase 1. The gate conductive material film may be formed through a deposition process. For example, the gate conductive material film may be formed through a magnetron sputtering deposition process. - For example, as shown in
FIGS. 4a and 5a , the gate conductive material film is patterned to form the gate conductive layer Gate located in the display area A and the plurality ofconductive lines 2 located in the bezel area B. The gate conductive layer Gate includes the plurality of gate lines GL and the plurality ofgates 52 used to form the oxidethin film transistors 5. The plurality ofconductive lines 2 include at least one common electrode line used to provide the common voltage signal to the display area and/or at least one electrostatic protection line used to perform the electrostatic protection on thearray substrate 100. - For example, as shown in
FIGS. 4b and 5b , the gate insulating film GI′ covering the gate conductive layer Gate and the plurality ofconductive lines 2 is formed on the side of both the gate conductive layer Gate and the plurality ofconductive lines 2 away from thebase 1. The gate insulating film GI′ may be formed through a deposition process. For example, the gate insulating film GI′ may be formed through a chemical vapor deposition (CVD) process. - For example, as shown in
FIGS. 4c and 5c , the gate insulating film GI′ is patterned with a mask to form the gate insulating layer GI with the at least one via hole K. The at least one via hole K exposes the portion of the at least oneconductive line 2. Optionally, in the direction (the 0-0′ direction) perpendicular to the routing direction of the at least oneconductive line 2, the portion of the boundary of the orthogonal projection of the at least oneconductive line 2 on thebase 1 coincides with the portion of the boundary of the orthogonal projection of the at least one via hole K on thebase 1. It can be understood that the mask may have a pattern used to form the at least one via hole K in the bezel area B. - For example, as shown in
FIGS. 4d and 5d , theoxide semiconductor film 3 is formed on a side of the gate insulating layer GI away from thebase 1. Theoxide semiconductor film 3 is located both in the display area A and the bezel area B. Theoxide semiconductor film 3 is in direct contact with the at least oneconductive line 2 through the at least one via hole K in the gate insulating layer GI. Here, theoxide semiconductor film 3 may be formed through a deposition process. For example, theoxide semiconductor film 3 may be formed through a magnetron sputtering process. - For example, as shown in
FIGS. 4e and 5e to 5i , theoxide semiconductor film 3 is patterned to form theoxide semiconductor layer 3 a. Theoxide semiconductor layer 3 a includes the plurality ofactive layers 51 used to form the oxidethin film transistors 5, and theoxide semiconductor layer 3 a does not cover the at least oneconductive line 2. In other words, the orthogonal projection of theoxide semiconductor layer 3 a on thebase 1 is completely non-overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. - Here, in the process of patterning the
oxide semiconductor film 3, a substrate including theoxide semiconductor film 3 may be transported into the exposure machine for exposure. Since the oxide semiconductor material is usually the substance with the amorphous structure, and is poor in conductivity, the static electricity is easily generated in theoxide semiconductor film 3 in the exposure machine. Since theoxide semiconductor film 3 is in direct contact with the at least oneconductive line 2, the static electricity generated in theoxide semiconductor film 3 may be discharged into the at least oneconductive line 2, and be discharged through the at least oneconductive line 2, which reduces or even avoids the electrostatic accumulation, and effectively avoids the electrostatic breakdown. - After the
oxide semiconductor film 3 is patterned, the portion of theoxide semiconductor film 3 located above and inside the at least one via hole K is removed to expose the portion of the surface of the at least oneconductive line 2. - For example, as shown in
FIG. 5j , the source-drain conductive material film SD′ is formed on the side of theoxide semiconductor layer 3 a away from thebase 1, and the source-drain conductive material film SD′ is located both in the display area A and the bezel area B. That is, the source-drain conductive material film SD′ covers the exposed at least oneconductive line 2, the portion of the gate insulating layer GI that is not covered by theactive layers 51, and theactive layers 51. The source-drain conductive material film SD′ may be formed through a deposition process. For example, the source-drain conductive material film SD′ may be formed through a magnetron sputtering process. - For example, as shown in
FIGS. 4f and 5k , the source-drain conductive material film SD′ is patterned to form the source-drain conductive layer SD. The source-drain conductive layer SD includes the auxiliary lead(s) 6 located in the bezel area B and in direct contact with the at least oneconductive line 2 through the via hole(s) K, and both a plurality of data lines DL and thesources 53 and thedrains 54 of the oxidethin film transistors 5 located in the display area A. - The
auxiliary lead 6 may be connected in parallel with theconductive line 2 to reduce the resistance of theconductive line 2, which not only improves the stability of the electrical signal transmitted in the at least oneconductive line 2, but also reduces the dimension of the at least oneconductive line 2 in the direction perpendicular to the routing direction of the at least oneconductive line 2, thereby facilitating reduction in the size of the bezel area B, and facilitating realization of the narrow frame design for thearray substrate 100. - For example, as shown in
FIG. 51 , the passivation layer (PVX) 7 and theplanarization layer 9 are sequentially formed on a side of the source-drain conductive layer SD away from thebase 1. - For example, as shown in
FIGS. 4g and 5l , the plurality ofpixel electrodes 8 are formed on a side of the planarization layer away from thebase 1. The plurality ofpixel electrodes 8 are electrically connected to thedrains 54 of the plurality of oxidethin film transistors 5, respectively. A material of thepixel electrodes 8 may be, for example, ITO. - Furthermore, the method of manufacturing the array substrate may exemplarily further include: sequentially forming the light-emitting layer and the cathode layer on the side of the
pixel electrodes 8 away from thebase 1, the cathode layer extending to the bezel area B and being in direct contact with the auxiliary lead(s) 6 to form electrical connections; forming a protective layer on a side of the cathode layer away from thebase 1. Here, theconductive line 2 electrically connected to the auxiliary lead may be the common electrode line. - It will be noted that although the various steps of the method are described in a specific order in the drawings, this does not require or imply that these steps must be performed in the specific order, or that all the steps shown must be performed to achieve a desired result. Additionally or alternatively, certain steps may be omitted, a plurality of steps may be combined into one step for execution, and/or one step may be broken down into a plurality of steps for execution, which all should be regarded as parts of the present disclosure.
- Some embodiments of the present disclosure further provide an
array substrate 100. As shown inFIG. 6 , thearray substrate 100 may include abase 1, a plurality ofconductive lines 2 and a plurality of oxidethin film transistors 5. - In some examples, a material of the
base 1 may refer to the schematic descriptions in some of the above embodiments, which will not be repeated here. - In some examples, as shown in
FIG. 6 , the plurality of oxidethin film transistors 5 and the plurality ofconductive lines 2 are disposed on the same side of thebase 1. - For example, each oxide
thin film transistor 5 includes anactive layer 51, agate 52, asource 53 and adrain 54. Theactive layer 51 of any oxidethin film transistor 5 is obtained by patterning anoxide semiconductor film 3 that is in direct contact with at least one conductive line 2 (e.g., reference may be made to the method of manufacturing the array substrate provided in some of the above embodiments). Theactive layer 51 of any oxidethin film transistor 5 and the at least oneconductive line 2 are insulated from each other. - A category of the
active layers 51 is various. For example, the material of theactive layers 51 may be an oxide semiconductor material. Optionally, the oxide semiconductor material may be an amorphous oxide semiconductor material. For example, the amorphous oxide semiconductor material may be one of zinc oxide, indium oxide, stannic oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide or indium aluminum zinc oxide. - The
array substrate 100 provided by some embodiments of the present disclosure may be manufactured through the method of manufacturing the array substrate in some of the above embodiments. Since theactive layers 51 of the plurality of oxidethin film transistors 5 are obtained by patterning theoxide semiconductor film 3 that is in direct contact with the at least oneconductive line 2, and the at least oneconductive line 2 has a good conductivity, static electricity generated in theoxide semiconductor film 3 may be discharged into the at least oneconductive line 2, and be discharged through the at least oneconductive line 2, which avoids an electrostatic accumulation in anoxide semiconductor layer 3 a including a plurality ofactive layers 51, thereby avoiding an electrostatic breakdown, and effectively improving a yield of thearray substrate 100. - A structure of the
array substrate 100 in some embodiments of the present disclosure will be schematically described below with reference to the accompanying drawings. - Here, as shown in
FIG. 6 , the oxidethin film transistor 5 is a bottom-gate oxide thin film transistor, which is taken as an example. - Based on this, the plurality of
conductive lines 2 and thegates 52 of respective oxidethin film transistors 5 are located at a side of theactive layers 51 proximate to thebase 1. - In some examples, the plurality of
conductive lines 2 and thegates 52 are made of the same material and arranged in the same layer. - It will be noted that the “same layer” mentioned herein means that a film for forming a specific pattern is formed by using the same film-forming process, and then is patterned by a same patterning process by using the same mask to form a layer structure. Depending on different specific patterns, the same patterning process may include several exposure, development or etching processes, the specific patterns formed in the layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the plurality of
conductive lines 2 and thegates 52 may be manufactured in a same patterning process, which is beneficial to simplify a manufacturing process of thearray substrate 100. - In some embodiments, the
array substrate 100 further includes a gate insulating layer GI disposed between thegates 52 and theactive layers 51. Here, thegates 52 belong to a gate conductive layer Gate, and theactive layers 51 belong to theoxide semiconductor layer 3 a. That is, the gate insulating layer GI is located between the gate conductive layer Gate and theoxide semiconductor layer 3 a. For example, the gate conductive layer Gate may further include gate lines GL. - In some examples, as shown in
FIG. 6 , the gate insulating layer GI has at least one via hole K that exposes at least one portion of the at least oneconductive line 2. That is, an orthogonal projection of the at least one via hole K on thebase 1 is at least partially overlapped with an orthogonal projection of the at least oneconductive line 2 on thebase 1. - For example, in a direction (the 0-0′ direction) perpendicular to a routing direction of the at least one
conductive line 2, a portion of a boundary of the orthogonal projection of the at least oneconductive line 2 on thebase 1 coincides with a portion of a boundary of the orthogonal projection of the at least one via hole K on thebase 1. - The
oxide semiconductor film 3 may be electrically connected to the at least oneconductive line 2 through the at least one via hole K. In this way, in a case where the static electricity is generated in theoxide semiconductor film 3, the static electricity may be discharged into the at least oneconductive line 2 through a portion of theoxide semiconductor film 3 located in the at least one via hole K, and then the static electricity is discharged through the at least oneconductive line 2. - In some examples, as shown in
FIG. 6 , the array substrate further includes auxiliary lead(s) 6 that are in direct contact with the at least oneconductive line 2. - The auxiliary lead(s) 6 can be set in various ways, which may be selectively set according to actual needs.
- For example, as shown in
FIG. 6 , the auxiliary lead(s) 6 may be disposed on a side of the gate insulating layer GI away from thebase 1, and the auxiliary lead(s) 6 are in direct contact with the at least oneconductive line 2 through the at least one via hole K. In this way, the auxiliary lead(s) 6 may be used to reduce a resistance of the at least oneconductive line 2, thereby reducing a dimension of the at least oneconductive line 2 in the direction perpendicular to the routing direction of the at least oneconductive line 2, and reducing a space ratio of the at least oneconductive line 2 in thearray substrate 100. - For example, as shown in
FIG. 6 , the auxiliary lead(s) 6 and thesources 53 and thedrains 54 of the oxidethin film transistors 5 may be made of the same material and arranged in the same layer. In this way, the auxiliary lead(s) 6, thesources 53, and thedrains 54 may be manufactured in a same patterning process, which is beneficial to simplify the manufacturing process of thearray substrate 100. - Here, for example, a film including the auxiliary lead(s) 6, the
sources 53 and thedrains 54 may be referred to as a source-drain conductive layer SD. Optionally, the source-drain conductive layer SD may further include data lines DL and power lines. - In some examples, as shown in
FIG. 6 , orthogonal projection(s) of the auxiliary lead(s) 6 on thebase 1 are at least partially overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. - For example, the auxiliary lead(s) 6 are in one-to-one correspondence with the at least one
conductive line 2. The orthogonal projection of theauxiliary lead 6 on thebase 1 is at least partially overlapped with the orthogonal projection of a correspondingconductive line 2 on thebase 1, which may include: a partial misalignment being present between theauxiliary lead 6 and theconductive line 2, so that a portion of the orthogonal projection of theauxiliary lead 6 on thebase 1 is overlapped with a portion of the orthogonal projection of the correspondingconductive line 2 on thebase 1; or, the orthogonal projection of theauxiliary lead 6 on thebase 1 being located within the orthogonal projection of the correspondingconductive line 2 on thebase 1. - In some examples, as shown in
FIG. 4g , a routing direction of theauxiliary lead 6 is the same or substantially the same as the routing direction of the at least oneconductive line 2. That is, an angle between a routing direction of a portion of theauxiliary lead 6 and a routing direction of a portion of theconductive line 2 that is overlapped with the portion of theauxiliary lead 6 is 0° or approximately 0°. This is beneficial to ensure the reduction in the resistance of the at least oneconductive line 2. - In some embodiments, as shown in
FIG. 6 , thearray substrate 100 may further include apassivation layer 7 disposed on a side of both thesources 53 and thedrains 54 away from the base 1 (i.e., covering the oxide thin film transistors 5). - In some examples, as shown in
FIG. 7 , in a case where thearray substrate 100 does not include theauxiliary lead 6, a portion of thepassivation layer 7 may be located in the at least one via hole K in the gate insulating layer GI. In this way, it is possible to prevent a conductive layer (e.g., pixel electrodes 8) subsequently formed from forming electrical connection(s) with the at least oneconductive line 2, so as to avoid signal crosstalk. - In some embodiments, as shown in
FIG. 6 , thearray substrate 100 may further include thepixel electrodes 8 disposed at a side of thepassivation layer 7 away from thebase 1. Thepixel electrodes 8 may be, for example, electrically connected to thedrains 54 of the oxidethin film transistors 5. - Optionally, the
array substrate 100 may further include a planarization layer disposed between thepassivation layer 7 and thepixel electrodes 8. - In some embodiments, as shown in
FIG. 6 , thearray substrate 100 has a display area A and a bezel area B located beside the display area A. For “beside the display area A”, reference may be made to the schematic descriptions in some of the above examples. - In some examples, the oxide
thin film transistors 5 in thearray substrate 100 may be located in the display area A. Among the plurality ofconductive lines 2, the at least oneconductive line 2 electrically connected to theoxide semiconductor film 3 may be located in the display area A, or may be located in the bezel area B. - Here, in a case where the at least one
conductive line 2 is located in the display area A, the at least oneconductive line 2 may be second common electrode line(s) that transmit a common voltage signal to an electrode layer (e.g., a common electrode layer or a cathode layer) in the array substrate. In a case where the at least oneconductive line 2 is located in the bezel area B, the at least oneconductive line 2 may be first common electrode line(s) used to provide a common voltage signal to the display area A, or may be electrostatic protection line(s) used to perform an electrostatic protection on thearray substrate 100. - An implementation manner of the array substrate in the present disclosure will be exemplarily introduced below to further explain and describe the structure and principle of the array substrate in the present disclosure.
- In an
exemplary array substrate 100, as shown inFIG. 6 , thearray substrate 100 may include thebase 1, the plurality ofconductive lines 2, the gate conductive layer Gate, the gate insulating layer GI, theoxide semiconductor layer 3 a, the source-drain conductive layer SD, thepassivation layer 7 and the plurality ofpixel electrodes 8. - For example, the
base 1 may be a glass base. Thebase 1 may have a display area and a bezel area around the display area. - For example, the plurality of
conductive lines 2 may be located in the bezel area of thebase 1. The gate conductive layer Gate may be located in the display area of thebase 1. The gate conductive layer Gate and the plurality ofconductive lines 2 may be disposed on the same side and located on the same surface of thebase 1. For example, the gate conductive layer Gate and the plurality ofconductive lines 2 are made of the same material and arranged in the same layer. The gate conductive layer Gate may include the plurality of gate lines GL and the plurality ofgates 52 used to form the oxidethin film transistors 5. - For example, the gate insulating layer GI may be disposed on a side of both the plurality of
conductive lines 2 and the gate conductive layer Gate away from thebase 1. The gate insulating layer GI has the at least one via hole K, and the at least one via hole K exposes a portion of the at least one of the plurality ofconductive lines 2. That is, the orthogonal projection of the at least one via hole K on thebase 1 is partially overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. - For example, the
oxide semiconductor layer 3 a may be disposed at the side of the gate conductive layer Gate away from thebase 1. Theoxide semiconductor layer 3 a includes the plurality ofactive layers 51 used to form the oxidethin film transistors 5, and an orthogonal projection of theoxide semiconductor layer 3 a on thebase 1 is completely non-overlapped with the orthogonal projection of the at least oneconductive line 2 on thebase 1. Theoxide semiconductor layer 3 a is obtained by patterning theoxide semiconductor film 3 that is in direct contact with the at least oneconductive line 2. - For example, the source-drain conductive layer SD may be disposed on a side of the
oxide semiconductor layer 3 a away from thebase 1. The source-drain conductive layer SD may include the auxiliary lead(s) 6 electrically connected to the at least oneconductive line 2 through the at least one via hole K in the gate insulating layer GI, a plurality of source-drain layer leads (e.g., data lines DL), and thesources 53 and thedrains 54 of the oxidethin film transistors 5. The auxiliary lead(s) 6 may be disposed in the bezel area B, and the source-drain layer leads, thesources 53, and thedrains 54 are disposed in the display area A. - For example, the
passivation layer 7 may be formed on a side of the source-drain conductive layer SD away from thebase 1. Thepassivation layer 7 may expose portions of thedrains 54 in the source-drain conductive layer SD. - For example, the plurality of
pixel electrodes 8 may be disposed at the side of thepassivation layer 7 away from thebase 1. The plurality ofpixel electrodes 8 may be electrically connected to the plurality ofdrains 54 in one-to-one correspondence. - The
array substrate 100 may be manufactured through the method of manufacturing the array substrate in some of the above embodiments, and the structure, principle and effects of thearray substrate 100 have been described in detail in the method of manufacturing the array substrate in some of the above embodiments, which will not be repeated here. - Some embodiments of the present disclosure further provide a
display apparatus 1000. As shown inFIGS. 8 and 9 , thedisplay apparatus 1000 includes thearray substrate 100 as described in some of the above embodiments. - Beneficial effects that may be achieved by the
display apparatus 1000 in some embodiments of the present disclosure are the same as the beneficial effects that may be achieved by thearray substrate 100 in some of the above embodiments, which will not be repeated here. - A category of the
display apparatus 1000 is various, which may be selectively set according to actual needs. - In some examples, as shown in
FIG. 8 , thedisplay apparatus 1000 may be a liquid crystal display (LCD) apparatus. In this case, thedisplay apparatus 1000 may further include anopposite substrate 200 arranged opposite to thearray substrate 100, and aliquid crystal layer 300 disposed between thearray substrate 100 and theopposite substrate 200. - For example, the
opposite substrate 200 may be a transparent substrate, or may be a color film substrate (as shown inFIG. 8 ). In a case where theopposite substrate 200 is the transparent substrate, thearray substrate 100 may further include a color film layer and/or black matrixes disposed on a side of thepixel electrodes 8 proximate to theopposite substrate 200. - In some other examples, as shown in
FIG. 9 , thedisplay apparatus 1000 may be an organic light-emitting diode (OLED) display apparatus. In this case, thedisplay apparatus 1000 may further include a plurality of light-emittingdevices 400 disposed on a side of the plurality of oxidethin film transistors 5 in thearray substrate 100 away from thebase 1. - For example, the
pixel electrode 8 in thearray substrate 100 may be referred to as an anode layer of the light-emittingdevice 400. On this basis, the light-emittingdevice 400 may further include a light-emitting layer and a cathode layer that are sequentially stacked on a side of the anode layer away from thebase 1. - In some embodiments, the
display apparatus 100 may be any apparatus that displays images whether in motion (e.g., a video) or stationary (e.g., a static image), and whether literal or graphical. It is anticipated that the described embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDA), handheld or portable computers, global positioning system (GPS) receivers/navigators, cameras, moving picture experts group 4 (MP4) video players, video cameras, game consoles, watches, clocks, calculators, television monitors, computer monitors, car displays (e.g., odometer displays), navigators, cockpit controllers and/or displays, camera view displays (e.g., rear-view camera displays in vehicles), electronic photographs, electronic billboards or direction boards, projectors, building structures, packaging and aesthetic structures (e.g., a display for an image of a piece of jewelry). - It can be understood that the present disclosure does not limit the application thereof to the detailed structures and arrangements of the components proposed in the description. The present disclosure may have other implementation manners, and may be implemented and executed in various ways. The above deformation and modification forms fall within the scope of the present disclosure. It can be understood that the present disclosure disclosed and defined in the description extends to all alternative combinations of two or more individual features mentioned or obvious in the context and/or the accompanying drawings. All these different combinations constitute various alternative aspects of the present disclosure.
- The forgoing descriptions are merely specific implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Changes or replacements that any person skilled in the art could readily conceive of within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (20)
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CN201910913692.1 | 2019-09-25 | ||
CN201910913692.1A CN110518023B (en) | 2019-09-25 | 2019-09-25 | Array substrate and preparation method thereof |
PCT/CN2020/117632 WO2021057883A1 (en) | 2019-09-25 | 2020-09-25 | Array substrate and preparation method therefor, and display apparatus |
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US20220028901A1 US20220028901A1 (en) | 2022-01-27 |
US20220278134A2 true US20220278134A2 (en) | 2022-09-01 |
US12021091B2 US12021091B2 (en) | 2024-06-25 |
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US20220028901A1 (en) | 2022-01-27 |
WO2021057883A1 (en) | 2021-04-01 |
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