WO2021057883A1

WO2021057883A1 - Array substrate and preparation method therefor, and display apparatus

Info

Publication number: WO2021057883A1
Application number: PCT/CN2020/117632
Authority: WO
Inventors: 林滨; 曾勇; 霍亚洲; 李梁梁; 陈周煜
Original assignee: 京东方科技集团股份有限公司; 福州京东方光电科技有限公司
Priority date: 2019-09-25
Filing date: 2020-09-25
Publication date: 2021-04-01
Also published as: CN110518023B; US20220278134A2; CN110518023A; US20220028901A1; US12021091B2

Abstract

A preparation method for an array substrate, comprising: providing a substrate; forming multiple wires on the substrate; forming an oxide semiconductor thin film on the side of the multiple wires furthest from the substrate, the oxide semiconductor thin film covering the multiple wires and being in direct contact with at least one signal line, the at least one wire being configured to guide out the static electricity produced in the oxide semiconductor thin film; and, using a photolithography process, performing patterning processing on the oxide semiconductor thin film to remove the part in direct contact with the at least one wire and form an oxide semiconductor layer comprising active layers of multiple oxide thin film transistors.

Description

Array substrate, preparation method thereof, and display device

This application claims the priority of the Chinese patent application with application number 201910913692.1 filed on September 25, 2019, the entire content of which is incorporated into this application by reference.

Technical field

The present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.

Background technique

The oxide thin film transistor uses an oxide semiconductor material as an active layer, which has good uniformity, and is especially suitable for large-area display requirements.

Summary of the invention

In one aspect, a method for manufacturing an array substrate is provided. The preparation method of the array substrate includes: providing a substrate; forming a plurality of wires on one side of the substrate; forming an oxide semiconductor film on the side of the plurality of wires away from the substrate, and the oxide The semiconductor thin film covers the plurality of wires and directly contacts with at least one wire; the at least one wire is configured to extract static electricity generated in the oxide semiconductor thin film; and the oxide semiconductor thin film is processed by a photolithography process. The patterning process removes the part directly in contact with the at least one wire to form an oxide semiconductor layer including an active layer of a plurality of oxide thin film transistors.

In some embodiments, the manufacturing method of the array substrate further includes: before forming the oxide semiconductor film, forming a gate conductive layer including the gates of a plurality of oxide thin film transistors; The multiple wires are located on the same side of the substrate. A gate insulating film is formed on the side of the plurality of wires and the gate conductive layer away from the substrate; the gate insulating film covers the plurality of wires and the gate conductive layer. The gate insulating film is patterned to form a gate insulating layer with at least one via; the at least one via exposes at least a part of the surface of the at least one wire, and the at least one via is in the substrate The orthographic projection on the substrate at least partially overlaps the orthographic projection of the at least one wire on the substrate. Wherein, the oxide semiconductor film is in direct contact with the at least one wire through the at least one via hole.

In some embodiments, along the line direction perpendicular to the at least one wire, a part of the boundary of the orthographic projection of the at least one wire on the substrate is connected to the at least one via on the substrate. Part of the boundary of the orthographic projection coincides.

In some embodiments, the material of the plurality of wires includes a metal material; the plurality of wires and the gate conductive layer are formed in the same patterning process.

In some embodiments, the method for preparing the array substrate further includes: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the substrate, and the source-drain conductive layer includes a conductive layer connected to each active layer. The source electrode and the drain electrode in direct contact with the layer, and an auxiliary lead directly in contact with the at least one wire.

In some embodiments, the array substrate has a display area and a frame area located beside the display area. The auxiliary lead is located in the frame area. The at least one wire is configured to transmit a common voltage signal to the display area or to protect the array substrate from static electricity. The auxiliary lead is configured to be connected in parallel with the at least one wire to reduce the resistance of the at least one wire.

In some embodiments, the material of the oxide semiconductor film includes zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide It is one of indium aluminum zinc oxide and indium aluminum zinc oxide.

In some embodiments, the orthographic projection of the oxide semiconductor layer on the substrate and the orthographic projection of the at least one wire on the substrate overlap at most.

In another aspect, an array substrate is provided. The array substrate includes: a substrate; a plurality of wires arranged on one side of the substrate; and a plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of wires are arranged on the substrate The same side of the bottom. Wherein, each oxide thin film transistor includes a gate, an active layer, a source and a drain; the active layers of the plurality of oxide thin film transistors are formed by patterning an oxide semiconductor thin film directly in contact with at least one wire. And the active layer and the at least one wire are insulated from each other.

In some embodiments, the array substrate further includes a gate insulating layer disposed between the gate and the active layer. The gate insulating layer has at least one via, the at least one via exposes at least a part of the surface of the at least one wire, and the orthographic projection of the at least one via on the substrate is in line with the at least one wire. The orthographic projections on the substrate at least partially overlap. The oxide semiconductor film directly contacts the at least one wire through the at least one via hole.

In some embodiments, the array substrate further includes: auxiliary leads arranged on a side of the gate insulating layer away from the substrate. The auxiliary lead directly contacts the at least one wire through the at least one via hole.

In some embodiments, the array substrate further includes: auxiliary leads with the same material as the source electrode and the drain electrode and arranged in the same layer. The auxiliary lead is in direct contact with the at least one wire.

In some embodiments, the orthographic projection of the auxiliary lead on the substrate and the orthographic projection of the at least one wire on the substrate at least partially overlap.

In some embodiments, the routing direction of the auxiliary lead is the same or substantially the same as the routing direction of the at least one wire.

In some embodiments, the array substrate further includes a passivation layer disposed on a side of the source electrode and the drain electrode away from the substrate. A part of the passivation layer is located in the at least one via and is in direct contact with the at least one wire.

In some embodiments, the array substrate has a display area and a frame area located beside the display area. The at least one wire is located in the frame area. The at least one wire includes a common electrode wire or an electrostatic protection wire. The common electrode line is configured to transmit a common voltage signal to the display area; the electrostatic protection line is configured to perform electrostatic protection on the array substrate.

In some embodiments, the gate electrode and the plurality of wires have the same material and are arranged in the same layer.

In another aspect, a display device is provided. The display device includes: the array substrate as described in any of the above embodiments.

In some embodiments, the display device further includes: a counter substrate disposed opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the counter substrate.

In some embodiments, the display device further includes: a plurality of light-emitting devices arranged on a side of the array substrate away from the substrate of the array substrate with a plurality of oxide thin film transistors.

Description of the drawings

In order to explain the technical solutions of the present disclosure more clearly, the following will briefly introduce the drawings that need to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are merely appendices to some embodiments of the present disclosure. Figures, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual size of the product, the actual process of the method, and the actual timing of the signal involved in the embodiments of the present disclosure.

FIG. 1 is a structural diagram of static electricity accumulated in an oxide semiconductor film according to the related art;

FIG. 2 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure;

FIG. 3 is a flowchart of another method for manufacturing an array substrate according to some embodiments of the present disclosure;

4a to 4g are schematic diagrams of a manufacturing process of an array substrate according to some embodiments of the present disclosure;

5a to 5l are schematic diagrams of a preparation process along the O-O' direction in the preparation process shown in Figs. 4a to 4g;

Fig. 6 is a structural diagram of an array substrate according to some embodiments of the present disclosure;

FIG. 7 is a structural diagram of another array substrate according to some embodiments of the present disclosure;

FIG. 8 is a structural diagram of a display device according to some embodiments of the present disclosure;

FIG. 9 is a structural diagram of another display device according to some embodiments of the present disclosure.

detailed description

The technical solutions in some embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those of ordinary skill in the art fall within the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms such as the third-person singular form "comprises" and the present participle form "comprising" are used throughout the specification and claims. Interpreted as open and inclusive means "including, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" "example)" or "some examples" are intended to indicate that a specific feature, structure, material, or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

Hereinafter, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expression "connected" and its extensions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

"A and/or B" includes the following three combinations: A only, B only, and the combination of A and B.

As used herein, depending on the context, the term "if" is optionally interpreted as meaning "when" or "when" or "in response to determination" or "in response to detection." Similarly, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is detected" is optionally interpreted to mean "when determining..." or "in response to determining..." Or "when [stated condition or event] is detected" or "in response to detecting [stated condition or event]".

The use of "applicable to" or "configured to" in this document means open and inclusive language, which does not exclude devices suitable for or configured to perform additional tasks or steps.

In addition, the use of "based on" means openness and inclusiveness, because processes, steps, calculations or other actions "based on" one or more of the stated conditions or values may be based on additional conditions or exceed the stated values in practice.

As used herein, "about" or "approximately" includes the stated value as well as an average value within an acceptable range of deviation of the specified value, where the acceptable range of deviation is considered by those of ordinary skill in the art to be discussed The measurement and the error associated with the measurement of a specific quantity (ie, the limitations of the measurement system).

The exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.

In the related art, for example, a photolithography process can be used to prepare an active layer forming an oxide thin film transistor.

That is, in the process of forming the active layer of the oxide thin film transistor, a layer of oxide semiconductor material film may be deposited first, and then a photoresist layer may be formed on one side surface of the oxide semiconductor material film. The resist layer is exposed and developed to obtain a patterned photoresist layer, and the patterned photoresist layer can be used to pattern the oxide semiconductor material film to obtain an active layer.

However, the oxide semiconductor material film is prone to generate and accumulate static electricity in the exposure machine, and then electrostatic breakdown (Electro-Static Discharge, ESD) phenomenon may occur, which reduces the yield of array substrates including oxide thin film transistors.

In an implementation manner, an oxide thin film transistor is taken as an example of a bottom-gate thin film transistor. As shown in FIG. 1, in the process of preparing an oxide thin film transistor, for example, a plurality of gates 1'may be formed first, and then On one side of the plurality of gates 1', a gate insulating layer 2'covering the plurality of gates 1'and an oxide semiconductor material film 3'covering the gate insulating layer 2'are sequentially formed, and then a photolithography process is used to The oxide semiconductor material film 3'is patterned.

Since the oxide semiconductor material is usually a substance with an amorphous structure, its conductivity is poor. During the process of exposing the photoresist layer in the exposure machine, static electricity is easily generated in the oxide semiconductor material film 3'. Not only that, the oxide semiconductor material film 3'can also form a parasitic capacitance structure with other conductive structures. For example, the oxide semiconductor material film 3'can form a parasitic capacitance structure with the gate 1'and induce different gates. A parasitic capacitance structure is formed between 1'. In the case where a large amount of static electricity generated in the oxide semiconductor material film 3'accumulates, the phenomenon of electrostatic breakdown is prone to occur.

Based on this, some embodiments of the present disclosure provide a method for manufacturing an array substrate. As shown in FIG. 2, the preparation method of the array substrate includes: S100-S400.

S100, a substrate 1 is provided.

The above-mentioned substrate 1 includes multiple materials, which can be selected and set according to actual needs.

In some examples, the above-mentioned substrate 1 may be a substrate of inorganic material, or a substrate of organic material.

For example, in an embodiment of the present disclosure, the material of the substrate 1 may be soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, or other materials. In another embodiment of the present disclosure, the material of the substrate 1 may be polymethyl methacrylate (PMMA for short), polyvinyl alcohol (PVA for short), or polyvinyl phenol (PMMA for short). , PVP for short), Polyethersulfone (PES for short), Polyimide (PI for short), polyamide, polyacetal, Polycarbonate (PC for short), Polyterephthalic acid Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a combination of at least two of them.

Here, when the substrate 1 uses an inorganic material, the substrate 1 may be a rigid substrate; when the substrate 1 uses an organic material, the substrate 1 may be a flexible substrate.

S200, as shown in FIG. 4a and FIG. 5a, a plurality of conductive lines 2 are formed on the substrate 1.

In some examples, the material of the aforementioned wire 2 may include one conductive material or a combination of multiple conductive materials.

Exemplarily, the material of the wire 2 may include a metal material, a conductive metal oxide material, a conductive metal nitride material, a conductive polymer material, a conductive composite material, or a combination of at least two of them.

Optionally, the foregoing metal material may be, for example, platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination of at least two of them.

Optionally, the aforementioned conductive metal oxide material may be, for example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO) metal oxide, or doped metal oxide.

Optionally, the aforementioned conductive metal nitride material may be titanium nitride or the like, for example.

Optionally, the above-mentioned conductive polymer material can be, for example, polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/polystyrene sulfonic acid (PEDOT/PSS) or among them At least a combination of the two, or the above-mentioned materials doped with dopants; among them, the dopant can be, for example, acids such as hydrochloric acid, sulfuric acid, and sulfonic acid, or Lewis acids such as PF6, AsF5, and FeCl3, or halogens such as iodide ion. Ion, or metal ions such as sodium ion and potassium ion.

Optionally, the aforementioned conductive composite material may be, for example, a conductive composite material dispersed with carbon black, graphite powder, metal particles, or the like.

In some examples, the above-mentioned wire 2 may be a single-layer structure composed of a layer of conductive material, or may be a multi-layer structure formed by sequentially stacking multiple layers of conductive materials.

For example, the wire 2 in the present disclosure may be a single-layer structure formed by a layer of metal material.

For another example, the wire 2 in the present disclosure may have a three-layer structure formed by a first metal layer, a second metal layer, and a first metal layer that are sequentially stacked. Wherein, the first metal layer may be a single-layer structure formed of at least one metal material, the second metal layer may be a single-layer structure formed of at least one metal material, and the metal material included in the first metal layer and the second metal layer The metal material included in the metal layer is different.

S300, as shown in FIGS. 4d and 5d, an oxide semiconductor film 3 is formed on the side of the plurality of wires 2 away from the substrate 1. The oxide semiconductor film 3 covers the plurality of wires 2 and directly contacts with at least one wire 2. That is, the oxide semiconductor thin film 3 may be in direct contact with one wire 2 or may be in direct contact with a plurality of wires 2. The at least one wire 2 is configured to discharge static electricity generated in the oxide semiconductor thin film 3.

In some examples, for example, a process such as magnetron sputtering may be used to prepare and form the above-mentioned oxide semiconductor film 3.

In some examples, the material of the above-mentioned oxide semiconductor thin film 3 may be an amorphous oxide semiconductor material.

For example, the oxide semiconductor material may be zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), Aluminum zinc oxide (AZO), yttrium zinc oxide (YZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (Indium aluminum zinc oxide) One of zinc oxide, IAZO for short. Optionally, the above-mentioned oxide semiconductor material may be in an amorphous state, that is, the above-mentioned oxide semiconductor material may be an amorphous oxide semiconductor material.

Exemplarily, the above-mentioned oxide semiconductor film 3 may be an amorphous indium gallium zinc oxide film.

S400, as shown in FIG. 4e and FIG. 5i, the oxide semiconductor thin film 3 is patterned to remove the portion directly in contact with the at least one wire 2 to form an oxide layer 51 including a plurality of oxide thin film transistors 5.物 Semiconductor layer 3a. The oxide semiconductor layer 3a and the above-mentioned at least one wire 2 are insulated from each other.

In some examples, in the above-mentioned S400, for example, a photolithography process may be used to pattern the oxide semiconductor film 3.

Exemplarily, as shown in FIGS. 5e to 5i, the oxide semiconductor thin film 3 is patterned by a photolithography process, including: S410 to S450.

S410, as shown in FIG. 5e, a photoresist layer PR is formed on the surface of the oxide semiconductor film 3 away from the substrate 1.

Exemplarily, a coating process may be used to coat a photoresist on the surface of the oxide semiconductor film 3 away from the substrate 1 to form a photoresist layer PR.

There are many types of the above-mentioned photoresist. For example, the above-mentioned photoresist may be a positive photoresist, or the above-mentioned photoresist may be a negative photoresist.

Hereinafter, the method for preparing the array substrate is schematically illustrated by taking the photoresist as a positive photoresist as an example.

S420, as shown in FIG. 5f, exposing the above-mentioned photoresist layer PR.

Exemplarily, the photoresist layer PR may be exposed in an exposure machine.

Exemplarily, in the process of exposing the photoresist layer PR, static electricity is generated in the oxide semiconductor film 3. In the case where the oxide semiconductor film 3 is electrically connected to at least one wire 2, the static electricity generated in the oxide semiconductor film 3 can be discharged into the at least one wire 2, and the static electricity is discharged through the at least one wire 2 to reduce Even the accumulation of static electricity in the oxide semiconductor thin film 3 is avoided, thereby avoiding the phenomenon of electrostatic breakdown caused by a large amount of static electricity accumulated in the oxide semiconductor thin film 3.

S430, as shown in FIG. 5g, the exposed photoresist layer PR is developed, and the exposed part of the photoresist layer PR is removed to obtain a patterned photoresist layer PR'. The patterned photoresist layer PR' exposes a part of the surface of the oxide semiconductor film 3 away from the substrate 1 and covers the rest of the oxide semiconductor film 3.

S440, as shown in FIG. 5h, using the patterned photoresist layer PR' as a mask, the oxide semiconductor film 3 is patterned, and the unpatterned light in the oxide semiconductor film 3 is removed by etching. The part covered by the resist layer PR' retains the part covered by the patterned photoresist layer PR' in the oxide semiconductor film 3, that is, the oxide semiconductor layer 3a.

It can be understood that the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 above overlap at most, and the oxide semiconductor layer 3a and the at least one wire 2 are insulated from each other. . In this way, the effective electrical connection between the at least one wire 2 and the thin film formed in the subsequent preparation can be ensured, and the power supply caused by the oxide semiconductor layer 3a sandwiched between the at least one wire 2 and the thin film formed in the subsequent preparation can be avoided. In the case of undesirable situations, it is possible to avoid adding an additional process to remove the portion of the oxide semiconductor layer 3a covering the at least one wire 2.

S450, as shown in FIG. 5i, remove the patterned photoresist layer PR'.

The manufacturing method of the array substrate provided by some embodiments of the present disclosure is to form a plurality of wires 2 on one side of the substrate 1, and after the oxide semiconductor film 3 is formed, the oxide semiconductor film 3 and at least one wire are formed. 2 Direct contact, so that in the process of patterning the oxide semiconductor film 3, the static electricity generated in the oxide semiconductor film 3 can be discharged to at least one wire 2 with good conductivity, which is beneficial to reduce the The accumulation of static electricity on the oxide semiconductor layer 3a of the multiple active layers 51 avoids the phenomenon of electrostatic breakdown and improves the yield of the prepared array substrate.

It should be noted that there are many types of thin film transistors 5 in the formed array substrate, which can be selected and set according to actual needs.

In some embodiments, the oxide thin film transistor 5 in the formed array substrate may be a bottom-gate oxide thin film transistor. In other embodiments, the oxide thin film transistor 5 in the formed array substrate may be a top gate type oxide thin film transistor.

Hereinafter, taking the oxide thin film transistor 5 in the formed array substrate as a bottom-gate oxide thin film transistor as an example, the preparation method of the array substrate will be schematically described. As shown in FIGS. 4a to 4c and FIGS. 5a to 5c, the preparation method of the array substrate may further include: S210 to S230.

S210, as shown in FIG. 4a and FIG. 5a, before the above S300, a gate conductive layer Gate is formed. The gate conductive layer Gate is located on the same side of the substrate 1 as the multiple wires 2 described above.

Exemplarily, the aforementioned gate conductive layer Gate may include a plurality of gate lines and a plurality of gate electrodes 52 of the oxide thin film transistor 5. Each gate 52 may be disposed opposite to the active layer 51 formed by subsequent preparation.

In some examples, the material and hierarchical structure of the gate conductive layer Gate may be the same as or different from the plurality of conductive lines 2.

In an embodiment of the present disclosure, the gate conductive layer Gate and the plurality of wires 2 may be provided on the same surface, and have the same structure and material, that is, the gate conductive layer Gate and the plurality of wires 2 may be on the same surface. Preparation and formation in the sub-patterning process.

For example, the gate conductive layer Gate and the plurality of wires 2 can be formed by the following method:

A gate conductive material film is formed on one side of the substrate 1; then the gate conductive material film is patterned to simultaneously form the plurality of wires 2 and the gate conductive layer Gate.

Optionally, the above-mentioned gate conductive material film may be patterned through a photolithography process.

S220, as shown in FIGS. 4b and 5b, a gate insulating film GI' is formed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1. The gate insulating film GI' covers the gate conductive layer Gate and the plurality of wires 2.

Optionally, the material of the gate insulating film GI' may be silicon oxide, silicon oxynitride, silicon nitride, or other insulating materials. The gate insulating film GI' can be prepared by, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process.

S230, as shown in FIG. 4c and FIG. 5c, the gate insulating film GI' is patterned to form a gate insulating layer GI having at least one via hole K. The at least one via K exposes at least a part of the surface of the at least one wire 2, and the orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap. Wherein, the oxide semiconductor film 3 directly contacts the at least one wire 2 through the at least one via K.

Exemplarily, the gate insulating film GI' may be patterned through a photolithography process to obtain the gate insulating layer GI.

Optionally, the gate insulating layer GI covers the gate conductive layer Gate. The orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap, that is, the at least one via K exposes a part of the at least one wire 2. Wherein, the number of via holes K may be one or multiple.

Here, the relationship between the at least one via K and the at least one wire 2 includes multiple types, which can be selected and set according to actual needs.

Exemplarily, the at least one via K may correspond to the at least one wire 2 in a one-to-one correspondence, that is, one via K may expose a part of the wire 2.

Exemplarily, when the number of the at least one via K is multiple, one wire 2 may correspond to at least two vias K in the multiple vias K, that is, the at least two vias K In the hole K, each via K can expose a part of a corresponding wire 2.

Exemplarily, when the number of the at least one wire 2 is multiple, one via K may correspond to at least two wires 2 of the multiple wires 2, that is, the via K simultaneously exposes the Part of at least two wires 2.

Correspondingly, in the above S300, the formed oxide semiconductor film 3 can directly contact the at least one wire 2 through the at least one via K. In the above S400, in the process of patterning the oxide semiconductor film 3, the static electricity generated in the oxide semiconductor film 3 can pass through the portion of the oxide semiconductor film 3 located in the at least one via hole K. Release to the at least one wire 2 and lead out through the at least one wire 2.

In addition, in the above S400, after the oxide semiconductor layer 3a is formed, the oxide semiconductor layer 3a may expose the at least one via K, and further expose a part of the at least one wire 2. In other words, after the oxide semiconductor film 3 is patterned, the orthographic projection of the formed oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one via K on the substrate 1 can be disjoint. Stack, completely remove the oxide semiconductor material in the at least one via hole K.

In an embodiment of the present disclosure, as shown in FIG. 5c, along the line direction perpendicular to the at least one wire 2, a part of the boundary of the orthographic projection of the at least one wire 2 on the substrate 1 is different from the at least one wire 2 above. A portion of the boundary of the orthographic projection of the via K on the substrate 1 overlaps, that is, along the routing direction perpendicular to the at least one wire 2, the at least one via K completely exposes the at least one wire 2, so that the At least one wire 2 can have a larger contact area with the oxide semiconductor film 3, and the diffusion efficiency of the electrostatic charge in the oxide semiconductor film 3 can be improved.

In some embodiments, the method for preparing the above-mentioned array substrate may further include preparing the source electrode 53 and the drain electrode 54 of the oxide thin film transistor 5. For example, the preparation method of the array substrate may further include: S500.

S500, as shown in FIGS. 4f and 5k, a source-drain conductive layer SD is formed on the side of the oxide semiconductor layer 3a away from the substrate 1. Wherein, the source-drain conductive layer SD may include a plurality of sources 52 and a plurality of drains 53, which are electrically connected to the plurality of active layers 51 in a one-to-one correspondence, and the plurality of drains 53 are connected to a plurality of The source layers 51 are electrically connected in a one-to-one correspondence.

It can be understood that an oxide thin film transistor 5 may include an active layer 51, a source 52 and a drain 53.

Optionally, as shown in FIGS. 4f and 5k, the source-drain conductive layer SD may further include auxiliary leads 6, and the auxiliary leads 6 are electrically connected to the at least one wire 2 described above. For example, the auxiliary lead 6 and the above-mentioned at least one wire 2 can be directly contacted in a one-to-one correspondence to form an electrical connection.

By electrically connecting the auxiliary lead 6 and the aforementioned at least one wire 2, the auxiliary lead 6 can be used to reduce the resistance of the wire 2 electrically connected to the auxiliary lead 6 and improve the stability of the electrical signal transmitted in the wire 2. Not only that, because the auxiliary lead 6 can reduce the resistance of the wire 2 electrically connected to it, so that the line width of the wire 2 (that is, the size of the wire 2 in the direction perpendicular to its routing) can be reduced, thereby reducing The space ratio of the wire 2 in the array substrate is reduced.

In an embodiment of the present disclosure, the source-drain conductive layer SD may be formed by the following method.

Exemplarily, as shown in FIG. 5j, a source-drain conductive material film SD' may be formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' covers the at least one conductive wire 2 described above. At least one exposed portion of the via hole K, a portion of the gate insulating layer GI not covered by the active layer 51, and the active layer 51.

Optionally, the material of the source-drain conductive material film SD' can be titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), Tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta) or an alloy thereof or a combination of at least two of the foregoing materials. The source-drain conductive material film SD' can be a single-layer structure formed by a layer of conductive material, or a multilayer structure formed by multiple layers of conductive materials stacked in sequence.

Optionally, a sputtering process can be used to form the source-drain conductive material film SD'.

Exemplarily, as shown in FIG. 5k, the source-drain conductive material film SD' may be patterned to form the source-drain conductive layer SD including the auxiliary lead 6, the source 53 and the drain 54.

Optionally, the source-drain conductive material film SD' can be patterned through a photolithography process.

Optionally, the source-drain conductive layer SD may also include source-drain layer leads, such as voltage leads and data lines.

Optionally, the orthographic projections on the substrate 1 of the auxiliary lead 6 and the wire 2 electrically connected to the auxiliary lead 6 may be overlapped with each other or may be partially overlapped.

In some embodiments, as shown in FIG. 4g and FIG. 51, the formed array substrate 100 may have a display area A and a frame area B located beside the display area A. Correspondingly, the substrate 1 also has a frame area B and a display area A. Wherein, the orthographic projection of the frame area B of the array substrate 100 on the substrate 1 coincides with the frame area B of the substrate 1, and the orthographic projection of the display area A of the array substrate 100 on the substrate 1 is the same as the display area A of the substrate 1. coincide.

Exemplarily, the side refers to one side, two sides, three layers, or peripheral side of the display area A (as shown in FIG. 4g). This means that the frame area B can be located on one side, two sides, or three sides of the display area A, or the frame area B can surround the display area A.

In some examples, as shown in FIG. 4g and FIG. 51, at least one wire 2 directly in contact with the oxide semiconductor thin film 3 may be formed in the frame area B of the array substrate 100. At this time, the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be an electrostatic protection line used to protect the array substrate 100 from static electricity.

The above-mentioned at least one wire 2 may have a larger size in the direction perpendicular to its routing direction, so as to ensure that it has a smaller impedance, thereby ensuring the stability of the electrical signal transmitted by it. By electrically connecting the at least one wire 2 with the auxiliary lead 6, the resistance of the at least one wire 2 can be reduced, and the line width of the at least one wire 2 can be reduced, which is beneficial to reduce the size of the frame area B, so that The array substrate 100 can realize a narrow frame design.

In other examples, at least one wire 2 directly in contact with the oxide semiconductor film 3 may be formed in the display area A of the array substrate 100. At this time, the at least one wire 2 may be a second common electrode line that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate.

In some embodiments, as shown in FIG. 51, the manufacturing method of the array substrate of the present disclosure may further include: forming a passivation layer (PVX) 7 on the side of the oxide thin film transistor 5 away from the substrate 1. As shown in FIGS. 4g and 51, a plurality of pixel electrodes 8 are formed on the side of the passivation layer 7 away from the substrate 1, and the plurality of pixel electrodes 8 are connected to the source 53 or drain of the plurality of oxide thin film transistors 5, respectively. The poles 54 are electrically connected in a one-to-one correspondence.

Furthermore, as shown in FIG. 51, the method for preparing the array substrate of the present disclosure may further include: before forming the pixel electrode 8, forming a planarization layer covering the passivation layer 7 so as to provide a flat surface for the pixel electrode 8. Here, the pixel electrode 8 may be formed on the side surface of the planarization layer away from the substrate 1.

Based on this, the prepared array substrate 100 can be applied to LCD (Liquid Crystal Display, liquid crystal display device). At this time, the manufacturing method of the array substrate 100 may further include: forming a common electrode on the side of the pixel electrode 8 away from the substrate 1.

In an embodiment of the present disclosure, the manufacturing method of the array substrate of the present disclosure may further include: sequentially forming a light-emitting layer and a cathode layer on the side of the pixel electrode 8 away from the substrate 1, and the at least one wire 2 is the first In the case of a common electrode line or a second common electrode line, the cathode layer may be electrically connected to the above-mentioned at least one wire 2, or to the auxiliary lead 6, or to the at least one wire 2 and the auxiliary lead 6 at the same time.

Based on this, the prepared array substrate can be applied to an OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display device.

Hereinafter, an implementation manner of the preparation method of the array substrate of the present disclosure is exemplarily introduced, so as to further explain and illustrate the principle and effect of the preparation method of the array substrate of the present disclosure. The preparation method of this exemplary array substrate is as follows.

Exemplarily, a substrate 1 is provided. The substrate 1 is a glass substrate. Wherein, the substrate 1 has a display area A and a frame area B surrounding the display area A.

A gate conductive material film is formed on one side of the substrate 1, and the gate conductive material film covers the display area A and the frame area B of the substrate 1. The above-mentioned gate conductive material film can be formed by a deposition method, for example, the gate conductive material film can be formed by a magnetron sputtering deposition method.

Exemplarily, as shown in FIGS. 4a and 5a, the gate conductive material film is patterned to form a gate conductive layer Gate located in the display area A and a plurality of wires 2 located in the frame area B. Wherein, the gate conductive layer Gate includes a plurality of gate lines and a plurality of gates 52 for forming an oxide thin film transistor 5; the plurality of wires 2 includes at least one common electrode line for providing a common voltage signal for the display area and/ Or an electrostatic protection wire used for electrostatic protection of the array substrate 100.

Exemplarily, as shown in FIGS. 4b and 5b, a gate insulating film GI' covering the gate conductive layer Gate and the plurality of conductive lines 2 is formed on the side of the gate conductive layer Gate and the plurality of conductive lines 2 away from the substrate 1. The gate insulating film GI' can be formed by a deposition method, for example, the gate insulating film GI' can be formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD) method.

Exemplarily, as shown in FIGS. 4c and 5c, the gate insulating film GI' is patterned with the help of a mask to form a gate insulating layer GI having at least one via K. The at least one via K exposes a part of the at least one wire 2. Optionally, along the routing direction perpendicular to the at least one wire 2, a part of the boundary of the orthographic projection of the at least one wire 2 on the substrate 1 and the boundary of the orthographic projection of the at least one via K on the substrate 1 Part of coincidence. It can be understood that the mask may have a pattern for forming at least one via K in the frame area B.

Exemplarily, as shown in FIGS. 4d and 5d, an oxide semiconductor film 3 is formed on the side of the gate insulating layer GI away from the substrate 1. The oxide semiconductor film 3 is located in the display area A and the frame area B at the same time. Wherein, the oxide semiconductor film 3 is in direct contact with the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI. Here, the oxide semiconductor thin film 3 may be formed by a deposition method, for example, the oxide semiconductor thin film 3 may be formed by a magnetron sputtering method.

Illustratively, as shown in FIGS. 4e and 5e to 5i, the oxide semiconductor thin film 3 is patterned to form an oxide semiconductor layer 3a. Wherein, the oxide semiconductor layer 3a includes a plurality of active layers 51 for forming an oxide thin film transistor 5, and the oxide semiconductor layer 3a does not cover the at least one wire 2 described above. In other words, the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 do not overlap at all.

Here, in the process of patterning the oxide semiconductor thin film 3, the substrate containing the oxide semiconductor thin film 3 may be transported into an exposure machine for exposure. Since oxide semiconductor materials are usually amorphous materials, they have poor electrical conductivity and are prone to static electricity in the exposure machine. Since the oxide semiconductor film 3 is in direct contact with the at least one wire 2, the static electricity generated in the oxide semiconductor film 3 can be discharged to the at least one wire 2, and the at least one wire 2 is led out, reducing or even avoiding the accumulation of static electricity. , Effectively avoid the occurrence of electrostatic breakdown (ESD) phenomenon.

After the oxide semiconductor film 3 is patterned, the portion of the oxide semiconductor film 3 above and inside the at least one via K will be removed, exposing part of the surface of the at least one wire 2.

Exemplarily, as shown in FIG. 5j, a source-drain conductive film material SD' is formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' is located in the display area A and the frame area B at the same time. That is, the source-drain conductive material film SD' covers the exposed at least one wire 2, the portion of the gate insulating layer GI that is not covered by the active layer 51, and the active layer 51. The source and drain conductive material film SD' can be formed by a deposition method, for example, the source and drain conductive material film SD' can be formed by a magnetron sputtering method.

Exemplarily, as shown in FIG. 4f and FIG. 5k, the source-drain conductive material film SD' is patterned to form a source-drain conductive layer SD. Wherein, the source-drain conductive layer SD includes auxiliary leads 6 located in the frame area B and directly contacting the at least one wire 2 through the via K, and multiple data lines and the source of each oxide thin film transistor 5 located in the display area A. Pole 53 and drain 54 and so on.

The auxiliary lead 6 can be connected in parallel with the at least one wire 2 to reduce the resistance of the at least one wire 2, which not only improves the stability of the electrical signal transmitted in the at least one wire 2, but also reduces the at least one wire 2. The size in the direction perpendicular to the routing direction is beneficial to reduce the size of the frame area B, and is beneficial to realize the narrow frame design of the array substrate 100.

Exemplarily, as shown in FIG. 51, on the side of the source and drain conductive layer SD away from the substrate 1, a passivation layer 7 (PVX) and a planarization layer are sequentially formed.

Exemplarily, as shown in FIGS. 4g and 51, a plurality of pixel electrodes 8 are formed on the side of the planarization layer away from the substrate 1, wherein the plurality of pixel electrodes 8 are connected to the drains of the plurality of oxide thin film transistors 5, respectively. Pole 54 is electrically connected. The material of the pixel electrode 8 may be ITO, for example.

Furthermore, the preparation method of the exemplary array substrate may further include: forming a light-emitting layer and a cathode layer in sequence on the side of the pixel electrode 8 away from the substrate 1, wherein the cathode layer extends to the frame area B and is directly connected to the auxiliary lead 6 The contact forms an electrical connection. Here, the wire 2 electrically connected to the auxiliary lead may be a common electrode wire. On the side of the cathode layer away from the substrate 1, a protective layer is formed.

It should be noted that although the various steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be performed in the specific order, or that all the steps shown must be performed. Achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step to be executed, and/or one step may be decomposed into multiple steps to be executed, etc., all should be regarded as a part of the present disclosure.

Some embodiments of the present disclosure also provide an array substrate 100. As shown in FIG. 6, the array substrate 100 may include a substrate 1, a plurality of wires 2 and a plurality of oxide thin film transistors 5.

In some examples, the material of the substrate 1 can refer to the schematic descriptions in some of the above-mentioned embodiments, which will not be repeated here.

In some examples, as shown in FIG. 6, the plurality of oxide thin film transistors 5 and the plurality of wires 2 are arranged on the same side of the substrate 1.

Exemplarily, each oxide thin film transistor 5 includes an active layer 51, a gate 52, a source 53 and a drain 54. The active layer 51 of any oxide thin film transistor 5 is obtained by patterning the oxide semiconductor thin film 3 directly in contact with at least one wire 2 (for example, refer to the preparation of the array substrate provided in some of the above embodiments). Method), and the active layer 51 of any oxide thin film transistor 5 and the at least one wire 2 are insulated from each other.

The material of the above-mentioned active layer 51 includes multiple types. Exemplarily, the material of the active layer 51 may be an oxide semiconductor material. Optionally, the oxide semiconductor material may be an amorphous oxide semiconductor material. For example, the amorphous oxide semiconductor material may be zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium. A kind of aluminum zinc oxide.

The array substrate 100 provided by some embodiments of the present disclosure can be prepared and formed by the preparation method of the array substrate provided in some of the above embodiments, because the active layer 51 of the plurality of oxide thin film transistors 5 is combined with the above at least one The oxide semiconductor film 3 directly in contact with the wire 2 is obtained by patterning, and the at least one wire 2 has good conductivity. Therefore, the static electricity generated in the oxide semiconductor film 3 can be released into the at least one wire 2 through the At least one wire 2 is led out to avoid the accumulation of static electricity in the oxide semiconductor layer 3a including multiple active layers 51, thereby avoiding electrostatic breakdown, and effectively improving the yield of the array substrate 100.

The structure of the array substrate 100 provided in some embodiments of the present disclosure will be schematically described below with reference to the accompanying drawings.

Here, as shown in FIG. 6, the oxide thin film transistor 5 is taken as an example of a bottom-gate oxide thin film transistor.

Based on this, the multiple wires 2 and the gate 52 in each oxide thin film transistor 5 are located on the side of the active layer 51 close to the substrate 1.

In some examples, the plurality of wires 2 and each gate 52 are made of the same material and arranged in the same layer.

It should be noted that the “same layer” mentioned in this article refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form a patterning process. Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses. In this way, the above-mentioned multiple conductive lines 2 and each gate 52 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the manufacturing process of the array substrate 100.

In some embodiments, the array substrate 100 further includes: a gate insulating layer GI disposed between the gate 52 and the active layer 51. Here, the gate 52 belongs to the gate conductive layer Gate, and the active layer 51 belongs to the oxide semiconductor layer 3a, that is, the gate insulating layer GI is located between the gate conductive layer Gate and the oxide semiconductor layer 3a. Exemplarily, the gate conductive layer Gate may further include gate lines.

In some examples, as shown in FIG. 6, the gate insulating layer GI has at least one via K exposing a portion of the at least one wire 2, that is, the orthographic projection of the at least one via K on the substrate 1 and the at least one via K The orthographic projection of a wire 2 on the substrate 1 at least partially overlaps.

Exemplarily, along the routing direction of the at least one wire 2 described above, a part of the boundary of the orthographic projection of the at least one signal line 2 on the substrate 1 is different from the boundary of the orthographic projection of the at least one via K on the substrate 1 One part coincides.

Wherein, the above-mentioned oxide semiconductor film 3 may be electrically connected to the above-mentioned at least one wire 2 through the at least one via K. In this way, when static electricity is generated in the oxide semiconductor film 3, the static electricity can be discharged to the at least one wire 2 through the portion of the oxide semiconductor film 3 located in the at least one via K, and then the at least one wire 2 can pass through the at least one wire 2. Export static electricity.

In some examples, as shown in FIG. 6, the array substrate further includes an auxiliary lead 6 directly in contact with the above-mentioned at least one wire 2.

The above-mentioned auxiliary lead 6 can be set in multiple ways, which can be selected and set according to actual needs.

Exemplarily, as shown in FIG. 6, the auxiliary lead 6 may be arranged on the side of the gate insulating layer GI away from the substrate 1, and the auxiliary lead 6 directly contacts the at least one wire 2 through the at least one via K. In this way, the auxiliary lead 6 can be used to reduce the resistance of the at least one wire 2, thereby reducing the size of the at least one wire 2 perpendicular to its routing direction, and reducing the space ratio of the at least one wire 2 in the array substrate 100 .

Exemplarily, as shown in FIG. 6, the auxiliary lead 6 may have the same material as the source 53 and the drain 54 of the oxide thin film transistor 5 and be arranged in the same layer. In this way, the auxiliary lead 6, the source electrode 53 and the drain electrode 54 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the array substrate 100.

Here, for example, the film including the auxiliary lead 6, the source electrode 53 and the drain electrode 54 may be referred to as a source-drain conductive layer SD. Optionally, the source-drain conductive layer SD may also include data lines, power lines, and the like.

In some examples, as shown in FIG. 6, the orthographic projection of the auxiliary lead 6 on the substrate 1 and the orthographic projection of the aforementioned at least one wire 2 on the substrate 1 at least partially overlap.

Exemplarily, the auxiliary lead 6 corresponds to the above-mentioned at least one wire 2 in a one-to-one correspondence. The orthographic projection of the auxiliary lead 6 on the substrate 1 and the corresponding orthographic projection of the wire 2 on the substrate 1 at least partially overlap, which may include: a partial misalignment between the auxiliary lead 6 and the wire 2 so that the auxiliary lead 6 is on the substrate 1 A part of the orthographic projection of the corresponding wire 2 overlaps with a part of the orthographic projection of the corresponding wire 2 on the substrate 1; or, the orthographic projection of the auxiliary lead 6 on the substrate 1 is located on the orthographic projection of the corresponding wire 2 on the substrate 1. Within the projection range.

In some examples, as shown in FIG. 4g, the routing direction of the auxiliary lead 6 is the same or substantially the same as the routing direction of the at least one wire 2 described above. That is, the angle between the routing direction of the auxiliary lead 6 and the routing direction of the at least one wire 2 is 0° or close to 0°. This is beneficial to ensure the effect of reducing the resistance of the at least one wire 2.

In some embodiments, as shown in FIG. 6, the array substrate 100 may further include: a passivation layer 7 disposed on the side of the source electrode 53 and the drain electrode 54 away from the substrate 1 (that is, covering each oxide thin film transistor 5) .

In some examples, as shown in FIG. 7, when the array substrate 100 does not include the auxiliary lead 6, a part of the passivation layer 7 may be located in at least one via K of the gate insulating layer GI. In this way, it is possible to prevent the subsequently formed conductive layer (for example, the pixel electrode 8) from forming an electrical connection with the above-mentioned at least one wire 2 and avoid signal crosstalk.

In some embodiments, as shown in FIG. 6, the array substrate 100 may further include: a pixel electrode 8 disposed on the side of the passivation layer 7 away from the substrate 1. The pixel electrode 8 may be electrically connected to the drain 54 of the oxide thin film transistor 5, for example.

Optionally, the array substrate 100 may further include a planarization layer provided between the passivation layer 7 and the pixel electrode 8.

In some embodiments, as shown in FIG. 6, the array substrate 100 has a display area A and a frame area B located beside the display area A. For the "side", reference may be made to the schematic description in some of the foregoing examples.

In some examples, the oxide thin film transistor 5 in the array substrate 100 may be located in the display area A. Among the multiple signal lines 2 described above, at least one wire 2 electrically connected to the oxide semiconductor thin film 3 may be located in the display area A, or may be located in the frame area B.

Here, in the case where the above-mentioned at least one signal line 2 is located in the display area A, the at least one wire 2 may be a second common signal that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate. Electrode wire. In the case where the above-mentioned at least one wire 2 is located in the frame area B, the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be used to perform processing on the array substrate 100. Electrostatic protection wire for electrostatic protection.

Hereinafter, an implementation manner of the array substrate of the present disclosure is exemplarily introduced to further explain and illustrate the structure and principle of the array substrate of the present disclosure.

In the exemplary array substrate 100, as shown in FIG. 6, the array substrate 100 may include a substrate 1, a plurality of wires 2, a gate conductive layer Gate, a gate insulating layer GI, an oxide semiconductor layer 3a, source and drain conductive layers. Layer SD, passivation layer 7 and a plurality of pixel electrodes 8.

Exemplarily, the substrate 1 may be a glass substrate. The substrate 1 may have a display area A and a frame area B surrounding the display area A.

Exemplarily, the above-mentioned multiple wires 2 may be located in the frame area B of the substrate 1. The aforementioned gate conductive layer Gate may be located in the display area A of the substrate 1. The gate conductive layer Gate and the plurality of wires 2 may be arranged on the same side of the substrate 1 and on the same surface, for example, the two materials are the same and arranged in the same layer. Wherein, the gate conductive layer Gate may include a plurality of gate lines and a plurality of gates 52 for forming the oxide thin film transistor 5.

Exemplarily, the gate insulating layer GI may be disposed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1. The gate insulating layer GI has at least one via K, and the at least one via K exposes at least one wire 2 of the plurality of wires 2, that is, the orthographic projection of the gate insulating layer GI on the substrate 1 and the at least one wire 2 The orthographic projections of the wires 2 on the substrate 1 partially overlap.

Exemplarily, the oxide semiconductor layer 3a may be provided on the side of the gate conductive layer Gate away from the substrate 1. The oxide semiconductor layer 3a includes a plurality of active layers 51 for forming oxide thin film transistors 5, and the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 is the same as the orthographic projection of the at least one wire 2 on the substrate 1. The projections do not overlap at all. Among them, the oxide semiconductor layer 3 a is obtained by patterning the oxide semiconductor thin film 3 a directly in contact with the at least one wire 2.

Exemplarily, the source-drain conductive layer SD may be provided on the side of the oxide semiconductor layer 3a away from the substrate 1. The source-drain conductive layer SD may include an auxiliary lead 6 electrically connected to the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI, a plurality of source and drain layer leads (such as data lines), and each oxide thin film transistor 5 The source 53 and drain 54 and so on. Wherein, the auxiliary lead 6 can be arranged in the frame area B, and the source and drain layer leads, the source electrode 53 and the drain electrode 54 are arranged in the display area A.

Exemplarily, the passivation layer 7 may be formed on the side of the source and drain conductive layer SD away from the substrate 1. The passivation layer 7 may, for example, cover the source-drain conductive layer SD and retain a part of the drain 54 in the source-drain conductive layer SD.

Exemplarily, a plurality of pixel electrodes 8 may be arranged on the side of the passivation layer 7 away from the substrate 1. The plurality of pixel electrodes 8 may be electrically connected to the plurality of drain electrodes 54 in a one-to-one correspondence.

Since the array substrate 100 of the present disclosure can be prepared by the preparation method of the array substrate provided in some of the above-mentioned embodiments, and the structure, principle and effect of the array substrate 100 have been compared with the preparation method of the array substrate provided in some of the above-mentioned embodiments It is described in detail in, so I won’t repeat it here.

Some embodiments of the present disclosure also provide a display device 1000. As shown in FIGS. 8 and 9, the display device 1000 further includes the array substrate 100 as described in some of the above embodiments.

The beneficial effects that can be achieved by the display device 1000 provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 100 provided in some of the foregoing embodiments, and will not be repeated here.

There are many types of the above-mentioned display device 1000, which can be selected and set according to actual needs.

In some examples, as shown in FIG. 8, the display device 1000 may be an LCD. At this time, the display device 1000 may further include a counter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.

Exemplarily, the above-mentioned counter substrate 200 may be a transparent substrate, or may also be a color filter substrate (as shown in FIG. 8). In the case where the counter substrate 200 is a transparent substrate, the array substrate 100 may further include a color filter layer and/or a black matrix disposed on the side of the pixel electrode 8 close to the counter substrate 200.

In other examples, as shown in FIG. 9, the display device 1000 may be an OLED display device. At this time, the display device 1000 may further include: a plurality of light-emitting devices 400 arranged on a side of the array substrate 100 away from the substrate 1 with a plurality of oxide thin film transistors 5.

Exemplarily, the pixel electrode 8 in the array substrate 100 may be referred to as the anode layer of the light emitting device 400. On this basis, the light-emitting device 400 may further include a light-emitting layer and a cathode layer that are sequentially stacked on the side of the anode layer away from the substrate 1.

In some embodiments, the above-mentioned display device 1000 may be any device that displays whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (Personal Digital Assistants). Assistant, PDA for short), handheld or portable computer, Global Positioning System (GPS) receiver/navigator, camera, Moving Picture Experts Group 4 (MP4 for short) video player, camera , Game consoles, watches, clocks, calculators, television monitors, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, camera view displays (e.g., vehicle Rear view camera displays), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (for example, a display of an image of a piece of jewelry), etc.

It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments, and can be implemented and executed in various ways. The aforementioned deformations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or obvious in the text and/or drawings. All these different combinations constitute multiple alternative aspects of the present disclosure.

The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art who thinks of changes or substitutions within the technical scope disclosed in the present disclosure shall cover Within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

A method for preparing an array substrate includes:

Provide substrate;

Forming a plurality of wires on the substrate;

An oxide semiconductor film is formed on the side of the plurality of wires away from the substrate; the oxide semiconductor film covers the plurality of wires and is in direct contact with at least one wire; the at least one wire is configured to lead out Static electricity generated in the oxide semiconductor film;

Using a photolithography process, the oxide semiconductor thin film is patterned, and the portion directly in contact with the at least one wire is removed to form an oxide semiconductor layer including an active layer of a plurality of oxide thin film transistors.
The manufacturing method of the array substrate according to claim 1, further comprising:

Before forming the oxide semiconductor thin film, forming a gate conductive layer including the gates of a plurality of oxide thin film transistors; the gate conductive layer and the plurality of wires are located on the same side of the substrate;

Forming a gate insulating film on the side of the plurality of wires and the gate conductive layer away from the substrate; the gate insulating film covers the plurality of wires and the gate conductive layer;

The gate insulating film is patterned to form a gate insulating layer with at least one via; the at least one via exposes at least a part of the surface of the at least one wire, and the at least one via is in the substrate The orthographic projection on the substrate at least partially overlaps the orthographic projection of the at least one wire on the substrate;

Wherein, the oxide semiconductor film is in direct contact with the at least one wire through the at least one via hole.
The method for manufacturing an array substrate according to claim 2, wherein, along the line direction perpendicular to the at least one wire, a part of the boundary of the orthographic projection of the at least one wire on the substrate is connected to the at least one wire. A part of the boundary of the orthographic projection of a via on the substrate coincides.
The manufacturing method of the array substrate according to claim 2 or 3, wherein the material of the plurality of wires includes a metal material;

The plurality of conductive lines and the gate conductive layer are formed in the same patterning process.
4. The method for manufacturing an array substrate according to any one of claims 1 to 4, further comprising:

A source-drain conductive layer is formed on the side of the oxide semiconductor layer away from the substrate. The source-drain conductive layer includes a source electrode and a drain electrode directly in contact with each active layer, and is connected to the at least one wire Direct contact auxiliary lead.
5. The method for manufacturing an array substrate according to claim 5, wherein the array substrate has a display area and a frame area located beside the display area;

The at least one wire and the auxiliary lead are located in the frame area;

The at least one wire is configured to transmit a common voltage signal to the display area, or to protect the array substrate from static electricity;

The auxiliary lead is configured to be connected in parallel with the at least one wire to reduce the resistance of the at least one wire.
The method for preparing an array substrate according to any one of claims 1 to 6, wherein the material of the oxide semiconductor film includes zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum oxide One of zinc, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide.
The method for manufacturing an array substrate according to any one of claims 1 to 7, wherein the orthographic projection of the oxide semiconductor layer on the substrate is opposite to the orthographic projection of the at least one wire on the substrate. The projections overlap at most.
An array substrate, including:

Substrate

A plurality of wires arranged on one side of the substrate; and,

A plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of wires are arranged on the same side of the substrate;

Wherein, each oxide thin film transistor includes a gate, an active layer, a source and a drain; the active layers of the plurality of oxide thin film transistors are formed by patterning an oxide semiconductor thin film directly in contact with at least one wire. And the active layer and the at least one wire are insulated from each other.
9. The array substrate according to claim 9, further comprising: a gate insulating layer provided between the gate and the active layer;

The gate insulating layer has at least one via, the at least one via exposes at least a part of the surface of the at least one wire, and the orthographic projection of the at least one via on the substrate is in line with the at least one wire. The orthographic projections on the substrate at least partially overlap;

The oxide semiconductor film directly contacts the at least one wire through the at least one via hole.
9. The array substrate according to claim 10, further comprising: auxiliary leads arranged on a side of the gate insulating layer away from the substrate;

The auxiliary lead directly contacts the at least one wire through the at least one via hole.
9. The array substrate according to claim 9, further comprising: auxiliary leads which are made of the same material as the source electrode and the drain electrode and arranged in the same layer;

The auxiliary lead is in direct contact with the at least one wire.
The array substrate according to claim 11 or 12, wherein the orthographic projection of the auxiliary lead on the substrate and the orthographic projection of the at least one wire on the substrate at least partially overlap.
The array substrate according to any one of claims 11 to 13, wherein the routing direction of the auxiliary lead is the same or substantially the same as the routing direction of the at least one wire.
9. The array substrate according to claim 10, further comprising: a passivation layer disposed on a side of the source electrode and the drain electrode away from the substrate;

A part of the passivation layer is located in the at least one via hole and directly contacts the at least one wire.
15. The array substrate according to any one of claims 9-15, wherein the array substrate has a display area and a frame area located beside the display area;

The at least one wire is located in the frame area;

The at least one wire includes a common electrode wire or an electrostatic protection wire;

The common electrode line is configured to transmit a common voltage signal to the display area;

The electrostatic protection wire is configured to perform electrostatic protection on the array substrate.
The array substrate according to any one of claims 9 to 16, wherein the gate electrode and the plurality of conductive lines have the same material and are arranged in the same layer.
A display device, comprising: the array substrate according to any one of claims 9-17.
The display device according to claim 18, further comprising:

A counter substrate disposed opposite to the array substrate; and,

A liquid crystal layer provided between the array substrate and the counter substrate.
The display device according to claim 19, further comprising:

A plurality of oxide thin film transistors arranged on the array substrate are arranged on a plurality of light-emitting devices on the side of the substrate away from the array substrate.