WO2021057883A1 - Array substrate and preparation method therefor, and display apparatus - Google Patents
Array substrate and preparation method therefor, and display apparatus Download PDFInfo
- Publication number
- WO2021057883A1 WO2021057883A1 PCT/CN2020/117632 CN2020117632W WO2021057883A1 WO 2021057883 A1 WO2021057883 A1 WO 2021057883A1 CN 2020117632 W CN2020117632 W CN 2020117632W WO 2021057883 A1 WO2021057883 A1 WO 2021057883A1
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- wire
- substrate
- array substrate
- layer
- oxide semiconductor
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
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- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Definitions
- the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
- the oxide thin film transistor uses an oxide semiconductor material as an active layer, which has good uniformity, and is especially suitable for large-area display requirements.
- a method for manufacturing an array substrate includes: providing a substrate; forming a plurality of wires on one side of the substrate; forming an oxide semiconductor film on the side of the plurality of wires away from the substrate, and the oxide
- the semiconductor thin film covers the plurality of wires and directly contacts with at least one wire; the at least one wire is configured to extract static electricity generated in the oxide semiconductor thin film; and the oxide semiconductor thin film is processed by a photolithography process.
- the patterning process removes the part directly in contact with the at least one wire to form an oxide semiconductor layer including an active layer of a plurality of oxide thin film transistors.
- the manufacturing method of the array substrate further includes: before forming the oxide semiconductor film, forming a gate conductive layer including the gates of a plurality of oxide thin film transistors; The multiple wires are located on the same side of the substrate.
- a gate insulating film is formed on the side of the plurality of wires and the gate conductive layer away from the substrate; the gate insulating film covers the plurality of wires and the gate conductive layer.
- the gate insulating film is patterned to form a gate insulating layer with at least one via; the at least one via exposes at least a part of the surface of the at least one wire, and the at least one via is in the substrate
- the orthographic projection on the substrate at least partially overlaps the orthographic projection of the at least one wire on the substrate.
- the oxide semiconductor film is in direct contact with the at least one wire through the at least one via hole.
- a part of the boundary of the orthographic projection of the at least one wire on the substrate is connected to the at least one via on the substrate. Part of the boundary of the orthographic projection coincides.
- the material of the plurality of wires includes a metal material; the plurality of wires and the gate conductive layer are formed in the same patterning process.
- the method for preparing the array substrate further includes: forming a source-drain conductive layer on a side of the oxide semiconductor layer away from the substrate, and the source-drain conductive layer includes a conductive layer connected to each active layer.
- the source electrode and the drain electrode in direct contact with the layer, and an auxiliary lead directly in contact with the at least one wire.
- the array substrate has a display area and a frame area located beside the display area.
- the auxiliary lead is located in the frame area.
- the at least one wire is configured to transmit a common voltage signal to the display area or to protect the array substrate from static electricity.
- the auxiliary lead is configured to be connected in parallel with the at least one wire to reduce the resistance of the at least one wire.
- the material of the oxide semiconductor film includes zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide It is one of indium aluminum zinc oxide and indium aluminum zinc oxide.
- the orthographic projection of the oxide semiconductor layer on the substrate and the orthographic projection of the at least one wire on the substrate overlap at most.
- an array substrate in another aspect, includes: a substrate; a plurality of wires arranged on one side of the substrate; and a plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of wires are arranged on the substrate The same side of the bottom.
- each oxide thin film transistor includes a gate, an active layer, a source and a drain; the active layers of the plurality of oxide thin film transistors are formed by patterning an oxide semiconductor thin film directly in contact with at least one wire. And the active layer and the at least one wire are insulated from each other.
- the array substrate further includes a gate insulating layer disposed between the gate and the active layer.
- the gate insulating layer has at least one via, the at least one via exposes at least a part of the surface of the at least one wire, and the orthographic projection of the at least one via on the substrate is in line with the at least one wire.
- the orthographic projections on the substrate at least partially overlap.
- the oxide semiconductor film directly contacts the at least one wire through the at least one via hole.
- the array substrate further includes: auxiliary leads arranged on a side of the gate insulating layer away from the substrate.
- the auxiliary lead directly contacts the at least one wire through the at least one via hole.
- the array substrate further includes: auxiliary leads with the same material as the source electrode and the drain electrode and arranged in the same layer.
- the auxiliary lead is in direct contact with the at least one wire.
- the orthographic projection of the auxiliary lead on the substrate and the orthographic projection of the at least one wire on the substrate at least partially overlap.
- the routing direction of the auxiliary lead is the same or substantially the same as the routing direction of the at least one wire.
- the array substrate further includes a passivation layer disposed on a side of the source electrode and the drain electrode away from the substrate. A part of the passivation layer is located in the at least one via and is in direct contact with the at least one wire.
- the array substrate has a display area and a frame area located beside the display area.
- the at least one wire is located in the frame area.
- the at least one wire includes a common electrode wire or an electrostatic protection wire.
- the common electrode line is configured to transmit a common voltage signal to the display area; the electrostatic protection line is configured to perform electrostatic protection on the array substrate.
- the gate electrode and the plurality of wires have the same material and are arranged in the same layer.
- a display device in another aspect, includes: the array substrate as described in any of the above embodiments.
- the display device further includes: a counter substrate disposed opposite to the array substrate; and a liquid crystal layer disposed between the array substrate and the counter substrate.
- the display device further includes: a plurality of light-emitting devices arranged on a side of the array substrate away from the substrate of the array substrate with a plurality of oxide thin film transistors.
- FIG. 1 is a structural diagram of static electricity accumulated in an oxide semiconductor film according to the related art
- FIG. 2 is a flowchart of a method for manufacturing an array substrate according to some embodiments of the present disclosure
- FIG. 3 is a flowchart of another method for manufacturing an array substrate according to some embodiments of the present disclosure.
- 4a to 4g are schematic diagrams of a manufacturing process of an array substrate according to some embodiments of the present disclosure.
- 5a to 5l are schematic diagrams of a preparation process along the O-O' direction in the preparation process shown in Figs. 4a to 4g;
- Fig. 6 is a structural diagram of an array substrate according to some embodiments of the present disclosure.
- FIG. 7 is a structural diagram of another array substrate according to some embodiments of the present disclosure.
- FIG. 8 is a structural diagram of a display device according to some embodiments of the present disclosure.
- FIG. 9 is a structural diagram of another display device according to some embodiments of the present disclosure.
- first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
- connection and its extensions may be used.
- connection may be used to indicate that two or more components are in direct physical or electrical contact with each other.
- the embodiments disclosed herein are not necessarily limited to the content of this document.
- a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
- the term “if” is optionally interpreted as meaning “when” or “when” or “in response to determination” or “in response to detection.”
- the phrase “if it is determined" or “if [the stated condition or event] is detected” is optionally interpreted to mean “when determining" or “in response to determining" Or “when [stated condition or event] is detected” or “in response to detecting [stated condition or event]”.
- exemplary embodiments are described herein with reference to cross-sectional views and/or plan views as idealized exemplary drawings.
- the thickness of layers and regions are exaggerated for clarity. Therefore, variations in the shape with respect to the drawings due to, for example, manufacturing technology and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the shape of the area shown herein, but include shape deviations due to, for example, manufacturing.
- an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the area of the device, and are not intended to limit the scope of the exemplary embodiments.
- a photolithography process can be used to prepare an active layer forming an oxide thin film transistor.
- a layer of oxide semiconductor material film may be deposited first, and then a photoresist layer may be formed on one side surface of the oxide semiconductor material film.
- the resist layer is exposed and developed to obtain a patterned photoresist layer, and the patterned photoresist layer can be used to pattern the oxide semiconductor material film to obtain an active layer.
- the oxide semiconductor material film is prone to generate and accumulate static electricity in the exposure machine, and then electrostatic breakdown (Electro-Static Discharge, ESD) phenomenon may occur, which reduces the yield of array substrates including oxide thin film transistors.
- ESD Electro-Static Discharge
- an oxide thin film transistor is taken as an example of a bottom-gate thin film transistor.
- a plurality of gates 1' may be formed first, and then On one side of the plurality of gates 1', a gate insulating layer 2'covering the plurality of gates 1'and an oxide semiconductor material film 3'covering the gate insulating layer 2'are sequentially formed, and then a photolithography process is used to The oxide semiconductor material film 3'is patterned.
- the oxide semiconductor material is usually a substance with an amorphous structure, its conductivity is poor.
- static electricity is easily generated in the oxide semiconductor material film 3'.
- the oxide semiconductor material film 3' can also form a parasitic capacitance structure with other conductive structures.
- the oxide semiconductor material film 3' can form a parasitic capacitance structure with the gate 1'and induce different gates.
- a parasitic capacitance structure is formed between 1'. In the case where a large amount of static electricity generated in the oxide semiconductor material film 3'accumulates, the phenomenon of electrostatic breakdown is prone to occur.
- some embodiments of the present disclosure provide a method for manufacturing an array substrate.
- the preparation method of the array substrate includes: S100-S400.
- a substrate 1 is provided.
- the above-mentioned substrate 1 includes multiple materials, which can be selected and set according to actual needs.
- the above-mentioned substrate 1 may be a substrate of inorganic material, or a substrate of organic material.
- the material of the substrate 1 may be soda-lime glass, quartz glass, sapphire glass, etc., or may be stainless steel, aluminum, nickel, or other materials.
- the material of the substrate 1 may be polymethyl methacrylate (PMMA for short), polyvinyl alcohol (PVA for short), or polyvinyl phenol (PMMA for short).
- PMMA polymethyl methacrylate
- PVA polyvinyl alcohol
- PMMA polyvinyl phenol
- PVP polyethersulfone
- PES Polyimide
- polyamide polyacetal
- PC Polycarbonate
- PC Polyterephthalic acid Polyethylene terephthalate
- PEN polyethylene naphthalate
- the substrate 1 when the substrate 1 uses an inorganic material, the substrate 1 may be a rigid substrate; when the substrate 1 uses an organic material, the substrate 1 may be a flexible substrate.
- a plurality of conductive lines 2 are formed on the substrate 1.
- the material of the aforementioned wire 2 may include one conductive material or a combination of multiple conductive materials.
- the material of the wire 2 may include a metal material, a conductive metal oxide material, a conductive metal nitride material, a conductive polymer material, a conductive composite material, or a combination of at least two of them.
- the foregoing metal material may be, for example, platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination of at least two of them.
- the aforementioned conductive metal oxide material may be, for example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO) metal oxide, or doped metal oxide.
- ITO indium tin oxide
- FTO fluorine-doped tin oxide
- doped metal oxide doped metal oxide.
- the aforementioned conductive metal nitride material may be titanium nitride or the like, for example.
- the above-mentioned conductive polymer material can be, for example, polyaniline, polypyrrole, polythiophene, polyacetylene, poly(3,4-ethylenedioxythiophene)/polystyrene sulfonic acid (PEDOT/PSS) or among them At least a combination of the two, or the above-mentioned materials doped with dopants; among them, the dopant can be, for example, acids such as hydrochloric acid, sulfuric acid, and sulfonic acid, or Lewis acids such as PF6, AsF5, and FeCl3, or halogens such as iodide ion. Ion, or metal ions such as sodium ion and potassium ion.
- the dopant can be, for example, acids such as hydrochloric acid, sulfuric acid, and sulfonic acid, or Lewis acids such as PF6, AsF5, and FeCl3, or halogens such as iodide ion. Ion
- the aforementioned conductive composite material may be, for example, a conductive composite material dispersed with carbon black, graphite powder, metal particles, or the like.
- the above-mentioned wire 2 may be a single-layer structure composed of a layer of conductive material, or may be a multi-layer structure formed by sequentially stacking multiple layers of conductive materials.
- the wire 2 in the present disclosure may be a single-layer structure formed by a layer of metal material.
- the wire 2 in the present disclosure may have a three-layer structure formed by a first metal layer, a second metal layer, and a first metal layer that are sequentially stacked.
- the first metal layer may be a single-layer structure formed of at least one metal material
- the second metal layer may be a single-layer structure formed of at least one metal material
- the metal material included in the first metal layer and the second metal layer is different.
- an oxide semiconductor film 3 is formed on the side of the plurality of wires 2 away from the substrate 1.
- the oxide semiconductor film 3 covers the plurality of wires 2 and directly contacts with at least one wire 2. That is, the oxide semiconductor thin film 3 may be in direct contact with one wire 2 or may be in direct contact with a plurality of wires 2.
- the at least one wire 2 is configured to discharge static electricity generated in the oxide semiconductor thin film 3.
- a process such as magnetron sputtering may be used to prepare and form the above-mentioned oxide semiconductor film 3.
- the material of the above-mentioned oxide semiconductor thin film 3 may be an amorphous oxide semiconductor material.
- the oxide semiconductor material may be zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), indium zinc oxide (IZO), zinc tin oxide (ZTO), Aluminum zinc oxide (AZO), yttrium zinc oxide (YZO), indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (Indium aluminum zinc oxide)
- ZnO zinc oxide
- IAZO indium gallium zinc oxide
- IAZO indium aluminum zinc oxide
- the above-mentioned oxide semiconductor material may be in an amorphous state, that is, the above-mentioned oxide semiconductor material may be an amorphous oxide semiconductor material.
- the above-mentioned oxide semiconductor film 3 may be an amorphous indium gallium zinc oxide film.
- the oxide semiconductor thin film 3 is patterned to remove the portion directly in contact with the at least one wire 2 to form an oxide layer 51 including a plurality of oxide thin film transistors 5.
- the oxide semiconductor layer 3a and the above-mentioned at least one wire 2 are insulated from each other.
- a photolithography process may be used to pattern the oxide semiconductor film 3.
- the oxide semiconductor thin film 3 is patterned by a photolithography process, including: S410 to S450.
- a photoresist layer PR is formed on the surface of the oxide semiconductor film 3 away from the substrate 1.
- a coating process may be used to coat a photoresist on the surface of the oxide semiconductor film 3 away from the substrate 1 to form a photoresist layer PR.
- the above-mentioned photoresist may be a positive photoresist, or the above-mentioned photoresist may be a negative photoresist.
- the method for preparing the array substrate is schematically illustrated by taking the photoresist as a positive photoresist as an example.
- the photoresist layer PR may be exposed in an exposure machine.
- static electricity is generated in the oxide semiconductor film 3.
- the static electricity generated in the oxide semiconductor film 3 can be discharged into the at least one wire 2, and the static electricity is discharged through the at least one wire 2 to reduce Even the accumulation of static electricity in the oxide semiconductor thin film 3 is avoided, thereby avoiding the phenomenon of electrostatic breakdown caused by a large amount of static electricity accumulated in the oxide semiconductor thin film 3.
- the exposed photoresist layer PR is developed, and the exposed part of the photoresist layer PR is removed to obtain a patterned photoresist layer PR'.
- the patterned photoresist layer PR' exposes a part of the surface of the oxide semiconductor film 3 away from the substrate 1 and covers the rest of the oxide semiconductor film 3.
- the oxide semiconductor film 3 is patterned, and the unpatterned light in the oxide semiconductor film 3 is removed by etching.
- the part covered by the resist layer PR' retains the part covered by the patterned photoresist layer PR' in the oxide semiconductor film 3, that is, the oxide semiconductor layer 3a.
- the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 above overlap at most, and the oxide semiconductor layer 3a and the at least one wire 2 are insulated from each other. .
- the effective electrical connection between the at least one wire 2 and the thin film formed in the subsequent preparation can be ensured, and the power supply caused by the oxide semiconductor layer 3a sandwiched between the at least one wire 2 and the thin film formed in the subsequent preparation can be avoided.
- the manufacturing method of the array substrate is to form a plurality of wires 2 on one side of the substrate 1, and after the oxide semiconductor film 3 is formed, the oxide semiconductor film 3 and at least one wire are formed. 2 Direct contact, so that in the process of patterning the oxide semiconductor film 3, the static electricity generated in the oxide semiconductor film 3 can be discharged to at least one wire 2 with good conductivity, which is beneficial to reduce the
- the accumulation of static electricity on the oxide semiconductor layer 3a of the multiple active layers 51 avoids the phenomenon of electrostatic breakdown and improves the yield of the prepared array substrate.
- the oxide thin film transistor 5 in the formed array substrate may be a bottom-gate oxide thin film transistor. In other embodiments, the oxide thin film transistor 5 in the formed array substrate may be a top gate type oxide thin film transistor.
- the preparation method of the array substrate may further include: S210 to S230.
- a gate conductive layer Gate is formed.
- the gate conductive layer Gate is located on the same side of the substrate 1 as the multiple wires 2 described above.
- the aforementioned gate conductive layer Gate may include a plurality of gate lines and a plurality of gate electrodes 52 of the oxide thin film transistor 5.
- Each gate 52 may be disposed opposite to the active layer 51 formed by subsequent preparation.
- the material and hierarchical structure of the gate conductive layer Gate may be the same as or different from the plurality of conductive lines 2.
- the gate conductive layer Gate and the plurality of wires 2 may be provided on the same surface, and have the same structure and material, that is, the gate conductive layer Gate and the plurality of wires 2 may be on the same surface. Preparation and formation in the sub-patterning process.
- the gate conductive layer Gate and the plurality of wires 2 can be formed by the following method:
- a gate conductive material film is formed on one side of the substrate 1; then the gate conductive material film is patterned to simultaneously form the plurality of wires 2 and the gate conductive layer Gate.
- the above-mentioned gate conductive material film may be patterned through a photolithography process.
- a gate insulating film GI' is formed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1.
- the gate insulating film GI' covers the gate conductive layer Gate and the plurality of wires 2.
- the material of the gate insulating film GI' may be silicon oxide, silicon oxynitride, silicon nitride, or other insulating materials.
- the gate insulating film GI' can be prepared by, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) process.
- the gate insulating film GI' is patterned to form a gate insulating layer GI having at least one via hole K.
- the at least one via K exposes at least a part of the surface of the at least one wire 2, and the orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap.
- the oxide semiconductor film 3 directly contacts the at least one wire 2 through the at least one via K.
- the gate insulating film GI' may be patterned through a photolithography process to obtain the gate insulating layer GI.
- the gate insulating layer GI covers the gate conductive layer Gate.
- the orthographic projection of the at least one via K on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 at least partially overlap, that is, the at least one via K exposes a part of the at least one wire 2.
- the number of via holes K may be one or multiple.
- the relationship between the at least one via K and the at least one wire 2 includes multiple types, which can be selected and set according to actual needs.
- the at least one via K may correspond to the at least one wire 2 in a one-to-one correspondence, that is, one via K may expose a part of the wire 2.
- one wire 2 may correspond to at least two vias K in the multiple vias K, that is, the at least two vias K In the hole K, each via K can expose a part of a corresponding wire 2.
- one via K may correspond to at least two wires 2 of the multiple wires 2, that is, the via K simultaneously exposes the Part of at least two wires 2.
- the formed oxide semiconductor film 3 can directly contact the at least one wire 2 through the at least one via K.
- the static electricity generated in the oxide semiconductor film 3 can pass through the portion of the oxide semiconductor film 3 located in the at least one via hole K. Release to the at least one wire 2 and lead out through the at least one wire 2.
- the oxide semiconductor layer 3a may expose the at least one via K, and further expose a part of the at least one wire 2.
- the orthographic projection of the formed oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one via K on the substrate 1 can be disjoint. Stack, completely remove the oxide semiconductor material in the at least one via hole K.
- a part of the boundary of the orthographic projection of the at least one wire 2 on the substrate 1 is different from the at least one wire 2 above.
- the method for preparing the above-mentioned array substrate may further include preparing the source electrode 53 and the drain electrode 54 of the oxide thin film transistor 5.
- the preparation method of the array substrate may further include: S500.
- a source-drain conductive layer SD is formed on the side of the oxide semiconductor layer 3a away from the substrate 1.
- the source-drain conductive layer SD may include a plurality of sources 52 and a plurality of drains 53, which are electrically connected to the plurality of active layers 51 in a one-to-one correspondence, and the plurality of drains 53 are connected to a plurality of The source layers 51 are electrically connected in a one-to-one correspondence.
- an oxide thin film transistor 5 may include an active layer 51, a source 52 and a drain 53.
- the source-drain conductive layer SD may further include auxiliary leads 6, and the auxiliary leads 6 are electrically connected to the at least one wire 2 described above.
- the auxiliary lead 6 and the above-mentioned at least one wire 2 can be directly contacted in a one-to-one correspondence to form an electrical connection.
- the auxiliary lead 6 can be used to reduce the resistance of the wire 2 electrically connected to the auxiliary lead 6 and improve the stability of the electrical signal transmitted in the wire 2. Not only that, because the auxiliary lead 6 can reduce the resistance of the wire 2 electrically connected to it, so that the line width of the wire 2 (that is, the size of the wire 2 in the direction perpendicular to its routing) can be reduced, thereby reducing The space ratio of the wire 2 in the array substrate is reduced.
- the source-drain conductive layer SD may be formed by the following method.
- a source-drain conductive material film SD' may be formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' covers the at least one conductive wire 2 described above. At least one exposed portion of the via hole K, a portion of the gate insulating layer GI not covered by the active layer 51, and the active layer 51.
- the material of the source-drain conductive material film SD' can be titanium (Ti), platinum (Pt), ruthenium (Ru), gold (Au), silver (Ag), molybdenum (Mo), aluminum (Al), Tungsten (W), copper (Cu), neodymium (Nd), chromium (Cr), tantalum (Ta) or an alloy thereof or a combination of at least two of the foregoing materials.
- the source-drain conductive material film SD' can be a single-layer structure formed by a layer of conductive material, or a multilayer structure formed by multiple layers of conductive materials stacked in sequence.
- a sputtering process can be used to form the source-drain conductive material film SD'.
- the source-drain conductive material film SD' may be patterned to form the source-drain conductive layer SD including the auxiliary lead 6, the source 53 and the drain 54.
- the source-drain conductive material film SD' can be patterned through a photolithography process.
- the source-drain conductive layer SD may also include source-drain layer leads, such as voltage leads and data lines.
- the orthographic projections on the substrate 1 of the auxiliary lead 6 and the wire 2 electrically connected to the auxiliary lead 6 may be overlapped with each other or may be partially overlapped.
- the formed array substrate 100 may have a display area A and a frame area B located beside the display area A.
- the substrate 1 also has a frame area B and a display area A.
- the orthographic projection of the frame area B of the array substrate 100 on the substrate 1 coincides with the frame area B of the substrate 1
- the orthographic projection of the display area A of the array substrate 100 on the substrate 1 is the same as the display area A of the substrate 1. coincide.
- the side refers to one side, two sides, three layers, or peripheral side of the display area A (as shown in FIG. 4g).
- the frame area B can be located on one side, two sides, or three sides of the display area A, or the frame area B can surround the display area A.
- At least one wire 2 directly in contact with the oxide semiconductor thin film 3 may be formed in the frame area B of the array substrate 100.
- the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be an electrostatic protection line used to protect the array substrate 100 from static electricity.
- the above-mentioned at least one wire 2 may have a larger size in the direction perpendicular to its routing direction, so as to ensure that it has a smaller impedance, thereby ensuring the stability of the electrical signal transmitted by it.
- the resistance of the at least one wire 2 can be reduced, and the line width of the at least one wire 2 can be reduced, which is beneficial to reduce the size of the frame area B, so that The array substrate 100 can realize a narrow frame design.
- At least one wire 2 directly in contact with the oxide semiconductor film 3 may be formed in the display area A of the array substrate 100.
- the at least one wire 2 may be a second common electrode line that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate.
- the manufacturing method of the array substrate of the present disclosure may further include: forming a passivation layer (PVX) 7 on the side of the oxide thin film transistor 5 away from the substrate 1.
- PVX passivation layer
- FIGS. 4g and 51 a plurality of pixel electrodes 8 are formed on the side of the passivation layer 7 away from the substrate 1, and the plurality of pixel electrodes 8 are connected to the source 53 or drain of the plurality of oxide thin film transistors 5, respectively.
- the poles 54 are electrically connected in a one-to-one correspondence.
- the method for preparing the array substrate of the present disclosure may further include: before forming the pixel electrode 8, forming a planarization layer covering the passivation layer 7 so as to provide a flat surface for the pixel electrode 8.
- the pixel electrode 8 may be formed on the side surface of the planarization layer away from the substrate 1.
- the prepared array substrate 100 can be applied to LCD (Liquid Crystal Display, liquid crystal display device).
- the manufacturing method of the array substrate 100 may further include: forming a common electrode on the side of the pixel electrode 8 away from the substrate 1.
- the manufacturing method of the array substrate of the present disclosure may further include: sequentially forming a light-emitting layer and a cathode layer on the side of the pixel electrode 8 away from the substrate 1, and the at least one wire 2 is the first
- the cathode layer may be electrically connected to the above-mentioned at least one wire 2, or to the auxiliary lead 6, or to the at least one wire 2 and the auxiliary lead 6 at the same time.
- the prepared array substrate can be applied to an OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) display device.
- OLED Organic Light Emitting Diode, Organic Light Emitting Diode
- a substrate 1 is provided.
- the substrate 1 is a glass substrate.
- the substrate 1 has a display area A and a frame area B surrounding the display area A.
- a gate conductive material film is formed on one side of the substrate 1, and the gate conductive material film covers the display area A and the frame area B of the substrate 1.
- the above-mentioned gate conductive material film can be formed by a deposition method, for example, the gate conductive material film can be formed by a magnetron sputtering deposition method.
- the gate conductive material film is patterned to form a gate conductive layer Gate located in the display area A and a plurality of wires 2 located in the frame area B.
- the gate conductive layer Gate includes a plurality of gate lines and a plurality of gates 52 for forming an oxide thin film transistor 5;
- the plurality of wires 2 includes at least one common electrode line for providing a common voltage signal for the display area and/ Or an electrostatic protection wire used for electrostatic protection of the array substrate 100.
- a gate insulating film GI' covering the gate conductive layer Gate and the plurality of conductive lines 2 is formed on the side of the gate conductive layer Gate and the plurality of conductive lines 2 away from the substrate 1.
- the gate insulating film GI' can be formed by a deposition method, for example, the gate insulating film GI' can be formed by a chemical vapor deposition (Chemical Vapor Deposition, CVD) method.
- the gate insulating film GI' is patterned with the help of a mask to form a gate insulating layer GI having at least one via K.
- the at least one via K exposes a part of the at least one wire 2.
- the mask may have a pattern for forming at least one via K in the frame area B.
- an oxide semiconductor film 3 is formed on the side of the gate insulating layer GI away from the substrate 1.
- the oxide semiconductor film 3 is located in the display area A and the frame area B at the same time.
- the oxide semiconductor film 3 is in direct contact with the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI.
- the oxide semiconductor thin film 3 may be formed by a deposition method, for example, the oxide semiconductor thin film 3 may be formed by a magnetron sputtering method.
- the oxide semiconductor thin film 3 is patterned to form an oxide semiconductor layer 3a.
- the oxide semiconductor layer 3a includes a plurality of active layers 51 for forming an oxide thin film transistor 5, and the oxide semiconductor layer 3a does not cover the at least one wire 2 described above.
- the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 and the orthographic projection of the at least one wire 2 on the substrate 1 do not overlap at all.
- the substrate containing the oxide semiconductor thin film 3 may be transported into an exposure machine for exposure. Since oxide semiconductor materials are usually amorphous materials, they have poor electrical conductivity and are prone to static electricity in the exposure machine. Since the oxide semiconductor film 3 is in direct contact with the at least one wire 2, the static electricity generated in the oxide semiconductor film 3 can be discharged to the at least one wire 2, and the at least one wire 2 is led out, reducing or even avoiding the accumulation of static electricity. , Effectively avoid the occurrence of electrostatic breakdown (ESD) phenomenon.
- ESD electrostatic breakdown
- the portion of the oxide semiconductor film 3 above and inside the at least one via K will be removed, exposing part of the surface of the at least one wire 2.
- a source-drain conductive film material SD' is formed on the side of the oxide semiconductor layer 3a away from the substrate 1, and the source-drain conductive material film SD' is located in the display area A and the frame area B at the same time. That is, the source-drain conductive material film SD' covers the exposed at least one wire 2, the portion of the gate insulating layer GI that is not covered by the active layer 51, and the active layer 51.
- the source and drain conductive material film SD' can be formed by a deposition method, for example, the source and drain conductive material film SD' can be formed by a magnetron sputtering method.
- the source-drain conductive material film SD' is patterned to form a source-drain conductive layer SD.
- the source-drain conductive layer SD includes auxiliary leads 6 located in the frame area B and directly contacting the at least one wire 2 through the via K, and multiple data lines and the source of each oxide thin film transistor 5 located in the display area A. Pole 53 and drain 54 and so on.
- the auxiliary lead 6 can be connected in parallel with the at least one wire 2 to reduce the resistance of the at least one wire 2, which not only improves the stability of the electrical signal transmitted in the at least one wire 2, but also reduces the at least one wire 2.
- the size in the direction perpendicular to the routing direction is beneficial to reduce the size of the frame area B, and is beneficial to realize the narrow frame design of the array substrate 100.
- a passivation layer 7 (PVX) and a planarization layer are sequentially formed.
- a plurality of pixel electrodes 8 are formed on the side of the planarization layer away from the substrate 1, wherein the plurality of pixel electrodes 8 are connected to the drains of the plurality of oxide thin film transistors 5, respectively.
- Pole 54 is electrically connected.
- the material of the pixel electrode 8 may be ITO, for example.
- the preparation method of the exemplary array substrate may further include: forming a light-emitting layer and a cathode layer in sequence on the side of the pixel electrode 8 away from the substrate 1, wherein the cathode layer extends to the frame area B and is directly connected to the auxiliary lead 6
- the contact forms an electrical connection.
- the wire 2 electrically connected to the auxiliary lead may be a common electrode wire.
- a protective layer is formed on the side of the cathode layer away from the substrate 1, a protective layer is formed.
- the array substrate 100 may include a substrate 1, a plurality of wires 2 and a plurality of oxide thin film transistors 5.
- the material of the substrate 1 can refer to the schematic descriptions in some of the above-mentioned embodiments, which will not be repeated here.
- the plurality of oxide thin film transistors 5 and the plurality of wires 2 are arranged on the same side of the substrate 1.
- each oxide thin film transistor 5 includes an active layer 51, a gate 52, a source 53 and a drain 54.
- the active layer 51 of any oxide thin film transistor 5 is obtained by patterning the oxide semiconductor thin film 3 directly in contact with at least one wire 2 (for example, refer to the preparation of the array substrate provided in some of the above embodiments). Method), and the active layer 51 of any oxide thin film transistor 5 and the at least one wire 2 are insulated from each other.
- the material of the above-mentioned active layer 51 includes multiple types.
- the material of the active layer 51 may be an oxide semiconductor material.
- the oxide semiconductor material may be an amorphous oxide semiconductor material.
- the amorphous oxide semiconductor material may be zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum zinc oxide, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium.
- the array substrate 100 provided by some embodiments of the present disclosure can be prepared and formed by the preparation method of the array substrate provided in some of the above embodiments, because the active layer 51 of the plurality of oxide thin film transistors 5 is combined with the above at least one The oxide semiconductor film 3 directly in contact with the wire 2 is obtained by patterning, and the at least one wire 2 has good conductivity. Therefore, the static electricity generated in the oxide semiconductor film 3 can be released into the at least one wire 2 through the At least one wire 2 is led out to avoid the accumulation of static electricity in the oxide semiconductor layer 3a including multiple active layers 51, thereby avoiding electrostatic breakdown, and effectively improving the yield of the array substrate 100.
- the oxide thin film transistor 5 is taken as an example of a bottom-gate oxide thin film transistor.
- the multiple wires 2 and the gate 52 in each oxide thin film transistor 5 are located on the side of the active layer 51 close to the substrate 1.
- the plurality of wires 2 and each gate 52 are made of the same material and arranged in the same layer.
- the “same layer” mentioned in this article refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form a patterning process.
- a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
- the above-mentioned multiple conductive lines 2 and each gate 52 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the manufacturing process of the array substrate 100.
- the array substrate 100 further includes: a gate insulating layer GI disposed between the gate 52 and the active layer 51.
- the gate 52 belongs to the gate conductive layer Gate
- the active layer 51 belongs to the oxide semiconductor layer 3a, that is, the gate insulating layer GI is located between the gate conductive layer Gate and the oxide semiconductor layer 3a.
- the gate conductive layer Gate may further include gate lines.
- the gate insulating layer GI has at least one via K exposing a portion of the at least one wire 2, that is, the orthographic projection of the at least one via K on the substrate 1 and the at least one via K The orthographic projection of a wire 2 on the substrate 1 at least partially overlaps.
- a part of the boundary of the orthographic projection of the at least one signal line 2 on the substrate 1 is different from the boundary of the orthographic projection of the at least one via K on the substrate 1 One part coincides.
- the above-mentioned oxide semiconductor film 3 may be electrically connected to the above-mentioned at least one wire 2 through the at least one via K.
- the static electricity can be discharged to the at least one wire 2 through the portion of the oxide semiconductor film 3 located in the at least one via K, and then the at least one wire 2 can pass through the at least one wire 2.
- Export static electricity when static electricity is generated in the oxide semiconductor film 3, the static electricity can be discharged to the at least one wire 2 through the portion of the oxide semiconductor film 3 located in the at least one via K, and then the at least one wire 2 can pass through the at least one wire 2.
- the array substrate further includes an auxiliary lead 6 directly in contact with the above-mentioned at least one wire 2.
- auxiliary lead 6 can be set in multiple ways, which can be selected and set according to actual needs.
- the auxiliary lead 6 may be arranged on the side of the gate insulating layer GI away from the substrate 1, and the auxiliary lead 6 directly contacts the at least one wire 2 through the at least one via K.
- the auxiliary lead 6 can be used to reduce the resistance of the at least one wire 2, thereby reducing the size of the at least one wire 2 perpendicular to its routing direction, and reducing the space ratio of the at least one wire 2 in the array substrate 100 .
- the auxiliary lead 6 may have the same material as the source 53 and the drain 54 of the oxide thin film transistor 5 and be arranged in the same layer. In this way, the auxiliary lead 6, the source electrode 53 and the drain electrode 54 can be prepared and formed at the same time in one patterning process, which is beneficial to simplify the preparation process of the array substrate 100.
- the film including the auxiliary lead 6, the source electrode 53 and the drain electrode 54 may be referred to as a source-drain conductive layer SD.
- the source-drain conductive layer SD may also include data lines, power lines, and the like.
- the orthographic projection of the auxiliary lead 6 on the substrate 1 and the orthographic projection of the aforementioned at least one wire 2 on the substrate 1 at least partially overlap.
- the auxiliary lead 6 corresponds to the above-mentioned at least one wire 2 in a one-to-one correspondence.
- the orthographic projection of the auxiliary lead 6 on the substrate 1 and the corresponding orthographic projection of the wire 2 on the substrate 1 at least partially overlap, which may include: a partial misalignment between the auxiliary lead 6 and the wire 2 so that the auxiliary lead 6 is on the substrate 1 A part of the orthographic projection of the corresponding wire 2 overlaps with a part of the orthographic projection of the corresponding wire 2 on the substrate 1; or, the orthographic projection of the auxiliary lead 6 on the substrate 1 is located on the orthographic projection of the corresponding wire 2 on the substrate 1. Within the projection range.
- the routing direction of the auxiliary lead 6 is the same or substantially the same as the routing direction of the at least one wire 2 described above. That is, the angle between the routing direction of the auxiliary lead 6 and the routing direction of the at least one wire 2 is 0° or close to 0°. This is beneficial to ensure the effect of reducing the resistance of the at least one wire 2.
- the array substrate 100 may further include: a passivation layer 7 disposed on the side of the source electrode 53 and the drain electrode 54 away from the substrate 1 (that is, covering each oxide thin film transistor 5) .
- a part of the passivation layer 7 may be located in at least one via K of the gate insulating layer GI. In this way, it is possible to prevent the subsequently formed conductive layer (for example, the pixel electrode 8) from forming an electrical connection with the above-mentioned at least one wire 2 and avoid signal crosstalk.
- the array substrate 100 may further include: a pixel electrode 8 disposed on the side of the passivation layer 7 away from the substrate 1.
- the pixel electrode 8 may be electrically connected to the drain 54 of the oxide thin film transistor 5, for example.
- the array substrate 100 may further include a planarization layer provided between the passivation layer 7 and the pixel electrode 8.
- the array substrate 100 has a display area A and a frame area B located beside the display area A.
- the display area A For the "side”, reference may be made to the schematic description in some of the foregoing examples.
- the oxide thin film transistor 5 in the array substrate 100 may be located in the display area A.
- at least one wire 2 electrically connected to the oxide semiconductor thin film 3 may be located in the display area A, or may be located in the frame area B.
- the at least one wire 2 may be a second common signal that transmits a common voltage signal to an electrode layer (for example, a common electrode layer or a cathode layer) in the array substrate.
- Electrode wire In the case where the above-mentioned at least one wire 2 is located in the frame area B, the at least one wire 2 may be a first common electrode line used to provide a common voltage signal to the display area A, or may also be used to perform processing on the array substrate 100.
- Electrostatic protection wire for electrostatic protection.
- the array substrate 100 may include a substrate 1, a plurality of wires 2, a gate conductive layer Gate, a gate insulating layer GI, an oxide semiconductor layer 3a, source and drain conductive layers. Layer SD, passivation layer 7 and a plurality of pixel electrodes 8.
- the substrate 1 may be a glass substrate.
- the substrate 1 may have a display area A and a frame area B surrounding the display area A.
- the above-mentioned multiple wires 2 may be located in the frame area B of the substrate 1.
- the aforementioned gate conductive layer Gate may be located in the display area A of the substrate 1.
- the gate conductive layer Gate and the plurality of wires 2 may be arranged on the same side of the substrate 1 and on the same surface, for example, the two materials are the same and arranged in the same layer.
- the gate conductive layer Gate may include a plurality of gate lines and a plurality of gates 52 for forming the oxide thin film transistor 5.
- the gate insulating layer GI may be disposed on the side of the plurality of wires 2 and the gate conductive layer Gate away from the substrate 1.
- the gate insulating layer GI has at least one via K, and the at least one via K exposes at least one wire 2 of the plurality of wires 2, that is, the orthographic projection of the gate insulating layer GI on the substrate 1 and the at least one wire 2
- the orthographic projections of the wires 2 on the substrate 1 partially overlap.
- the oxide semiconductor layer 3a may be provided on the side of the gate conductive layer Gate away from the substrate 1.
- the oxide semiconductor layer 3a includes a plurality of active layers 51 for forming oxide thin film transistors 5, and the orthographic projection of the oxide semiconductor layer 3a on the substrate 1 is the same as the orthographic projection of the at least one wire 2 on the substrate 1.
- the projections do not overlap at all.
- the oxide semiconductor layer 3 a is obtained by patterning the oxide semiconductor thin film 3 a directly in contact with the at least one wire 2.
- the source-drain conductive layer SD may be provided on the side of the oxide semiconductor layer 3a away from the substrate 1.
- the source-drain conductive layer SD may include an auxiliary lead 6 electrically connected to the above-mentioned at least one wire 2 through at least one via K in the gate insulating layer GI, a plurality of source and drain layer leads (such as data lines), and each oxide thin film transistor 5 The source 53 and drain 54 and so on.
- the auxiliary lead 6 can be arranged in the frame area B, and the source and drain layer leads, the source electrode 53 and the drain electrode 54 are arranged in the display area A.
- the passivation layer 7 may be formed on the side of the source and drain conductive layer SD away from the substrate 1.
- the passivation layer 7 may, for example, cover the source-drain conductive layer SD and retain a part of the drain 54 in the source-drain conductive layer SD.
- a plurality of pixel electrodes 8 may be arranged on the side of the passivation layer 7 away from the substrate 1.
- the plurality of pixel electrodes 8 may be electrically connected to the plurality of drain electrodes 54 in a one-to-one correspondence.
- the array substrate 100 of the present disclosure can be prepared by the preparation method of the array substrate provided in some of the above-mentioned embodiments, and the structure, principle and effect of the array substrate 100 have been compared with the preparation method of the array substrate provided in some of the above-mentioned embodiments It is described in detail in, so I won’t repeat it here.
- Some embodiments of the present disclosure also provide a display device 1000. As shown in FIGS. 8 and 9, the display device 1000 further includes the array substrate 100 as described in some of the above embodiments.
- the beneficial effects that can be achieved by the display device 1000 provided by some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 100 provided in some of the foregoing embodiments, and will not be repeated here.
- the display device 1000 may be an LCD. At this time, the display device 1000 may further include a counter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200.
- the above-mentioned counter substrate 200 may be a transparent substrate, or may also be a color filter substrate (as shown in FIG. 8).
- the array substrate 100 may further include a color filter layer and/or a black matrix disposed on the side of the pixel electrode 8 close to the counter substrate 200.
- the display device 1000 may be an OLED display device. At this time, the display device 1000 may further include: a plurality of light-emitting devices 400 arranged on a side of the array substrate 100 away from the substrate 1 with a plurality of oxide thin film transistors 5.
- the pixel electrode 8 in the array substrate 100 may be referred to as the anode layer of the light emitting device 400.
- the light-emitting device 400 may further include a light-emitting layer and a cathode layer that are sequentially stacked on the side of the anode layer away from the substrate 1.
- the above-mentioned display device 1000 may be any device that displays whether it is moving (for example, video) or fixed (for example, still image), and whether it is text or image. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (Personal Digital Assistants).
- electronic devices such as (but not limited to) mobile phones, wireless devices, and personal data assistants (Personal Digital Assistants).
- PDA Personal Digital Assistant
- handheld or portable computer Global Positioning System (GPS) receiver/navigator
- camera Moving Picture Experts Group 4 (MP4 for short) video player
- camera Game consoles, watches, clocks, calculators, television monitors, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays
- camera view displays e.g., vehicle Rear view camera displays
- electronic photographs electronic billboards or signs
- projectors architectural structures, packaging and aesthetic structures (for example, a display of an image of a piece of jewelry), etc.
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Abstract
Description
Claims (20)
- 一种阵列基板的制备方法,包括:A method for preparing an array substrate includes:提供衬底;Provide substrate;在所述衬底上形成多条导线;Forming a plurality of wires on the substrate;在所述多条导线远离所述衬底的一侧形成氧化物半导体薄膜;所述氧化物半导体薄膜覆盖所述多条导线并与至少一条导线直接接触;所述至少一条导线被配置为,导出所述氧化物半导体薄膜中产生的静电;An oxide semiconductor film is formed on the side of the plurality of wires away from the substrate; the oxide semiconductor film covers the plurality of wires and is in direct contact with at least one wire; the at least one wire is configured to lead out Static electricity generated in the oxide semiconductor film;采用光刻工艺,对所述氧化物半导体薄膜进行图案化处理,去除与所述至少一条导线直接接触的部分,形成包括多个氧化物薄膜晶体管的有源层的氧化物半导体层。Using a photolithography process, the oxide semiconductor thin film is patterned, and the portion directly in contact with the at least one wire is removed to form an oxide semiconductor layer including an active layer of a plurality of oxide thin film transistors.
- 根据权利要求1所述的阵列基板的制备方法,还包括:The manufacturing method of the array substrate according to claim 1, further comprising:在形成所述氧化物半导体薄膜之前,形成包括多个氧化物薄膜晶体管的栅极的栅导电层;所述栅导电层与所述多条导线位于所述衬底的同一侧;Before forming the oxide semiconductor thin film, forming a gate conductive layer including the gates of a plurality of oxide thin film transistors; the gate conductive layer and the plurality of wires are located on the same side of the substrate;在所述多条导线和所述栅导电层远离所述衬底的一侧形成栅绝缘薄膜;所述栅绝缘薄膜覆盖所述多条导线和所述栅导电层;Forming a gate insulating film on the side of the plurality of wires and the gate conductive layer away from the substrate; the gate insulating film covers the plurality of wires and the gate conductive layer;对所述栅绝缘薄膜进行图案化处理,形成具有至少一个过孔的栅绝缘层;所述至少一个过孔暴露所述至少一条导线的至少一部分表面,所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠;The gate insulating film is patterned to form a gate insulating layer with at least one via; the at least one via exposes at least a part of the surface of the at least one wire, and the at least one via is in the substrate The orthographic projection on the substrate at least partially overlaps the orthographic projection of the at least one wire on the substrate;其中,所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。Wherein, the oxide semiconductor film is in direct contact with the at least one wire through the at least one via hole.
- 根据权利要求2所述的阵列基板的制备方法,其中,沿垂直于所述至少一条导线的走线方向,所述至少一条导线在所述衬底上的正投影边界的一部分,与所述至少一个过孔在所述衬底上的正投影边界的一部分重合。The method for manufacturing an array substrate according to claim 2, wherein, along the line direction perpendicular to the at least one wire, a part of the boundary of the orthographic projection of the at least one wire on the substrate is connected to the at least one wire. A part of the boundary of the orthographic projection of a via on the substrate coincides.
- 根据权利要求2或3所述的阵列基板的制备方法,其中,所述多条导线的材料包括金属材料;The manufacturing method of the array substrate according to claim 2 or 3, wherein the material of the plurality of wires includes a metal material;所述多条导线和所述栅导电层在同一次构图工艺中形成。The plurality of conductive lines and the gate conductive layer are formed in the same patterning process.
- 根据权利要求1~4中任一项所述的阵列基板的制备方法,还包括:4. The method for manufacturing an array substrate according to any one of claims 1 to 4, further comprising:在所述氧化物半导体层远离所述衬底的一侧形成源漏导电层,所述源漏导电层包括与每个有源层直接接触的源极和漏极,以及与所述至少一条导线直接接触的辅助引线。A source-drain conductive layer is formed on the side of the oxide semiconductor layer away from the substrate. The source-drain conductive layer includes a source electrode and a drain electrode directly in contact with each active layer, and is connected to the at least one wire Direct contact auxiliary lead.
- 根据权利要求5所述的阵列基板的制备方法,其中,所述阵列基板具有显示区和位于所述显示区旁侧的边框区;5. The method for manufacturing an array substrate according to claim 5, wherein the array substrate has a display area and a frame area located beside the display area;所述至少一条导线和所述辅助引线位于所述边框区;The at least one wire and the auxiliary lead are located in the frame area;所述至少一条导线被配置为,向所述显示区传输公共电压信号,或对所述阵列基板进行静电防护;The at least one wire is configured to transmit a common voltage signal to the display area, or to protect the array substrate from static electricity;所述辅助引线被配置为,与所述至少一条导线形成并联,降低所述至少一条导线的电阻。The auxiliary lead is configured to be connected in parallel with the at least one wire to reduce the resistance of the at least one wire.
- 根据权利要求1~6中任一项所述的阵列基板的制备方法,其中,所述氧化物半导体薄膜的材料包括氧化锌、氧化铟、氧化锡、铟锌氧化物、氧化锌锡、氧化铝锌、氧化钇锌、氧化铟锡锌、铟镓锌氧化物和铟铝锌氧中的一种。The method for preparing an array substrate according to any one of claims 1 to 6, wherein the material of the oxide semiconductor film includes zinc oxide, indium oxide, tin oxide, indium zinc oxide, zinc tin oxide, aluminum oxide One of zinc, yttrium zinc oxide, indium tin zinc oxide, indium gallium zinc oxide, and indium aluminum zinc oxide.
- 根据权利要求1~7中任一项所述的阵列基板的制备方法,其中,所述氧化物半导体层在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至多部分重叠。The method for manufacturing an array substrate according to any one of claims 1 to 7, wherein the orthographic projection of the oxide semiconductor layer on the substrate is opposite to the orthographic projection of the at least one wire on the substrate. The projections overlap at most.
- 一种阵列基板,包括:An array substrate, including:衬底;Substrate设置在所述衬底一侧的多条导线;以及,A plurality of wires arranged on one side of the substrate; and,多个氧化物薄膜晶体管,所述多个氧化物薄膜晶体管与所述多条导线设置在所述衬底的同一侧;A plurality of oxide thin film transistors, the plurality of oxide thin film transistors and the plurality of wires are arranged on the same side of the substrate;其中,每个氧化物薄膜晶体管包括栅极、有源层、源极和漏极;所述多个氧化物薄膜晶体管的有源层为通过对与至少一条导线直接接触的氧化物半导体薄膜进行图案化处理而获得的,且所述有源层与所述至少一条导线相互绝缘。Wherein, each oxide thin film transistor includes a gate, an active layer, a source and a drain; the active layers of the plurality of oxide thin film transistors are formed by patterning an oxide semiconductor thin film directly in contact with at least one wire. And the active layer and the at least one wire are insulated from each other.
- 根据权利要求9所述的阵列基板,还包括:设置在所述栅极与所述有源层之间的栅绝缘层;9. The array substrate according to claim 9, further comprising: a gate insulating layer provided between the gate and the active layer;所述栅绝缘层具有至少一个过孔,所述至少一个过孔暴露所述至少一条导线的至少一部分表面,所述至少一个过孔在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠;The gate insulating layer has at least one via, the at least one via exposes at least a part of the surface of the at least one wire, and the orthographic projection of the at least one via on the substrate is in line with the at least one wire. The orthographic projections on the substrate at least partially overlap;所述氧化物半导体薄膜通过所述至少一个过孔与所述至少一条导线直接接触。The oxide semiconductor film directly contacts the at least one wire through the at least one via hole.
- 根据权利要求10所述的阵列基板,还包括:设置在所述栅绝缘层远离所述衬底一侧的辅助引线;9. The array substrate according to claim 10, further comprising: auxiliary leads arranged on a side of the gate insulating layer away from the substrate;所述辅助引线通过所述至少一个过孔与所述至少一条导线直接接触。The auxiliary lead directly contacts the at least one wire through the at least one via hole.
- 根据权利要求9所述的阵列基板,还包括:与所述源极和所述漏极材料相同且同层设置的辅助引线;9. The array substrate according to claim 9, further comprising: auxiliary leads which are made of the same material as the source electrode and the drain electrode and arranged in the same layer;所述辅助引线与所述至少一条导线直接接触。The auxiliary lead is in direct contact with the at least one wire.
- 根据权利要求11或12所述的阵列基板,其中,所述辅助引线在所述衬底上的正投影与所述至少一条导线在所述衬底上的正投影至少部分重叠。The array substrate according to claim 11 or 12, wherein the orthographic projection of the auxiliary lead on the substrate and the orthographic projection of the at least one wire on the substrate at least partially overlap.
- 根据权利要求11~13中任一项所述的阵列基板,其中,所述辅助引线的走线方向与所述至少一条导线的走线方向相同或大致相同。The array substrate according to any one of claims 11 to 13, wherein the routing direction of the auxiliary lead is the same or substantially the same as the routing direction of the at least one wire.
- 根据权利要求10所述的阵列基板,还包括:设置在所述源极和所述漏极远离所述衬底一侧的钝化层;9. The array substrate according to claim 10, further comprising: a passivation layer disposed on a side of the source electrode and the drain electrode away from the substrate;所述钝化层中的一部分位于所述至少一个过孔内,并与所述至少一条导线直接接触。A part of the passivation layer is located in the at least one via hole and directly contacts the at least one wire.
- 根据权利要求9~15中任一项所述的阵列基板,其中,所述阵列基板具有显示区和位于所述显示区旁侧的边框区;15. The array substrate according to any one of claims 9-15, wherein the array substrate has a display area and a frame area located beside the display area;所述至少一条导线位于所述边框区;The at least one wire is located in the frame area;所述至少一条导线包括公共电极线或静电防护线;The at least one wire includes a common electrode wire or an electrostatic protection wire;所述公共电极线被配置为,向所述显示区传输公共电压信号;The common electrode line is configured to transmit a common voltage signal to the display area;所述静电防护线被配置为,对所述阵列基板进行静电防护。The electrostatic protection wire is configured to perform electrostatic protection on the array substrate.
- 根据权利要求9~16中任一项所述的阵列基板,其中,所述栅极和所述多条导线材料相同且同层设置。The array substrate according to any one of claims 9 to 16, wherein the gate electrode and the plurality of conductive lines have the same material and are arranged in the same layer.
- 一种显示装置,包括:如权利要求9~17中任一项所述的阵列基板。A display device, comprising: the array substrate according to any one of claims 9-17.
- 根据权利要求18所述的显示装置,还包括:The display device according to claim 18, further comprising:与所述阵列基板相对设置的对置基板;以及,A counter substrate disposed opposite to the array substrate; and,设置在所述阵列基板和所述对置基板之间的液晶层。A liquid crystal layer provided between the array substrate and the counter substrate.
- 根据权利要求19所述的显示装置,还包括:The display device according to claim 19, further comprising:设置在所述阵列基板的多个氧化物薄膜晶体管远离所述阵列基板的衬底一侧的多个发光器件。A plurality of oxide thin film transistors arranged on the array substrate are arranged on a plurality of light-emitting devices on the side of the substrate away from the array substrate.
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