WO2021056785A1 - 反相器的制作方法及反相器 - Google Patents

反相器的制作方法及反相器 Download PDF

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Publication number
WO2021056785A1
WO2021056785A1 PCT/CN2019/120003 CN2019120003W WO2021056785A1 WO 2021056785 A1 WO2021056785 A1 WO 2021056785A1 CN 2019120003 W CN2019120003 W CN 2019120003W WO 2021056785 A1 WO2021056785 A1 WO 2021056785A1
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Prior art keywords
layer
active layer
inverter
substrate
barrier layer
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PCT/CN2019/120003
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English (en)
French (fr)
Inventor
谢华飞
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/626,352 priority Critical patent/US11328961B2/en
Publication of WO2021056785A1 publication Critical patent/WO2021056785A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Definitions

  • the present invention relates to the field of display technology, in particular to a manufacturing method of an inverter and an inverter.
  • liquid crystal display devices Liquid Crystal Display, LCD
  • organic light-emitting diode display devices Organic Light Flat display devices including Emitting Display (OLED)
  • LCD liquid crystal display devices
  • OLED Organic Light Flat display devices
  • mobile phones TVs, personal digital assistants, digital cameras, notebook computers, and desktop computers.
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS inverters need to have bipolar characteristics, that is, they need to include an N-type thin film transistor and a P-type thin film transistor.
  • CMOS inverters use the same semiconductor material to achieve bipolar characteristics.
  • the asymmetric electrode allows a semiconductor material to obtain bipolar characteristics to construct a CMOS inverter.
  • Carbon Nanotube (CNT) thin film transistors Compared with the traditional Thin Film Transistor (TFT) technology, Carbon Nanotube (CNT) thin film transistors have obvious advantages in terms of device performance and manufacturing process, and the process temperature and process complexity are lower. More importantly, the carbon nanotube film can be prepared with a carbon nanotube solution, which can realize large-scale low-cost manufacturing using a printing process. Therefore, carbon nanotube thin film transistors have great application prospects in future display driver backplanes, flexible electronic products, and biodetectors.
  • TFT Thin Film Transistor
  • the purpose of the present invention is to provide a method for manufacturing an inverter, which can simplify the manufacturing process of the inverter and reduce the manufacturing cost of the inverter.
  • the object of the present invention is also to provide an inverter, which can simplify the manufacturing process of the inverter and reduce the manufacturing cost of the inverter.
  • the present invention provides a manufacturing method of an inverter, which includes the following steps:
  • Step S1 fabricating a substrate, and forming a first insulating layer on the substrate;
  • Step S2 forming a semiconductor carbon nanotube film on the first insulating layer
  • Step S3 patterning the semiconductor carbon nanotube film to form a first active layer and a second active layer distributed at intervals;
  • Step S4 forming a first barrier layer on the first active layer, forming a second barrier layer on the second active layer, the first barrier layer being an electrophilic film layer, and the second barrier layer
  • the layer is the electron-donating film layer
  • Step S5 forming a first source and a first drain that are in contact with and spaced apart from both ends of the first active layer, and a second source that is in contact with and spaced apart from both ends of the second active layer And a second drain, and the first drain is connected to the second source.
  • the step of fabricating a substrate in the step S1 includes fabricating a heavily doped silicon wafer as the substrate.
  • the step of making a base in the step S1 includes: providing a flexible substrate, covering the flexible substrate with a buffer layer, and forming first and second gates arranged at intervals on the buffer layer to obtain the The base;
  • the first active layer and the second active layer are respectively arranged corresponding to the first gate and the second gate.
  • the step of making a base in the step S1 includes: providing a glass substrate, and forming a first grid and a second grid spaced apart on the glass substrate to obtain the base;
  • the first active layer and the second active layer are respectively arranged corresponding to the first gate and the second gate.
  • the semiconductor carbon nanotube film is formed by a solution printing process
  • the material of the first barrier layer is silicon nitride
  • the material of the second barrier layer is silicon oxide
  • the present invention provides an inverter including a substrate, a first insulating layer provided on the substrate, a first active layer and a second active layer spaced apart on the first insulating layer, and A first barrier layer on the first active layer, a second barrier layer provided on the second active layer, a first source electrode that is in contact with both ends of the first active layer and is spaced apart from each other, and A first drain, and a second source and a second drain that are in contact with and spaced apart from both ends of the second active layer, and the first drain is connected to the second source;
  • the materials of the first active layer and the second active layer are semiconductor carbon nanotubes, the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donating film layer.
  • the substrate is a heavily doped silicon wafer.
  • the base includes a flexible substrate, a buffer layer provided on the flexible substrate, and spaced first and second gates provided on the buffer layer;
  • the first active layer and the second active layer are respectively arranged corresponding to the first gate and the second gate.
  • the base includes a glass substrate, and spaced first and second grids arranged on the glass substrate;
  • the first active layer and the second active layer are respectively arranged corresponding to the first gate and the second gate.
  • the material of the first barrier layer is silicon nitride, and the material of the second barrier layer is silicon oxide.
  • the present invention also provides an inverter, including a substrate, a first insulating layer provided on the substrate, a first active layer and a second active layer spaced apart on the first insulating layer, and A first barrier layer on the first active layer, a second barrier layer provided on the second active layer, and first source electrodes that are in contact with both ends of the first active layer and are spaced apart from each other A second source and a second drain that are in contact with the first drain and both ends of the second active layer and are spaced apart from each other, and the first drain is connected to the second source;
  • the materials of the first active layer and the second active layer are semiconductor-type carbon nanotubes, the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donating film layer;
  • the material of the first barrier layer is silicon nitride, and the material of the second barrier layer is silicon oxide;
  • the first barrier layer and the first active layer form an N-type device, and the second barrier layer and the second active layer form a P-type device.
  • the present invention provides a method for manufacturing an inverter, which includes the following steps: step S1, fabricating a substrate, and forming a first insulating layer on the substrate; step S2, forming on the first insulating layer Semiconductor-type carbon nanotube film; step S3, patterning the semiconductor-type carbon nanotube film to form a first active layer and a second active layer distributed at intervals; step S4, in the first active layer A first barrier layer is formed on the upper surface, a second barrier layer is formed on the second active layer, the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donating film layer; step S5, forming A first source and a first drain that are in contact with and spaced apart from both ends of the first active layer, and a second source and a second drain that are in contact with and spaced apart from both ends of the second active layer The first drain electrode is connected to the second source electrode.
  • the manufacture of the inverter can be simplified Process, reduce the manufacturing cost of the inverter.
  • the invention also provides an inverter, which can simplify the manufacturing process of the inverter and reduce the manufacturing cost of the inverter.
  • FIG. 1 is a schematic diagram of step S1 of the first embodiment of the manufacturing method of the inverter of the present invention
  • step S2 is a schematic diagram of step S2 and step S3 of the first embodiment of the manufacturing method of the inverter of the present invention
  • step S5 is a schematic diagram of step S5 of the first embodiment of the manufacturing method of the inverter of the present invention and a structural diagram of the first embodiment of the inverter of the present invention
  • step S1 of the second embodiment of the manufacturing method of the inverter of the present invention is a schematic diagram of step S1 of the second embodiment of the manufacturing method of the inverter of the present invention.
  • step S2 and step S3 of the second embodiment of the manufacturing method of the inverter of the present invention are schematic diagrams of step S2 and step S3 of the second embodiment of the manufacturing method of the inverter of the present invention.
  • step S4 of the second embodiment of the manufacturing method of the inverter of the present invention are schematic diagrams of step S4 of the second embodiment of the manufacturing method of the inverter of the present invention.
  • step S5 of the second embodiment of the manufacturing method of the inverter of the present invention is a schematic diagram of step S5 of the second embodiment of the manufacturing method of the inverter of the present invention and a structural diagram of the second embodiment of the inverter of the present invention
  • step S1 of the third embodiment of the manufacturing method of the inverter of the present invention is a schematic diagram of step S1 of the third embodiment of the manufacturing method of the inverter of the present invention.
  • step S2 is a schematic diagram of step S2 and step S3 of the third embodiment of the manufacturing method of the inverter of the present invention.
  • FIG. 13 and 14 are schematic diagrams of step S4 of the third embodiment of the method for manufacturing an inverter of the present invention.
  • step S5 of the third embodiment of the manufacturing method of the inverter of the present invention is a schematic diagram of step S5 of the third embodiment of the manufacturing method of the inverter of the present invention and a structural diagram of the third embodiment of the inverter of the present invention
  • Fig. 16 is a flow chart of the manufacturing method of the inverter of the present invention.
  • the present invention provides a manufacturing method of an inverter, which includes the following steps:
  • step S1 a substrate 1 is fabricated, and a first insulating layer 2 is formed on the substrate 1.
  • the substrate 1 is a heavily doped silicon wafer.
  • the step of making the base 1 in the step S1 includes: providing a flexible substrate 10, covering the flexible substrate 10 with a buffer layer 20 , Forming a first gate 31 and a second gate 32 arranged at intervals on the buffer layer 20 to obtain the substrate 1.
  • the step of making the base 1 in the step S1 includes: providing a glass substrate 10', and forming a space on the glass substrate 10' The first gate 31' and the second gate 32' are arranged to obtain the substrate 1.
  • the manufacturing method of the inverter of the present invention is applicable to silicon wafer substrates, flexible substrates and glass substrate devices at the same time.
  • the process of forming the first gate and the second gate includes: cleaning the substrate 1, and depositing a whole surface on the substrate by means of physical vapor deposition or evaporation.
  • the conductive film is then coated with photoresist, and then the photoresist is exposed through a photomask, and then developed, acid wet etching and elution are performed to complete the photolithography of the conductive film to obtain the first gate and The second gate.
  • the first insulating layer 2 is produced by atomic layer deposition or chemical vapor deposition.
  • the material of the first insulating layer 2 is one or a combination of hafnium dioxide, silicon oxide, silicon nitride, and aluminum oxide.
  • the material of the first insulating layer 2 is silicon oxide, and in the second and third embodiments of the present invention, the material of the first insulating layer 2 is nitrogen. Silicone.
  • Step S2 forming a semiconductor-type carbon nanotube film on the first insulating layer 2.
  • the semiconductor-type carbon nanotube film is produced by a solution printing film forming process, and the semiconductor-type carbon nanotube film is a semiconductor-type single-walled carbon nanotube (sc-SWCNT).
  • the semiconductor carbon nanotube film produced by the solution printing film forming process has the advantages of simple and easy operation, no need for vacuum, high temperature and high pressure environment and conditions, easy large-area and rapid preparation, and rich sources of carbon elements and stable chemical properties. And it is non-toxic, which is conducive to the construction of green and cheap devices.
  • the inverter By using bipolar semiconductor carbon nanotubes as the active layer, the inverter has the advantages of simple structure, low power consumption, and high stability.
  • Step S3 patterning the semiconductor-type carbon nanotube film to form a first active layer 51 and a second active layer 52 distributed at intervals.
  • the step S3 includes: patterning the semiconductor-type carbon nanotube film through the processes of coating photoresist, photomask exposure, development, and plasma dry etching to obtain The first active layer 51 and the second active layer 52.
  • the first active layer 51 and the second active layer 52 are provided corresponding to the first gate 31 and the second gate 32, respectively. .
  • the first active layer 51 and the second active layer 52 correspond to the first gate 31' and the second gate 32, respectively. 'Set.
  • Step S4 forming a first barrier layer 61 on the first active layer 51, forming a second barrier layer 62 on the second active layer 52, the first barrier layer 61 being an electrophilic film layer,
  • the second barrier layer 62 is an electron donating film layer.
  • the step S4 specifically includes: A first photoresist layer is formed on the source layer 52;
  • the material of the first barrier layer 61 is silicon nitride, and the material of the second barrier layer 62 is silicon oxide.
  • first barrier layer 61 and the first active layer 51 form an N-type device
  • second barrier layer 62 and the second active layer 52 form a P-type device, thereby realizing dual inverters. Polarity characteristics.
  • Step S5 forming a first source 71 and a first drain 72 in contact with both ends of the first active layer 51 and spaced apart from each other, and a first source 71 and a first drain 72 in contact with both ends of the second active layer 52 and spaced apart from each other
  • the second source 73 and the second drain 74 are connected, and the first drain 72 is connected to the second source 73.
  • a conductive film on the entire surface is deposited on the substrate by means of physical vapor deposition or evaporation, followed by coating photoresist, exposing, Development, acid wet etching, and elution of the photoresist are completed to complete the patterning of the conductive film to obtain the first source 71, the first drain 72, the second source 73, and the second drain 74.
  • the present invention also provides an inverter, which includes a substrate 1, a first insulating layer 2 disposed on the substrate 1, and spaced apart on the first insulating layer 2
  • An electrode 73 and a second drain 74 where the first drain 72 is connected to the second source 73;
  • the materials of the first active layer 51 and the second active layer 52 are semiconductor carbon nanotubes, the first barrier layer 61 is an electrophilic film layer, and the second barrier layer 62 is an electron donating film layer.
  • the substrate 1 is a heavily doped silicon wafer.
  • the base 1 includes a flexible substrate 10, a buffer layer 20 provided on the flexible substrate 10, and a buffer layer 20 provided on the flexible substrate 10.
  • the first grid 31 and the second grid 32 arranged at intervals;
  • the first active layer 51 and the second active layer 52 are respectively disposed corresponding to the first gate 31 and the second gate 32.
  • the base 1 includes a glass substrate 10' and spaced first grids 31' arranged on the glass substrate 10' And the second gate 32';
  • the first active layer 51 and the second active layer 52 are respectively disposed corresponding to the first gate 31' and the second gate 32'.
  • the manufacturing method of the inverter of the present invention is applicable to silicon wafer substrates, flexible substrates and glass substrate devices at the same time.
  • the material of the first barrier layer 61 is silicon nitride, and the material of the second barrier layer 62 is silicon oxide.
  • first barrier layer 61 and the first active layer 51 form an N-type device
  • second barrier layer 62 and the second active layer 52 form a P-type device, thereby realizing dual inverters. Polarity characteristics.
  • the first active layer 51 and the second active layer 52 can be produced by a solution printing film forming process
  • the semiconductor type carbon nanotubes are semiconductor type single-walled carbon nanotubes (sc-SWCNT).
  • the semiconductor carbon nanotube film produced by the solution printing film forming process has the advantages of simple and easy operation, no need for vacuum, high temperature and high pressure environment and conditions, easy large-area and rapid preparation, and rich sources of carbon elements and stable chemical properties. And it is non-toxic, which is conducive to the construction of green and cheap devices.
  • the inverter By using bipolar semiconductor carbon nanotubes as the active layer, the inverter has the advantages of simple structure, low power consumption, and high stability.
  • the present invention provides a method for fabricating an inverter, which includes the following steps: step S1, fabricating a substrate, and forming a first insulating layer on the substrate; step S2, forming a semiconductor on the first insulating layer Type carbon nanotube film; step S3, patterning the semiconductor type carbon nanotube film to form a first active layer and a second active layer distributed at intervals; step S4, on the first active layer A first barrier layer is formed, a second barrier layer is formed on the second active layer, the first barrier layer is an electrophilic film layer, and the second barrier layer is an electron donating film layer; step S5, forming and A first source and a first drain that are in contact with and spaced apart from both ends of the first active layer, and a second source and a second drain that are in contact with and spaced apart from both ends of the second active layer , And the first drain electrode is connected to the second source electrode.
  • the manufacturing process of the inverter can be simplified , Reduce the production cost of the inverter.
  • the invention also provides an inverter, which can simplify the manufacturing process of the inverter and reduce the manufacturing cost of the inverter.

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一种反相器的制作方法及反相器。所述反相器的制作方法包括如下步骤：制作基底（1），并在基底（1）上形成第一绝缘层（2）；在第一绝缘层（2）上形成半导体型碳纳米管薄膜；对半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层（51）和第二有源层（52）；在第一有源层（51）上形成第一阻挡层（61），在第二有源层（52）上形成第二阻挡层（62），第一阻挡层（61）为亲电子膜层，第二阻挡层（62）为供电子膜层；形成与第一有源层（51）的两端接触且相互间隔的第一源极（71）和第一漏极（72）以及与第二有源层（52）的两端接触且相互间隔的第二源极（73）和第二漏极（74），且第一漏极（72）与第二源极（73）相连，通过采用半导体型碳纳米管作为有源层配合亲电子膜层和供电子膜层作为阻挡层，能够简化反相器的制作工艺，降低反相器的制作成本。

Description

反相器的制作方法及反相器 技术领域
本发明涉及显示技术领域，尤其涉及一种反相器的制作方法及反相器。
 背景技术
随着显示技术的发展，包括液晶显示装置（Liquid Crystal Display，LCD）及有机发光二极管显示装置（Organic Light Emitting Display，OLED）在内的平面显示装置已经成为最为常见的显示装置，被广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品之中。
无论是液晶显示装置还是有机发光二极管显示装置CMOS（Complementary Metal Oxide Semiconductor，互补式金属氧化物半导体）反相器均是装置中的一个重要器件，主要作用为接收一输入信号，并输出与输入信号逻辑相反的一输出信号。
通常CMOS反相器需要具有双极性特性，也即需要包括一个N型薄膜晶体管和一个P型薄膜晶体管，目前绝大部分的CMOS反相器是通过同一种半导体材料来实现双极性特性的，例如对于一种半导体材料，由于作为源漏电极的金属材料功函数的不同会造成不同类型的载流子传输，通过不对称电极使一种半导体材料得到双极性特性从而构筑CMOS反相器；对同一种电极材料的不同修饰也可以调节载流子传输性质达到平衡以制备CMOS反相器，但无论是采用不同的电极材料，还是对同一电极材料进行不同修饰，都需要在特定位置精确地集成不同电极材料或者对电极材料进行特定的修饰，工艺复杂，成本较高。
相比于传统的薄膜晶体管（Thin Film Transistor，TFT）技术，碳纳米管（Carbon Nanotube，CNT）薄膜晶体管在器件性能和制备工艺方面具有明显的优势，且工艺温度以及工艺复杂度都较低，更重要的是碳纳米管薄膜可以采用碳纳米管溶液制备，能够实现利用印刷工艺实现大规模低成本制造。因此，碳纳米管薄膜晶体管在未来显示驱动背板、柔性电子产品及生物探测器方面极具应用前景。
 技术问题
本发明的目的在于提供一种反相器的制作方法，能够简化反相器的制作工艺，降低反相器的制作成本。
本发明的目的还在于提供一种反相器，能够简化反相器的制作工艺，降低反相器的制作成本。
 技术解决方案
为实现上述目的，本发明提供一种反相器的制作方法，包括如下步骤：
步骤S1、制作基底，并在所述基底上形成第一绝缘层；
步骤S2、在第一绝缘层上形成半导体型碳纳米管薄膜；
步骤S3、对所述半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层和第二有源层；
步骤S4、在所述第一有源层上形成第一阻挡层，在所述第二有源层上形成第二阻挡层，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；
步骤S5、形成与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，且所述第一漏极与所述第二源极相连。
所述步骤S1中制作基底的步骤包括制作一重掺杂硅片作为所述基底。
所述步骤S1中制作基底的步骤包括：提供一柔性衬底，在所述柔性衬底上覆盖缓冲层，在所述缓冲层上形成间隔排列的第一栅极及第二栅极，得到所述基底；
所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
所述步骤S1中制作基底的步骤包括：提供一玻璃衬底，在所述玻璃衬底上形成间隔排列的第一栅极及第二栅极，得到所述基底；
所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
所述步骤S2中采用溶液打印工艺形成所述半导体型碳纳米管薄膜，所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅。
本发明提供一种反相器，包括基底、设于所述基底上的第一绝缘层、位于所述第一绝缘层上间隔分布的第一有源层和第二有源层、设于所述第一有源层上的第一阻挡层、设于所述第二有源层上的第二阻挡层、与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，所述第一漏极与所述第二源极相连；
所述第一有源层及第二有源层的材料为半导体型碳纳米管，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层。
所述基底为重掺杂硅片。
所述基底包括柔性衬底、设于所述柔性衬底上的缓冲层以及设于所述缓冲层上的间隔排列的第一栅极及第二栅极；
所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
所述基底包括玻璃衬底以及设于所述玻璃衬底上的间隔排列的第一栅极及第二栅极；
所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅。
本发明还提供一种反相器，包括基底、设于所述基底上的第一绝缘层、位于所述第一绝缘层上间隔分布的第一有源层和第二有源层、设于所述第一有源层上的第一阻挡层、设于所述第二有源层上的第二阻挡层、与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，所述第一漏极与所述第二源极相连；
所述第一有源层及第二有源层的材料为半导体型碳纳米管，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；
所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅；
所述第一阻挡层及第一有源层形成一N型器件，所述第二阻挡层及第二有源层形成一P型器件。
 有益效果
本发明的有益效果：本发明提供一种反相器的制作方法，包括如下步骤：步骤S1、制作基底，并在所述基底上形成第一绝缘层；步骤S2、在第一绝缘层上形成半导体型碳纳米管薄膜；步骤S3、对所述半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层和第二有源层；步骤S4、在所述第一有源层上形成第一阻挡层，在所述第二有源层上形成第二阻挡层，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；步骤S5、形成与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，且所述第一漏极与所述第二源极相连，通过采用半导体型碳纳米管作为有源层配合亲电子膜层和供电子膜层作为阻挡层，能够简化反相器的制作工艺，降低反相器的制作成本。本发明还提供一种反相器，能够简化反相器的制作工艺，降低反相器的制作成本。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的反相器的制作方法的第一实施例的步骤S1的示意图；
图2为本发明的反相器的制作方法的第一实施例的步骤S2及步骤S3的示意图；
图3及图4为本发明的反相器的制作方法的第一实施例的步骤S4的示意图；
图5为本发明的反相器的制作方法的第一实施例的步骤S5的示意图暨本发明的反相器的第一实施例的结构图；
图6为本发明的反相器的制作方法的第二实施例的步骤S1的示意图；
图7为本发明的反相器的制作方法的第二实施例的步骤S2及步骤S3的示意图；
图8及图9为本发明的反相器的制作方法的第二实施例的步骤S4的示意图；
图10为本发明的反相器的制作方法的第二实施例的步骤S5的示意图暨本发明的反相器的第二实施例的结构图；
图11为本发明的反相器的制作方法的第三实施例的步骤S1的示意图；
图12为本发明的反相器的制作方法的第三实施例的步骤S2及步骤S3的示意图；
图13及图14为本发明的反相器的制作方法的第三实施例的步骤S4的示意图；
图15为本发明的反相器的制作方法的第三实施例的步骤S5的示意图暨本发明的反相器的第三实施例的结构图；
图16为本发明的反相器的制作方法的流程图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图16，本发明提供一种反相器的制作方法，包括如下步骤：
步骤S1、制作基底1，并在所述基底1上形成第一绝缘层2。
具体地，如图1所示，在本发明的第一实施例中，所述基底1为重掺杂型硅片。
具体地，如图6所示，在本发明的第二实施例中，所述步骤S1中制作基底1的步骤包括：提供一柔性衬底10，在所述柔性衬底10上覆盖缓冲层20，在所述缓冲层20上形成间隔排列的第一栅极31及第二栅极32，得到所述基底1。
具体地，如图10所示，在本发明的第三实施例中，所述步骤S1中制作基底1的步骤包括：提供一玻璃衬底10’，在所述玻璃衬底10’上形成间隔排列的第一栅极31’及第二栅极32’，得到所述基底1。
从而，本发明的反相器的制作方法同时适用于硅片基底、柔性基底及玻璃基底的器件。
具体地，在本发明的第二及第三实施例中，形成第一栅极及第二栅极的过程包括：清洗基底1，以物理气相沉积或蒸镀的方式在基板上沉积一整面的导电膜，接着涂布光刻胶，然后通过一道光罩对光刻胶进行曝光，然后进行显影、酸液湿刻及洗脱，以完成对导电膜的光刻，得到第一栅极及第二栅极。
具体地，本发明以原子层沉积或化学气相沉积制作所述第一绝缘层2。
具体地，所述第一绝缘层2的材料为二氧化铪、氧化硅、氮化硅及氧化铝中的一种或多种的组合。
优选地，在本发明的第一实施例中，所述第一绝缘层2的材料为氧化硅，在本发明的第二及第三实施例中，所述第一绝缘层2的材料为氮化硅。
步骤S2、在第一绝缘层2上形成半导体型碳纳米管薄膜。
具体地，所述步骤S2中通过溶液打印成膜工艺制作所述半导体型碳纳米管薄膜，所述半导体型碳纳米管薄膜为半导体型单壁碳纳米管（sc-SWCNT）。
需要说明的是，通过溶液打印成膜工艺制作半导体型碳纳米管薄膜，具有简单易行，无需真空高温高压环境与条件，易于大面积快速制备的优点，且碳元素来源丰富，化学性质稳定，且没有毒性，有利于构建绿色、廉价器件，通过采用具有双极性的半导体型碳纳米管作为有源层，使得反相器具有结构简单、低功耗、高稳定性的优点。
步骤S3、对所述半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层51和第二有源层52。
具体地，请参阅图2、图7及图12，所述步骤S3包括：通过涂布光刻胶、光罩曝光、显影及等离子体干刻工艺对半导体型碳纳米管薄膜进行图案化，得到第一有源层51和第二有源层52。
具体地，如图7所示，在本发明的第二实施例中，所述第一有源层51及第二有源层52分别对应所述第一栅极31及第二栅极32设置。
具体地，如图12所示，在本发明的第三实施例中，所述第一有源层51及第二有源层52分别对应所述第一栅极31’及第二栅极32’设置。
步骤S4、在所述第一有源层51上形成第一阻挡层61，在所述第二有源层52上形成第二阻挡层62，所述第一阻挡层61为亲电子膜层， 所述第二阻挡层62为供电子膜层。
具体地， 如图3与图4、图8与图9以及图13与图14所示，所述步骤S4具体包括：在所述第一绝缘层2、第一有源层51及第二有源层52上形成第一光刻胶层；
去除第一有源层51上的第一光刻胶层，在剩余的第一光刻胶层及第一有源层51上形成第一阻挡薄膜，去除剩余的第一光刻胶层及位于剩余的第一光刻胶层上的第一阻挡薄膜，得到位于第一有源层51上的第一阻挡层61；
在所述第一绝缘层4、第一阻挡层61及第二有源层52上形成第二光刻胶层；
去除第二有源层52上的第二光刻胶层，在剩余的第二光刻胶层及第二有源层52上形成第二阻挡薄膜，去除剩余的第二光刻胶层及位于剩余的第二光刻胶层上的第二阻挡薄膜，得到位于第二有源层52上的第二阻挡层62；
优选地，所述第一阻挡层61的材料为氮化硅，第二阻挡层62的材料为氧化硅。
进一步地，所述第一阻挡层61及第一有源层51形成一N型器件，所述第二阻挡层62及第二有源层52形成一P型器件，从而实现反相器的双极性特性。
步骤S5、形成与所述第一有源层51的两端接触且相互间隔的第一源极71和第一漏极72以及与所述第二有源层52的两端接触且相互间隔的第二源极73和第二漏极74，且所述第一漏极72与所述第二源极73相连。
具体地，如图5、图10及图15所示，所述步骤S5中，以物理气相沉积或蒸镀的方式在基板上沉积一整面的导电膜，接着涂布光刻胶、曝光、显影、酸液湿刻、洗脱光刻胶，完成导电膜的图案化，得到第一源极71、第一漏极72、第二源极73和第二漏极74。
请参阅图5、图10或图15，本发明还提供一种反相器，包括基底1、设于所述基底1上的第一绝缘层2、位于所述第一绝缘层2上间隔分布的第一有源层51和第二有源层52、设于所述第一有源层51上的第一阻挡层61、设于所述第二有源层52上的第二阻挡层62、与所述第一有源层51的两端接触且相互间隔的第一源极71和第一漏极72以及与所述第二有源层52的两端接触且相互间隔的第二源极73和第二漏极74，所述第一漏极72与所述第二源极73相连；
所述第一有源层51及第二有源层52的材料为半导体型碳纳米管，所述第一阻挡层61为亲电子膜层， 所述第二阻挡层62为供电子膜层。
具体地，如图5所示，在本发明的第一实施例中，所述基底1为重掺杂硅片。
具体地，如图10所示，在本发明的第二实施例中，所述基底1包括柔性衬底10、设于所述柔性衬底10上的缓冲层20以及设于所述缓冲层20上的间隔排列的第一栅极31及第二栅极32；
所述第一有源层51及第二有源层52分别对应所述第一栅极31及第二栅极32设置。
具体地，如图10所示，在本发明的第三实施例中，所述基底1包括玻璃衬底10’以及设于所述玻璃衬底10’上的间隔排列的第一栅极31’及第二栅极32’；
所述第一有源层51及第二有源层52分别对应所述第一栅极31’及第二栅极32’设置。
从而，本发明的反相器的制作方法同时适用于硅片基底、柔性基底及玻璃基底的器件。
优选地，所述第一阻挡层61的材料为氮化硅，第二阻挡层62的材料为氧化硅。
进一步地，所述第一阻挡层61及第一有源层51形成一N型器件，所述第二阻挡层62及第二有源层52形成一P型器件，从而实现反相器的双极性特性。
具体地，所述第一有源层51及第二有源层52可通过溶液打印成膜工艺制作，所述半导体型碳纳米管为半导体型单壁碳纳米管（sc-SWCNT）。
需要说明的是，通过溶液打印成膜工艺制作半导体型碳纳米管薄膜，具有简单易行，无需真空高温高压环境与条件，易于大面积快速制备的优点，且碳元素来源丰富，化学性质稳定，且没有毒性，有利于构建绿色、廉价器件，通过采用具有双极性的半导体型碳纳米管作为有源层，使得反相器具有结构简单、低功耗、高稳定性的优点。
综上所述，本发明提供一种反相器的制作方法，包括如下步骤：步骤S1、制作基底，并在所述基底上形成第一绝缘层；步骤S2、在第一绝缘层上形成半导体型碳纳米管薄膜；步骤S3、对所述半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层和第二有源层；步骤S4、在所述第一有源层上形成第一阻挡层，在所述第二有源层上形成第二阻挡层，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；步骤S5、形成与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，且所述第一漏极与所述第二源极相连，通过采用半导体型碳纳米管作为有源层配合亲电子膜层和供电子膜层作为阻挡层，能够简化反相器的制作工艺，降低反相器的制作成本。本发明还提供一种反相器，能够简化反相器的制作工艺，降低反相器的制作成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (11)

  1. 一种反相器的制作方法，包括如下步骤：
    步骤S1、制作基底，并在所述基底上形成第一绝缘层；
    步骤S2、在第一绝缘层上形成半导体型碳纳米管薄膜；
    步骤S3、对所述半导体型碳纳米管薄膜进行图案化，形成间隔分布的第一有源层和第二有源层；
    步骤S4、在所述第一有源层上形成第一阻挡层，在所述第二有源层上形成第二阻挡层，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；
    步骤S5、形成与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，且所述第一漏极与所述第二源极相连。
  2. 如权利要求1所述的反相器的制作方法，其中，所述步骤S1中制作基底的步骤包括制作一重掺杂硅片作为所述基底。
  3. 如权利要求1所述的反相器的制作方法，其中，所述步骤S1中制作基底的步骤包括：提供一柔性衬底，在所述柔性衬底上覆盖缓冲层，在所述缓冲层上形成间隔排列的第一栅极及第二栅极，得到所述基底；
    所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
  4. 如权利要求1所述的反相器的制作方法，其中，所述步骤S1中制作基底的步骤包括：提供一玻璃衬底，在所述玻璃衬底上形成间隔排列的第一栅极及第二栅极，得到所述基底；
    所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
  5. 如权利要求1所述的反相器的制作方法，其中，所述步骤S2中采用溶液打印工艺形成所述半导体型碳纳米管薄膜，所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅。
  6. 一种反相器，包括基底、设于所述基底上的第一绝缘层、位于所述第一绝缘层上间隔分布的第一有源层和第二有源层、设于所述第一有源层上的第一阻挡层、设于所述第二有源层上的第二阻挡层、与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，所述第一漏极与所述第二源极相连；
    所述第一有源层及第二有源层的材料为半导体型碳纳米管，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层。
  7. 如权利要求6所述的反相器，其中，所述基底为重掺杂硅片。
  8. 如权利要求6所述的反相器，其中，所述基底包括柔性衬底、设于所述柔性衬底上的缓冲层以及设于所述缓冲层上的间隔排列的第一栅极及第二栅极；
    所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
  9. 如权利要求6所述的反相器，其中，所述基底包括玻璃衬底以及设于所述玻璃衬底上的间隔排列的第一栅极及第二栅极；
    所述第一有源层及第二有源层分别对应所述第一栅极及第二栅极设置。
  10. 如权利要求6所述的反相器，其中，所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅。
  11. 一种反相器，包括基底、设于所述基底上的第一绝缘层、位于所述第一绝缘层上间隔分布的第一有源层和第二有源层、设于所述第一有源层上的第一阻挡层、设于所述第二有源层上的第二阻挡层、与所述第一有源层的两端接触且相互间隔的第一源极和第一漏极以及与所述第二有源层的两端接触且相互间隔的第二源极和第二漏极，所述第一漏极与所述第二源极相连；
    所述第一有源层及第二有源层的材料为半导体型碳纳米管，所述第一阻挡层为亲电子膜层， 所述第二阻挡层为供电子膜层；
    所述第一阻挡层的材料为氮化硅，第二阻挡层的材料为氧化硅；
    所述第一阻挡层及第一有源层形成一N型器件，所述第二阻挡层及第二有源层形成一P型器件。
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