WO2021056732A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2021056732A1
WO2021056732A1 PCT/CN2019/117535 CN2019117535W WO2021056732A1 WO 2021056732 A1 WO2021056732 A1 WO 2021056732A1 CN 2019117535 W CN2019117535 W CN 2019117535W WO 2021056732 A1 WO2021056732 A1 WO 2021056732A1
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WIPO (PCT)
Prior art keywords
layer
insulating layer
gate
photoresist
substrate
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PCT/CN2019/117535
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English (en)
French (fr)
Inventor
夏慧
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Tcl华星光电技术有限公司
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Priority to US16/616,968 priority Critical patent/US11187950B2/en
Publication of WO2021056732A1 publication Critical patent/WO2021056732A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a preparation method thereof.
  • GOA technology (Gate Driver on Array) is the array substrate row drive technology. It uses the original array process of the liquid crystal display panel to fabricate the horizontal scan line drive circuit on the substrate around the display area, so that it can replace the external integrated circuit board (Integrated Circuit, IC) to complete the driving of the horizontal scan line. GOA technology can reduce the bonding process of external ICs, which has the opportunity to increase production capacity and reduce product costs.
  • a TGP (tracking gate line in pixel) display panel the display panel is mainly composed of an array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the array substrate and the color filter substrate.
  • the array substrate can be divided into a display area (display region) and non-display region (non-display region), in which a plurality of pixel units arranged in an array are arranged on the display region, and each pixel unit includes a thin film transistor and a pixel electrode connected to the thin film transistor. electrode).
  • the array substrate sequentially includes a substrate, a gate layer, a first insulating layer, a gate tracking layer, and a second insulating layer, wherein the gate tracking layer is provided in a non-display area.
  • the preparation method of the array substrate includes the following steps: preparing a gate layer on a substrate; preparing a first insulating layer on the upper surface of the gate layer; depositing a metal material on the upper surface of the first insulating layer to form a gate Polar tracking layer; coating a photoresist solution on the upper surface of the gate tracking layer to form a photoresist layer; using a mask to expose and develop the photoresist layer to form the patterned photoresist layer Etch the substrate so that the patterned photoresist layer and the first insulating layer are etched at the same position to form a through hole to achieve the purpose of exposing the gate layer; and removing ⁇ photoresist layer.
  • the through hole may be deposited by a conductive layer (such as an ITO layer), so that the conductive layer is connected to the gate layer, and the gate layer is connected to the gate tracking layer through the conductive layer.
  • a conductive layer such as an ITO layer
  • the preparation process of the array substrate is complicated, and the production cost is high.
  • the data lines or gate lines on the array substrate extend from the edge of the display panel to the display area.
  • the long distance and narrow line width often cause defects such as short (short circuit) or open (open circuit).
  • the traditional design has a large space at the edge of the panel, which conflicts with the display panel with a narrow frame.
  • the purpose of the present invention is to provide an array substrate and a preparation method thereof, so as to solve the problem that the GOA circuit space in the prior art is compressed to realize the narrow frame of the display panel, which will cause the poor antistatic ability of the display panel, and the prior art
  • the manufacturing process of the array substrate is complicated and the production cost is high.
  • the present invention provides an array substrate including a substrate, a gate layer, a first insulating layer, a gate tracking layer, and a second insulating layer; the gate layer is attached to the surface of one side of the substrate; The first insulating layer is attached to the gate layer and the surface of one side of the substrate; the first insulating layer is provided with through holes;
  • the gate tracking layer is attached to the surface of the first insulating layer on the side away from the substrate, fills the through holes, and is connected to the gate layer; the second insulating layer is provided on the gate The pole tracking layer and the first insulating layer are away from the surface on the side of the substrate.
  • the first insulating layer is an inorganic substance, and its material includes tantalum oxide and/or aluminum zirconium oxide; the second insulating layer is an organic substance, and its material includes polymethyl methacrylate.
  • the array substrate further includes an active layer, a source/drain layer, and a data line layer, which are provided on the surface of the second insulating layer on the side away from the substrate; the source/drain layer is provided on the second insulating layer.
  • the second insulating layer is on the surface on the side away from the substrate; the data line layer is provided on the surface of the second insulating layer on the side away from the substrate, and is connected to the source and drain layers; wherein, the active The layer is located between two adjacent source and drain layers.
  • the present invention also provides a method for preparing an array substrate, which includes the following steps: a substrate setting step, a substrate is provided; a gate layer preparation step, a gate layer is prepared on the upper surface of the substrate; a first insulating layer In the preparation step, a first insulating layer is prepared on the upper surface of the gate layer and the substrate so that the first insulating layer is provided with through holes; the gate tracking layer is prepared in the upper surface of the first insulating layer Depositing a metal material to form a gate tracking layer, filling the through hole, and connecting to the gate layer; and a second insulating layer preparation step, on the upper surface of the first insulating layer and the gate tracking layer Prepare a second insulating layer.
  • the gate layer preparation step includes the following steps: a first metal layer preparation step, a metal material is deposited on the upper surface of the substrate to form a first metal film layer; a first photoresist layer preparation step, in the second The upper surface of a metal layer is coated with a photoresist solution to form a first photoresist layer; the first exposure step is to expose the first photoresist layer; the first development step is to develop the first photoresist layer Processing, forming the patterned first photoresist layer; a first wet etching step, performing wet etching processing on the substrate to form the patterned gate layer; and a first removing step, removing the first Photoresist layer.
  • the step of preparing the first insulating layer includes the following steps: a step of preparing a second photoresist layer: coating a photoresist solution on the upper surface of the gate layer to form a second photoresist layer; and a second exposure step: The second photoresist layer is exposed to light; the second developing step is to develop the second photoresist layer to form the patterned second photoresist layer; the deposition step is to perform the second photoresist layer on the second photoresist layer.
  • the thickness of the first insulating layer is smaller than the thickness of the second photoresist layer.
  • the gate tracking layer preparation step includes the following steps: a second metal layer preparation step: depositing a metal material on the upper surface of the first insulating layer to form a second metal film layer; and a third photoresist layer preparation step, A photoresist solution is coated on the upper surface of the second metal film layer to form a third photoresist layer; the third exposure step is to expose the third photoresist layer; and the third development step is to The photoresist layer is developed to form the patterned third photoresist layer; the second wet etching step is to perform wet etching on the substrate to form the patterned gate tracking layer; and third removal Step, removing the patterned third photoresist layer.
  • the method further includes the following steps: a step of preparing an active layer: preparing an active layer on the upper surface of the second insulating layer.
  • the method further includes the following steps: a step of preparing a source-drain layer: a source-drain layer is prepared on the upper surface of the second insulating layer, and the active layer is located adjacent to each other. Between the two source and drain layers
  • the method further includes the following step: a step of preparing a data line layer, preparing a data line layer on the upper surface of the second insulating layer.
  • the technical effect of the present invention is to provide an array substrate and a preparation method thereof.
  • One end of the gate tracking layer is directly connected to the gate layer through a through hole, and the other end is connected to the IC circuit in the non-display area, wherein the gate tracking layer Set in the display area to reduce the wiring space in the non-display area, so that the display panel can achieve the effect of a narrow frame.
  • the gate tracking layer when the gate tracking layer is in contact with the gate layer, the gate tracking layer and the gate can be reduced.
  • the contact resistance between the layers, and the preparation process of the array substrate is simple.
  • FIG. 1 is a flow chart of the method for manufacturing the array substrate according to the embodiment
  • FIG. 3 is a flow chart of the steps of preparing the first insulating layer according to this embodiment
  • FIG. 5 is a flowchart of the steps of preparing the gate tracking layer according to the embodiment.
  • FIG. 6 is a cross-sectional view of the gate tracking layer prepared in this embodiment
  • FIG. 7 is a cross-sectional view of preparing a second insulating layer in this embodiment.
  • FIG. 8 is a cross-sectional view of the array substrate according to the embodiment.
  • FIG. 9 is a cross-sectional view of another array substrate according to this embodiment.
  • FIG. 10 is a plan view of the array substrate according to the embodiment.
  • this embodiment provides a method for manufacturing an array substrate, which includes the following steps S1 to S8.
  • the S1 substrate setting step is to set a glass substrate commonly used in the prior art.
  • the preparation step of the S2 gate layer includes the following steps S21 to S26.
  • S21 The first metal layer preparation step is to deposit a metal material on the upper surface of the substrate to form a first metal film layer.
  • the structure of the first metal film layer may be a molybdenum-copper structure or a molybdenum-aluminum-molybdenum structure. These structures can avoid the gate Undercutting occurs during the subsequent processing.
  • the user uses a first mask to coat a photoresist solution on the upper surface of the first metal layer to form a first photoresist layer.
  • first exposure step of S23 exposure processing is performed on the first photoresist layer under UV light conditions.
  • first developing step of S24 a developing solution is used to develop the first photoresist layer to form the patterned first photoresist layer.
  • S26 a first removal step, removing the first photoresist layer.
  • a first insulating layer 3 is prepared on the upper surface of the gate layer 2 and the substrate 1, so that the first insulating layer 3 is provided with a through hole 100.
  • the thickness of the first insulating layer 3 is between 0.8um and 1.2um.
  • the step of preparing the first insulating layer in S3 includes the following steps S31 to S35.
  • a second mask is used to coat the upper surface of the gate layer 2 with a photoresist solution to form a second photoresist layer (not shown).
  • the first insulating layer is an inorganic substance, and its material includes one or two of tantalum oxide and aluminum zirconium oxide, and the thickness of the second photoresist layer is greater than 1000A.
  • exposure processing is performed on the second photoresist layer under the irradiation of UV light.
  • second developing step of S33 the user uses a developing solution to develop the second photoresist layer to form the patterned second photoresist layer.
  • an inorganic material is deposited on the upper surface of the second photoresist layer to form the first insulating layer 3, and the thickness of the first insulating layer 3 is greater than 500 ⁇ .
  • the second removal step of S35 the user removes the first insulating layer 3 corresponding to the position while removing the patterned second photoresist layer, and then forms the through hole 100 at the position.
  • the thickness of the first insulating layer is smaller than the thickness of the second photoresist layer.
  • the thickness of the second photoresist layer is more than 3 times the thickness of the first insulating layer to ensure that during the process of depositing the first insulating layer on the second photoresist layer, the first insulating layer.
  • a dry etching method is generally used to etch the first insulating layer, so that the first insulating layer is provided with through holes.
  • the plasma can easily insulate the first insulating layer.
  • the surface of the gate layer on the lower surface of the layer is damaged, so that when the metal at the formed through hole is in contact with the gate layer, the contact resistance is likely to increase.
  • the S4 gate tracking layer preparation step is to deposit a metal material on the upper surface of the first insulating layer to form a gate tracking layer 4, fill the through hole, and connect to the gate layer 2.
  • the preparation step of the S4 gate tracking layer includes the following steps S41 to S46.
  • a second metal layer preparation step a metal material is deposited on the upper surface of the first insulating layer to form a second metal film layer (not shown).
  • a third mask is used to coat a photoresist solution on the upper surface of the second metal film layer to form a third photoresist layer.
  • S43 the third exposure step: performing exposure processing on the third photoresist layer.
  • the user uses a developing solution to develop the third photoresist layer to form the patterned third photoresist layer.
  • wet etching is performed on the substrate to form a patterned gate tracking layer 4.
  • S46 The third removing step, removing the patterned third photoresist layer.
  • the gate tracking 4 layer covers the upper surface of the first insulating layer 3, fills the through hole, and is connected to the gate layer 2.
  • the gate tracking layer 4 is in contact with the gate layer 2, and the contact resistance between the gate tracking layer 4 and the gate layer 2 can be reduced.
  • the gate tracking layer is arranged in the display area, one end of which is directly connected to the gate layer, and the other end is connected to the IC circuit in the non-display area, which can reduce the wiring space in the non-display area and make The panel achieves the effect of a narrow border.
  • a second insulating layer 5 is prepared on the upper surface of the first insulating layer 3 and the gate tracking layer 4.
  • the second insulating layer 5 is made of organic material, and its material includes polymethyl methacrylate, which is elastic and has a good sealing function.
  • the thickness of the second insulating layer 5 is between 5um and 7um.
  • an active layer 6 is prepared on the upper surface of the second insulating layer 5.
  • the active layer is an organic semiconductor pentacene (Pentacene), which has good flexibility.
  • a source and drain layer 7 is prepared on the upper surface of the second insulating layer 5, and the active layer 6 is located between two adjacent source and drain layers 7.
  • the structure of the source and drain layer 7 may be a molybdenum-copper structure or a molybdenum-aluminum-molybdenum structure, which can avoid undercutting of the source and drain during subsequent processing.
  • a data line layer 8 is prepared on the upper surface of the second insulating layer 5.
  • the execution sequence of the active layer preparation step, the source and drain layer preparation step, and the data line layer preparation step described above can be changed, and this implementation does not specifically limit it.
  • This embodiment provides a method for preparing an array substrate.
  • a gate tracking layer is provided between two adjacent insulating layers.
  • the gate tracking layer is provided in the display area, one end of which is directly connected to the gate layer, and the other One end is connected to the IC circuit in the non-display area.
  • the gate tracking layer is arranged in the display area, which can reduce the wiring space in the non-display area, so that the display panel achieves the effect of a narrow frame.
  • the gate tracking layer is in contact with the gate layer through a through hole, reducing the contact resistance between the gate tracking layer and the gate layer, and isolating the gate layer from the source and drain layer and the data line layer through the insulating layer Effect, while ensuring the insulating effect of the gate layer.
  • the thickness of the first insulating layer is smaller than the thickness of the second insulating layer, so that the array substrate has the characteristics of a flexible narrow frame.
  • the array substrate includes a substrate 1, a gate layer 2, a first insulating layer 3, a gate tracking layer 4, a second insulating layer 4, an active layer 6, The source drain layer 7 and the data line layer 9.
  • the gate layer 2 is attached to the upper surface of the substrate 1, and the structure of the gate layer 2 is a molybdenum-copper structure or a molybdenum-aluminum-molybdenum structure. These structures can prevent the gate layer 2 from undercutting during subsequent processing.
  • the first insulating layer 3 is attached to the upper surface of the gate layer 2 and the substrate 1; the first insulating layer 3 is provided with a through hole 100.
  • the first insulating layer 3 is an inorganic substance, and its material includes one or two of tantalum oxide and aluminum zirconium oxide.
  • the thickness of the first insulating layer 3 is between 0.8um and 1.2um.
  • the gate tracking layer 4 is attached to the upper surface of the first insulating layer 3 to fill the through hole 100 and is connected to the gate layer 2.
  • the aperture at the bottom of the through hole 100 is smaller than the aperture at the top of the through hole, and the bus bar of the through hole is between 40° and 70° in the vertical direction to prevent undercutting when the gate tracking layer 4 and the gate layer 2 are connected.
  • the gate tracking layer 4 is arranged zigzag, such as in an S shape, a Z shape, etc., to ensure a stable connection between the gate tracking layer 4 and the gate layer 2 and prevent the gate tracking layer 4 from being peeled off.
  • the contact area between the gate tracking layer 4 and the gate layer 2 can be increased, thereby enhancing the gate The tightness of the connection between the tracking layer 4 and the gate layer 2.
  • the electrical connection function can be realized through other through holes 100 without affecting the use.
  • the second insulating layer 5 is provided on the upper surfaces of the gate tracking layer 4 and the first insulating layer 3.
  • the second insulating layer 5 is organic, and its material includes polymethyl methacrylate.
  • the thickness of the first insulating layer 3 is smaller than the thickness of the second insulating layer 5, so that the array substrate has the characteristics of a flexible narrow frame.
  • the thickness of the second insulating layer 5 is between 5um and 7um.
  • the active layer 6, the source drain layer 7 and the data line layer 8 are all provided on the upper surface of the second insulating layer 5.
  • the source-drain layer 7 may be a molybdenum-copper structure or a molybdenum-aluminum-molybdenum structure, which can avoid undercutting of the source and drain during subsequent processing.
  • the data line layer 8 is connected to the source and drain layers, and the active layer 6 is located between two adjacent source and drain layers 7.
  • FIG. 10 it is a plan view of the array substrate of this embodiment. It can be seen from the figure that the gate layer 2 and the gate tracking layer 5 are connected through a through hole 100. Specifically, the gate layer 2 is a gate trace, and the gate tracking layer 5 is a gate trace. One end of the gate trace line is connected to the gate trace through a through hole, and the other end is connected to the IC circuit in the non-display area. Among them, the gate tracking layer is arranged in the display area to reduce the wiring space in the non-display area, so that the display panel can achieve the effect of a narrow frame, ensure the performance of the circuit, and improve the quality of the display panel.
  • the array substrate may also include other devices or functional layers such as anode wiring, pixel definition layer, etc.
  • the improvement of the array substrate of the present invention is that the gate tracking layer is arranged in the display area and directly It is connected to the gate layer through a through hole. Therefore, for other devices or functional layers such as anode wiring and pixel definition layer, reference can be made to the prior art, which will not be repeated here.

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Abstract

一种阵列基板及其制备方法，所述阵列基板包括基板（1）、栅极层（2）、第一绝缘层（3）、栅极追踪层（4）以及第二绝缘层（5）；所述阵列基板的制备方法包括基板设置步骤（S1）、栅极层制备步骤（S2）、第一绝缘层制备步骤（S3）、栅极追踪层制备步骤（S4）以及第二绝缘层制备步骤（S5）。

Description

一种阵列基板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
 背景技术
目前，窄边框甚至无边框屏成为当期市场小尺寸手机的主流方向，为了尽可能的增大屏占比，实现手机屏的窄边框甚至无边框化，需要将左右边沿以及上下边沿区域尽可能缩小。
GOA技术（Gate Driver on Array）即阵列基板行驱动技术，是运用液晶显示面板的原有阵列制程将水平扫描线的驱动电路制作在显示区周围的基板上，使之能替代外接集成电路板（Integrated Circuit，IC）来完成水平扫描线的驱动。GOA技术能减少外接IC的焊接（bonding)工序，有机会提升产能并降低产品成本。
现有技术中，为了制作窄边框或无边框的显示产品，通常是通过压缩GOA电路的空间以实现显示区域左右两边的窄边框化，然而，该做法对GOA电路的性能以及液晶显示面板整体的抗静电能力造成不利影响。
现有技术中，提出了一种TGP（tracking gate line in pixel）显示面板，该显示面板主要是由一阵列基板、一彩膜基板以及一夹于阵列基板与彩膜基板之间的液晶层所构成，其中阵列基板可分为显示区（display region）与非显示区（non-display region），其中在显示区上配置有以阵列排列的多个像素单元，而每一像素单元包括薄膜晶体管以及与薄膜晶体管连接的像素电极（pixel electrode）。
现有技术中，阵列基板依次包括基板、栅极层、第一绝缘层、栅极追踪层以及第二绝缘层，其中，栅极追踪层设于非显示区内。阵列基板的制备方法包括如下步骤，在一基板上制备一栅极层；在所述栅极层上表面制备一第一绝缘层；在所述第一绝缘层上表面沉积金属材料，形成一栅极追踪层；在所述栅极追踪层上表面涂覆光阻溶液，形成光阻层；采用掩膜板对所述光阻层进行曝光、显影处理后，形成图案化的所述光阻层；对所述基板进行刻蚀处理，使得图案化的所述光阻层与所述第一绝缘层在同一位置被刻蚀，形成通孔，达到所述栅极层暴露的目的；以及去除所述光阻层。后续步骤中，该通孔可能被导体层（如ITO层）沉积，使得导体层连接至栅极层，进而使得栅极层通过导体层连接至栅极追踪层。现有技术中，阵列基板的制备工艺较复杂，生产成本高，当该阵列基板与其他部件共同构成显示面板时，由于阵列基板上的数据线或栅极线从显示面板的边缘到显示区域的距离较远，线宽较窄，导致经常会发生short（短路）或open（断路）等不良，另外传统设计对panel边缘处的空间较大，与实现窄边框的显示面板存在冲突。
 技术问题
本发明的目的在于，提供一种阵列基板及其制备方法，以解决现有技术中存在的GOA电路空间被压缩实现显示面板窄边框会引起显示面板的抗静电能力不佳，以及现有技术中制备阵列基板的工艺复杂、生产成本高的技术问题。
 技术解决方案
为了实现上述目的，本发明提供一种阵列基板包括基板、栅极层、第一绝缘层、栅极追踪层以及第二绝缘层；栅极层，贴附于所述基板一侧的表面；所述第一绝缘层贴附于所述栅极层及所述基板一侧的表面；所述第一绝缘层设有通孔；
所述栅极追踪层贴附于所述第一绝缘层远离所述基板一侧的表面，填充所述通孔，且连接至所述栅极层；所述第二绝缘层设于所述栅极追踪层及所述第一绝缘层远离所述基板一侧的表面。
进一步地，所述第一绝缘层为无机物，其材质包括钽氧化物和/或铝锆氧化物；所述第二绝缘层为有机物，其材质包括聚甲基丙烯酸甲酯。
进一步地，所述阵列基板还包括有源层、源漏极层以及数据线层，设于所述第二绝缘层远离所述基板一侧的表面；所述源漏极层设于所述第二绝缘层远离所述基板一侧的表面；所述数据线层设于所述第二绝缘层远离所述基板一侧的表面，且连接至所述源漏极层；其中，所述有源层位于相邻的两个源漏极层之间。
为实现上述目的，本发明还提供一种阵列基板制备方法，包括如下步骤，基板设置步骤，设置一基板；栅极层制备步骤，在所述基板上表面制备一栅极层；第一绝缘层制备步骤，在所述栅极层及所述基板上表面制备一第一绝缘层，使得所述第一绝缘层设有通孔；栅极追踪层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成一栅极追踪层，填充所述通孔，且连接至所述栅极层；以及第二绝缘层制备步骤，在所述第一绝缘层、所述栅极追踪层上表面制备一第二绝缘层。
进一步地，所述栅极层制备步骤包括如下步骤，第一金属层制备步骤，在所述基板上表面沉积金属材料，形成第一金属膜层；第一光阻层制备步骤，在所述第一金属层上表面涂覆光阻溶液，形成第一光阻层；第一曝光步骤，对所述第一光阻层进行曝光处理；第一显影步骤，对所述第一光阻层进行显影处理，形成图案化的所述第一光阻层；第一湿蚀刻步骤，对所述基板进行湿蚀刻处理，形成图案化的所述栅极层；以及第一去除步骤，去除所述第一光阻层。
进一步地，所述第一绝缘层制备步骤包括如下步骤第二光阻层制备步骤，在所述栅极层上表面涂覆光阻溶液，形成第二光阻层；第二曝光步骤，对所述第二光阻层进行曝光处理；第二显影步骤，对所述第二光阻层进行显影处理，形成图案化的所述第二光阻层；沉积步骤，在所述第二光阻层上表面沉积无机材料，形成所述第一绝缘层；以及第二去除步骤，去除图案化的所述第二光阻层与该位置相对应的所述第一绝缘层，形成所述通孔；其中，所述第一绝缘层的厚度小于所述第二光阻层的厚度。
进一步地，所述栅极追踪层制备步骤包括如下步骤，第二金属层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成第二金属膜层；第三光阻层制备步骤，在所述第二金属膜层上表面涂覆光阻溶液，形成第三光阻层；第三曝光步骤，对所述第三光阻层进行曝光处理；第三显影步骤，对所述第三光阻层进行显影处理，形成图案化的所述第三光阻层；第二湿刻蚀步骤，对所述基板进行湿刻蚀处理形成图案化的所述栅极追踪层；以及第三去除步骤，去除图案化的所述第三光阻层。
进一步地，在所述第二绝缘层制备步骤之后，还包括如下步骤，有源层制备步骤，在所述第二绝缘层上表面制备一有源层。
进一步地，在所述第二绝缘层制备步骤之后，还包括如下步骤，源漏极层制备步骤，在所述第二绝缘层上表面制备一源漏极层，所述有源层位于相邻的两个源漏极层之间
进一步地，在所述第二绝缘层制备步骤之后，还包括如下步骤，数据线层制备步骤，在所述第二绝缘层上表面制备一数据线层。
 有益效果
本发明的技术效果在于，提供一种阵列基板及其制备方法，栅极追踪层的一端通过一通孔直接连接至栅极层，另一端连接至非显示区的IC电路，其中，栅极追踪层设于显示区内，减少非显示区的走线空间，使得显示面板实现窄边框的效果，另外，栅极追踪层与栅极层接触时，可以降低所述栅极追踪层与所述栅极层之间的接触电阻，且阵列基板的制备工艺简单。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本实施例所述阵列基板制备方法的流程图；
图2为本实施例所述栅极层制备步骤的流程图；
图3为本实施例所述第一绝缘层制备步骤的流程图；
图4为本实施例制备第一绝缘层的截面图；
图5为本实施例所述栅极追踪层制备步骤的流程图；
图6为本实施例制备栅极追踪层的截面图；
图7为本实施例制备第二绝缘层的截面图；
图8为本实施例一种所述阵列基板的截面图；
图9为本实施例另一种所述阵列基板的截面图；
图10为实施例所述阵列基板的平面图。
附图中部分标识如下：
1基板；                    2栅极层；
3第一绝缘层；              4栅极层追踪层；
5第二绝缘层；              6有源层；
7源漏极层；                8数据线层；
100通孔。
 本发明的实施方式
以下参考说明书附图介绍本发明的优选实施例，用以举例证明本发明可以实施，这些实施例可以向本领域中的技术人员完整介绍本发明的技术内容，使得本发明的技术内容更加清楚和便于理解。然而本发明可以通过许多不同形式的实施例来得以体现，本发明的保护范围并非仅限于文中提到的实施例。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
如图1所示，本实施例提供一种阵列基板的制备方法，包括如下步骤S1~S8。S1基板设置步骤，设置一现有技术中常用的玻璃基板。
S2栅极层制备步骤，在所述基板上表面制备一栅极层，所述栅极层贴附于所述基板的部分上表面。如图2所示，S2栅极层制备步骤包括如下步骤S21~S26。S21第一金属层制备步骤，在所述基板上表面沉积金属材料，形成第一金属膜层，该第一金属膜层的结构可以为钼铜结构或者钼铝钼结构，这些结构可以避免栅极在后续加工的过程中发生底切现象。S22第一光阻层制备步骤，用户使用第一掩膜板在所述第一金属层上表面涂覆光阻溶液，形成第一光阻层。S23第一曝光步骤，在UV光照的条件下，对所述第一光阻层进行曝光处理。S24第一显影步骤，采用显影液对所述第一光阻层进行显影处理，形成图案化的所述第一光阻层。S25第一湿蚀刻步骤，对所述基板进行湿蚀刻处理，形成图案化的所述栅极层。S26第一去除步骤，去除所述第一光阻层。
如图3~4所示，S3第一绝缘层制备步骤，在栅极层2及基板1上表面制备一第一绝缘层3，使得第一绝缘层3设有通孔100。第一绝缘层3的厚度在0.8um~1.2um之间。S3第一绝缘层制备步骤包括如下步骤S31~S35。S31第二光阻层制备步骤，采用第二掩膜板在栅极层2上表面涂覆光阻溶液，形成第二光阻层（图未示）。所述第一绝缘层为无机物，其材质包括钽氧化物与铝锆氧化物中的一种或两种，所述第二光阻层的厚度大于1000A。S32第二曝光步骤，在UV光的照射下，对所述第二光阻层进行曝光处理。S33第二显影步骤，用户采用显影液对所述第二光阻层进行显影处理，形成图案化的所述第二光阻层。S34沉积步骤，在所述第二光阻层上表面沉积无机材料，形成第一绝缘层3，第一绝缘层3的厚度大于500A。S35第二去除步骤，用户在去除图案化的所述第二光阻层的同时，也去除与该位置相对应的第一绝缘层3，进而在该位置形成通孔100。
本实施例中，所述第一绝缘层的厚度小于所述第二光阻层的厚度。优选地，所述第二光阻层的厚度为所述第一绝缘层的厚度的3倍以上，以确保在所述第二光阻层沉积所述第一绝缘层的过程中，所述第一绝缘层与图案化的所述第二光阻层接触的位置发生断裂的现象，无需对所述第一绝缘层进行蚀刻处理，使得所述第一绝缘层设有通孔。现有技术中，一般采用干刻蚀方法对所述第一绝缘层进行蚀刻处理，使得所述第一绝缘层设有通孔，在此干刻蚀过程中，等离子容易对所述第一绝缘层下表面的栅极层的表面造成损伤，使得形成的通孔处的金属与栅极层接触时，容易导致接触电阻增加。
如图5~6所示，S4栅极追踪层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成一栅极追踪层4，填充所述通孔，且连接至栅极层2。S4栅极追踪层制备步骤包括如下步骤S41~S46。S41第二金属层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成第二金属膜层（图未示）。S42第三光阻层制备步骤，采用第三掩膜板在所述第二金属膜层上表面涂覆光阻溶液，形成第三光阻层。S43第三曝光步骤，对所述第三光阻层进行曝光处理。S44第三显影步骤，用户采用显影液对所述第三光阻层进行显影处理，形成图案化的所述第三光阻层。S45第二湿刻蚀步骤，对所述基板进行湿刻蚀处理，形成图案化的栅极追踪层4。S46第三去除步骤，去除图案化的所述第三光阻层。栅极追踪4层覆于第一绝缘层3的上表面，填充所述通孔，且连接至栅极层2。栅极追踪层4与栅极层2接触，可以降低栅极追层4与栅极层2之间的接触电阻。与现有技术相比，栅极追踪层设于显示区内，其一端直接连接至栅极层，其另一端连接至非显示区的IC电路，可以减少非显示区的走线空间，使得显示面板实现窄边框的效果。
如图7所示，S5第二绝缘层制备步骤，在第一绝缘层3、栅极追踪层4上表面制备一第二绝缘层5。第二绝缘层5为有机物，其材质包括聚甲基丙烯酸甲酯，富有弹性，具有良好密封功能。第二绝缘层5的厚度在5um~7um之间。
如图8所示，S6有源层制备步骤，在第二绝缘层5上表面制备一有源层6。所述有源层为有机半导体并五苯（Pentacene），具有良好的柔韧性。
S7源漏极层制备步骤，参照图8，在第二绝缘层5上表面制备一源漏极层7，有源层6位于相邻的两个源漏极层7之间。源漏极层7的结构可以为钼铜结构或者钼铝钼结构，这些结构可以避免源漏极在后续加工的过程中发生底切现象。
S8数据线层制备步骤，参照图8，在第二绝缘层5上表面制备一数据线层8。
前文所述的有源层制备步骤、源漏极层制备步骤及数据线层制备步骤的执行顺序可调换，本实施不做具体的限定。
本实施例提供一种阵列基板的制备方法，在相邻的两个绝缘层之间设置栅极追踪层，该栅极追踪层设于显示区内，其一端直接连接至栅极层，其另一端连接至非显示区的IC电路。与现有技术相比，栅极追踪层设于显示区内，可以减少非显示区的走线空间，使得显示面板实现窄边框的效果。另外，栅极追踪层通过一通孔与栅极层接触，降低栅极追层与所述栅极层之间的接触电阻，通过绝缘层使得栅极层与源漏极层与数据线层达到隔离效果，同时保证了栅极层的绝缘效果。本实施例中的所述第一绝缘层的厚度小于所述第二绝缘层的厚度，使得阵列基板具有柔性窄边框的特点。
本实施例还提供一种阵列基板，参照图8，所述阵列基板包括基板1、栅极层2、第一绝缘层3、栅极追踪层4、第二绝缘层4、有源层6、源漏极层7以及数据线层9。
栅极层2贴附于基板1的上表面，栅极层2的结构为钼铜结构或钼铝钼结构，这些结构可以避免栅极层2在后续加工的过程中发生底切现象。
第一绝缘层3贴附于栅极层2及基板1的上表面；第一绝缘层3设有通孔100。第一绝缘层3为无机物，其材质包括钽氧化物与铝锆氧化物中的一种或两种。第一绝缘层3的厚度在0.8um~1.2um之间。
栅极追踪层4贴附于第一绝缘层3的上表面，填充通孔100，且连接至栅极层2。通孔100底部的孔径小于其顶部的孔径，通孔的母线与竖直方向的直线在40°~70°之间，防止栅极追踪层4与栅极层2连接时出现底切现象。栅极追踪层4曲折排布，如呈S形、Z形等，目的是为了保证栅极追踪层4与栅极层2稳固连接，防止栅极追踪层4被剥落。
如图9所示，在另一实施例中，当第一绝缘层3设有多个通孔100时，可以增加栅极追踪层4与栅极层2之间的接触面积，进而增强栅极追踪层4与栅极层2连接的紧密性。当某一通孔100处的栅极追踪层4与栅极层2接触不良时，可以通过其他通孔100实现电连接功能，不影响使用。
第二绝缘层5设于栅极追踪层4及第一绝缘层3的上表面。第二绝缘层5为有机物，其材质包括聚甲基丙烯酸甲酯。另外，第一绝缘层3的厚度小于第二绝缘层5的厚度，使得阵列基板具有柔性窄边框的特点。第二绝缘层5的厚度在5um~7um之间。
有源层6、源漏极层7以及数据线层8都设于第二绝缘层5的上表面。源漏极层7可以为钼铜结构或者钼铝钼结构，这些结构可以避免源漏极在后续加工的过程中发生底切现象。数据线层8连接至所述源漏极层，有源层6位于相邻的两个源漏极层7之间。
如图10所示，为本实施所述阵列基板的平面图，从图中可以看出栅极层2与栅极追踪层5通过通孔100进行连接的。具体地，栅极层2为栅极走线，栅极追踪层5为栅极追踪线。栅极追踪线的一端通过一通孔之间连接至栅极走线，另一端连接至非显示区的IC电路。其中，栅极追踪层设于显示区内，减少非显示区的走线空间，使得显示面板实现窄边框的效果，保证电路的性能，提高显示面板的质量。
本实施例中，所述阵列基板还可以包括如阳极走线、像素定义层等其他的器件或功能层，而本发明的阵列基板的改进点在于栅极追踪层设于显示区内，并直接通过一通孔连接至栅极层，因此，对于阳极走线、像素定义层等其他的器件或功能层可以参照现有技术，对此不在一一赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种阵列基板，其包括：
    基板；
    栅极层，贴附于所述基板一侧的表面；
    第一绝缘层，贴附于所述栅极层及所述基板一侧的表面；所述第一绝缘层设有通孔；
    栅极追踪层，贴附于所述第一绝缘层远离所述基板一侧的表面，填充所述通孔，且连接至所述栅极层；以及
    第二绝缘层，设于所述栅极追踪层及所述第一绝缘层远离所述基板一侧的表面。
  2. 如权利要求1所述的阵列基板，其中，
    所述第一绝缘层为无机物，其材质包括钽氧化物和/或铝锆氧化物；
    所述第二绝缘层为有机物，其材质包括聚甲基丙烯酸甲酯。
  3. 如权利要求1所述的阵列基板，其中，还包括
    有源层，设于所述第二绝缘层远离所述基板一侧的表面；
    源漏极层，设于所述第二绝缘层远离所述基板一侧的表面；以及
    数据线层，设于所述第二绝缘层远离所述基板一侧的表面，且连接至所述源漏极层；
    其中，所述有源层位于相邻的两个源漏极层之间。
  4. 一种阵列基板的制备方法，其中，包括如下步骤：
    基板设置步骤，设置一基板；
    栅极层制备步骤，在所述基板上表面制备一栅极层；
    第一绝缘层制备步骤，在所述栅极层及所述基板上表面制备一第一绝缘层，使得所述第一绝缘层设有通孔；
    栅极追踪层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成一栅极追踪层，填充所述通孔，且连接至所述栅极层；以及
    第二绝缘层制备步骤，在所述第一绝缘层、所述栅极追踪层上表面制备一第二绝缘层。
  5. 如权利要求4所述的阵列基板的制备方法，其中，
    所述栅极层制备步骤包括如下步骤：
    第一金属层制备步骤，在所述基板上表面沉积金属材料，形成第一金属膜层；
    第一光阻层制备步骤，在所述第一金属层上表面涂覆光阻溶液，形成第一光阻层；
    第一曝光步骤，对所述第一光阻层进行曝光处理；
    第一显影步骤，对所述第一光阻层进行显影处理，形成图案化的所述第一光阻层；
    第一湿蚀刻步骤，对所述基板进行湿蚀刻处理，形成图案化的所述栅极层；以及
    第一去除步骤，去除所述第一光阻层。
  6. 如权利要求4所述的阵列基板的制备方法，其中，
    所述第一绝缘层制备步骤包括如下步骤：
    第二光阻层制备步骤，在所述栅极层上表面涂覆光阻溶液，形成第二光阻层；
    第二曝光步骤，对所述第二光阻层进行曝光处理；
    第二显影步骤，对所述第二光阻层进行显影处理，形成图案化的所述第二光阻层；
    沉积步骤，在所述第二光阻层上表面沉积无机材料，形成所述第一绝缘层；以及
    第二去除步骤，去除图案化的所述第二光阻层与该位置相对应的所述第一绝缘层，形成所述通孔；
    其中，所述第一绝缘层的厚度小于所述第二光阻层的厚度。
  7. 如权利要求4所述的阵列基板的制备方法，其中，
    所述栅极追踪层制备步骤包括如下步骤：
    第二金属层制备步骤，在所述第一绝缘层上表面沉积金属材料，形成第二金属膜层；
    第三光阻层制备步骤，在所述第二金属膜层上表面涂覆光阻溶液，形成第三光阻层；
    第三曝光步骤，对所述第三光阻层进行曝光处理；
    第三显影步骤，对所述第三光阻层进行显影处理，形成图案化的所述第三光阻层；
    第二湿刻蚀步骤，对所述基板进行湿刻蚀处理形成图案化的所述栅极追踪层；以及
    第三去除步骤，去除图案化的所述第三光阻层。
  8. 如权利要求4所述的阵列基板的制备方法，其中，
    在所述第二绝缘层制备步骤之后，还包括如下步骤：
    有源层制备步骤，在所述第二绝缘层上表面制备一有源层。
  9. 如权利要求4所述的阵列基板的制备方法，其中，
    在所述第二绝缘层制备步骤之后，还包括如下步骤：
    源漏极层制备步骤，在所述第二绝缘层上表面制备一源漏极层，所述有源层位于相邻的两个源漏极层之间。
  10. 如权利要求4所述的阵列基板的制备方法，其中，
    在所述第二绝缘层制备步骤之后，还包括如下步骤：
    数据线层制备步骤，在所述第二绝缘层上表面制备一数据线层。
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