WO2014190657A1 - 像素单元及其制备方法、阵列基板、显示装置 - Google Patents
像素单元及其制备方法、阵列基板、显示装置 Download PDFInfo
- Publication number
- WO2014190657A1 WO2014190657A1 PCT/CN2013/085280 CN2013085280W WO2014190657A1 WO 2014190657 A1 WO2014190657 A1 WO 2014190657A1 CN 2013085280 W CN2013085280 W CN 2013085280W WO 2014190657 A1 WO2014190657 A1 WO 2014190657A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- storage capacitor
- layer
- layer structure
- insulating layer
- thin film
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000003990 capacitor Substances 0.000 claims abstract description 152
- 238000003860 storage Methods 0.000 claims abstract description 150
- 239000010409 thin film Substances 0.000 claims description 73
- 238000000034 method Methods 0.000 claims description 44
- 229910044991 metal oxide Inorganic materials 0.000 claims description 29
- 150000004706 metal oxides Chemical group 0.000 claims description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims description 28
- 238000000059 patterning Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 230000000149 penetrating effect Effects 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 13
- 238000007772 electroless plating Methods 0.000 claims description 10
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- 229910052750 molybdenum Inorganic materials 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 223
- 238000010586 diagram Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 4
- 239000007769 metal material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 2
- 239000008139 complexing agent Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 235000002906 tartaric acid Nutrition 0.000 description 2
- 239000011975 tartaric acid Substances 0.000 description 2
- VMHLLURERBWHNL-UHFFFAOYSA-M Sodium acetate Chemical compound [Na+].CC([O-])=O VMHLLURERBWHNL-UHFFFAOYSA-M 0.000 description 1
- 239000006172 buffering agent Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- -1 molybdenum ions Chemical class 0.000 description 1
- 239000003002 pH adjusting agent Substances 0.000 description 1
- 235000017281 sodium acetate Nutrition 0.000 description 1
- 239000001632 sodium acetate Substances 0.000 description 1
- 229910052979 sodium sulfide Inorganic materials 0.000 description 1
- GRVFOGOEDUUMBP-UHFFFAOYSA-N sodium sulfide (anhydrous) Chemical compound [Na+].[Na+].[S-2] GRVFOGOEDUUMBP-UHFFFAOYSA-N 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
Definitions
- Pixel unit and preparation method thereof array substrate, display device
- Embodiments of the present invention relate to a liquid crystal display device, and in particular to a pixel unit, a method of fabricating the same, an array substrate, and a display device. Background technique
- the aperture ratio of the liquid crystal display device is defined as the ratio of the area of the light transmissive portion of the pixel unit to the total area of the pixel unit (including the area of the opaque portion).
- the area of the opaque portion must be reduced as much as possible; at the same time, the total area of the pixel unit must be minimized to ensure the highest possible resolution.
- the opaque portion is mainly a thin film transistor (TFT), a gate signal line, a data line, a storage capacitor (Cs), and a black matrix material, and the sum of the areas of these portions determines the aperture ratio of one pixel.
- TFT thin film transistor
- Cs storage capacitor
- one end of the pixel is used as a storage capacitor electrode, wherein the pixel electrode material is a transparent metal oxide such as ITO (indium tin oxide), and the other end is made of an opaque metal material as the other electrode of the storage capacitor.
- the storage capacitor has a two-layer structure, and the relative area of the two layers determines the capacitance of the storage capacitor; wherein, the ITO pixel electrode can transmit light, and the metal material is opaque.
- the technical problem to be solved by the present invention is to provide a pixel unit with a reduced storage area and a high aperture ratio, and a method for fabricating the same, in which the area of the storage capacitor of the existing pixel unit is large and the aperture ratio is lowered.
- a pixel unit including a storage capacitor, wherein the storage capacitor includes a first electrode and a second electrode; and the first electrode includes a plurality of layer structures electrically connected to each other, The second electrode includes a plurality of layer structures electrically connected to each other, and a layer structure of the first electrode and the second electrode are alternately disposed in different layers, the plurality of layer structures of the first electrode and the The plurality of layer structures of the second electrode at least partially overlap, and the number of layers of the layer structure of the first electrode and the second electrode are the same; the topmost structure of the storage capacitor in a direction away from the substrate is a pixel electrode of the pixel unit .
- the storage capacitor includes a first layer structure, a second layer structure, a third layer structure, and a fourth layer structure in a direction away from the substrate.
- the fourth layer structure of the storage capacitor is a pixel unit.
- the pixel electrode is electrically connected to the second layer structure of the storage capacitor to form a first electrode of the storage capacitor; the first layer structure of the storage capacitor is electrically connected to the third layer structure to form a second electrode of the storage capacitor.
- the pixel unit further includes a thin film transistor of a top gate structure, the active region of the thin film transistor and the first layer structure of the storage capacitor are disposed in the same layer, and the first insulating layer covers the active of the thin film transistor a first layer structure of the region and the storage capacitor; a second layer structure of the gate and the storage capacitor of the thin film transistor is disposed on the first insulating layer, and the second insulating layer covers the gate of the thin film transistor and the second layer of the storage capacitor a third layer structure of a source, a drain, and a storage capacitor of the thin film transistor is disposed on the second insulating layer, and a third insulating layer covers a source, a drain, and a third layer structure of the storage capacitor of the thin film transistor,
- the first layer structure and the third layer structure of the storage capacitor are electrically connected through a via hole penetrating through the first insulating layer and the second insulating layer; the pixel electrode is disposed on the third insulating layer, wherein the The
- the material of the active region of the thin film transistor is a metal oxide semiconductor.
- the first layer structure of the storage capacitor includes a metal oxide semiconductor layer formed in synchronization with an active region of a thin film transistor, and the metal oxide semiconductor layer of the first layer structure is provided with a metal layer.
- the metal layer is made of at least one of molybdenum, copper, aluminum, and tungsten.
- a method of fabricating the above pixel unit includes the steps of: sequentially forming a pattern of respective layer structures including storage capacitors on a substrate by a patterning process.
- the storage capacitor is a four-layer storage capacitor
- the method for fabricating the pixel unit includes the following steps: forming a first layer structure of a storage capacitor on a substrate; forming a first on the substrate completing the above steps An insulating layer; formed on the first insulating layer by a patterning process including storage a pattern of a second layer structure of the capacitor; forming a second insulating layer on the substrate on which the above steps are performed, and forming a through-first insulating layer in a portion of the first layer structure of the storage capacitor that does not overlap with the second layer structure by a patterning process And a first via hole of the second insulating layer; forming a pattern of the third layer structure including the storage capacitor by a patterning process on the substrate completing the above steps, and the third layer structure of the storage capacitor passes through the first insulating layer and the second layer a first via of the insulating layer is connected to the first layer structure of the storage capacitor; a third insulating layer is formed on the substrate
- the pixel unit further includes a thin film transistor of a top gate structure
- the method for fabricating the pixel unit includes the steps of: forming a first layer structure of a storage capacitor on a substrate while forming an active region of the thin film transistor; Forming a first insulating layer on the substrate on which the above steps are completed, and forming a pattern of a second layer structure including a storage capacitor and a gate of the thin film transistor on the first insulating layer by a patterning process; forming a surface on the substrate on which the above steps are completed a second insulating layer through which a first via hole penetrating the first insulating layer and the second insulating layer is formed in a portion of the first layer structure of the storage capacitor that does not overlap with the second layer structure, and a source of the thin film transistor a drain via forming a third via and a fourth via extending through the first insulating layer and the second insulating layer; forming a third layer structure including a storage capacitor and a thin film transistor
- the forming a first layer structure of a storage capacitor on a substrate while forming an active region of the thin film transistor includes the steps of: preparing a metal oxide semiconductor material layer on the substrate, and the metal oxide semiconductor material Coating a photoresist layer on the layer, exposing and developing the photoresist, wherein the remaining photoresist in the active region has a thickness greater than a thickness of the photoresist in the storage capacitor region, and The photoresist of the active region is spaced apart from the photoresist of the storage capacitor region; the exposed metal oxide semiconductor material layer is removed by etching; the remaining thickness of the storage capacitor region is removed by etching; by electroless plating The process forms a metal layer on the metal oxide semiconductor layer of the first layer structure of the storage capacitor; stripping removes the remaining photoresist.
- the metal layer is made of at least one of molybdenum, copper, aluminum, and tungsten.
- the exposing the photoresist comprises: exposing the photoresist through a halftone mask or a gray scale mask.
- an array substrate includes the above pixel unit.
- a display device includes the above array substrate.
- FIG. 1 is a schematic structural diagram of a pixel unit according to Embodiment 2 of the present invention.
- FIG. 2a is a schematic diagram showing a first layer structure step 1011 of forming a storage capacitor of a pixel unit according to Embodiment 4 of the present invention
- 2b is a first layer structural step of forming a storage capacitor of a pixel unit according to Embodiment 4 of the present invention
- FIG. 2c is a schematic diagram showing a first layer structure step 1013 of forming a storage capacitor of a pixel unit according to Embodiment 4 of the present invention
- FIG. 2d is a schematic diagram showing a first layer structure step 1014 of forming a storage capacitor of a pixel unit according to Embodiment 4 of the present invention
- FIG. 2e is a schematic diagram showing a first layer structure step 1015 of forming a storage capacitor of a pixel unit according to Embodiment 4 of the present invention
- FIG. 3 is a schematic structural diagram of a pixel unit after completing step 102 in the method for fabricating a pixel unit according to Embodiment 4 of the present invention
- FIG. 4 is a schematic structural view of a pixel unit after the completion of step 104 in the method of fabricating a pixel unit according to Embodiment 4 of the present invention.
- the reference numerals are: 101, a substrate; 102, a first layer structure of a storage capacitor; 103, an active region; 104, a metal oxide semiconductor film layer; 105, a photoresist; 201, a first insulating layer; a second layer structure of the storage capacitor; 203, a gate; 301, a second insulating layer; 302, a third layer structure of the storage capacitor; 303, a source; 304, a drain; 3051, a first via; Two vias; 3053, a third via hole; 3054, a fourth via hole; 3055, a fifth via hole; 401, a third insulating layer; 402, a fourth layer structure of the storage capacitor (pixel electrode).
- the embodiment provides a pixel unit, including a storage capacitor, the storage capacitor includes a first electrode and a second electrode; the first electrode includes a plurality of layer structures electrically connected to each other, and the second electrode includes electrical connections with each other a plurality of layer structures, the layer structures of the two electrodes are alternately disposed in different layers, all the layer structures at least partially overlap, and the number of layers of the structure of the first electrode and the second electrode are equal; the storage capacitor is in a direction away from the substrate
- the topmost structure is the pixel electrode of the pixel unit.
- the first electrode and the second electrode of the storage capacitor of the pixel unit of the present embodiment each include a multi-layer structure, so that it is smaller than the area of the existing storage capacitor, and the aperture ratio can be effectively improved.
- the embodiment provides a pixel unit including a capacitor of a four-layer structure and a thin film transistor of a top gate structure.
- the active region 103 of the thin film transistor and the first layer structure 102 of the storage capacitor are disposed in the same layer (ie, a layer directly disposed on the substrate), and the first insulating layer 201 covers the active region 103 of the thin film transistor and A first layer structure 102 of storage capacitors.
- the second layer structure 202 of the gate electrode 203 and the storage capacitor of the thin film transistor is disposed on the first insulating layer 201, and the second insulating layer 301 covers the gate electrode 203 of the thin film transistor and the second layer structure 202 of the storage capacitor.
- the source 303, the drain 304 and the third layer structure 302 of the storage capacitor are disposed on the second insulating layer 301.
- the third insulating layer 401 covers the source 303, the drain 304 and the storage capacitor of the thin film transistor.
- the first layer structure 102 and the third layer structure 302 of the storage capacitor are electrically connected by a first via 3051 extending through the first insulating layer 201 and the second insulating layer 301, and the source 303 and the drain 304 of the thin film transistor are
- the active region 103 of the thin film transistor is connected through a third via 3053 and a fourth via 3054 extending through the first insulating layer 201 and the second insulating layer 301, respectively.
- the pixel electrode 402 is disposed on the third insulating layer 401, wherein the second layer structure 202 of the pixel electrode 402 and the storage capacitor is electrically connected through the second via 3052 of the second insulating layer 301 and the third insulating layer 401.
- the pixel electrode 402 is electrically connected to the drain electrode 304 of the thin film transistor through the fifth via hole 3055 of the third insulating layer 401 extending over the drain electrode 304 of the thin film transistor.
- the first layer structure 102 of the storage capacitor is disposed in the same layer as the active region 103 of the thin film transistor
- the second layer structure 202 and the gate electrode 203 of the thin film transistor are disposed in the same layer
- the third layer structure 302 and the thin film transistor The source 303 and the drain 304 are disposed on the same layer, so that each layer structure of the thin film transistor can be formed by one patterning process at the time of fabrication, that is, the process step can be omitted, and the cost can be saved.
- each layer of the storage capacitor can also be in different layers from the structure of the thin film transistor, so that the layers of the thin film transistor and the storage capacitor need to be separately fabricated, but the storage capacitor is still larger than the existing storage capacitor. When it is reduced, the aperture ratio can also be effectively increased.
- the material of the active region 103 of the thin film transistor is a metal oxide semiconductor.
- the first layer structure 102 of the storage capacitor includes a metal oxide semiconductor layer formed in synchronization with the thin film transistor active region 103, and the metal oxide semiconductor layer of the first layer structure 102 is provided with a metal layer.
- the metal layer is made of at least one of molybdenum, copper, aluminum, and tungsten.
- the first layer structure 102 of the storage capacitor formed at the same time is also a metal oxide semiconductor material, so the first layer structure 102 is not electrically conductive and cannot be directly used as an electrode, so A metal layer for conducting is formed on the first layer structure 102.
- the pixel unit in this embodiment is only a storage capacitor including a four-layer structure and a top gate type thin film transistor.
- the storage capacitance of the pixel unit may also be a six-layer, eight-layer, and more layer structure (the number of layer structures is The storage capacitor of even number), the type of thin film transistor can also be other types (bottom gate type thin film transistor), as long as the total relative area of the two electrodes of the storage capacitor is constant (ie, the capacitance is constant).
- the area of the storage capacitor i.e., the area occupied on the substrate, that is, the area opaque
- the pixel unit of the structure is within the scope of the present invention.
- This embodiment provides a method for preparing a pixel unit for the pixel unit described in Embodiments 1 and 2, including the following steps: A pattern of a multilayer structure including a storage capacitor of the pixel unit is formed on the substrate.
- an insulating layer is formed on the layer structure, and an insulating layer covering the two layer structures is formed in a portion where the adjacent two layer structures are not overlapped.
- the hole is used for two odd-numbered layer electrical connections and two even-numbered layer electrical connections to form a first electrode and a second electrode of the storage capacitor, respectively, and the number of layers of the first electrode is the same as the number of layers of the second electrode.
- the pixel unit further includes a thin film transistor, and a thin film transistor is also formed while forming a storage capacitor of the pixel unit.
- this embodiment provides a method for preparing a pixel unit for the pixel unit of Embodiment 2, which includes the following steps:
- a first layer structure 102 of storage capacitors is formed on substrate 101 while forming active regions 103 of the thin film transistors, as shown in Figures 2a-2e.
- step 101 can include, for example:
- a pattern including an active layer and a first layer structure is separately formed on the substrate 101 by a patterning process using a metal oxide semiconductor material, for example, a metal oxide semiconductor film is first formed on the substrate 101.
- the layer 104 is formed on the metal oxide semiconductor film layer 104, and the photoresist 105 is exposed and developed, wherein the remaining photoresist 105 on the active region 103 has a thickness greater than that of the storage capacitor region.
- the thickness of the photoresist 105 is such that the photoresist 105 on the active region 103 is spaced apart from the photoresist 105 of the storage capacitor region.
- the exposing the photoresist 105 includes:
- the photoresist 105 is exposed through a halftone mask or a gray scale mask.
- step 1012 the exposed metal oxide semiconductor film layer 104 is removed by etching.
- step 1013 the remaining thickness of the photoresist 105 of the storage capacitor region is removed by etching.
- a metal layer is formed over the metal oxide semiconductor region of the first layer structure 102 of the storage capacitor by an electroless plating process.
- the electroless plating process is easy and low in cost; and since the complexing agent in the chemical liquid used in the electroless plating process of the present scheme is tartaric acid, it can modify the surface of the metal and the metal oxide without SiO The surface of SiN, etc. causes a change, so it will only be in the first layer structure 102 of the exposed storage capacitor.
- a metal layer is formed on the metal oxide semiconductor region (because the thin film transistor active region 103 is still covered by the photoresist at this time, a metal layer is not formed), so that there is no influence on the performance of the top gate thin film transistor.
- the metal layer is made of at least one of molybdenum, copper, aluminum, and tungsten.
- an electroless molybdenum plating solution is applied onto a substrate 101 having a structure as shown in FIG. 2c at a temperature between room temperature and 100 ° C, and the reaction is completed.
- the structure shown in Figure 2d is followed by washing, drying, and subsequent steps.
- the composition of the electroless plating liquid may include: 0.1-0.3 mol/L sulfuric acid phase; 0.05-0.15 mol/L sodium sulfide (stabilizer), which is used for ensuring the stability of molybdenum ions; 0.1 ⁇ lmol/L Sodium acetate (buffering agent); 0.1 ⁇ lmol/L of tartaric acid (complexing agent), which can be used to increase the polarity of phase ions, make the crystal of the obtained coating layer smooth and smooth, and at the same time stabilize the plating solution; water.
- stabilizer sodium sulfide
- buffering agent 0.1 ⁇ lmol/L of tartaric acid
- complexing agent complexing agent
- a metal layer directly by a patterning process without using an electroless plating process, so that it requires an additional patterning process, but its application range is wider, for example, it can be used for a bottom gate type thin film transistor, and is active.
- the material of the region may also not be a metal oxide semiconductor.
- step 1015 the remaining photoresist 105 is stripped and removed.
- a first insulating layer 201 is formed on the substrate 101 that completes the above steps, and a pattern including the thin film transistor gate is formed while forming a pattern of the second layer structure 202 of the storage capacitor on the first insulating layer 201 by a patterning process.
- the graph of 203 gives the structure shown in FIG.
- a second insulating layer 301 is formed on the substrate 101 that completes the above steps, and a first insulating layer 201 and a second insulating layer are formed on a portion of the first layer structure 102 and the second layer structure 202 where the storage capacitor does not overlap.
- the first via 3051 of the layer 301 forms a third via 3053 and a fourth via 3054 extending through the first insulating layer 201 and the second insulating layer 301 at the source and drain regions above the active region 103 of the thin film transistor. .
- step 104 while forming a pattern of the third layer structure 302 of the storage capacitor by the patterning process on the substrate 101 that completes the above steps, a pattern including the thin film transistor source 303 and the drain 304 is formed, and the source of the thin film transistor is formed.
- the drain 304 passes through the third via 3053 and the fourth pass respectively.
- the hole 3054 is connected to the thin film transistor active region 103 to obtain a structure as shown in FIG.
- step a third insulating layer 401 is formed on the substrate 101 that completes the above steps, and a second insulating layer 301 and a third insulating layer are formed over a portion where the third layer structure 302 of the storage capacitor and the second layer structure 202 are not overlapped. While the second via 3052 of the layer 401 is simultaneously formed, a fifth via 3055 penetrating through the third insulating layer 401 is formed on the thin film transistor drain 304, as shown in FIG.
- a pattern of a fourth layer structure 402 including a storage capacitor is formed by a patterning process on the substrate 101 that completes the above steps, and the fourth layer structure 402 of the storage capacitor passes through the second layer through the third insulating layer 401.
- the hole 3052 is connected to the drain 304 of the thin film transistor to obtain a structure as shown in FIG.
- the preparation method of the storage capacitor is also diverse (for example, may be 6 layers, 8 layers, etc.), and will not be described one by one, but as long as it can form a multilayer structure of storage capacitors (even layers)
- the structure is within the scope of protection of the present invention.
- This embodiment provides an array substrate including the above pixel unit.
- the array substrate of the present embodiment has the above-described pixel unit, its aperture ratio is high.
- This embodiment provides a display device including the array substrate described in Embodiment 5.
- the display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., any product or component having a display function.
- the display device of this embodiment has the array substrate of the embodiment 5, so that it has a better opening ratio, a better visual effect, and a better picture effect.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
一种像素单元及其制备方法、阵列基板、显示装置,可解决现有的两层结构的存储电容的占用面积大且开口率低的问题。像素单元包括存储电容,存储电容包括第一电极和第二电极;所述第一电极包括电连接的多个层结构(102,302),第二电极包括电连接的多个层结构(202,402),第一电极和第二电极的各层结构交替设置在不同层,第一电极的多个层结构(102,302)和第二电极的多个层结构(202,402)至少部分重叠,且第一电极与第二电极的结构的层结构的层数相同;存储电容在远离基底(101)的方向上的最顶层结构为像素单元的像素电极(402)。像素单元的电容为多层结构,减小了电容尺寸,提高了开口率。
Description
像素单元及其制备方法、 阵列基板、 显示装置 技术领域
本发明的实施例涉及液晶显示装置, 具体涉及一种像素单元及其制备方 法、 阵列基板、 显示装置。 背景技术
液晶显示装置的开口率(aperture )定义为像素单元可透光部分的面积与 像素单元总面积(包括不透光部分的面积) 的比值。 为了提高开口率, 必须 尽可能地减小不透光部分的面积; 同时, 还要保证像素单元总面积最小化, 以保证尽可能高的分辨率。
在一个像素单元中, 不透光的部分主要是薄膜晶体管 (TFT ) 、 栅极信 号线、 数据线、 存储电容(Cs ) 、 黑矩阵材料, 这些部分的面积的总和决定 一个像素的开口率。
在独立存储电容的设计中, 一端由像素电极充当存储电容电极, 其中像 素电极材料为透明金属氧化物, 如 ITO (氧化铟锡) , 另一端采用不透光金 属材料作为存储电容的另一电极, 即该存储电容为两层结构, 两层的相对面 积决定了存储电容的电容量; 其中, ITO像素电极可以透光, 而金属材料不 透光。
发明人发现现有技术中至少存在如下问题: 现有的两层结构的存储电容 中, 不透光金属材料电极的面积需要较大以保证存储电容两电极的相对面积 (从而保证电容量) , 这会对开口率造成一定程度的影响。 发明内容
本发明所要解决的技术问题包括, 针对现有的像素单元的存储电容的面 积较大从而导致开口率下降的问题, 提供一种存储电容面积减小并且开口率 高的像素单元及其制备方法、 阵列基板、 显示装置。
在一个示例中, 提供一种像素单元, 其包括存储电容, 其中, 所述存储 电容包括第一电极和第二电极;所述第一电极包括相互电连接的多个层结构,
所述第二电极包括相互电连接的多个层结构, 所述第一电极和所述第二电极 的层结构交替设置在不同层, 所述第一电极的所述多个层结构和所述第二电 极的所述多个层结构至少部分重叠, 且第一电极与第二电极的层结构的层数 相同; 所述存储电容在远离基底的方向上的最顶层结构为像素单元的像素电 极。
在一个示例中, 在远离基底的方向上, 所述存储电容依次包括第一层结 构、 第二层结构、 第三层结构、 第四层结构; 所述存储电容的第四层结构为 像素单元的像素电极, 且与存储电容的第二层结构电连接, 构成存储电容的 第一电极; 所述存储电容的第一层结构与第三层结构电连接, 构成存储电容 的第二电极。
在一个示例中, 所述像素单元还包括顶栅结构的薄膜晶体管, 所述薄膜 晶体管的有源区与存储电容的第一层结构设于同一层中, 第一绝缘层覆盖薄 膜晶体管的有源区与存储电容的第一层结构; 所述薄膜晶体管的栅极与存储 电容的第二层结构设于第一绝缘层上, 第二绝缘层覆盖薄膜晶体管的栅极与 存储电容的第二层结构; 所述薄膜晶体管的源极、 漏极以及存储电容的第三 层结构设于第二绝缘层上, 第三绝缘层覆盖薄膜晶体管的源极、 漏极以及存 储电容的第三层结构, 其中, 所述存储电容的第一层结构与第三层结构间通 过贯穿第一绝缘层和第二绝缘层中的过孔电连接; 所述像素电极设于第三绝 缘层上, 其中所述像素电极与存储电容的第二层结构间通过贯穿第二绝缘层 和第三绝缘层中的过孔电连接。
在一个示例中, 所述薄膜晶体管的有源区的材料为金属氧化物半导体。 在一个示例中, 所述存储电容的第一层结构包括与薄膜晶体管有源区同 步形成的金属氧化物半导体层, 所述第一层结构的金属氧化物半导体层上设 有金属层。
在一个示例中, 所述金属层由钼、 铜、 铝、 钨中的至少一种制成。 在一个示例中, 一种上述像素单元的制备方法包括如下步骤: 通过构图 工艺在基底上依次形成包括存储电容的各层结构的图形。
在一个示例中, 所述存储电容为四层结构的存储电容, 所述像素单元的 制备方法包括如下步骤: 在基底上形成存储电容的第一层结构; 在完成上述 步骤的基底上形成第一绝缘层; 通过构图工艺在第一绝缘层上形成包括存储
电容的第二层结构的图形; 在完成上述步骤的基底上形成第二绝缘层, 通过 构图工艺在存储电容的第一层结构的未与第二层结构重叠的部分中形成贯穿 第一绝缘层和第二绝缘层的第一过孔; 在完成上述步骤的基底上通过构图工 艺形成包括存储电容的第三层结构的图形, 且存储电容的第三层结构通过贯 穿第一绝缘层和第二绝缘层的第一过孔与存储电容的第一层结构连接; 在完 成上述步骤的基底上形成第三绝缘层, 通过构图工艺在存储电容的第二层结 构的未与第三层结构重叠的部分中形成贯穿第二绝缘层和第三绝缘层的第二 过孔; 在完成上述步骤的基底上通构图工艺形成包括存储电容的第四层结构 的图形, 且存储电容的第四层结构通过贯穿第二绝缘层和第三绝缘层的第二 过孔与存储电容的第二层结构连接。
在一个示例中, 所述像素单元还包括顶栅结构的薄膜晶体管, 所述像素 单元的制备方法包括如下步骤: 在基底上形成存储电容的第一层结构, 同时 形成薄膜晶体管的有源区; 在完成上述步骤的基底上形成第一绝缘层, 且通 过构图工艺在第一绝缘层上形成包括存储电容的第二层结构和薄膜晶体管的 栅极的图形; 在完成上述步骤的基底上形成第二绝缘层, 通过构图工艺在存 储电容的第一层结构的未与第二层结构未重叠的部分中形成贯穿第一绝缘层 和第二绝缘层的第一过孔, 同时在薄膜晶体管的源、 漏区形成贯穿第一绝缘 层和第二绝缘层的第三过孔和第四过孔; 在完成上述步骤的基底上通过构图 工艺形成包括存储电容的第三层结构和薄膜晶体管源极、 漏极的图形, 且所 述薄膜晶体管的源、 漏极分别通过第三过孔和第四过孔与薄膜晶体管有源区 连接; 在完成上述步骤的基底上形成第三绝缘层, 在存储电容的第三层结构 与第二层结构的未重叠的部分中形成贯穿第二绝缘层和第三绝缘层的第二过 孔的同时, 在薄膜晶体管漏极上方形成贯穿第三绝缘层的第五过孔; 在完成 上述步骤的基底上通过构图工艺形成包括存储电容的第四层结构的图形, 且 所述存储电容的第四层结构通过贯穿第三绝缘层的第五过孔与薄膜晶体管的 漏极连接。
在一个示例中, 所述在基底上形成存储电容的第一层结构, 同时形成薄 膜晶体管的有源区, 包括如下步骤:在基底上制备金属氧化物半导体材料层, 并在金属氧化物半导体材料层上涂覆光刻胶层, 对光刻胶进行曝光、 显影, 其中剩余的位于有源区的光刻胶的厚度大于存储电容区的光刻胶的厚度, 且
有源区的光刻胶与存储电容区的光刻胶间隔开; 通过刻蚀去除棵露的金属氧 化物半导体材料层; 通过刻蚀去除存储电容区的剩余厚度的光刻胶; 通过化 学镀工艺在存储电容的第一层结构的金属氧化物半导体层上形成金属层; 剥 离去除剩余的光刻胶。
在一个示例中, 所述金属层是由钼、 铜、 铝、 钨中的至少一种制成。 在一个示例中, 所述对光刻胶曝光包括: 通过半色调掩膜板或灰阶掩膜 板对光刻胶曝光。
在一个示例中, 一种阵列基板包括上述像素单元。
在一个示例中, 一种显示装置包括上述阵列基板。 附图说明
图 1为本发明的实施例 2的像素单元的结构示意图;
图 2a为本发明的实施例 4的形成像素单元的存储电容的第一层结构步骤 1011示意图;
图 2b为本发明的实施例 4的形成像素单元的存储电容的第一层结构步骤
1012示意图;
图 2c为本发明的实施例 4的形成像素单元的存储电容的第一层结构步骤 1013示意图;
图 2d为本发明的实施例 4的形成像素单元的存储电容的第一层结构步骤 1014示意图;
图 2e为本发明的实施例 4的形成像素单元的存储电容的第一层结构步骤 1015示意图;
图 3为本发明的实施例 4的制备像素单元的方法中, 在完成步骤 102之 后的像素单元的结构示意图; 以及
图 4为本发明的实施例 4的制备像素单元的方法中, 在完成步骤 104之 后的像素单元的结构示意图。
其中附图标记为: 101、 基底; 102、 存储电容的第一层结构; 103、 有源 区; 104、 金属氧化物半导体膜层; 105、 光刻胶; 201、 第一绝缘层; 202、 存储电容的第二层结构; 203、 栅极; 301、 第二绝缘层; 302、 存储电容的第 三层结构; 303、 源极; 304、 漏极; 3051、 第一过孔; 3052、 第二过孔; 3053、
第三过孔; 3054、 第四过孔; 3055、 第五过孔; 401、 第三绝缘层; 402、 存 储电容的第四层结构 (像素电极) 。 具体实施方式
为使本领域技术人员更好地理解本发明实施例的技术方案, 下面结合附 图和具体实施方式对本发明作进一步详细描述。
实施例 1
本实施例提供一种像素单元, 包括存储电容, 所述存储电容包括第一电 极和第二电极; 所述第一电极包括相互电连接的多个层结构, 所述第二电极 包括相互电连接的多个层结构, 两电极的各层结构交替设置在不同层, 所有 层结构至少部分重叠, 且第一电极与第二电极的结构的层数相等; 所述存储 电容在远离基底的方向上的最顶层结构为像素单元的像素电极。
本实施例的像素单元的存储电容的第一电极和第二电极均包括多层结 构, 故其与现有的存储电容的面积相比较小, 可以有效提高开口率。
实施例 2
结合图示 1所示,本实施例提供一种像素单元,其包括四层结构的电容, 同时还包括顶栅结构的薄膜晶体管。
其中, 所述薄膜晶体管的有源区 103与存储电容的第一层结构 102设于 同一层(即直接设在基底上的层) 中, 第一绝缘层 201覆盖薄膜晶体管的有 源区 103与存储电容的第一层结构 102。
所述薄膜晶体管的栅极 203与存储电容的第二层结构 202设于第一绝缘 层 201上, 第二绝缘层 301覆盖薄膜晶体管的栅极 203与存储电容的第二层 结构 202。
所述薄膜晶体管的源极 303、 漏极 304以及存储电容的第三层结构 302 设于第二绝缘层 301上, 第三绝缘层 401覆盖薄膜晶体管的源极 303、 漏极 304以及存储电容的第三层结构 302。
所述存储电容的第一层结构 102与第三层结构 302通过贯穿第一绝缘层 201和第二绝缘层 301的第一过孔 3051电连接,所述薄膜晶体管的源极 303、 漏极 304分别通过贯穿第一绝缘层 201和第二绝缘层 301的第三过孔 3053、 第四过孔 3054与薄膜晶体管的有源区 103相连。
所述像素电极 402设于第三绝缘层 401上, 其中, 所述像素电极 402与 存储电容的第二层结构 202通过贯穿第二绝缘层 301和第三绝缘层 401的第 二过孔 3052电连接,同时像素电极 402通过贯穿薄膜晶体管漏极 304上方的 第三绝缘层 401的第五过孔 3055与薄膜晶体管的漏极 304电连接。
其中, 将存储电容的第一层结构 102与薄膜晶体管的有源区 103设置于 同一层、 第二层结构 202与薄膜晶体管的栅极 203设置于同一层、 第三层结 构 302与薄膜晶体管的源极 303和漏极 304设置于同一层, 因而可以在制作 时与薄膜晶体管的各层结构分别通过一次构图工艺形成, 也就是说不用增加 工艺步骤, 也可以节约成本。
当然, 存储电容的各层结构也可与薄膜晶体管的结构分别位于不同的层 中, 这样需要分别制作薄膜晶体管和存储电容的各层结构, 但是其存储电容 和现有的存储电容相比较面积仍然减小了, 也可以有效地提高开口率。
在一个示例中, 所述薄膜晶体管的有源区 103的材料为金属氧化物半导 体。
在一个示例中, 所述存储电容的第一层结构 102包括与薄膜晶体管有源 区 103同步形成的金属氧化物半导体层, 所述第一层结构 102的金属氧化物 半导体层上设有金属层, 其中, 所述金属层由钼、 铜、 铝、 钨中的至少一种 制成。
当有源区 103材料为金属氧化物半导体时, 与其同步形成的存储电容的 第一层结构 102也是金属氧化物半导体材料, 故第一层结构 102不导电, 不 能直接作为电极,因此这时还要在第一层结构 102上形成用于导电的金属层。
当然本实施中的像素单元只是以包括四层结构的存储电容和顶栅型的薄 膜晶体管为例, 当然像素单元的存储电容也可以是六层、 八层以及更多层结 构 (层结构数为偶数) 的存储电容, 薄膜晶体管的类型也可以为其它类型的 (底栅型薄膜晶体管) , 只要在保证存储电容的两个电极的总相对面积不变 (即电容量不变 )的情况下减小了存储电容的面积(即在基底上占据的面积, 也就是不透光的面积) , 该结构的像素单元就在本发明的保护范围内。
实施例 3
本实施例针对实施例 1、2中所述的像素单元提供了一种像素单元的制备 方法, 包括下述步骤:
在基底上形成包括像素单元的存储电容的多层结构的图形。
其中, 在每形成存储电容的一层结构后, 就在该层结构上形成一层绝缘 层, 在相邻两个层结构未重叠的部分形成贯穿这两个层结构上覆盖的绝缘层 的过孔, 用于两奇数层电连接以及两偶数层电连接, 分别形成存储电容的第 一电极和第二电极, 且第一电极的层数与第二电极的层数相同。
当然, 像素单元还包括薄膜晶体管, 在形成像素单元的存储电容的同时 也形成了薄膜晶体管。
实施例 4
结合图 1、 图 2a-2e、 图 3和图 4所示, 本实施例针对实施例 2的像素单 元提供了一种像素单元的制备方法, 包括如下步骤:
在步骤 101 ,在基底 101上形成存储电容的第一层结构 102, 同时形成薄 膜晶体管的有源区 103, 如图 2a-2e所示。
其中步骤 101可以包括例如:
如图 2a所示, 在步骤 1011 , 在基底 101上通过构图工艺利用金属氧化 物半导体材料分别形成包括有源层与第一层结构的图形, 例如, 首先在基底 101上形成金属氧化物半导体膜层 104,并在金属氧化物半导体膜层 104上形 成光刻胶 105 , 对光刻胶 105进行曝光、 显影, 其中剩余的位于有源区 103 上的光刻胶 105的厚度大于存储电容区的光刻胶 105的厚度, 且有源区 103 上的光刻胶 105与存储电容区的光刻胶 105间隔开。
例如, 所述对光刻胶 105曝光包括:
通过半色调掩膜板或灰阶掩膜板对光刻胶 105曝光。
如图 2b所示, 在步骤 1012, 通过刻蚀去除棵露的金属氧化物半导体膜 层 104。
如图 2c所示, 在步骤 1013, 通过刻蚀去除存储电容区的剩余厚度的光 刻胶 105。
如图 2d所示, 在步骤 1014, 通过化学镀工艺在存储电容的第一层结构 102的金属氧化物半导体区上形成金属层。
化学镀工艺筒单易行, 成本低; 且由于本方案中的化学镀工艺中使用的 化学液中的络合剂为酒石酸, 其可使金属及金属氧化物表面改性, 而不会对 SiO、 SiN等表面造成改变, 因此其只会在棵露的存储电容的第一层结构 102
的金属氧化物半导体区上形成金属层(因为薄膜晶体管有源区 103此时仍被 光刻胶覆盖, 故不会形成金属层) , 故对于顶栅型薄膜晶体管的性能没有影 响。
例如, 所述金属层是由钼、 铜、 铝、 钨中的至少一种制成。
以形成钼金属层作为化学镀工艺的例子: 在室温至 100°C间的温度下, 将化学镀钼液涂布在具有如图 2c所示结构的基底 101上,待其反应完全即可 得到如图 2d所示的结构, 之后清洗、 烘干, 进行后续步骤。 其中, 化学镀相 液的成分可包括: 0.1~0.3mol/L的硫酸相; 0.05~0.15mol/L的硫化钠 (稳定剂), 其用于保证钼离子的稳定; 0.1~lmol/L的醋酸钠 (緩沖剂); 0.1~lmol/L的酒 石酸 (络合剂), 其可用于使相离子的极性增大, 使所得的镀层结晶细致光滑, 同时还可以稳定镀液; 余量的水。 当然, 以上只是化学镀 ]液的一个示例, 其成分可以变化, 例如其中还可含有加速剂、 pH值调节剂等其他物质, 且各 已有组分的浓度、 物质选择也可不同。
由于通过化学镀形成导电层的工艺是已知的, 故在此不再对其进行详细 介绍。
当然, 如果不使用化学镀工艺, 而采用构图工艺直接形成金属层也是可 行的, 这样其需要增加一次构图工艺, 但是其适用范围也更广, 例如可用于 底栅型的薄膜晶体管, 且有源区的材料也可以不是金属氧化物半导体。
如图 2e所示, 在步骤 1015, 剥离去除剩余的光刻胶 105。
在步骤 102,在完成上述步骤的基底 101上形成第一绝缘层 201 ,且通过 构图工艺在第一绝缘层 201上形成存储电容的第二层结构 202的图形的同时, 形成包括薄膜晶体管栅极 203的图形, 得到如图 3所示的结构。
在步骤 103 ,在完成上述步骤的基底 101上形成第二绝缘层 301 ,在存储 电容的第一层结构 102与第二层结构 202未重叠的部分上形成贯穿第一绝缘 层 201和第二绝缘层 301的第一过孔 3051的同时, 在薄膜晶体管的有源区 103上方的源、 漏区形成贯穿第一绝缘层 201和第二绝缘层 301的第三过孔 3053和第四过孔 3054。
在步骤 104, 在完成上述步骤的基底 101上通过构图工艺形成存储电容 的第三层结构 302的图形的同时, 形成包括薄膜晶体管源极 303、 漏极 304 的图形,且所述薄膜晶体管的源、漏极 304分别通过第三过孔 3053和第四过
孔 3054与薄膜晶体管有源区 103连接, 得到如图 4所示的结构。 在步骤 105 ,在完成上述步骤的基底 101上形成第三绝缘层 401 ,在存储 电容的第三层结构 302与第二层结构 202未重叠的部分上方形成贯穿第二绝 缘层 301和第三绝缘层 401的第二过孔 3052的同时,在薄膜晶体管漏极 304 上形成贯穿第三绝缘层 401的第五过孔 3055, 如图 1所示。
在步骤 106, 在完成上述步骤的基底 101上通过构图工艺形成包括存储 电容的第四层结构 402的图形, 且所述存储电容的第四层结构 402通过贯穿 第三绝缘层 401的第二过孔 3052与薄膜晶体管的漏极 304连接,得到如图 1 所示的结构。
当然,根据薄膜晶体管结构的不同,存储电容的制备方法也是多样的(例 如可为 6层、 8层等) , 在此不再逐一描述, 但是只要其可以形成存储电容 的多层结构 (偶数层结构)就属于本发明的保护范围。
实施例 5
本实施例提供了一种阵列基板, 该阵列基板包括上述像素单元。
当然, 在阵列基板中还应具有数据线、 扫描线等其他的已知结构, 在此 不再详细描述。
由于本实施例的阵列基板具有上述的像素单元, 故其开口率较高。
实施例 6
本实施例提供了一种显示装置, 该显示装置包括实施例 5中所述的阵列 基板。 该显示装置可以为: 手机、 平板电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例 5中的阵列基板, 故其具有更好的开 口率, 视觉效果更好, 画面效果更好。
当然, 本实施例的显示装置中还可以包括其他常规结构, 如电源单元、 显示驱动单元等。
可以理解的是, 以上实施方式仅仅是为了说明本发明实施例的原理而采 用的示例性实施方式, 然而本发明并不局限于此。 对于本领域内的普通技术 人员而言, 在不脱离本发明实施例的精神和实质的情况下, 可以做出各种变 型和改进, 这些变型和改进也视为本发明的保护范围。
Claims
1.一种像素单元, 包括存储电容, 其中, 所述存储电容包括第一电极和 第二电极;
所述第一电极包括相互电连接的多个层结构, 所述第二电极包括相互电 连接的多个层结构, 所述第一电极和所述第二电极的层结构交替设置在不同 层, 所述第一电极的所述多个层结构和所述第二电极的所述多个层结构至少 部分重叠, 且第一电极与第二电极的层结构的层数相同;
所述存储电容在远离基底的方向上的最顶层结构为像素单元的像素电 极。
2.根据权利要求 1所述的像素单元, 其中, 在远离基底的方向上, 所述 存储电容依次包括第一层结构、 第二层结构、 第三层结构、 第四层结构; 所述存储电容的第四层结构为像素单元的像素电极, 且与存储电容的第 二层结构电连接, 构成存储电容的第一电极;
所述存储电容的第一层结构与第三层结构电连接, 构成存储电容的第二 电极。
3.根据权利要求 2所述的像素单元, 还包括顶栅结构的薄膜晶体管, 所述薄膜晶体管的有源区与存储电容的第一层结构设于同一层中, 第一 绝缘层覆盖薄膜晶体管的有源区与存储电容的第一层结构;
所述薄膜晶体管的栅极与存储电容的第二层结构设于第一绝缘层上, 第 二绝缘层覆盖薄膜晶体管的栅极与存储电容的第二层结构;
所述薄膜晶体管的源极、 漏极以及存储电容的第三层结构设于第二绝缘 层上,第三绝缘层覆盖薄膜晶体管的源极、漏极以及存储电容的第三层结构, 其中, 所述存储电容的第一层结构与第三层结构间通过贯穿第一绝缘层 和第二绝缘层中的过孔电连接;
所述像素电极设于第三绝缘层上, 其中,
所述像素电极与存储电容的第二层结构间通过贯穿第二绝缘层和第三绝 缘层中的过孔电连接。
4.根据权利要求 3所述的像素单元, 其中, 所述薄膜晶体管的有源区的 材料为金属氧化物半导体。
5.根据权利要求 4所述的像素单元, 其中, 所述存储电容的第一层结构 包括与薄膜晶体管有源区同步形成的金属氧化物半导体层, 所述第一层结构 的金属氧化物半导体层上设有金属层。
6.根据权利要求 5所述的像素单元, 其中, 所述金属层由钼、 铜、 铝、 钨中的至少一种制成。
7.一种如权 1至 6中任意一项所述的像素单元的制备方法, 包括如下步 骤:
通过构图工艺在基底上依次形成包括存储电容的各层结构的图形。
8.根据权利要求 7所述的像素单元的制备方法, 其中, 所述存储电容为 四层结构的存储电容, 所述像素单元的制备方法包括如下步骤:
在基底上形成存储电容的第一层结构;
在完成上述步骤的基底上形成第一绝缘层;
通过构图工艺在第一绝缘层上形成包括存储电容的第二层结构的图形; 在完成上述步骤的基底上形成第二绝缘层, 通过构图工艺在存储电容的 第一层结构的未与第二层结构重叠的部分中形成贯穿第一绝缘层和第二绝缘 层的第一过孔;
在完成上述步骤的基底上通过构图工艺形成包括存储电容的第三层结构 的图形, 且存储电容的第三层结构通过贯穿第一绝缘层和第二绝缘层的第一 过孔与存储电容的第一层结构连接;
在完成上述步骤的基底上形成第三绝缘层, 通过构图工艺在存储电容的 第二层结构的未与第三层结构重叠的部分中形成贯穿第二绝缘层和第三绝缘 层的第二过孔;
在完成上述步骤的基底上通构图工艺形成包括存储电容的第四层结构的 图形, 且存储电容的第四层结构通过贯穿第二绝缘层和第三绝缘层的第二过 孔与存储电容的第二层结构连接。
9.根据权利要求 8所述的像素单元的制备方法, 其中, 所述像素单元还 包括顶栅结构的薄膜晶体管, 所述像素单元的制备方法包括如下步骤:
在基底上形成存储电容的第一层结构, 同时形成薄膜晶体管的有源区; 在完成上述步骤的基底上形成第一绝缘层, 且通过构图工艺在第一绝缘 层上形成包括存储电容的第二层结构和薄膜晶体管的栅极的图形;
在完成上述步骤的基底上形成第二绝缘层, 通过构图工艺在存储电容的 第一层结构的未与第二层结构未重叠的部分中形成贯穿第一绝缘层和第二绝 缘层的第一过孔, 同时在薄膜晶体管的源、 漏区形成贯穿第一绝缘层和第二 绝缘层的第三过孔和第四过孔;
在完成上述步骤的基底上通过构图工艺形成包括存储电容的第三层结构 和薄膜晶体管源极、 漏极的图形, 且所述薄膜晶体管的源、 漏极分别通过第 三过孔和第四过孔与薄膜晶体管有源区连接;
在完成上述步骤的基底上形成第三绝缘层, 在存储电容的第三层结构与 第二层结构的未重叠的部分中形成贯穿第二绝缘层和第三绝缘层的第二过孔 的同时, 在薄膜晶体管漏极上方形成贯穿第三绝缘层的第五过孔;
在完成上述步骤的基底上通过构图工艺形成包括存储电容的第四层结构 的图形, 且所述存储电容的第四层结构通过贯穿第三绝缘层的第五过孔与薄 膜晶体管的漏极连接。
10.根据权利要求 9所述的像素单元的制备方法, 其中, 所述在基底上 形成存储电容的第一层结构, 同时形成薄膜晶体管的有源区, 包括如下步骤: 在基底上制备金属氧化物半导体材料层, 并在金属氧化物半导体材料层 上涂覆光刻胶层, 对光刻胶进行曝光、 显影, 其中剩余的位于有源区的光刻 胶的厚度大于存储电容区的光刻胶的厚度, 且有源区的光刻胶与存储电容区 的光刻胶间隔开;
通过刻蚀去除棵露的金属氧化物半导体材料层;
通过刻蚀去除存储电容区的剩余厚度的光刻胶;
通过化学镀工艺在存储电容的第一层结构的金属氧化物半导体层上形成 金属层;
剥离去除剩余的光刻胶。
11.根据权利要求 10所述的像素单元的制备方法, 其中, 所述金属层是 由钼、 铜、 铝、 钨中的至少一种制成。
12.根据权利要求 10所述的像素单元的制备方法, 其中, 所述对光刻胶 曝光包括:
通过半色调掩膜板或灰阶掩膜板对光刻胶曝光。
13. 一种阵列基板, 包括权利要求 1~6中任意一项所述的像素单元。
14.一种显示装置, 包括权利要求 13所述的阵列基板。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310200428.6 | 2013-05-27 | ||
CN201310200428.6A CN103293790B (zh) | 2013-05-27 | 2013-05-27 | 像素单元及其制备方法、阵列基板、显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014190657A1 true WO2014190657A1 (zh) | 2014-12-04 |
Family
ID=49094929
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2013/085280 WO2014190657A1 (zh) | 2013-05-27 | 2013-10-16 | 像素单元及其制备方法、阵列基板、显示装置 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN103293790B (zh) |
WO (1) | WO2014190657A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10249645B2 (en) | 2014-02-05 | 2019-04-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103293790B (zh) * | 2013-05-27 | 2016-01-06 | 京东方科技集团股份有限公司 | 像素单元及其制备方法、阵列基板、显示装置 |
CN104716154B (zh) * | 2013-12-11 | 2018-12-18 | 昆山国显光电有限公司 | 一种有机发光显示装置及其制备方法 |
CN103943634A (zh) * | 2014-03-17 | 2014-07-23 | 京东方科技集团股份有限公司 | 阵列基板、显示装置及其电容结构 |
CN104965362A (zh) * | 2015-06-04 | 2015-10-07 | 京东方科技集团股份有限公司 | 一种阵列基板及其制备方法、显示装置 |
CN105116585A (zh) * | 2015-09-16 | 2015-12-02 | 深圳市华星光电技术有限公司 | 一种触摸面板、阵列基板及其制造方法 |
TWI575732B (zh) * | 2016-05-25 | 2017-03-21 | 友達光電股份有限公司 | 畫素結構及其顯示面板 |
CN105914229B (zh) * | 2016-06-24 | 2017-12-15 | 京东方科技集团股份有限公司 | 一种amoled显示基板及其制作方法、显示装置 |
CN107579083B (zh) * | 2017-09-30 | 2024-06-11 | 京东方科技集团股份有限公司 | 阵列基板及制备方法和显示装置 |
US10804411B2 (en) | 2017-11-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and method of forming the same |
CN108257977B (zh) | 2018-01-10 | 2021-01-01 | 京东方科技集团股份有限公司 | 显示背板及其制作方法、显示面板和显示装置 |
CN108878453A (zh) * | 2018-06-29 | 2018-11-23 | 上海天马微电子有限公司 | 一种阵列基板、显示面板及显示装置 |
CN108957884B (zh) * | 2018-07-23 | 2021-07-27 | Tcl华星光电技术有限公司 | 阵列基板、液晶面板和阵列基板制作方法 |
CN110164870A (zh) * | 2019-05-14 | 2019-08-23 | 深圳市华星光电半导体显示技术有限公司 | 含电容背板构造 |
CN115995470A (zh) * | 2019-08-23 | 2023-04-21 | 京东方科技集团股份有限公司 | 显示基板及其制造方法、显示装置 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007013013A (ja) * | 2005-07-01 | 2007-01-18 | Sharp Corp | 半導体装置、半導体装置製造方法、薄膜トランジスタアレイ基板、及び、液晶表示装置 |
CN102213881A (zh) * | 2010-04-12 | 2011-10-12 | 精工爱普生株式会社 | 电光装置及电子设备 |
US20120007083A1 (en) * | 2010-07-07 | 2012-01-12 | Samsung Mobile Display Co., Ltd. | Organic light-emitting display device and manufacturing method of the same |
CN103094295A (zh) * | 2013-01-23 | 2013-05-08 | 北京京东方光电科技有限公司 | 平板探测器及其制作方法、摄像装置 |
CN103293790A (zh) * | 2013-05-27 | 2013-09-11 | 京东方科技集团股份有限公司 | 像素单元及其制备方法、阵列基板、显示装置 |
CN203311138U (zh) * | 2013-05-27 | 2013-11-27 | 京东方科技集团股份有限公司 | 像素单元、阵列基板及显示装置 |
-
2013
- 2013-05-27 CN CN201310200428.6A patent/CN103293790B/zh active Active
- 2013-10-16 WO PCT/CN2013/085280 patent/WO2014190657A1/zh active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007013013A (ja) * | 2005-07-01 | 2007-01-18 | Sharp Corp | 半導体装置、半導体装置製造方法、薄膜トランジスタアレイ基板、及び、液晶表示装置 |
CN102213881A (zh) * | 2010-04-12 | 2011-10-12 | 精工爱普生株式会社 | 电光装置及电子设备 |
US20120007083A1 (en) * | 2010-07-07 | 2012-01-12 | Samsung Mobile Display Co., Ltd. | Organic light-emitting display device and manufacturing method of the same |
CN103094295A (zh) * | 2013-01-23 | 2013-05-08 | 北京京东方光电科技有限公司 | 平板探测器及其制作方法、摄像装置 |
CN103293790A (zh) * | 2013-05-27 | 2013-09-11 | 京东方科技集团股份有限公司 | 像素单元及其制备方法、阵列基板、显示装置 |
CN203311138U (zh) * | 2013-05-27 | 2013-11-27 | 京东方科技集团股份有限公司 | 像素单元、阵列基板及显示装置 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10249645B2 (en) | 2014-02-05 | 2019-04-02 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module |
US10811435B2 (en) | 2014-02-05 | 2020-10-20 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module |
US11107837B2 (en) | 2014-02-05 | 2021-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semicondutor device, the display device, and the display module |
US11699762B2 (en) | 2014-02-05 | 2023-07-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic device including the semiconductor device, the display device, and the display module |
Also Published As
Publication number | Publication date |
---|---|
CN103293790B (zh) | 2016-01-06 |
CN103293790A (zh) | 2013-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2014190657A1 (zh) | 像素单元及其制备方法、阵列基板、显示装置 | |
US9412760B1 (en) | Array substrate and manufacturing method thereof, and display device | |
US11665940B2 (en) | Display substrate for avoiding breaks and preparation method thereof, bonding method of display panel and display apparatus | |
JP4657915B2 (ja) | パッド電極形成方法及びこれを用いた液晶表示素子の製造方法並びに該方法により製造された液晶表示素子 | |
US9478565B2 (en) | Array substrate and method for fabricating the same, and display panel | |
WO2018201770A1 (zh) | 阵列基板及其制备方法、显示装置 | |
WO2014190698A1 (zh) | 一种阵列基板及其制作方法 | |
JP6521534B2 (ja) | 薄膜トランジスタとその作製方法、アレイ基板及び表示装置 | |
WO2014127587A1 (zh) | 阵列基板及其制造方法、显示装置 | |
WO2014044054A1 (zh) | Tft阵列基板及其制作方法、液晶显示设备 | |
WO2014015453A1 (zh) | 薄膜晶体管、阵列基板及其制作方法、显示装置 | |
CN103123911B (zh) | 像素结构及其制作方法 | |
WO2014206035A1 (zh) | 阵列基板及其制作方法、显示面板和显示装置 | |
JP2006338008A (ja) | 開口率が向上したアレイ基板、その製造方法及びそれを含む表示装置。 | |
WO2019061936A1 (zh) | 显示面板及其制作方法 | |
US9053988B2 (en) | TFT array substrate, manufacturing method of the same and display device | |
WO2017140058A1 (zh) | 阵列基板及其制作方法、显示面板及显示装置 | |
EP2497107A1 (en) | Mask level reduction for mofet | |
WO2014015628A1 (zh) | 阵列基板及其制作方法、显示装置 | |
US6500702B2 (en) | Method for manufacturing thin film transistor liquid crystal display | |
WO2016026207A1 (zh) | 阵列基板及其制作方法和显示装置 | |
WO2021077674A1 (zh) | 阵列基板的制作方法及阵列基板 | |
JP4954868B2 (ja) | 導電層を備えた基板の製造方法 | |
CN104952887A (zh) | 一种阵列基板及其制备方法、显示装置 | |
US8421096B2 (en) | Pixel structure and display panel |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13886139 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 22.03.2016) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13886139 Country of ref document: EP Kind code of ref document: A1 |