WO2021056158A1 - 源极驱动电路及驱动方法、显示装置 - Google Patents

源极驱动电路及驱动方法、显示装置 Download PDF

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Publication number
WO2021056158A1
WO2021056158A1 PCT/CN2019/107364 CN2019107364W WO2021056158A1 WO 2021056158 A1 WO2021056158 A1 WO 2021056158A1 CN 2019107364 W CN2019107364 W CN 2019107364W WO 2021056158 A1 WO2021056158 A1 WO 2021056158A1
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Prior art keywords
terminal
amplifier
power signal
signal
level
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PCT/CN2019/107364
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English (en)
French (fr)
Inventor
杨燕
洪青桦
刘蕊
孙伟
陈明
谷其兵
陈相逸
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980001768.1A priority Critical patent/CN113168801B/zh
Priority to US16/960,574 priority patent/US11205372B2/en
Priority to PCT/CN2019/107364 priority patent/WO2021056158A1/zh
Publication of WO2021056158A1 publication Critical patent/WO2021056158A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a source driving circuit, a driving method, and a display device.
  • the display panel usually adopts a progressive scan method to realize the display of the picture.
  • the control chip needs to scan all pixel units in the display area line by line.
  • a source driving circuit including a buffer amplifier for generating a driving signal according to an original driving signal, the buffer amplifier including: a first amplifier and a second amplifier.
  • the high-level terminal of the first amplifier is connected to the first power signal terminal, the low-level terminal is connected to the second power signal terminal, and the output terminal is used to output a positive drive signal;
  • the high-level terminal of the second amplifier is connected to the third power signal terminal ,
  • the low-level terminal is connected to the fourth power signal terminal, and the output terminal is used to output a negative driving signal; wherein the voltage of the second power signal terminal is less than the voltage of the third power signal terminal.
  • the voltage of the first power signal terminal is an analog power signal voltage; the voltage of the fourth power signal terminal is the voltage of the ground terminal; the voltage of the second power signal terminal is less than a half-value analog The voltage of the power signal; the voltage of the third power signal terminal is greater than the voltage of the half-value analog power signal.
  • the buffer amplifier further includes a switch component; the low-level terminal of the first amplifier is connected to the second power signal terminal through the switch component, and the fifth power signal terminal is selected.
  • the voltage of the fifth power signal terminal is equal to the voltage of the half-value analog power signal.
  • the source driving circuit further includes: a detection circuit, an arithmetic circuit, and a control circuit.
  • the detection circuit is used to detect the potential of the effective pulse signal of each row of the original driving signal in real time;
  • the arithmetic circuit is connected to the detection circuit and is used to calculate the effective pulse signal of the current row and the effective pulse signal of the previous row in real time according to the potential of the effective pulse signal of each row Potential difference;
  • the control circuit is connected to the arithmetic circuit and the switch component, and is used to send a control signal to the switch component according to the potential difference between the current row effective pulse signal and the previous row effective pulse signal to control the drive of the switch component State; wherein, when the potential difference between the effective pulse signal of the current row and the effective pulse signal of the previous row is greater than a preset value, the switch assembly is controlled to work in the first driving state for at least part of the period of the current row; the current row effective pulse signal When the potential difference between the effective pulse signal of the previous row is less than
  • the switch assembly includes: a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit.
  • the first switch unit is connected to the low-level terminal of the first amplifier, the second power signal terminal, and the first control terminal, and is used to respond to the signal of the first control terminal to connect the low-level terminal of the first amplifier with The second power signal terminal;
  • the second switch unit is connected to the high-level terminal of the second amplifier, the third power signal terminal, and the first control terminal, and is used to respond to the signal from the first control terminal to communicate with the
  • the high-level terminal of the second amplifier is connected to the third power signal terminal;
  • the third switch unit is connected to the low-level terminal of the first amplifier, the fifth power signal terminal, and the second control terminal for responding to the first amplifier.
  • the signal of the second control terminal is connected to the low level terminal of the first amplifier and the fifth power signal terminal; the fourth switch unit is connected to the high level terminal of the second amplifier, the fifth power signal terminal, and the first power signal terminal.
  • the second control terminal is used to respond to the signal of the second control terminal to connect the high level terminal of the second amplifier and the fifth power signal terminal.
  • the first switch unit includes a first switch transistor, a first end of the first switch transistor is connected to a low-level end of the first amplifier, and a second end is connected to the second The power signal terminal, the control terminal is connected to the first control terminal;
  • the second switch unit includes a second switch transistor, the first terminal of the second switch transistor is connected to the high-level terminal of the second amplifier, the second terminal is connected to the third power signal terminal, and the control terminal is connected to the first terminal. Control terminal;
  • the third switch unit includes a third switch transistor, the first end of the third switch transistor is connected to the low level end of the first amplifier, the second end is connected to the fifth power signal end, and the control end is connected to the Second control terminal
  • the fourth switch unit includes a fourth switch transistor, a first terminal of the fourth switch transistor is connected to the high-level terminal of the second amplifier, a second terminal is connected to the fifth power signal terminal, and a control terminal is connected to the The second control terminal.
  • the first switch transistor, the second switch transistor, the third switch transistor, and the fourth switch transistor are N-type transistors or P-type transistors.
  • a source driving circuit driving method for driving the above-mentioned source driving circuit includes:
  • the second amplifier is used to output a negative drive signal.
  • the source driving circuit further includes a switch component
  • the method further includes:
  • the low-level terminal and the second power signal terminal of the first amplifier are turned on, and the high-level terminal and the third power signal terminal of the second amplifier are turned on;
  • the low-level terminal and the fifth power signal terminal of the first amplifier are turned on, and the high-level terminal and the fifth power signal terminal of the second amplifier are turned on.
  • the source driving circuit further includes a detection circuit, an arithmetic circuit, and a control circuit
  • the method further includes:
  • the switch assembly is controlled to work in the second driving state during the driving period of the current row.
  • a display device including the above-mentioned source driving circuit.
  • the present disclosure provides a source driving circuit, a driving circuit, and a display device.
  • the source driving circuit includes a buffer amplifier for generating a driving signal according to an original driving signal.
  • the buffer amplifier includes a first amplifier and a second amplifier.
  • the high-level terminal of the first amplifier is connected to the first power signal terminal, the low-level terminal is connected to the second power signal terminal, and the output terminal is used to output a positive drive signal;
  • the high-level terminal of the second amplifier is connected to the third power signal terminal ,
  • the low-level terminal is connected to the fourth power signal terminal, and the output terminal is used to output a negative driving signal; wherein the voltage of the second power signal terminal is less than the voltage of the third power signal terminal.
  • the present disclosure provides a source drive circuit that can increase the voltage of the drive signal output by the analog power signal AVDD, thereby solving the technical problem of insufficient charging of the sub-pixel unit; on the other hand, the source drive provided by the present disclosure
  • the circuit increases the voltage difference between the high-level end and the low-level end of the first amplifier and the second amplifier, thereby increasing the speed of the amplifier output voltage change, reducing the time of driving signal generation, and solving the problem caused by the increase of the analog power signal AVDD.
  • the voltage of 0 gray scale is to increase the target voltage drop when the data signal becomes 0 gray scale, thereby increasing the rate of the data signal voltage drop, thereby further reducing the speed at which the data signal changes to 0 gray scale.
  • FIG. 1 is a schematic diagram of the structure of a source driving circuit in the related art
  • FIG. 2 is a timing diagram of the output signal of the source driving circuit in the related art
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the source driving circuit of the present disclosure.
  • FIG. 4 is a timing diagram of output signals in an exemplary embodiment of the source driving circuit of the present disclosure
  • FIG. 5 is a comparison diagram of the related art and the output driving signal generated image of the source driving circuit in the present disclosure
  • FIG. 6 is a schematic structural diagram of another exemplary embodiment of the source driving circuit of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another exemplary embodiment of the source driving circuit of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another exemplary embodiment of the source driving circuit of the present disclosure.
  • FIG. 9 is a schematic structural diagram of another exemplary embodiment of the source driving circuit of the present disclosure.
  • FIG. 10 is a flowchart of an exemplary embodiment of the driving method of the source driving circuit of the present disclosure.
  • the charging time of each row of sub-pixel units is getting smaller and smaller, and the voltage drop caused by the resistance of the data line and its parasitic capacitance is taken into account, so that it is far away from the source driving circuit.
  • the charging voltage of the sub-pixel unit cannot meet the preset requirement, which eventually causes uneven display of the display panel.
  • the related technology can increase the voltage of the driving signal by increasing the voltage of the analog power signal AVDD, thereby solving the above technical problem.
  • the analog power signal AVDD is increased, the potential difference between the effective pulses of adjacent rows of the driving signal will increase.
  • the effective pulse voltage of the first row is 16V
  • the effective pulse voltage of the second row is 8V
  • the effective pulse voltage of the first row is 18V
  • the effective pulse voltage of the second row is 9V.
  • the voltage difference (8V) of the effective pulse voltage between adjacent rows of the former is smaller than the voltage difference (9V) of the effective pulse voltage between adjacent rows of the latter.
  • the source driving circuit may include a buffer amplifier for generating a driving signal according to the original driving signal.
  • the buffer amplifier may Including: a first amplifier OP11, a second amplifier OP12.
  • the high-level end of the first amplifier OP11 receives the analog power signal AVDD, the low-level end receives the half-value analog power signal HAVDD, and the output end is used to output the positive polarity drive signal; the high-level end of the second amplifier OP12 receives the half-value analog power signal HAVDD ,
  • the low level terminal is connected to the ground terminal GND, and the output terminal is used to output a negative polarity drive signal.
  • the buffer amplifier is used to increase the carrying capacity of the signal, so as to convert the original driving signal with a weak carrying capacity into a driving signal with a stronger carrying capacity. As shown in Figure 2, it is a timing diagram of the output signal of the source drive circuit in the related art.
  • OP11 refers to the positive drive signal output by the first amplifier OP11
  • OP12 refers to the negative drive signal output by the second amplifier OP12
  • LV255 refers to the drive signal.
  • LV0 refers to the voltage of the drive signal at 0 gray scale.
  • the voltage range of the first amplifier OP11 output driving signal is between the voltage of the half-value analog power signal HAVDD and the voltage of the analog power signal AVDD
  • the voltage range of the second amplifier OP12 output driving signal is the voltage of the half-value analog power signal HAVDD.
  • the voltage of the positive drive signal is equal to the voltage of the negative drive signal at 0 gray scale.
  • the buffer amplifier Since the buffer amplifier also needs time to convert the signal, and the greater the voltage difference between the adjacent line pulse signals of the original driving signal, the longer the buffer amplifier needs to convert the signal. Therefore, an increase in the voltage of the analog power signal AVDD will increase the time for the source driving circuit to output the driving signal. As a result, the data signal cannot reach the preset voltage within the interval between adjacent effective pulses.
  • the source driving circuit includes The drive signal generates a buffer amplifier for the drive signal.
  • the buffer amplifier includes a first amplifier OP1 and a second amplifier OP2.
  • the high-level terminal of the first amplifier OP1 is connected to the first power signal terminal AVDD, the low-level terminal is connected to the second power signal terminal HAVDD-, and the output terminal is used to output a positive polarity drive signal; the high-level terminal of the second amplifier OP2 is connected to the first power signal terminal HAVDD-.
  • the three power signal terminals HAVDD+ are connected, the low level terminal is connected to the fourth power signal terminal VSS, and the output terminal is used to output a negative drive signal; wherein the level of the second power signal terminal HAVDD- is smaller than the third power signal terminal HAVDD+ Level.
  • the voltage of the first power signal terminal AVDD may be the voltage of the analog power signal AVDD
  • the voltage of the second power signal terminal HAVDD- may be less than the voltage of the half-value analog power signal HAVDD
  • the voltage of the third power signal terminal HAVDD+ may be greater than half.
  • the value simulates the voltage of the power signal HAVDD
  • the voltage of the fourth power signal terminal VSS may be the voltage of the ground terminal.
  • the voltage of the second power signal terminal HAVDD- is located between the voltage of the first power signal terminal AVDD and the voltage of the fourth power signal terminal VSS
  • the voltage of the third power signal terminal HAVDD+ is located between the voltage of the first power signal terminal AVDD and the voltage of the fourth power signal terminal Between VSS voltage.
  • FIG. 4 it is a timing diagram of the output signal in an exemplary embodiment of the source driving circuit of the present disclosure.
  • OP1 refers to the positive driving signal output by the first amplifier OP1
  • OP2 refers to the negative driving signal output by the second amplifier OP2.
  • Signal LV255 refers to the voltage of the drive signal at 255 gray scale
  • LV0 refers to the voltage of the drive signal at 0 gray scale.
  • the voltage range of the driving signal output by the first amplifier OP1 is between the voltage of the second power signal terminal HAVDD- and the voltage of the first power signal terminal AVDD
  • the voltage range of the driving signal output by the second amplifier OP2 is in the third power signal terminal.
  • the present disclosure provides a source drive circuit.
  • the source drive circuit provided in the present disclosure can increase the voltage of the drive signal output by the analog power signal AVDD by increasing the voltage of the analog power signal AVDD, thereby solving the technical problem of insufficient charging of the sub-pixel unit;
  • the source drive circuit provided by the present disclosure increases the voltage difference between the high-level end and the low-level end of the first amplifier and the second amplifier, thereby increasing the speed of the amplifier output voltage change and reducing the time for generating the driving signal.
  • the gamma voltage of 0 gray corresponds to the second power signal terminal HAVDD- and the third power signal terminal respectively.
  • the voltage of the power signal terminal HAVDD+ by setting the level of the second power signal terminal to be smaller than the level of the third power signal terminal, can reduce the voltage of 0 gray scale under positive polarity drive and increase the 0 gray scale level under negative polarity drive That is, increase the target voltage drop when the data signal becomes 0 gray scale, thereby increasing the rate of the data signal voltage drop, and further shortening the speed at which the data signal turns to 0 gray scale. As shown in FIG.
  • the left image is the screen generated by the source driving circuit output driving signal in the related art
  • the right side is the image generated by the source driving circuit in the related art.
  • the source driver circuit outputs the image generated by the drive signal
  • the left and right images are both images driven by the same image signal.
  • the black and white contrast of the left picture is less than the black and white contrast of the right picture, specifically, the clarity of the words "BOE" in the right picture is higher than the clarity of the words "BOE” in the left picture.
  • the source drive circuit is provided with two power signal terminals: the voltage of the second power signal terminal HAVDD- and the third power signal terminal HAVDD+.
  • this setting can improve the display effect, it will also increase the source The power consumption of the pole drive circuit.
  • the voltage difference between the effective pulses of adjacent rows of the driving signal is small, there will not be the technical problem of "the data signal cannot reach the preset voltage within the interval between adjacent effective pulses". As shown in FIG.
  • the buffer amplifier may further include a switch component 1; the low-level end of the first amplifier OP1 passes through the switch component 1 is alternatively connected to the second power signal terminal HAVDD- and the fifth power signal terminal HAVDD; the high-level terminal of the second amplifier OP2 is connected to the third power signal terminal HAVDD+ and the third power signal terminal HAVDD+ through the switch component The five power signal terminals HAVDD are alternatively connected; the switch component is used to connect the low level terminal of the first amplifier OP1 and the second power signal terminal HAVDD- in the first driving state, and to connect the first power signal terminal HAVDD- The high-level terminal of the second amplifier OP2 and the third power signal terminal HAVDD+; in the second driving state, the low-level terminal of the first amplifier OP1 and the fifth power signal terminal HAVDD are connected, and the second amplifier is connected The high level terminal of OP2 and the fifth power signal terminal HAVDD.
  • the switch assembly works in the first driving state, thereby solving the technical problem that the data signal cannot reach the preset voltage within the interval of adjacent effective pulses;
  • the switch component works in the second driving state, thereby solving the technical problem of high power consumption of the source driving circuit.
  • the switch component may include: a first switch unit 11, a second switch unit 12, The third switch unit 13 and the fourth switch unit 14.
  • the first switch unit 11 is connected to the low-level terminal of the first amplifier OP1, the second power signal terminal HAVDD-, and the first control terminal CN1, and is used to respond to the signal of the first control terminal CN1 to communicate with the first control terminal CN1.
  • the low level terminal of an amplifier OP1 is connected to the second power signal terminal HAVDD-; the second switch unit 12 is connected to the high level terminal of the second amplifier OP2, the third power signal terminal HAVDD+, and the first control terminal CN1, Used to respond to the signal of the first control terminal CN1 to connect the high-level terminal of the second amplifier OP2 with the third power signal terminal HAVDD+; the third switch unit 13 is connected to the low-level terminal of the first amplifier OP1
  • the fifth power signal terminal HAVDD and the second control terminal CN2 are used to respond to the signal of the second control terminal CN2 to connect the low level terminal of the first amplifier OP1 and the fifth power signal terminal HAVDD;
  • the fourth switch unit 14 is connected to the high level terminal of the second amplifier OP2, the fifth power signal terminal HAVDD, and the second control terminal CN2, and is used to respond to the signal of the second control terminal CN2 to communicate with the The high level terminal of the second amplifier OP2 and the fifth power signal terminal HAVDD.
  • the first switching unit 11 may include a first switching transistor T1, The first terminal of the first switch transistor is connected to the low level terminal of the first amplifier OP1, the second terminal is connected to the second power signal terminal HAVDD-, and the control terminal is connected to the first control terminal CN1;
  • the second switch The unit 12 may include a second switching transistor T2, the first terminal of the second switching transistor is connected to the high-level terminal of the second amplifier OP2, the second terminal is connected to the third power signal terminal HAVDD+, and the control terminal is connected to the first Control terminal CN1;
  • the third switch unit 13 may include a third switch transistor T3, the first terminal of the third switch transistor is connected to the low level terminal of the first amplifier OP1, and the second terminal is connected to the fifth power supply
  • the signal terminal HAVDD, the control terminal is connected to the second control terminal CN2;
  • the fourth switch unit 14 may include a fourth switch transistor T1
  • FIG. 9 it is a schematic structural diagram of another exemplary embodiment of the source drive circuit of the present disclosure.
  • the source drive circuit further includes: a detection circuit 2, an arithmetic circuit 3, and a control circuit 4.
  • the detection circuit 2 is used to detect the potential of the effective pulse signal of each row of the original drive signal in real time;
  • the calculation circuit 3 is connected to the detection circuit 2 and is used to calculate the effective pulse signal of the current row and the effective pulse signal of the previous row in real time according to the potential of the effective pulse signal of each row The potential difference of the pulse signal;
  • the control circuit 4 is connected to the arithmetic circuit and the switch assembly, and is used to send a control signal to the switch assembly according to the potential difference between the effective pulse signal of the current row and the effective pulse signal of the previous row to control the The driving state of the switch component; wherein, when the potential difference between the effective pulse signal of the current row and the effective pulse signal of the previous row is greater than a preset value, the switch component is controlled to work in the first driving state
  • This setting can control the driving state of the switch component in real time, thereby solving the technical problem that the data signal cannot reach the preset voltage within the adjacent effective pulse interval; at the same time, it solves the technical problem of high power consumption of the source drive circuit.
  • the switch assembly can be controlled to operate in the first driving state during a part of the period of the effective pulse of the current row.
  • the switch component works in the first driving state during all periods of the effective pulse of the current row.
  • This exemplary embodiment also provides a source driving circuit driving method for driving the above-mentioned source driving circuit.
  • FIG. 10 it is a flowchart of an exemplary embodiment of the source driving circuit driving method of the present disclosure. , The method includes:
  • Step S1 In the forward driving stage, the first amplifier is used to output a positive driving signal
  • Step S2 In the reverse driving stage, the second amplifier is used to output a negative polarity driving signal.
  • the source driving circuit further includes a switch component
  • the method further includes:
  • the low-level terminal and the second power signal terminal of the first amplifier are turned on, and the high-level terminal and the third power signal terminal of the second amplifier are turned on;
  • the low-level terminal and the fifth power signal terminal of the first amplifier are turned on, and the high-level terminal and the fifth power signal terminal of the second amplifier are turned on.
  • the source drive circuit further includes a detection circuit, an arithmetic circuit, and a control circuit
  • the method further includes:
  • the switch assembly is controlled to work in the second driving state during the driving period of the current row.
  • the source driving circuit driving method provided in the present disclosure has the same technical features and working principles as the above-mentioned source driving circuit, and the above content has been described in detail, and will not be repeated here.
  • This exemplary embodiment also provides a display device including the above-mentioned source driving circuit.
  • the display device provided by the present disclosure has the same technical features and working principles as the above-mentioned source driving circuit, and the above-mentioned content has been explained in detail, and will not be repeated here.
  • the display device may include, but is not limited to, display devices such as televisions, mobile phones, VR display devices, and notebooks.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种源极驱动电路，该源极驱动电路包括用于根据原始驱动信号生成驱动信号的缓冲放大器，缓冲放大器包括：第一放大器(OP1)、第二放大器(OP2)。第一放大器(OP1)的高电平端与第一电源信号端(AVDD)连接，低电平端与第二电源信号端(HAVDD-)连接，输出端用于输出正极性驱动信号；第二放大器(OP2)的高电平端与第三电源信号端(HAVDD+)连接，低电平端与第四电源信号端(VSS)连接，输出端用于输出负极性驱动信号；其中，第二电源信号端(HAVDD-)的电压小于第三电源信号端(HAVDD+)的电压。源极驱动电路通过增加第一放大器(OP1)、第二放大器(OP2)高电平端和低电平端的压差，从而增加了缓冲放大器输出驱动信号的速度，减小驱动信号生成的时间。

Description

源极驱动电路及驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种源极驱动电路及驱动方法、显示装置。
背景技术
显示面板通常采用逐行扫描的方式实现画面的显示。在一帧的显示时间内，控制芯片需要逐行扫描显示区域内的所有像素单元。
随着显示面板帧率的提高，每一行子像素单元的充电时间越来越小，如何使得每一像素单元能够达到预设的充电要求，已经成为显示面板设计的关键问题。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种源极驱动电路，包括用于根据原始驱动信号生成驱动信号的缓冲放大器，所述缓冲放大器包括：第一放大器、第二放大器。第一放大器的高电平端与第一电源信号端连接，低电平端与第二电源信号端连接，输出端用于输出正极性驱动信号；第二放大器的高电平端与第三电源信号端连接，低电平端与第四电源信号端连接，输出端用于输出负极性驱动信号；其中，所述第二电源信号端的电压小于第三电源信号端的电压。
本公开的一种示例性实施例中，所述第一电源信号端的电压为模拟电源信号电压；所述第四电源信号端的电压为接地端的电压；所述第二电源信号端的电压小于半值模拟电源信号的电压；所述第三电源信号端的电压大于半值模拟电源信号的电压。
本公开的一种示例性实施例中，所述缓冲放大器还包括开关组件；所述第一放大器的低电平端通过所述开关组件与所述第二电源信号端连接、第五电源信号端择一连接；所述第二放大器的高电平端通过所述开关组件与所述第三电源信号端、所述第五电源信号端择一连接；所述开关组件用于：在第一驱动状态下，连接所述第一放大器的低电平端与所述第二电源信号端，以及连接所述第二放大器的高电平端与所述第三电源信号端；在第二驱动状态下，连接所述第一放大器的低电平端与所述第五电源信号端，以及连接第二放大器的高电平端与所述第五电源信号端。
本公开的一种示例性实施例中，所述第五电源信号端的电压等于半值模拟电源信号的 电压。
本公开的一种示例性实施例中，所述源极驱动电路还包括：检测电路、运算电路、控制电路。检测电路用于实时检测所述原始驱动信号各行有效脉冲信号的电位；运算电路与所述检测电路连接，用于根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；控制电路与所述运算电路、开关组件连接，用于根据当前行有效脉冲信号与上一行有效脉冲信号的电位差向所述开关组件发送一控制信号，以控制所述开关组件的驱动状态；其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。
本公开的一种示例性实施例中，所述开关组件包括：第一开关单元、第二开关单元、第三开关单元、第四开关单元。第一开关单元连接所述第一放大器的低电平端、所述第二电源信号端、第一控制端，用于响应所述第一控制端的信号以连通所述第一放大器的低电平端与所述第二电源信号端；第二开关单元连接所述第二放大器的高电平端、所述第三电源信号端、第一控制端，用于响应所述第一控制端的信号以连通所述第二放大器的高电平端与所述第三电源信号端；第三开关单元连接所述第一放大器的低电平端、所述第五电源信号端、第二控制端，用于响应所述第二控制端的信号以连通所述第一放大器的低电平端与所述第五电源信号端；第四开关单元连接所述第二放大器的高电平端、所述第五电源信号端、所述第二控制端，用于响应所述第二控制端的信号以连通所述第二放大器的高电平端与所述第五电源信号端。
本公开的一种示例性实施例中，所述第一开关单元包括第一开关晶体管，第一开关晶体管的第一端连接所述第一放大器的低电平端，第二端连接所述第二电源信号端，控制端连接所述第一控制端；
所述第二开关单元包括第二开关晶体管，第二开关晶体管的第一端连接所述第二放大器的高电平端，第二端连接所述第三电源信号端，控制端连接所述第一控制端；
所述第三开关单元包括第三开关晶体管，第三开关晶体管的第一端连接所述第一放大器的低电平端，第二端连接所述所述第五电源信号端，控制端连接所述第二控制端；
所述第四开关单元包括第四开关晶体管，第四开关晶体管的第一端连接所述第二放大器的高电平端，第二端连接所述所述第五电源信号端，控制端连接所述所述第二控制端。
本公开的一种示例性实施例中，所述第一开关晶体管、第二开关晶体管、第三开关晶 体管、第四开关晶体管为N型晶体管或P型晶体管。
根据本公开的一个方面，提供一种源极驱动电路驱动方法，用于驱动上述的源极驱动电路，该方法包括：
在正向驱动阶段，利用第一放大器输出正极性驱动信号；
在反向驱动阶段，利用第二放大器输出负极性驱动信号。
本公开的一种示例性实施例中，所述源极驱动电路还包括开关组件，所述方法还包括：
利用所述开关组件：
在第一驱动状态下，导通第一放大器的低电平端与第二电源信号端，以及导通第二放大器的高电平端与第三电源信号端；
在第二驱动状态下，导通第一放大器的低电平端与第五电源信号端，以及导通第二放大器的高电平端与第五电源信号端。
本公开的一种示例性实施例中，所述源极驱动电路还包括检测电路、运算电路、控制电路，所述方法还包括：
利用检测电路实时检测原始驱动信号各行有效脉冲信号的电位；
利用运算电路根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；
利用控制电路根据当前行有效脉冲信号与上一行有效脉冲信号的电位差向所述开关组件发送一控制信号，以控制所述开关组件的驱动状态；
其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；
当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的源极驱动电路。
本公开提供一种源极驱动电路及驱动电路、显示装置，该源极驱动电路包括用于根据原始驱动信号生成驱动信号的缓冲放大器，所述缓冲放大器包括：第一放大器、第二放大器。第一放大器的高电平端与第一电源信号端连接，低电平端与第二电源信号端连接，输出端用于输出正极性驱动信号；第二放大器的高电平端与第三电源信号端连接，低电平端与第四电源信号端连接，输出端用于输出负极性驱动信号；其中，所述第二电源信号端的电压小于第三电源信号端的电压。一方面，本公开提供源极驱动电路可以通过提高模拟电源信号AVDD的电压提高其输出的驱动信号的电压，从而解决子像素单元充电不足的技 术问题；另一方面，本公开提供的源极驱动电路通过增加第一放大器、第二放大器高电平端和低电平端的压差，从而增加了放大器输出电压变化的速度，减小驱动信号生成的时间，进而解决了由于模拟电源信号AVDD增加造成的驱动信号生成时间变长的技术问题；此外，通过将所述第二电源信号端的电平设置为小于第三电源信号端的电平，可以减小正向驱动0灰阶的电压以及增加反向驱动0灰阶的电压，即增大数据信号变为0灰阶时的目标压降，从而增加数据信号压降的速率，从而进一步缩短数据信号转变为0灰阶的速度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中源极驱动电路的结构示意图；
图2为相关技术中源极驱动电路输出信号的时序图；
图3为本公开源极驱动电路一种示例性实施例的结构示意图；
图4为本公开源极驱动电路一种示例性实施例中输出信号的时序图；
图5为相关技术与本公开中源极驱动电路输出驱动信号生成画面的对比图；
图6为本公开源极驱动电路另一种示例性实施例的结构示意图；
图7为本公开源极驱动电路另一种示例性实施例的结构示意图；
图8为本公开源极驱动电路另一种示例性实施例的结构示意图；
图9为本公开源极驱动电路另一种示例性实施例的结构示意图；
图10为本公开源极驱动电路驱动方法一种示例性实施例的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的 方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，随着显示面板帧率的提高，每一行子像素单元的充电时间越来越小，再考虑到数据线路电阻及其寄生电容造成的压降，从而使得远离源极驱动电路一侧的子像素单元的充电电压不能达到预设要求，最终造成显示面板显示不均匀。
基于上述技术问题，同时鉴于模拟电源信号AVDD为源极驱动电路提供基准电源，相关技术可以通过提高模拟电源信号AVDD的电压以提高驱动信号的电压，从而解决上述技术问题。然而，提高模拟电源信号AVDD后，驱动信号相邻行有效脉冲的电位差会有所增加。例如，以第一行显示255灰阶，第二行显示0灰阶为例，当模拟电源信号AVDD电压为18V时，第一行有效脉冲电压为16V，第二行有效脉冲电压为8V；当模拟电源信号AVDD电压为20V时，第一行有效脉冲电压为18V，第二行有效脉冲电压为9V。显然，前者相邻行有效脉冲电压的压差(8V)小于后者相邻行有效脉冲电压的压差(9V)。
如图1所示，为相关技术中源极驱动电路的结构示意图，相关技术中，源极驱动电路可以包括用于根据原始驱动信号生成驱动信号的缓冲放大器，相关技术中，所述缓冲放大器可以包括：第一放大器OP11、第二放大器OP12。第一放大器OP11的高电平端接收模拟电源信号AVDD，低电平端接收半值模拟电源信号HAVDD，输出端用于输出正极性驱动信号；第二放大器OP12的高电平端接收半值模拟电源信号HAVDD，低电平端连接接地端GND，输出端用于输出负极性驱动信号。该缓冲放大器用于提信号的带载能力，以将带载能力较弱的原始驱动信号转换为带载能力较强的驱动信号。如图2所述，为相关技术中源极驱动电路输出信号的时序图，OP11指第一放大器OP11输出的正极性驱动信号，OP12指第二放大器OP12输出的负极性驱动信号，LV255指驱动信号在255灰度下的电压，LV0指驱动信号在0灰度下的电压。其中，第一放大器OP11输出驱动信号的电压范围在半值模拟电源信号HAVDD的电压到模拟电源信号AVDD的电压之间，第二放大器OP12输出驱动信号的电压范围在半值模拟电源信号HAVDD的电压到接地端GND的电压之间。由于第一放大器OP11和第二放大器OP12共用半值模拟电源信号HAVDD，因此，在0灰度下，正极性驱动信号的电压与负极性驱动信号的电压相等。
由于该缓冲放大器转化信号也需要时间，且原始驱动信号相邻行脉冲信号的压差越大该缓冲放大器转化信号所需时间越长。因此，模拟电源信号AVDD电压的增加会增加源极驱动电路输出驱动信号的时间。从而导致数据信号在相邻有效脉冲间隔时间内无法达到 预设电压。
基于上述问题，本示例性实施例提供一种源极驱动电路，如图3所示，为本公开源极驱动电路一种示例性实施例的结构示意图，该源极驱动电路包括用于根据原始驱动信号生成驱动信号的缓冲放大器，所述缓冲放大器包括：第一放大器OP1、第二放大器OP2。第一放大器OP1的高电平端与第一电源信号端AVDD连接，低电平端与第二电源信号端HAVDD-连接，输出端用于输出正极性驱动信号；第二放大器OP2的高电平端与第三电源信号端HAVDD+连接，低电平端与第四电源信号端VSS连接，输出端用于输出负极性驱动信号；其中，所述第二电源信号端HAVDD-的电平小于第三电源信号端HAVDD+的电平。
其中，第一电源信号端AVDD的电压可以为模拟电源信号AVDD的电压，第二电源信号端HAVDD-的电压可以小于半值模拟电源信号HAVDD的电压，第三电源信号端HAVDD+的电压可以大于半值模拟电源信号HAVDD的电压，第四电源信号端VSS的电压可以为接地端的电压。第二电源信号端HAVDD-的电压位于第一电源信号端AVDD电压和第四电源信号端VSS电压之间；第三电源信号端HAVDD+的电压位于第一电源信号端AVDD电压和第四电源信号端VSS电压之间。
如图4所述，为本公开源极驱动电路一种示例性实施例中输出信号的时序图，OP1指第一放大器OP1输出的正极性驱动信号，OP2指第二放大器OP2输出的负极性驱动信号，LV255指驱动信号在255灰度下的电压，LV0指驱动信号在0灰度下的电压。其中，第一放大器OP1输出驱动信号的电压范围在第二电源信号端HAVDD-的电压到第一电源信号端AVDD的电压之间，第二放大器OP2输出驱动信号的电压范围在第三电源信号端HAVDD+的电压到第四电源信号端VSS的电压之间。其中，由于第二电源信号端HAVDD-的电压小于第三电源信号端HAVDD+的电压，在0灰阶时，第一放大器OP1输出驱动信号的电压小于第二放大器OP2输出驱动信号的电压。
本公开提供一种源极驱动电路，一方面，本公开提供的源极驱动电路可以通过提高模拟电源信号AVDD的电压提高其输出的驱动信号的电压，从而解决子像素单元充电不足的技术问题；另一方面，本公开提供的源极驱动电路通过增加第一放大器、第二放大器高电平端和低电平端的压差，从而增加了放大器输出电压变化的速度，减小驱动信号生成的时间，进而解决了由于模拟电源信号AVDD增加造成的驱动信号生成时间变长的技术问题；此外，在正负极性驱动中，0灰度的伽马电压分别对应第二电源信号端HAVDD-、第三电源信号端HAVDD+的电压，通过将所述第二电源信号端的电平设置为小于第三电源信号端的电平，可以减小正极性驱动下0灰阶的电压以及增加负极性驱动下0灰阶的电压，即增大数据信号变为0灰阶时的目标压降，从而增加数据信号压降的速率，进而进一步缩短数据信号转变为0灰阶的速度。如图5所示，为相关技术与本公开中源极驱动电路输出驱动信号生成画面的对比图，其中，左侧图为相关技术中源极驱动电路输出驱动信号生成 的画面，右侧为本公开中源极驱动电路输出驱动信号生成的画面，左侧画面和右侧画面均为相同图像信号驱动下形成的画面。显然，左侧画面黑白对比度小于右侧画面的黑白对比度，具体表现为，右侧画面中“BOE”字样的清晰程度高于左侧画面中“BOE”字样的清晰程度。
本示例性实施例中，该源极驱动电路设置有两个电源信号端：第二电源信号端HAVDD-、第三电源信号端HAVDD+的电压，该设置虽然可以改善显示效果，但也会增加源极驱动电路的功耗。当驱动信号相邻行有效脉冲的电压差较小时，并不会存在上述“数据信号在相邻有效脉冲间隔时间内无法达到预设电压”的技术问题。如图6所示，为本公开源极驱动电路另一种示例性实施例的结构示意图，所述缓冲放大器还可以包括开关组件1；所述第一放大器OP1的低电平端通过所述开关组件1与所述第二电源信号端HAVDD-、第五电源信号端HAVDD择一连接；所述第二放大器OP2的高电平端通过所述开关组件与所述第三电源信号端HAVDD+、所述第五电源信号端HAVDD择一连接；所述开关组件用于：在第一驱动状态下，连接所述第一放大器OP1的低电平端与所述第二电源信号端HAVDD-，以及连接所述第二放大器OP2的高电平端与所述第三电源信号端HAVDD+；在第二驱动状态下，连接所述第一放大器OP1的低电平端与所述第五电源信号端HAVDD，以及连接第二放大器OP2的高电平端与所述第五电源信号端HAVDD。其中，当驱动信号相邻行有效脉冲的电压差较大时，开关组件工作于第一驱动状态，从而解决数据信号在相邻有效脉冲间隔时间内无法达到预设电压的技术问题；其中，当驱动信号相邻行有效脉冲的电压差较小时，开关组件工作于第二驱动状态，从而解决源极驱动电路耗功耗较大的技术问题。
本示例性实施例中，如图7所示，为本公开源极驱动电路另一种示例性实施例的结构示意图，所述开关组件可以包括：第一开关单元11、第二开关单元12、第三开关单元13、第四开关单元14。第一开关单元11连接所述第一放大器OP1的低电平端、所述第二电源信号端HAVDD-、第一控制端CN1，用于响应所述第一控制端CN1的信号以连通所述第一放大器OP1的低电平端与所述第二电源信号端HAVDD-；第二开关单元12连接所述第二放大器OP2的高电平端、所述第三电源信号端HAVDD+、第一控制端CN1，用于响应所述第一控制端CN1的信号以连通所述第二放大器OP2的高电平端与所述第三电源信号端HAVDD+；第三开关单元13连接所述第一放大器OP1的低电平端、所述第五电源信号端HAVDD、第二控制端CN2，用于响应所述第二控制端CN2的信号以连通所述第一放大器OP1的低电平端与所述第五电源信号端HAVDD；第四开关单元14连接所述第二放大器OP2的高电平端、所述第五电源信号端HAVDD、所述第二控制端CN2，用于响应所述第二控制端CN2的信号以连通所述第二放大器OP2的高电平端与所述第五电源信号端HAVDD。
如图8所示，为本公开源极驱动电路另一种示例性实施例的结构示意图，本公开的一 种示例性实施例中，所述第一开关单元11可以包括第一开关晶体管T1，第一开关晶体管的第一端连接所述第一放大器OP1的低电平端，第二端连接所述第二电源信号端HAVDD-，控制端连接所述第一控制端CN1；所述第二开关单元12可以包括第二开关晶体管T2，第二开关晶体管的第一端连接所述第二放大器OP2的高电平端，第二端连接所述第三电源信号端HAVDD+，控制端连接所述第一控制端CN1；所述第三开关单元13可以包括第三开关晶体管T3，第三开关晶体管的第一端连接所述第一放大器OP1的低电平端，第二端连接所述所述第五电源信号端HAVDD，控制端连接所述第二控制端CN2；所述第四开关单元14可以包括第四开关晶体管T4，第四开关晶体管的第一端连接所述第二放大器OP2的高电平端，第二端连接所述所述第五电源信号端，控制端连接所述所述第二控制端CN2。其中，所述第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管为N型晶体管或P型晶体管。
本示例性实施例中，如图9所示，为本公开源极驱动电路另一种示例性实施例的结构示意图，所述源极驱动电路还包括：检测电路2、运算电路3、控制电路4。检测电路2用于实时检测所述原始驱动信号各行有效脉冲信号的电位；运算电路3与所述检测电路2连接，用于根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；控制电路4与所述运算电路、开关组件连接，用于根据当前行有效脉冲信号与上一行有效脉冲信号的电位差向所述开关组件发送一控制信号，以控制所述开关组件的驱动状态；其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。该设置可以实时控制开关组件的驱动状态，从而即解决了数据信号在相邻有效脉冲间隔时间内无法达到预设电压的技术问题；同时解决了源极驱动电路耗功耗较大的技术问题。其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，即可以控制所述开关组件在当前行有效脉冲的部分时段工作于所述第一驱动状态，也可以控制所述开关组件在当前行有效脉冲的全部时段工作于所述第一驱动状态。
本示例性实施例还提供一种源极驱动电路驱动方法，用于驱动上述的源极驱动电路，如图10所示，为本公开源极驱动电路驱动方法一种示例性实施例的流程图，该方法包括：
步骤S1：在正向驱动阶段，利用第一放大器输出正极性驱动信号；
步骤S2：在反向驱动阶段，利用第二放大器输出负极性驱动信号。
本示例性实施例中，所述源极驱动电路还包括开关组件，所述方法还包括：
利用所述开关组件：
在第一驱动状态下，导通第一放大器的低电平端与第二电源信号端，以及导通第二放大器的高电平端与第三电源信号端；
在第二驱动状态下，导通第一放大器的低电平端与第五电源信号端，以及导通第二放 大器的高电平端与第五电源信号端。
本示例性实施例中，所述源极驱动电路还包括检测电路、运算电路、控制电路，所述方法还包括：
利用检测电路实时检测原始驱动信号各行有效脉冲信号的电位；
利用运算电路根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；
利用控制电路根据当前行有效脉冲信号与上一行有效脉冲信号的电位差向所述开关组件发送一控制信号，以控制所述开关组件的驱动状态；
其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；
当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。
本公开提供的源极驱动电路驱动方法与上述的源极驱动电路具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。
本示例性实施例还提供一种显示装置，该显示装置包括上述的源极驱动电路。
本公开提供的显示装置与上述的源极驱动电路具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。
该显示装置可以包括但不限于电视机、手机、VR显示设备、笔记本等显示设备。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。

Claims (12)

  1. 一种源极驱动电路，该源极驱动电路包括用于将原始驱动信号生成驱动信号的缓冲放大器，其中，所述缓冲放大器包括：
    第一放大器，高电平端与第一电源信号端连接，低电平端与第二电源信号端连接，输出端用于输出正极性驱动信号；
    第二放大器，高电平端与第三电源信号端连接，低电平端与第四电源信号端连接，输出端用于输出负极性驱动信号；
    其中，所述第二电源信号端的电压小于第三电源信号端的电压。
  2. 根据权利要求1所述的源极驱动电路，其中，所述第一电源信号端的电压为模拟电源信号电压；
    所述第四电源信号端的电压为接地端的电压；
    所述第二电源信号端的电压小于半值模拟电源信号的电压；
    所述第三电源信号端的电压大于半值模拟电源信号的电压。
  3. 根据权利要求1所述的源极驱动电路，其中，所述缓冲放大器还包括开关组件；
    所述第一放大器的低电平端通过所述开关组件与所述第二电源信号端连接、第五电源信号端择一连接；
    所述第二放大器的高电平端通过所述开关组件与所述第三电源信号端、所述第五电源信号端择一连接；
    所述开关组件用于：
    在第一驱动状态下，连接所述第一放大器的低电平端与所述第二电源信号端，以及连接所述第二放大器的高电平端与所述第三电源信号端；
    在第二驱动状态下，连接所述第一放大器的低电平端与所述第五电源信号端，以及连接所述第二放大器的高电平端与所述第五电源信号端。
  4. 根据权利要求3所述的源极驱动电路，其中，所述第五电源信号端的电压等于半值模拟电源信号的电压。
  5. 根据权利要求3所述的源极驱动电路，其中，所述源极驱动电路还包括：
    检测电路，用于实时检测所述原始驱动信号各行有效脉冲信号的电位；
    运算电路，与所述检测电路连接，用于根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；
    控制电路，与所述运算电路、开关组件连接，用于根据当前行有效脉冲信号与上一行 有效脉冲信号的电位差向所述开关组件发送控制信号，以控制所述开关组件的驱动状态；
    其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；
    当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。
  6. 根据权利要求3所述的源极驱动电路，其中，所述开关组件包括：
    第一开关单元，连接所述第一放大器的低电平端、所述第二电源信号端、第一控制端，用于响应所述第一控制端的信号以连通所述第一放大器的低电平端与所述第二电源信号端；
    第二开关单元，连接所述第二放大器的高电平端、所述第三电源信号端、第一控制端，用于响应所述第一控制端的信号以连通所述第二放大器的高电平端与所述第三电源信号端；
    第三开关单元，连接所述第一放大器的低电平端、所述第五电源信号端、第二控制端，用于响应所述第二控制端的信号以连通所述第一放大器的低电平端与所述第五电源信号端；
    第四开关单元，连接所述第二放大器的高电平端、所述第五电源信号端、所述第二控制端，用于响应所述第二控制端的信号以连通所述第二放大器的高电平端与所述第五电源信号端。
  7. 根据权利要求6所述的源极驱动电路，其中，所述第一开关单元包括：
    第一开关晶体管，第一端连接所述第一放大器的低电平端，第二端连接所述第二电源信号端，控制端连接所述第一控制端；
    所述第二开关单元包括：
    第二开关晶体管，第一端连接所述第二放大器的高电平端，第二端连接所述第三电源信号端，控制端连接所述第一控制端；
    所述第三开关单元包括：
    第三开关晶体管，第一端连接所述第一放大器的低电平端，第二端连接所述所述第五电源信号端，控制端连接所述第二控制端；
    所述第四开关单元包括：
    第四开关晶体管，第一端连接所述第二放大器的高电平端，第二端连接所述所述第五电源信号端，控制端连接所述所述第二控制端。
  8. 根据权利要求7所述的源极驱动电路，其中，所述第一开关晶体管、第二开关晶体管、第三开关晶体管、第四开关晶体管为N型晶体管或P型晶体管。
  9. 一种源极驱动电路驱动方法，用于驱动权利要求1-8任一项所述的源极驱动电路，其中，包括：
    在正向驱动阶段，利用第一放大器输出正极性驱动信号；
    在反向驱动阶段，利用第二放大器输出负极性驱动信号。
  10. 根据权利要求9所述的源极驱动电路驱动方法，其中，所述源极驱动电路还包括开关组件，所述方法还包括：
    利用所述开关组件：
    在第一驱动状态下，导通第一放大器的低电平端与第二电源信号端，以及导通第二放大器的高电平端与第三电源信号端；
    在第二驱动状态下，导通第一放大器的低电平端与第五电源信号端，以及导通第二放大器的高电平端与第五电源信号端。
  11. 根据权利要求10所述的源极驱动电路驱动方法，其中，所述源极驱动电路还包括检测电路、运算电路、控制电路，所述方法还包括：
    利用检测电路实时检测原始驱动信号各行有效脉冲信号的电位；
    利用运算电路根据各行有效脉冲信号的电位实时计算当前行有效脉冲信号与上一行有效脉冲信号的电位差；
    利用控制电路根据当前行有效脉冲信号与上一行有效脉冲信号的电位差向所述开关组件发送一控制信号，以控制所述开关组件的驱动状态；
    其中，当前行有效脉冲信号与上一行有效脉冲信号的电位差大于预设值时，控制所述开关组件在当前行的至少部分时段工作于所述第一驱动状态；
    当前行有效脉冲信号与上一行有效脉冲信号的电位差小于预设值时，控制所述开关组件在当前行驱动时段内工作于所述第二驱动状态。
  12. 一种显示装置，其中，包括权利要求1-8任一项所述的源极驱动电路。
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