WO2021054321A1 - Dispositif à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif à semi-conducteur et son procédé de fabrication Download PDF

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WO2021054321A1
WO2021054321A1 PCT/JP2020/034906 JP2020034906W WO2021054321A1 WO 2021054321 A1 WO2021054321 A1 WO 2021054321A1 JP 2020034906 W JP2020034906 W JP 2020034906W WO 2021054321 A1 WO2021054321 A1 WO 2021054321A1
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semiconductor device
film
layer
inorganic film
manufacturing
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Japanese (ja)
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上田　大助
和樹 児玉
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国立大学法人東海国立大学機構
有限会社アルファシステム
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, particularly a semiconductor device having a self-aligned laminated electrode of a semiconductor epi layer and a conductive layer and a method for manufacturing the same.
  • Group III nitride wide-gap semiconductors represented by GaN are being applied to power devices that require high output and high voltage operation due to their features of high withstand voltage and high electron mobility. Since such a group III nitride semiconductor has a large band gap, the development of an ohmic contact electrode on the group III nitride semiconductor is one of the important issues.
  • Patent Document 1 discloses a method of forming alloy contacts at the source and drain of a transistor by using a lift-off method.
  • a material having a work function suitable for the conductive type of the base is used in order to realize ohmic contact.
  • further improvements are needed to reduce contact resistance.
  • different electrode materials are used on the n-type semiconductor and the p-type semiconductor, there is also a problem that the contact electrode forming process becomes complicated.
  • the method for manufacturing a semiconductor device is as follows.
  • PLD Pulse Laser Deposition
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the first inorganic film is composed of silicon oxide and is composed of silicon oxide.
  • the conductive film has hydrofluoric acid resistance and
  • the sixth step is characterized in that the first inorganic film is wet-etched with hydrofluoric acid.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the second inorganic film is characterized by being composed of Si, Ge or a mixture thereof.
  • n-type impurities can be introduced into n-type GaN (autodoping) by the vapor pressure of Si or Ge when the group III nitride layer is heated. Therefore, the impurity concentration of n-type GaN can be further increased.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the second inorganic film is characterized by being composed of Ru, Re or WN (tungsten nitride).
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the conductive film is characterized in that it is composed of TiN, WN or TaN.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the group III nitride layer contains at least a p-type group III nitride layer in contact with the n-type GaN.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the group III nitride layer is a cathode and an anode of a diode.
  • the characteristics of the diode can be improved.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the group III nitride layer is a source and a drain of the FET.
  • the distance between the source and drain electrodes of the FET can be shortened, and the on-resistance can be reduced.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the group III nitride layer is characterized by being a first clad layer having an n-type conductive type of LED and a second clad layer having a p-type conductive type.
  • the method for manufacturing a semiconductor device according to the present invention is as follows.
  • the LED is an ultraviolet LED
  • the n-type GaN film formed in the fourth step is characterized in that the optical bandgap is increased by the Bernstein moss shift effect.
  • the method for manufacturing a semiconductor device is as follows.
  • the luminous efficiency of the ultraviolet LED can be improved.
  • the semiconductor device according to the present invention is A semiconductor device having an electrode structure in which a pattern consisting of a laminated film of an Epi-n type GaN layer and a conductive film is formed on a p-type Group III nitride layer. In the cross section of the interface of the laminated film, the lower surface of the conductive film is symmetrical with respect to the upper surface of the Epi-n type GaN layer.
  • the semiconductor device according to the present invention is
  • the conductive film is characterized by being a metal or a metal compound having hydrofluoric acid resistance.
  • a tunnel junction can be realized between the p-type GaN layer and the Epi-n type GaN.
  • the semiconductor device according to the present invention is The Epi-n type GaN layer is characterized in that the optical bandgap is increased by the Burstein Moss shift effect.
  • the absorption of ultraviolet light by the Epi-n type GaN layer is reduced, and it can be suitably applied as a contact electrode of the clad layer of an LED (light emitting diode).
  • the present invention it is possible to provide a semiconductor device having a contact electrode capable of reducing contact resistance with a group III nitride and a method for manufacturing the same.
  • FIG. 5 is a cross-sectional view showing a main step for forming a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing a main step for forming a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the first embodiment.
  • FIG. 5 is a cross-sectional view showing a main step for forming a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the second embodiment.
  • FIG. 5 is a cross-sectional view of a diode having a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the third embodiment.
  • FIG. 5 is a cross-sectional view of a FET having a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the fourth embodiment.
  • FIG. 5 is a cross-sectional view showing a part of a main step for manufacturing an LED having a self-aligned contact electrode between a semiconductor epi layer and a conductive layer according to the fifth embodiment.
  • the schematic diagram which shows the impurity concentration dependence of the energy band of GaN and AlGaN. Graph showing an example of the result of full band calculation. Graph showing the relationship between carrier concentration and (n e) and the energy shift Delta] E g.
  • the experimental figure which shows the relationship between the mixed crystal ratio of the Mg-doped AlGaN layer and the acceptor ionization energy.
  • FIG. 1 is a cross-sectional view showing a main manufacturing process of a self-aligned contact electrode.
  • a substrate 100 for example, an epi substrate in which p + GaN layer 2 is formed on the epi layer 1 of GaN is prepared.
  • the first inorganic film 3 for example, silicon oxide (SiO 2 )
  • a second inorganic film 4 for example, Si, Ge or Si and Ge
  • CVD method CVD using SiH 4 or GeH 4
  • PVD method PVD method
  • a pattern of the photoresist film is formed by a lithography method, and the second inorganic film 4 is preferably used by using the pattern of the photoresist film as a mask, for example, anisotropic dry etching or the like.
  • the second inorganic 4a (hereinafter, may be simply referred to as the second inorganic 4a) is obtained by patterning by etching with the above. After that, the photoresist film is removed by ashing or the like.
  • the first inorganic film 3 is selectively equalized by isotropic etching (for example, wet etching using hydrofluoric acid) with the second inorganic film 4a as a mask.
  • a first inorganic film 3a (hereinafter, may be simply referred to as a first inorganic 3a) that is anisotropically etched to be patterned is obtained. Therefore, the second inorganic 4a and the first inorganic film 3a have the same pattern shape when viewed from the upper surface.
  • the wet etching may be a batch method or a single-wafer method. Further, since the GaN-based semiconductor and the second inorganic film 4 (Si, Ge) have hydrofluoric acid resistance, they are not etched in this step.
  • the side surface of the first inorganic film 3a is retracted by isotropic etching, and the cross section of the second inorganic film 4a has an overhang shape protruding from the side surface of the first inorganic film 3 in an eaves shape. Become. Further, the p + GaN layer (p-type GaN layer) 2 is exposed in the region not covered by the first inorganic film 3a. It should be noted that isotropic etching may be used, and isotropic dry etching may be used.
  • a film thickness of 10 [nm] or more and an n-type impurity concentration of 5 ⁇ 10 20 [/ cm 3 ] or more) are formed on the substrate 100.
  • it grows epitaxially on the exposed GaN layer (p + GaN layer 2 in the figure) to form a single crystal Epi-n ++ GaN layer (Epi-n type GaN layer) 51, but the second inorganic film.
  • a polycrystalline poly-n ++ GaN layer (poly-n type GaN layer) 52 is formed.
  • the Epi-n ++ GaN layer 51 becomes a pn junction on the p ++ GaN layer 2, but becomes an ohmic contact due to the tunnel junction.
  • Ga or GaN containing n-type dopant Si or Ge is used as the target, and the target is evaporated by a pulse laser (for example, a picosecond laser) while supplying nitrogen radicals, thereby n-type GaN. Can be formed.
  • the second inorganic film 4a formed on the substrate 100 is composed of Si or Ge, Si or Ge evaporated from the second inorganic film 4a when the n-type GaN is formed by the PLD method. Is doped into n-type GaN. As a result, the concentration of n-type impurities in GaN can be increased.
  • Ge has a higher vapor pressure at a lower temperature than Si, it can be more preferably used as a doping material for n-type GaN film formation.
  • the target material evaporates instantly at the location irradiated with the pulse laser to form a film on the substrate to be deposited, and the directivity of the film-formed particles is higher than that of other vapor deposition methods. high. Therefore, the Epi-n ++ GaN layer 51 and the poly-n ++ GaN layer 52 do not come into contact with each other due to the overhang-shaped second inorganic film 4.
  • the conductive film 6 for electrodes (for example, Ni, W, TiN, WN, TaN, etc.) is continuously subjected to the PLD method to resist hydrofluoric acid. A certain metal, alloy or metal compound, or a laminated film thereof) is formed. If a Ga (GaN) target and a metal target are prepared in the PLD device and the targets are replaced in the PLD device, the n ++ GaN layer (Epi-n ++ GaN layer 51, poly-) is continuously maintained while maintaining the vacuum. The n ++ GaN layer 52) and the conductive film 6 can be formed.
  • a Ga (GaN) target and a metal target are prepared in the PLD device and the targets are replaced in the PLD device, the n ++ GaN layer (Epi-n ++ GaN layer 51, poly-) is continuously maintained while maintaining the vacuum.
  • the n ++ GaN layer 52) and the conductive film 6 can be formed.
  • the metal (Ti, W, Ta) is evaporated by the PLD method while irradiating the nitrogen radical, and the nitrogen radical reacts with the metal (Ti, W, Ta).
  • a film can be formed by allowing the film to be formed. Since TiN, WN, and TaN can be formed without interrupting nitrogen radicals, nitrogen escape from the GaN layer can be prevented. Further, hydrofluoric acid-resistant metals generally tend to have weak adhesion to the Epi-n ++ GaN layer 51, whereas metal nitrides such as TiN, WN, and TaN have an extremely high adhesion strength. It has and can be suitably formed directly above the Epi-n ++ GaN layer 51.
  • the conductive film 6 is formed on the Epi-n ++ GaN layer 51 and the poly-n ++ GaN layer 52, but as described above, the film formation by the PLD method has a directivity as compared with other PVD methods. Since it is high, the conductive films 6 formed on these films do not come into contact with (connect to) each other. High directivity means that the angular distribution of particles emitted from the target surface is steep, and there are many particle components that are vertically incident on the surface of the film-forming object (incident angle is close to vertical). Means.
  • the conductive film 6 may be formed by the vacuum vapor deposition method, but the formation by the PLD method can maintain the interface with the Epi-n ++ GaN layer 51 cleanly and has high directivity, and is particularly high in the manufacturing process. Can be preferably used.
  • the first inorganic film 3a is removed by wet etching with hydrofluoric acid, and the Epi-n ++ GaN layer 51 and the conductive film 6 are formed on the substrate 100 by the lift-off method. Leave the laminate.
  • the lamination of the Epi-n ++ GaN layer 51 and the conductive film 6 is sometimes referred to as a laminated electrode because it is used for making an electrical connection with the underlying semiconductor layer.
  • the conductive film 6 can be formed on the Epi-n ++ GaN layer 51 in a self-aligned manner.
  • the Epi-n ++ GaN layer 51 and the conductive film 6 are self-aligned in this order, the Epi-n ++ in the cross section of the interface between the Epi-n ++ GaN layer 51 and the conductive film 6 is Epi-n ++.
  • the lower surface of the conductive film 6 is arranged symmetrically with respect to the upper surface of the GaN layer 51.
  • the base layer is not limited to this, and the base layer may be a Group III nitride.
  • the m-plane which is a Group III nitride, or N (nitrogen) polar plane or Group III (eg Ga) polar plane or non-polar plane, that is, the (11-20) plane and the a-plane, That is, the contact resistance between the (10-11) plane and the (10-12) plane and the (11-22) plane, which are semipolar planes such as the (11-0-0) plane, and the Group III nitride having the (11-22) plane as the surface is reduced.
  • the m-plane which is a Group III nitride, or N (nitrogen) polar plane or Group III (eg Ga) polar plane or non-polar plane, that is, the (11-20) plane and the a-plane, That is, the contact resistance between the (10-11) plane and the (10-12) plane and the (11-22) plane, which are semipolar planes such as the (11-0-0) plane,
  • Ru, Re or WN was placed on the substrate 100 by a vapor deposition method, a PVD method such as sputtering, or the like.
  • a third inorganic film 7 (for example, a film thickness of 200 to 500 [nm]) made of a metal having a catalytic action such as is formed.
  • the third inorganic film 7 may be formed by the PLD method.
  • a pattern of the photoresist film is formed by a lithography method, and the pattern of the photoresist film is used as a mask to form a third inorganic film 7.
  • the first inorganic film 3 is isotropically etched (for example, wet etching using hydrofluoric acid) with the third inorganic film 7a as a mask. Etching is performed to obtain a patterned first inorganic film 3a.
  • the cross section of the third inorganic film 7a has an overhang shape that protrudes like a canopy with respect to the side surface of the first inorganic film 3a.
  • an n-type GaN film (n ++ GaN film) is formed on the substrate 100 by the PLD method in the same manner as in the step of FIG. 2 (a).
  • the GaN that has reached the third inorganic film 7a is decomposed and re-evaporated by the catalytic action of the surface of the third inorganic film 7a. Therefore, unlike the step of FIG. 2A, the Epi-n ++ GaN layer 51 selectively grows epitaxially only on the exposed GaN layer (p + GaN layer 2 in the figure), but the third inorganic film No n ++ GaN film is formed on 7a.
  • the conductive film 6 for electrodes for example, Ni, W
  • the conductive film 6 for electrodes is continuously subjected to the PLD method.
  • a metal, alloy, or metal compound resistant to hydrofluoric acid such as TiN, WN, and TaN is formed.
  • the conductive film 6 is formed on the Epi-n ++ GaN layer 51 and the third inorganic film 7a, but since the film is formed by the highly directional PLD method, the conductive film 6 is formed on these films. The films 6 do not touch each other.
  • the first inorganic film 3a is removed by wet etching with hydrofluoric acid, and the Epi-n ++ GaN layer 51 and the conductive film are placed on the substrate 100 by the lift-off method.
  • the stack of 6 is left behind.
  • the third inorganic film 7a may be selectively removed by a chemical solution that selectively removes the material (for example, Ru) constituting the third inorganic film 7a.
  • the first inorganic film 3a can be left behind and used as an interlayer insulating film or a protective film.
  • the stacking of a self-aligned GaN semiconductor film and a conductive film that can be formed by the present invention is suitably applicable to a PN diode.
  • a Ni / Au laminated film has been used for p-type GaN
  • a Ti / Au laminated film has been used for n-type GaN as an ohmic electrode.
  • ohmic contact can be realized simultaneously with both conductive GaN layers. The diode characteristics are improved (eg, the forward current value is increased).
  • FIG. 4 shows an example of a darode using a GaN-based semiconductor.
  • a buffer layer 22 such as AlN is provided on a substrate 21 such as Si, sapphire, SiC, or GaN, and a periodic stack 24 of an i-GaN layer 231 and an i-AlGaN layer 232 is further formed on the buffer layer 22.
  • a p + AlGaN layer 25 is formed on the periodic stack 24.
  • the p + AlGaN layer 25 may have a shape formed on the side surface where the periodic stacking 24 is etched. A part of the periodic stacking 24 is removed by etching, and the lowermost i-GaN layer 23 is exposed.
  • the side wall cross section of the periodic stacking 24 may have a tapered shape.
  • the periodic lamination 24 may be wet-etched using the photoresist as an etching mask, or may be dry-etched under etching conditions in which the side surface of the photoresist, which is an etching mask, recedes.
  • an electrode composed of a laminate of the Epi-n ++ GaN layer 51 and the conductive film 6 is formed on the p ++ AlGaN layer 25 according to the first or second embodiment, and further, the periodic stack 24 and the electrode are formed.
  • An electrode made of a laminate of the Epi-n ++ GaN layer 51 and the conductive film 6 (for example, TiN or Ni / Au) is formed so as to be in contact with the exposed i-GaN layer 23.
  • the lamination of the Epi-n ++ GaN layer 51 formed on the p ++ AlGaN layer 25 and the conductive film 6 forms a pn junction.
  • the acceptor ionization energy is 150 [meV] for the GaN layer, but 450 [meV] for Al 0.4 Ga 0.6 N, which is an Al mixed crystal ratio.
  • ohmic contact is possible between the p ++ AlGaN layer 25 and the Epi-n ++ GaN layer 51 by tunnel junction as described below.
  • FIG. 9 shows a curve-fitted empirical formula superimposed on the result obtained by the above calculation as to how high the Fermi level is from the bottom of the conduction band.
  • the theoretical value of the carrier concentration obtained by full-band calculation is shown by ⁇ in the figure, and the empirical formula fitting the theoretical value is shown by the solid line in the figure.
  • FIG. 7 shows a band diagram of a junction when n ++ GaN is grown on p + AlGaN.
  • the Fermi level rises from the bottom of the conduction band.
  • Ohmic contact by tunnel junction requires that the energy of the electron and the energy of the hole match (Fig. 7 (b)).
  • p + AlGaN acceptor ionization energy (E A) and n ++ GaN difference Delta] E g of the conduction band and the Fermi level is that equal.
  • E A AlGaN acceptor ionization energy
  • an electrode made of a laminate of the Epi-n ++ GaN layer 51 and the conductive film 6 can be used in the cathode and anode regions of the diode having a pn junction.
  • a contact electrode made of a laminate of the Epi-n ++ GaN layer 51 and the conductive film 6 can be formed on different conductive GaN semiconductors at the same time. Therefore, the number of lithography steps can be reduced, which can contribute to the simplification of the manufacturing process.
  • Epi-n ++ GaN layer 51 is formed as E A of formula 2 may be used acceptor activation energy (contact with that) underlayer.
  • i-AlGaN 32 constituting a channel region is formed on i-GaN 31 which is a substrate, and a gate insulating film 33 (for example, SiN, Al oxide, Al nitride, Al nitride) is formed.
  • a gate electrode 34 (for example, Ru, WN, Ni / Au, etc.) is formed via an oxide or the like.
  • i-AlGaN 32 is etched with the gate electrode 34 as a mask, and Epi-n ++ is applied to the source and drain regions by the process described in the first or second embodiment.
  • a contact electrode made of a laminate of the GaN layer 51 and the conductive film 6 can be formed.
  • the first inorganic film 3 and the second inorganic film 7 are patterned in the same manner as in the steps shown in FIGS. 1 (b), (c), and (d).
  • the source and drain electrodes are formed by forming the n ++ GaN layer 51 and the conductive film 6 in the same manner as in the steps shown in FIGS. 2 (a), 2 (b) and 2 (c).
  • the gate material such as Ru has resistance to hydrofluoric acid, it does not dissolve in the above step.
  • the first inorganic film 3a may be formed so as to expose the gate insulating film 33 and the gate electrode 34.
  • the FET in which the gate electrode, the source, and the drain region are formed in a self-aligned manner by the process described in the first embodiment or the second embodiment. Can be manufactured.
  • a catalytic metal (or metal nitride film) such as Ru, Re or WN in at least the uppermost layer of the gate electrode 34, the gate electrode 34 is conductive without forming poly-GaN.
  • the film 6 is formed. Therefore, it is possible to prevent an increase in the resistance of the gate electrode 34.
  • the gate insulating film 33 and the gate electrode 34 are selected from materials having hydrofluoric acid resistance as described above. To do.
  • the source and drain regions sandwiching the channel region under the gate electrode and the Epi-n ++ GaN layer 51 and i-AlGaN 32 are in ohmic contact, low resistance contact can be realized. Therefore, the characteristics of the FET are improved (for example, the drive current is increased). Further, since the contact electrodes are formed in a self-aligned manner, it is not necessary to design the conductive film 6 to be smaller than the Epi-n ++ GaN layer 51 by a distance in consideration of the alignment error as in the conventional case. As a result, the distance between the source and drain electrodes is shortened as compared with the conventional case, and the on-resistance can be reduced.
  • the distance between the gate electrode and the source and drain electrodes can be adjusted.
  • the gate insulating film 33 is not exposed to the etching solution, and it is possible to allow the gate insulating film 33 to use a material having no hydrofluoric acid resistance, and to expand the options of the materials that can be used.
  • a silicon oxide film can be used as the gate insulating film 33.
  • the FET shown in FIG. 5 shows an example of a FET using recess etching, but the present invention is not limited to this.
  • the self-aligned laminated electrode of the present invention is also applied to the FET in which the source and drain regions are formed by introducing n-type and p-type impurities by ion implantation or the like, and the Epi-n ++ GaN layer 51 and the conductivity
  • the lamination with the film 6 can be used as a source and drain electrodes.
  • the laminate of the Epi-n ++ GaN layer 51 and the conductive film 6 makes ohmic contact on the n-type source and drain regions.
  • ohmic contact can be realized by tunnel junction between the Epi-n ++ GaN layer 51 and the p-type GaN-based semiconductor. Therefore, even when the p-type FET and the n-type FET are formed on one substrate , the stack of the Epi-n ++ GaN layer 51 and the conductive film 6 can be used as the source and drain electrodes of both conductive FETs at the same time. It can be formed and the manufacturing process can be simplified.
  • the self-aligned lamination of the GaN semiconductor film and the conductive film can be suitably used for the LED device.
  • the active layer 41 for example, multiple quantum wells of AlGaN and InGaN
  • the active layer 41 is provided with a first clad layer 42 and a p-type GaN layer composed of an n-type GaN layer.
  • a configuration is used in which the second clad layer 43 is sandwiched between the two clad layers 43.
  • the first clad layer 42 is formed on a substrate 44 such as sapphire via a GaN buffer layer 45.
  • Ohmic electrodes need to be formed on these clad layers. Conventionally, it is necessary to form a metal having a different work function corresponding to each conductive type. Therefore, it is necessary to perform the film forming process, the lithography process, and the etching process of the ohmic electrode on each conductive type clad layer. However, by laminating the GaN semiconductor and the conductive film of the present invention, ohmic electrodes can be formed in each clad layer in the same process, which can contribute to reduction of manufacturing cost or shortening of construction period.
  • a buffer layer 45 such as GaN, a first clad layer 42, an active layer 41, and a second clad layer 43 are formed in this order on a substrate 44 such as sapphire. Then, a part of the surface of the first clad layer 42 is exposed by a combination of lithography and dry etching (FIG. 6 (a)). After that, as described in the first embodiment or the second embodiment, the first inorganic film 3 and the second inorganic film 4 are formed, and the steps after FIG. 1 (c) or the steps after FIG. 3 (b) are performed. , The Epi-n ++ GaN layer 51 and the conductive film 6 are laminated on the first clad layer 42 and the second clad layer 43 (FIG. 6 (b)).
  • the configurations of the Epi-n ++ GaN layer 51 and the conductive film 6 formed on the first clad layer 42 and the second clad layer 43 are substantially (in terms of shape, crystallinity, and electrical characteristics). There is no difference.
  • the film thickness of the photoresist film used for patterning the second inorganic film 4 is set to be thicker than the thickness of the active layer 41 and the thickness of both clad layers, or resist coating conditions (for example, the number of rotations of the resist coater). ) May be optimized to achieve highly isotropic (conformal coating) conditions. Further, the photoresist film may be applied by spray coating. In addition to the above film forming method, the first inorganic film 3 and the second inorganic film 4 may cover the exposed side wall surfaces of the first clad layer 42, the active layer 41, and the second clad layer 43. If possible, it may be formed by another film forming method.
  • Ohmic contact is possible between the second clad layer 43 and the Epi-n ++ GaN layer 51 by tunnel junction as described above. Therefore, ohmic contact is possible with the second clad layer 43, the Epi-n ++ GaN layer 51, and the conductive film 6. Needless to say, ohmic contact is possible with the Epi-n ++ GaN layer 51 and the conductive film 6 on the first clad layer 42.
  • contact electrodes capable of achieving ohmic contact can be formed on the first clad layer 42 and the second clad layer 43, which are different conductive types, by the same process.
  • the LED manufacturing process can be simplified and the luminous efficiency of the LED is improved.
  • the self-aligned contact of the present invention further exerts a special effect on the ultraviolet LED.
  • the active layer 41 is composed of an AlGaN quantum well (for example, a five-layer quantum well of Al 0.6 Ga 0.4 N and Al 0.5 Ga 0.5 N), and the first clad
  • the layer 42 is composed of n-type AlGaN (for example, n + -Al 0.6 Ga 0.4 N), and the second clad layer 43 is p-type AlGaN (for example, p + -Al 0.6 Ga 0.4 N). It is composed of N).
  • the substrate 44 can be composed of, for example, a sapphire or an Al substrate, and can be composed of a buffer layer 45, for example, an AlN layer.
  • AlGaN used for ultraviolet LEDs has a wider bandgap than GaN. Therefore, it becomes more difficult to obtain ohmic contact between the second clad layer 43 (p-type AlGaN) and the electrode.
  • the acceptor ionization (activation) energy is 150 [meV] in the case of the GaN layer, whereas Al 0.6 Ga 0.4. It is known that the N layer is 450 [meV] (see FIG. 10).
  • electrodes corresponding to the respective conductive types are formed on the first clad layer 42 and the second clad layer 43, but the resistance is low on the second clad layer 43 which is a p-type semiconductor. Achieving ohmic contact is especially difficult. As the on-voltage increases due to the increase in contact resistance, heat is generated, causing a problem that light emission is reduced.
  • the p ++ GaN layer absorbs ultraviolet light and the luminous efficiency is lowered. There's a problem. In particular, the luminous efficiency of ultraviolet light of 364 [nm] or less is lowered due to the light absorption of the GaN material.
  • the contact electrode of the present embodiment can be solved and the luminous efficiency of the ultraviolet LED can be improved. Further, since the contact electrodes having the same configuration can be formed on the first clad layer 42 and the second clad layer 43, the manufacturing process can be simplified.
  • the Epi-n ++ GaN layer 51 is directly formed on the second clad layer 43 (p-type AlGaN) by the PLD method, and as described above, in a different type of conductive semiconductor, a tunnel is formed. Ohmic contact is possible by joining. Further, the conductive film 6 realizes non-alloy contact with the Epi-n ++ GaN layer 51, and can reduce the contact resistance with the second clad layer 43, which is a p-type region, as compared with the conventional case. Since non-alloy contact can be realized, heat treatment for alloying treatment is unnecessary, or the heat load can be reduced.
  • FIG. 7 shows changes in the energy bands of GaN and AlGaN when the concentration of n-type impurities in the GaN layer is increased.
  • the Fermi level moves to the conduction band side, changes from the state shown in FIG. 7 (a) to the state shown in FIG. 7 (b), and the tunnel current starts to flow. ..
  • the bandgap (optical bandgap) of GaN detected optically increases as compared with the forbidden band width (Burstine moss shift effect). That is, it is possible to control the ultraviolet light absorption characteristics of GaN by utilizing the Burstein Moss shift effect and reduce the ultraviolet light absorption.
  • the absorption of ultraviolet light of the Epi-n ++ GaN layer 51 is suppressed.
  • the tunnel junction enables ohmic contact with the first clad layer 42 and the second clad layer 43.
  • the conventional problems can be solved, and an ultraviolet LED having good luminous efficiency can be provided.
  • good contact resistance can be realized with respect to a GaN-based semiconductor by self-aligned lamination of an Epi-n ++ GaN layer and a conductive film.
  • the self-aligned lamination according to the present invention can be applied to various semiconductor devices as described above, and has high industrial applicability.

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Abstract

Le problème décrit par la présente invention est de fournir un procédé de fabrication d'un dispositif à semi-conducteur ayant une électrode de contact capable de réduire la résistance de contact de celui-ci avec un nitrure du groupe III. La solution selon l'invention porte sur un procédé de fabrication d'un dispositif à semi-conducteur qui consiste à : former, un premier film inorganique et un second film inorganique, qui sont constitués d'oxyde de silicium, par exemple, sur une couche de nitrure du groupe III ; former des motifs sur le second film inorganique ; graver de manière isotrope le premier film inorganique, par exemple avec de l'acide fluorhydrique, pour former un motif sur le premier film inorganique à l'aide du second film inorganique en tant que masque ; former un GaN de type n et un film conducteur à l'aide d'un procédé PLD ; et former une électrode stratifiée avec le GaN de type n et le film conducteur d'une manière auto-alignée en retirant le premier film inorganique et le second film inorganique. La présente invention peut s'appliquer à divers dispositifs à semi conducteur.
PCT/JP2020/034906 2019-09-18 2020-09-15 Dispositif à semi-conducteur et son procédé de fabrication WO2021054321A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0974246A (ja) * 1995-09-07 1997-03-18 Mitsubishi Electric Corp 半導体レーザ
JPH10256181A (ja) * 1997-03-14 1998-09-25 Japan Energy Corp 半導体装置の製造方法
JP2011238866A (ja) * 2010-05-13 2011-11-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2012188294A (ja) * 2011-03-08 2012-10-04 Tohoku Univ 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0974246A (ja) * 1995-09-07 1997-03-18 Mitsubishi Electric Corp 半導体レーザ
JPH10256181A (ja) * 1997-03-14 1998-09-25 Japan Energy Corp 半導体装置の製造方法
JP2011238866A (ja) * 2010-05-13 2011-11-24 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2012188294A (ja) * 2011-03-08 2012-10-04 Tohoku Univ 半導体装置の製造方法

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