WO2021051550A1 - 忆阻器的防过写电路及方法 - Google Patents

忆阻器的防过写电路及方法 Download PDF

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Publication number
WO2021051550A1
WO2021051550A1 PCT/CN2019/117428 CN2019117428W WO2021051550A1 WO 2021051550 A1 WO2021051550 A1 WO 2021051550A1 CN 2019117428 W CN2019117428 W CN 2019117428W WO 2021051550 A1 WO2021051550 A1 WO 2021051550A1
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voltage
circuit
signal
write
loop
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PCT/CN2019/117428
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English (en)
French (fr)
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王兴晟
黄恩铭
缪向水
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华中科技大学
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0059—Security or protection circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods

Definitions

  • the present invention belongs to the field of reading and writing of memristors, and more specifically, relates to an overwriting prevention circuit of a memristor and an overwriting prevention method.
  • the memristive materials when an appropriate voltage is applied, the memristive materials will switch between high resistance, low resistance or multi-resistance.
  • the low-resistance state is the state formed by the conductive path and has a low resistance value
  • the high-resistance state is the state where the conductive path is disconnected and has a high resistance value, and the resistance state is changed to realize data storage.
  • the memristor operation needs to select the appropriate operating voltage under various voltages according to logic control, but when the set operation is successful, the memristor is placed in a low-impedance state. At this time, if the set voltage continues to be applied to the memristor storage On the unit, a large current will be generated in the path corresponding to the operation, resulting in large power consumption. On the other hand, if the set voltage continues to exist, the set voltage loop will continue to conduct the set operation on the memristor, and the memristor memory cell will be set to a lower resistance, which will generate a larger current and increase the difficulty of reset. There will be a set operation at this time. In the same way, the reset operation also has a reset operation, the resistance will continue to decrease, increasing the difficulty of the set.
  • the present invention provides a memristor overwrite protection circuit, which is used to solve the problems caused by the large current and overoperation in the memristor write operation.
  • a memristor overwrite protection circuit which is characterized in that the circuit includes a signal control module, which is used to collect the memristor write loop current and generate a loop shutdown signal, so The loop shut-off signal performs voltage switching control shutting off the word line transistor of the memristor loop or the controllable switch set in the loop or the selector of the write voltage input, so as to realize the prevention of overwriting.
  • the loop shutdown signal is an analog signal or a logical digital signal.
  • the memristor write loop includes a voltage follower circuit electrically connected to the write voltage terminal of the memristor storage unit; the voltage follower circuit is electrically connected to the signal control module, and the voltage follower circuit has a The loop shut-off signal controls the voltage selector that switches the multiple input terminals of the write voltage and the write loop disconnect voltage.
  • the overwrite protection circuit further includes a first selector for current-limiting current input to the word line transistor, and the first selector includes a current-limiting switch that can be switched according to the loop shutdown signal. A plurality of input terminals of the voltage and the turn-off voltage of the word line transistor.
  • the signal control module includes a current-voltage conversion circuit and a current feedback module, wherein the current-voltage conversion circuit converts the current signal in the loop branch into a voltage signal, and the current feedback module converts the voltage The signal is converted into the loop shut-off signal.
  • the voltage selector input terminal of the voltage follower circuit is connected to the write voltage
  • the other input terminal of the voltage selector is connected to an amplifier
  • the other input terminal of the amplifier is connected to the selection voltage
  • the output terminal of the amplifier is connected to a feedback tube, and the voltage selector is also connected to the feedback tube to form a stable voltage follower circuit of the write voltage.
  • the current feedback module performs voltage conversion on the collected write loop voltage to directly realize that the word line transistor is turned off or the controllable switch set in the loop is turned off or the selector of the write voltage input performs voltage switching control off.
  • the current feedback module performs voltage conversion on the collected write loop voltage to directly realize that the word line transistor is turned off or the controllable switch set in the loop is turned off or the selector of the write voltage input performs voltage switching control off.
  • the current feedback module performs voltage conversion on the collected write loop voltage to directly realize that the word line transistor is turned off or the controllable switch set in the loop is turned off or the selector of the write voltage input performs voltage switching control off.
  • the selector that controls the switch to turn off or writes the voltage input performs voltage switching and turns off.
  • the invention also discloses a method for preventing overwriting of a memristor, which is characterized in that the method includes the following steps:
  • the write branch is disconnected according to the branch shut-off signal.
  • branch circuit is disconnected by turning off the conduction of the word line transistor in the write loop.
  • branch circuit is disconnected by turning off the controllable switch provided in the write loop. .
  • branch circuit is disconnected by turning off the write voltage input applied to the memristor memory cell.
  • the present invention proposes a circuit and method for preventing over-operation of the memristor, which is realized by generating a control signal to disconnect the write loop;
  • a selector is used to input the current-limiting voltage of the word line transistor, and the conduction performance of the word line transistor is fully utilized, and the voltage input to the word line transistor is controlled by a control signal, thereby controlling the word line transistor The way of gate voltage to achieve the turn-off of some loops, in this way to avoid over-write operation;
  • the present invention designs a voltage follower circuit for the write voltage, and the voltage follower circuit is also equipped with a voltage selector. On this basis, using a control signal to control the voltage selector can also realize the disconnection of the write loop.
  • the write module is optimized, and the problem of reading errors caused by random fluctuations in resistance caused by over-operation of the memristor is solved.
  • Fig. 1 is a schematic diagram of a memory cell used in a memristor read-write circuit implemented in accordance with the present invention
  • FIG. 2 is a schematic diagram of the storage architecture corresponding to the storage unit applied to the memristor read-write circuit implemented in accordance with the present invention
  • FIG. 3 is a schematic block diagram of one of the embodiments of the overwrite protection circuit of the memristor read-write circuit implemented according to the present invention.
  • FIG. 4 is a schematic block diagram of the second embodiment of the overwrite protection circuit of the memristor read-write circuit implemented according to the present invention.
  • FIG. 5 is a schematic block diagram of the third embodiment of the overwrite protection circuit of the memristor read-write circuit implemented according to the present invention.
  • FIG. 6 is a schematic diagram of the specific structure and composition of the anti-overwrite circuit of the bipolar memristor implemented according to the present invention.
  • Fig. 7 is a schematic diagram of a specific circuit structure of one embodiment of the current feedback module implemented according to the present invention.
  • Memristor unit in 1T1R structure 12 Bit line selection transistor in memory array 13: Word line transistor in 1T1R structure 4: First selector 14: Controllable switch
  • the first voltage follower circuit 22 The second voltage follower circuit 31: The first signal control module 32: The second signal control module
  • the first amplifier 212 the first voltage selector (set 2 to choose 1) 213: the first MOS feedback tube (PMOS transistor) 223: the second MOS feedback tube (PMOS transistor)
  • Second amplifier 222 Second voltage selector (reset terminal 2 select 1)
  • the first current conversion circuit (the set end diode is connected to the PMOS transistor)
  • Second current conversion circuit (reset end diode is connected to PMOS transistor)
  • Figure 1 is a memory cell used in a memristor read-write circuit implemented in accordance with the present invention. Its structure includes three parts, an upper electrode 111, a functional layer 110, and a lower electrode 112. It is a typical sandwich structure, the upper electrode and The electrode material of the lower electrode can be Ti, Ta, TiN, TaN, and the material of the functional layer can be HfOx.
  • the material of the upper electrode 111 of the memristive memory cell is TiN
  • the material of the functional layer 110 is HfOx
  • the material of the lower electrode 112 is Ti.
  • Fig. 2 is a schematic diagram of the basic memory architecture corresponding to the memory cell used in the memristor read-write circuit implemented according to the present invention, which is a traditional 1T1R architecture, that is, 1 transistor and 1 memristor unit.
  • the gate of the word line transistor 13 is connected to the word line control signal, the drain is connected to the lower electrode of the memristor, and the upper electrode 111 is connected to the drain of the selection transistor.
  • the scope of application of the read-write circuit of the present invention is not limited to the embodiment of the bipolar memory structure, and the electrode and functional layer materials are not strictly limited.
  • the design of the overwrite protection circuit and method involved in the present invention is mainly for application Read and write circuit and method of memristor for reading and writing voltage.
  • the concept of solving the problem mainly involves the following three aspects:
  • the first aspect is to judge whether the overwrite phenomenon has occurred through the loop current of the memristor. The existence of, will cause a large current phenomenon to the loop.
  • the second aspect is how to generate feedback signals from the overwrite signal to avoid the problems of overwriting.
  • the third aspect is to use the overwritten information to generate feedback to realize the closure of the memristor loop. So as to achieve the technical effect of preventing overwriting.
  • the memristor overwrite protection circuit of the present invention mainly includes the following connection structure, including a signal control module, which is used to collect the current of the memristor loop and generate a turn-off signal.
  • the line transistor 13 or the controllable switch element 14 or other circuit modules set up in the loop are turned off to stop the writing operation.
  • the turn-off signal can control the selector of the writing voltage input, thereby realizing the turning off of the writing signal in terms of the input source. Off.
  • FIGS 3 to 5 are block diagrams of one of the implementations of the overwrite protection circuit of the memristor read-write circuit implemented in accordance with the present invention.
  • the memory is mainly a bipolar memristor.
  • the cell is taken as an example to show the important technical solution of the present invention, but in practical applications, the overwrite protection circuit and method involved in the present invention are also applicable to unipolar memristor memory cells and bipolar memristor memory cells.
  • the circuit is set up as a symmetrical circuit structure of a unipolar memristor circuit set up.
  • the overwrite prevention circuit implemented by the present invention includes a first selector 4 electrically connected to the gate of the word line transistor 13, a first voltage follower circuit 21 connected to the upper electrode of the memory cell 1, and a first voltage follower circuit 21 electrically connected to the first voltage follower circuit 21.
  • a first signal control module 31 connected; a second voltage follower circuit 22 electrically connected to the source of the word line transistor 13 and a second signal control module 32 electrically connected to the second voltage follower circuit 22;
  • the first selector 4 In addition to the control signal terminal for selecting the SET and RESET voltage, the first selector 4 also includes control signal terminals from the first signal control module 31 and the second signal control module 32. These two control signal terminals are at When a write operation has occurred, the write operation voltage of the first selector 4 is controlled to be disconnected.
  • the first voltage follower circuit 21 and the second voltage follower circuit 22 maintain a stable write voltage application during the two-pole write voltage operation.
  • the input of the first voltage follower circuit 21 is connected to the V_set voltage, the output of the first voltage follower circuit 21 is connected to the upper electrode of the memory cell 1, and the output terminal of the first voltage follower circuit 21 is also connected to the first control signal module 31 , The output terminal of the first control signal module 31 is connected to the first selector 4.
  • the input of the second voltage follower circuit 22 is connected to the V_reset voltage, the output of the second voltage follower circuit 22 is connected to the source of the maximum current control module 3, and the output terminal of the second voltage follower circuit 22 is also connected to the second control signal module. 32 is connected, and the output terminal of the second control signal module 32 is connected to the first selector 4.
  • the first level uses the setting of a two-pole voltage follower circuit to maintain voltage stability and does not drift and change with the change of the memristor resistance, so that the first voltage follower circuit 21 (or second The output voltage of the voltage follower circuit 22) can stably output the V_set (or V_reset) voltage; the second level is to feedback the voltages of the two poles to generate a control signal.
  • the above-mentioned control signal controls the first selector 4 to turn off the word line transistor 13, so that the write branch is disconnected, so as to achieve the purpose of current limiting and overwriting prevention.
  • FIG. 4 it is an overwrite protection circuit corresponding to another embodiment of the present invention.
  • it is mainly the first control signal module 31 and
  • the control voltage generated by the second control signal module 32 is specifically used to control the shutdown of other elements in the loop of the storage unit 11, so that the write branch is disconnected, so as to achieve the purpose of write current limit and overwrite prevention.
  • the first voltage follower circuit 21 and the second voltage follower circuit 22 have voltage selection devices related to the circuit shutoff, the above two components can also be controlled to disconnect the branch circuit to achieve write current limit and protection. The technical effect of overwriting.
  • FIG. 5 it is the corresponding overwrite protection circuit in another embodiment implemented according to the present invention.
  • a controllable switch 14 is additionally provided in the branch, so that the first control signal module 31 is either The control signal generated by the second control signal module 32 can realize the disconnection of the branch, so as to achieve the technical effects of write current limit and overwrite prevention.
  • a voltage follower circuit is provided at the writing end of the memristor, mainly to maintain voltage stability and not change with the resistance of the memristor. Drift changes occur, specifically:
  • the first voltage follower circuit 21 includes a first amplifier 211, a first MOS feedback tube 213 and a first voltage selector 212, wherein the input terminal of the first amplifier 211 is connected to the V_set input voltage, The output terminal of the first amplifier 211 is connected to the gate of the first MOS feedback tube 213, wherein the other input terminal of the first amplifier 211 and the ground signal serve as the voltage selection terminal of the first voltage selector 212, and the first voltage selector 212
  • the output terminal of the first voltage selector 212 is connected to the upper electrode of the memristor unit, the output terminal of the first voltage selector 212 is also connected to the drain of the first MOS feedback tube 213, and the drain of the first MOS feedback tube 213 is connected to the upper electrode of the memristor unit. electrode.
  • the second voltage follower circuit 22 includes a second amplifier 221, a second MOS feedback tube 223, and a second voltage selector 222.
  • the input terminal of the second amplifier 221 is connected to the V_reset input voltage
  • the output terminal of the second amplifier 221 is connected to the gate of the second MOS feedback tube 223, and the other input terminal of the second amplifier 221 and the ground signal are used as the second voltage selection
  • the voltage selection terminal of the second voltage selector 222 is connected to the source of the word line transistor 13, and the output terminal of the second voltage selector 222 is also connected to the source of the second MOS feedback tube 223.
  • the source of the feedback tube 223 is connected to the source of the word line transistor 13.
  • analog signal control and digital signal control namely the first aspect , Is to use analog circuits to convert the collected and converted voltage signals without digital logic conversion directly to high and low level analog conversions to achieve turn-on or turn-off operations.
  • the second aspect is to convert analog signals into logic digital
  • the signal combination control method realizes the shutdown operation.
  • the first signal control module 31 includes a first current-to-voltage conversion circuit 312, a first current feedback module 311, and the first signal control module 31 includes a first current-voltage conversion circuit 312, a first current feedback module 311, and
  • the input terminal of a current conversion circuit 312 is connected to the source of the first MOS feedback tube 213, the output terminal is connected to the first current feedback module 311 of the next stage, and the output terminal of the first current feedback module is connected to the control terminal of the first selector 4 .
  • One embodiment of the first current conversion circuit 312 is a diode-connected PMOS transistor.
  • the second signal control module 32 includes a second current-to-voltage conversion circuit 322 and a second current feedback module 321.
  • the input terminal of the second current conversion circuit 322 is connected to the drain of the second MOS feedback tube 223, and the output terminal is connected to the drain of the second MOS feedback tube 223.
  • the output terminal of the second current feedback module 321 is connected to the control terminal of the first selector 4.
  • One embodiment of the second current feedback module 321 is a diode-connected PMOS transistor.
  • FIG. 7 is a schematic diagram of a specific circuit structure of the current feedback module in one of the embodiments of the present invention, where
  • the first and second current feedback modules 311 and 321 include three comparators.
  • the first terminal input of the voltage of these three comparators is the read voltage
  • the second terminal input is the reference voltage.
  • the comparison voltage is the three voltage parameters of the high resistance voltage, the low resistance voltage and the intermediate voltage, so that a logical judgment is made based on the three outputs of the comparator to obtain the corresponding control signal.
  • the current feedback module is composed of multiple comparators.
  • the working principle of the current feedback module is to generate a control signal based on the read voltage signal collected by the read circuit. This control signal can realize the disconnection of the overwrite branch. It can be set to multiple and compared with multiple reference voltage signals to achieve a more accurate and complex logic control signal.
  • the present invention also provides a method for preventing overwriting by a memristor, wherein the above method includes the following steps:
  • STEP1 Collect the write loop current signal of the memristor storage unit
  • STEP2 Generate branch shutdown signal based on write loop current signal
  • STEP3 Realize the disconnection of the writing branch according to the branch shutdown signal.
  • the above-mentioned STEP3 mainly includes the following specific operations:
  • the branch is disconnected by turning off the gate voltage of the word line transistor 13;
  • the branch circuit is disconnected by turning off the source current input applied to the memory cell
  • the branch circuit can be disconnected by turning off the separately provided controllable switch 14 provided in the branch circuit.
  • the disconnection of the source writing current is realized mainly by the source selection switching of the writing voltage input of the first voltage selector 212 and the second voltage selector 222. Shut down.
  • the first amplifier 211 acts as a follower, and the follower voltage V_set is applied to the upper end of the memory cell 1 through the first voltage selector 212; and the second voltage selector 222 selects the ground input, and the source of the word line transistor 13 Pole 132 is grounded.
  • the selection control signal will select the Vw_set voltage to act on the gate of the word line transistor 13.
  • the branch of the memory cell 11 will be turned on, and ⁇ Vset will act on the memory cell 11 to generate a branch current and generate a feedback voltage on the set terminal diode 312 .
  • the gate voltage applied to the word line transistor 13 is changed according to the operation. That is, the maximum current of the branch is controlled to a certain value by the Vgs of the word line transistor 13.
  • the memory cell will be set to low resistance.
  • the branch current increases, and the PMOS voltage connected to the set terminal diode 312 decreases, and the current feedback module 311 sends a feedback signal to the first voltage selector 212.
  • the word line voltage is selected to 0, thereby turning off the word line transistor 13, thereby disconnecting the branch and stopping the set operation to prevent over-set operation.
  • the second amplifier 221 acts as a follower and follows the voltage V_reset at the source of the word line transistor 13 through the second voltage selector 222; and the second voltage selector 222 selects the ground to ground the upper end of the memory cell.
  • the first selector 4 selects the Vw_reset voltage to act on the gate of the word line transistor 13.
  • the memory cell branch will be opened, - ⁇ Vreset will act on the memory cell, and at the same time, a branch current will be generated, and a feedback voltage will be generated on the diode 322 at the reset end.
  • the gate voltage applied to the word line transistor 13 is changed according to the operation, that is, the maximum current of the branch is controlled to a certain value through the Vgs of the word line transistor 13.
  • the memory cell will be placed in high impedance.
  • the current feedback module 321 sends a feedback signal to the first selector 4 to select the word line voltage to 0, thereby turning off the word line transistor 13, thereby turning the branch Disconnect, the reset operation stops, to prevent over-reset operation.
  • the feedback tube is clearly defined as PMOS, but this is not strictly limited. Different MOS tubes can be selected according to the conduction mode in the circuit, and the conduction connection of the poles can be modified and selected.
  • the maximum current control module is clearly defined as the word line selection transistor NMOS, but this is not limited, and different MOS transistors or modules are selected according to the conduction mode in the circuit.
  • the current-to-voltage conversion circuit is clearly defined as a diode, but this is not limited, and the module function can also be implemented according to other current-to-voltage circuit methods.
  • the specific setting method can be several comparators with circuit structure familiar to those skilled in the art, mainly to realize the actual readout signal and the reference which can be multiple or single.
  • the signal is logically selected to form a control signal.
  • the high-resistance and low-resistance settings correspond to the forward and reverse voltages applied by various operations such as writing, erasing, and reading, and the corresponding read-write circuit settings.
  • the specific settings can be set according to the material properties of the memory cell. SET ⁇ RESET current terminal.
  • various control signals need to be generated by the controller to realize the selection and read-write control of the memory cell array.
  • the controller settings are conventional settings of those skilled in the art.
  • the selector, voltage The circuit structure of the comparator is also a product such as a chip, a circuit, etc., which can be obtained in the prior art, and its specific structure form is not repeated here.
  • this invention patent relates to a circuit for reading and writing current limiting and preventing over-operation, mainly through word line transistor current limiting, and feedback module to prevent over-operation.
  • the writing module of the memristor is greatly optimized, and the random fluctuation of the resistance caused by the over-operation of the memristor is prevented.

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Abstract

本发明公开了一种忆阻器防过写电路及方法，其中该电路包括信号控制模块，其用于采集忆阻器写回路电流并生成回路关断信号，回路关断信号对忆阻器回路的字线晶体管或设置的可控开关或写电压输入的选择器进行电压切换控制关断；在方法上主要包括如下步骤：采集忆阻器存储单元的写回路电流信号；依据写回路电流信号生成支路关断信号；依据支路关断信号实现写支路的断开。按照本发明实现的防过写电路和方法，解决了忆阻器写操作中存在的大电流与过操作带来的电阻随机涨落问题。

Description

忆阻器的防过写电路及方法 [技术领域]
本发明属于忆阻器读写领域，更具体地，涉及一种忆阻器的防过写电路及防过写方法。
[背景技术]
以忆阻材料为基底的存储器，例如以HfOx为基底的材料或类似的材料，施加适当的电压，忆阻材料会在高阻、低阻或多阻之间进行转换。其中低阻态是导电通路形成的状态，具有低阻值，相反高阻态则是导电通路断开的状态，具有高阻值，以此阻值状态得变化实现数据存储。
忆阻器操作需要依据逻辑控制在多种大小的电压下选择相应合适的操作电压，但是当set操作成功后，忆阻器置于低阻状态，此时如果set电压继续施加在忆阻器存储单元上，则将在该操作对应的通路产生大电流，从而带来大功耗。另一方面，如果set电压持续存在，set电压回路持续导通将继续对忆阻器实行set操作，忆阻器存储单元将set到更低的电阻，从而产生更大电流，增加reset的难度，此时会出现过set操作。同理reset操作也存在过reset得操作，电阻将持续减小，增加set难度。
[发明内容]
针对现有技术的以上缺陷或改进需求，本发明提供了一种忆阻器的防过写电路，用于解决忆阻器写操作中存在的大电流与过操作带来的问题。
为实现上述目的，按照本发明，提供一种忆阻器的防过写电路，其特征在于，该电路包括信号控制模块，其用于采集忆阻器写回路电流并生成回路关断信号，所述回路关断信号对忆阻器回路的字线晶体管关断或回路中设置的可控开关关断或写电压输入的选择器进行电压切换控制关断，以此方式实现防过写。
进一步地，所述回路关断信号为模拟信号或逻辑数字信号。
进一步地，所述忆阻器写回路包括与忆阻器存储单元写电压端电连接的电压跟随电路；所述电压跟随电路电连接所述信号控制模块，所述电压跟随电路具有可依据所述回路关断信号控制切换写电压及写回路断开电压的多个输入端的电压选择器。
进一步地，所述防过写电路还包括有用于对所述字线晶体管进行限流电流输入的第一选择器，所述第一选择器包括有可依据所述回路关断信号控制切换限流电压及所述字线晶体管关断电压的多个输入端。
进一步地，所述信号控制模块，包括电流电压转化电路，电流反馈模块，其中所述电流电压转化电路将所述回路支路中的电流信号转化为电压信号，所述电流反馈模块将所述电压信号转化为所述回路关断信号。
进一步地，所述电压跟随电路的所述电压选择器输入一端接入所述写电压，所述电压选择器另外输入一端接放大器，所述放大器的另外一输入端接入所述选择电压，所述放大器输出端连接反馈管，所述电压选择器也接入反馈管以此形成写电压的稳定电压跟随回路。
进一步地，所述电流反馈模块将所述采集的写回路电压进行电压转换直接实现所述字线晶体管关断或回路中设置的可控开关关断或写电压输入的选择器进行电压切换控制关断，或包括有多个比较器，将所述采集的写回路电压与所述多个比较器的参考电压比较从而形成所述逻辑数字信号实现所述字线晶体管关断或回路中设置的可控开关关断或写电压输入的选择器进行电压切换控制关断。
本发明还公开了一种忆阻器的防过写方法，其特征在于，该方法包括如下步骤：
采集忆阻器存储单元的写回路电流信号
依据写回路电流信号生成支路关断信号
依据支路关断信号实现写支路的断开。
进一步地，通过关断写回路中的所述字线晶体管的导通的方式实现支路的断开。
进一步地，通过关断设置于写回路的可控开关的方式实现支路的断开。。
进一步地，通过关断施加于忆阻器存储单元的写电压输入的方式实现支路的断开。
总体而言，通过本发明所构思的以上技术方案与现有技术相比，具有以下有益效果：
(1)本发明提出了一种忆阻器的防过操作的电路和方法，通过产生控制信号的方式对写回路进行断开的方式实现；
(2)本发明中利用选择器对字线晶体管进行限流电压的输入，并充分利用字线晶体管的导通性能，利用控制信号对输入字线晶体管的电压进行输入控制，从而控制字线晶体管的栅极电压的方式实现过些回路的关断，以此方式避免过写操作；
(3)本发明对写电压设计了电压跟随电路，同时电压跟随电路中也具备有电压选择器，在此基础之上，利用控制信号对电压选择器进行控制也可实现写回路的断开，优化了写模块，且解决了忆阻器由于过操作带来的电阻随机涨落造成读出错误的问题。
[附图说明]
图1为按照本发明实现的忆阻器读写电路所应用的存储单元示意图；
图2为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的存储构架示意图；
图3为按照本发明实现的忆阻器读写电路的防过写电路的实施例之一的框图示意图；
图4为按照本发明实现的忆阻器读写电路的防过写电路的实施例之二的框图示意图；
图5为按照本发明实现的忆阻器读写电路的防过写电路的实施例之三的框图示意图；
图6为按照本发明实现的双极型忆阻器的防过写电路对应的具体结构组成示意图；
图7为按照本发明实现的电流反馈模块的其中一种实施方式的具体电路结构示意图。
11：1T1R结构中的忆阻器单元 12：存储阵列中的位线选择晶体管 13：1T1R结构中的字线晶体管 4：第一选择器 14：可控开关
111：忆阻器上电极(TiN) 110：忆阻器功能层(HfOx) 112：忆阻器下电极(TiN) 132：1T1R结构中的晶体管源极
21：第一电压跟随电路 22：第二电压跟随电路 31：第一信号控制模块 32：第二信号控制模块
211：第一放大器 212：第一电压选择器(set端2选1) 213：第一 MOS反馈管(PMOS晶体管) 223：第二MOS反馈管(PMOS晶体管)
221：第二放大器 222：第二电压选择器(reset端2选1)
312：第一电流转化电路(set端二极管连接PMOS晶体管)
322：第二电流转化电路(reset端二极管连接PMOS晶体管)
311：第一电流反馈模块(set端) 321：第二电流反馈模块(reset端)
[具体实施方式]
图1为按照本发明实现的忆阻器读写电路所应用的存储单元，其结构包含三个部分，上电极111，功能层110，下电极112，是一种典型的三明治结构，上电极和下电极的电极材料可以为Ti，Ta，TiN，TaN，功能层材料可以为HfOx。
在本发明所涉及的一种具体实施方式中，忆阻存储单元的上电极111材料为TiN，功能层110材料为HfOx，下电极112材料为Ti。
图2为按照本发明实现的忆阻器读写电路所应用的存储单元所对应的基础存储构架示意图，为传统的1T1R构架，即1个晶体管1个忆阻器单元。其中字线晶体管13的栅极接字线控制信号，漏极接忆阻器的下电极，上电极111接位选择晶体管漏极。
当然本发明的读写电路的适用范围并不限定为双极型存储结构的实施例，电极及功能层材料也并不严格限定，本发明涉及的防过写电路及方法的设计主要是针对施加读写电压的忆阻器的读写电路及读写方法。
按照本发明的忆阻器防过写电路及操作方法，主要涉及的解决问题的构思包括如下三个方面：第一方面是通过忆阻器的回路电流判断是否出现了过写的现象，过写的存在会给回路造成大电流的现象，第二方面是由过写的信号如何生成反馈信号规避过写存在的问题，第三方面是利用过写的信息生成反馈对忆阻器的回路实现关断从而达到防止过写的技术效果。
基于上述思路，本发明的忆阻器防过写电路主要包括如下连接结构，包括信号控制模块，其用于采集忆阻器回路电流并生成关断信号，关断信号对忆阻器回路的字线晶体管13或可控开关元件14或回路设置的其它电路模块实现关断从而使写操作停止，同样关断信号可以对写电压输入的选择器进行控制，从而在输入源方面实现写信号的关断。
图3至图5为按照本发明实现的忆阻器读写电路的防过写电路的其中一种实 施方式的框图示意图，在以下的实施方式中，主要是以双极型的忆阻器存储单元作为示例来展示本发明的重要技术方案，但是在实际的应用中，本发明所涉及的防过写电路及方法也适用于单极型的忆阻器存储单元，双极型忆阻器的电路设置为单极型忆阻器电路设置的对称电路结构形式。
实施例1
本发明实现的防过写电路，包括与字线晶体管13的栅极电连接的第一选择器4，与存储单元1上电极连接的第一电压跟随电路21及与第一电压跟随电路21电连接的第一信号控制模块31；与字线晶体管13源极电连接的第二电压跟随电路22及与第二电压跟随电路22电连接的第二信号控制模块32；
其中第一选择器4除了有进行SET与RESET电压选择的控制信号端，还包括有来自于第一信号控制模块31以及与第二信号控制模块32的控制信号端，这两个控制信号端在发生过写操作的情况下，会控制第一选择器4的写操作电压断开。
其中第一电压跟随电路21及第二电压跟随电路22在进行两极的写电压操作的过程中，保持稳定的写电压施加。
其中第一电压跟随电路21的输入接V_set电压，第一电压跟随电路21的输出接与存储单元1的上电极相连，同时第一电压跟随电路21的输出端还与第一控制信号模块31相连，第一控制信号模块31的输出端与第一选择器4相连。
其中第二电压跟随电路22的输入接V_reset电压，第二电压跟随电路22的输出接与最大电流控制模块3的源极相连，同时第二电压跟随电路22的输出端还与第二控制信号模块32相连，第二控制信号模块32的输出端与第一选择器4相连。
其中，按照上述电路架构的实现，第一层面利用两极的电压跟随电路的设置，保持电压稳定性并且不随忆组器阻值的改变而发生漂移改变，使得第一电压跟随电路21(或第二电压跟随电路22)的输出电压能够稳定输出V_set(或V_reset)电压；第二层面是将两极的电压反馈后生成控制信号，通过第一信号控制模块31、第二信号控制模块32的设置，通过上述控制信号来控制第一选择器4来关断字线晶体管13，从而使得写支路断开，以达到写限流和防过写的目的。
实施例2
如图4中所示，是按照本发明的另外一种实施方式所对应的防过写电路，此实，与第一种实施方式中的显著区别来看，主要是第一控制信号模块31及第二控制信号模块32所产生的控制电压，具体是用来控制存储单元11回路的其它元件的关断，从而使得写支路断开，以达到写限流和防过写的目的，在本实施方式中，由于第一电压跟随电路21和第二电压跟随电路22其中有关于回路关断的电压选择器件，同样也可控制上述两个部件使得支路断开，以达到写限流和防过写的技术效果。
实施例3
如图5中所示，是按照本发明实现的另外一种实施方式中所对应的防过写电路，此时，在支路中另外设置可控开关14，使得第一控制信号模块31或者是第二控制信号模块32所产生的控制信号能够实现支路的断开，从而达到写限流和防过写的技术效果。
进一步地，在上述的实施方式中，作为本发明的进一步的特征，在忆阻器的写入端都设置了电压跟随电路，主要是使得保持电压稳定性并且不随忆组器阻值的改变而发生漂移改变，具体来说：
如图6中所示，进一步地，第一电压跟随电路21，包括第一放大器211，第一MOS反馈管213及第一电压选择器212，其中第一放大器211的输入一端接V_set输入电压，第一放大器211的输出端接第一MOS反馈管213的栅极，其中，第一放大器211的另外一个输入端与接地信号作为第一电压选择器212的电压选择端，第一电压选择器212的输出端接忆阻器单元的上电极，其中第一电压选择器212的输出端还接第一MOS反馈管213的漏极，第一MOS反馈管213的漏极接忆阻器单元的上电极。
进一步地，第二电压跟随电路22，包括第二放大器221，第二MOS反馈管223及第二电压选择器222。其中第二放大器221的输入一端接V_reset输入电压，第二放大器221的输出端接第二MOS反馈管223的栅极，其中，第二放大器221的另外一个输入端与接地信号作为第二电压选择器222的电压选择端，第二电压选择器222的输出端接字线晶体管13的源极，其中第二电压选择器222的输出端还接第二MOS反馈管223的源极，第二MOS反馈管223的源极接字线晶体管13的源极。
作为本发明的其中重要的部分，即关断信号的产生，结合以上实施例中的控制不同部件的控制方法，皆存在有模拟信号控制和数字信号控制两种不同的控制方法，即第一方面，是通过模拟电路的方式将采集转化的电压信号不经过数字逻辑的转化直接进行高低电平的模拟式转化从而实现导通或关断的操作，第二方面，是通过模拟信号转化为逻辑数字信号组合的控制方式来实现关断操作。
作为实施例1所对应的具体电路结构，作为其中一种数字控制方法的实施例，进一步地，第一信号控制模块31，包括第一电流电压转化电路312，第一电流反馈模块311，其中第一电流转化电路312输入端接第一MOS反馈管213的源极，输出端方面接下一级的第一电流反馈模块311，第一电流反馈模块的输出端接第一选择器4的控制端。第一电流转化电路312的其中一种实施方式为二极管连接PMOS晶体管。
进一步地，第二信号控制模块32，包括第二电流电压转化电路322，第二电流反馈模块321，其中第二电流转化电路322输入端接第二MOS反馈管223的漏极，输出端方面接下一级的第二电流反馈模块321，第二电流反馈模块321的输出端接第一选择器4的控制端。第二电流反馈模块321的其中一种实施方式为二极管连接PMOS晶体管。
同样的，作为一种以数字逻辑信号来实现关断的操作方式，进一步地，如图7中所示，是按照本发明的其中一种实施方式中的电流反馈模块的具体电路结构示意图，其中第一、第二电流反馈模块311、321包括有三个比较器，这三个比较器的电压第一端输入都为读出的电压，第二端输入为参考电压，其中，在一个优选的实施方式中，比较电压分别为高阻电压、低阻电压和中间电压这三个电压参数，从而依据比较器的三个输出来进行逻辑的判断，从而获取相应的控制信号。
进一步地，其中电流反馈模块为多个比较器组成，电流反馈模块的工作原理是依据读电路采集的读电压信号来生成一个控制信号，这个控制信号能够实现过写支路的断开，比较器可以设置为多个，与多个参考电压信号进行比较，实现更为精准并且位数复杂的逻辑控制信号。
另外，本发明还提出了忆阻器防过写的方法，其中上述方法包括如下步骤：
STEP1：采集忆阻器存储单元的写回路电流信号
STEP2：依据写回路电流信号生成支路关断信号
STEP3：依据支路关断信号实现写支路的断开。
其中，上述STEP3中，主要包括有如下方法的具体操作：
第一种实施方式，通过关断字线晶体管13的栅极电压的方式实现支路的断开；
第二种实施方式，通过关断施加于存储单元的源电流输入的方式实现支路的断开；
第三种实施方式，通过关断设置于支路的另外设置的可控开关14的方式实现支路的断开。
进一步地，具体来说，结合了电压跟随电路的设置方式，实现源写电流的断开主要是通过对第一电压选择器212及第二电压选择器222的写电压输入的源选择切换来实现关断。
如图6中所示，按照本发明实现的双极型忆阻器的防过写电路的实施例1所对应的具体结构组成，下面将从Set，Reset两个操作实施方式的具体工作过程进一步对上述防过写的方法进行说明：
(1)Set操作过程，第一放大器211做跟随器，通过第一电压选择器212在存储单元1上端施加跟随电压V_set；而第二电压选择器222选择接地输入，将字线晶体管13的源极132接地。
选择控制信号将选择Vw_set电压作用于字线晶体管13的栅极，此时存储单元11支路将开通，ΔVset将作用于存储单元11，同时产生支路电流，在set端二极管312上产生反馈电压。首先作用在字线晶体管13的栅极电压是根据操作变化的。即通过字线晶体管13的Vgs将支路最大电流控制到一定的值。另外，当set成功后，存储单元将置于低阻，此时支路电流增大，set端二极管312连接的PMOS电压减小，则电流反馈模块311将反馈信号给第一电压选择器212将字线电压选到0，从而关闭字线晶体管13，从而将支路断开，set操作停止，达到防止过set操作。
(2)Reset操作过程，第二放大器221做跟随器，通过第二电压选择器222在字线晶体管13源极跟随电压V_reset；而第二电压选择器222选择接地，将存储单元上端接地。第一选择器4选择Vw_reset电压作用于字线晶体管13栅极。此时存储单元支路将开通，-ΔVreset将作用于存储单元，同时产生支路电流， 在reset端二极管322上产生反馈电压。
作用在字线晶体管13的栅极电压是根据操作变化的，即通过字线晶体管13的Vgs将支路最大电流控制到一定的值，当reset成功后，存储单元将置于高阻，此时支路电流减小，reset端二极管213连接的PMOS电压增大，则电流反馈模块321将反馈信号给第一选择器4将字线电压选到0，从而关闭字线晶体管13，从而将支路断开，reset操作停止，达到防止过reset操作。
值得注意的是，上述实施案例只是举出具体的实施方式，尤其是本发明的具体实施方式主要是以双极型忆阻器作为示例说明，但是对于单极型的忆阻器而言，采用对称电路结构的其中一部分即可。
上述实施方式中明确限定反馈管为PMOS，但这并不严格限定，依据在电路中的导通方式选择不同的MOS管，针对极的导通连接进行改型选择即可。
上述实施方式中明确限定最大电流控制模块为字线选择晶体管NMOS，但这并不限定，依据在电路中的导通方式选择不同的MOS管或者模块。
上述实施方式中明确限定电流电压转化电路为二极管，但这并不限定，依据其它的电流转电压的电路方式也可实现该模块功能。
另外，作为本发明中的产生控制信号的电流反馈电路，其具体设置方式可以为本领域技术人员熟知电路结构形式的若干比较器，主要是实现实际读出信号与可以是多个或单个的参考信号进行逻辑选择形成控制信号。
对于不同的双极性存储单元，高阻和低阻的设置对应写、擦、读等各种操作所施加的正反向电压及对应的读写电路设置，可依据存储单元材料性质设置具体的SET\RESET电流端。
按照本发明实现的读写电路，需要由控制器进行各类控制信号的产生实现存储单元阵列的选择及读写控制，该控制器设置为本领域技术人员的常规设置，另外，选择器、电压比较器电路结构也为现有技术能够获得的芯片、电路等产品，在此不再赘述其具体结构形式。
综上所述，该发明专利涉及一种读写限流与防止过操作的电路，主要通过字线晶体管限流，反馈模块防止过操作。大大优化了忆阻器的写模块，且阻止了忆阻器由于过操作带来的电阻随机涨落现象。
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不 用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (11)

  1. 一种忆阻器的防过写电路，其特征在于，该电路包括信号控制模块，其用于采集忆阻器写回路电流并生成回路关断信号，所述回路关断信号对忆阻器回路的字线晶体管(13)关断或回路中设置的可控开关(14)关断或写电压输入的选择器(212，222)进行电压切换控制关断，以此方式实现防过写。
  2. 如权利要求1中所述的防过写电路，其特征在于，所述回路关断信号为模拟信号或逻辑数字信号。
  3. 如权利要求1或2中所述的防过写电路，其特征在于，所述忆阻器写回路包括与忆阻器存储单元写电压端电连接的电压跟随电路(21，22)；所述电压跟随电路(21，22)电连接所述信号控制模块(31，32)，所述电压跟随电路(21，22)具有可依据所述回路关断信号控制切换写电压及写回路断开电压的多个输入端的电压选择器。
  4. 如权利要求3中所述的防过写电路，其特征在于，所述防过写电路还包括有用于对所述字线晶体管(13)进行限流输入的第一选择器(4)，所述第一选择器(4)包括有可依据所述回路关断信号控制切换限流电压及所述字线晶体管(13)关断电压的多个输入端。
  5. 如权利要求4所述的防过写电路，其特征在于，所述信号控制模块(31，32)，包括电流电压转化电路(312，322)，电流反馈模块(311，321)，其中所述电流电压转化电路(312，322)将所述回路支路中的电流信号转化为电压信号，所述电流反馈模块(311，321)将所述电压信号转化为所述回路关断信号。
  6. 如权利要求5所述的防过写电路，其特征在于，所述电压跟随电路(21，22)的所述电压选择器输入一端接入所述写电压，所述电压选择器另外输入一端接放大器，所述放大器的另外一输入端接入所述选择电压，所述放大器输出端连接反馈管，所述电压选择器也接入反馈管以此形成写电压的稳定电压跟随回路。
  7. 如权利要求6所述的防过写电路，其特征在于，所述电流反馈模块(311、321)将所述采集的写回路电压进行电压转换直接实现所述字线晶体管(13)关断或回路中设置的可控开关(14)关断或写电压输入的选择器(212，222)进行电压切换控制关断，或包括有多个比较器，将所述采集的写回路电压与所述多个比较器的参考电压比较从而形成所述逻辑数字信号实现所述字线晶体管(13)关 断或回路中设置的可控开关(14)关断或写电压输入的选择器(212，222)进行电压切换控制关断。
  8. [根据细则91更正 06.12.2019]
    一种忆阻器的防过写方法，其特征在于，该方法包括如下步骤：
    采集忆阻器存储单元的写回路电流信号
    依据写回路电流信号生成支路关断信号
    依据支路关断信号实现写支路的断开。
  9. [根据细则91更正 06.12.2019]　
    如权利要求7中所述的防过写方法，其特征在于，通过关断写回路中的所述字线晶体管(13)的导通的方式实现支路的断开。
  10. [根据细则91更正 06.12.2019]　
    如权利要求7中所述的防过写方法，其特征在于，通过关断设置于写回路的可控开关(14)的方式实现支路的断开。。
  11. [根据细则91更正 06.12.2019]　
    如权利要求7中所述的防过写方法，其特征在于，通过关断施加于忆阻器存储单元的写电压输入的方式实现支路的断开。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102169720A (zh) * 2010-02-25 2011-08-31 复旦大学 一种消除过写、误写现象的电阻随机存储器
CN104810049A (zh) * 2015-04-30 2015-07-29 中国科学院微电子研究所 一种脉冲宽度幅度自适应的阻变存储器写驱动电路
CN107195322A (zh) * 2017-07-11 2017-09-22 高科创芯(北京)科技有限公司 一种基于忆阻器的动态电源管理系统

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1593126B1 (en) * 2003-01-31 2009-03-25 Nxp B.V. Mram architecture for low power consumption and high selectivity
JP5012312B2 (ja) * 2007-08-15 2012-08-29 ソニー株式会社 記憶装置の駆動方法
US9911492B2 (en) * 2014-01-17 2018-03-06 International Business Machines Corporation Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period
CN105448332A (zh) * 2014-09-16 2016-03-30 复旦大学 一种电阻型随机读取存储器及其写操作方法
US9478287B2 (en) * 2015-01-29 2016-10-25 Taiwan Semiconductor Manufacturing Company Limited Circuits and methods for detecting write operation in resistive random access memory (RRAM) cells
US10424378B2 (en) * 2016-02-24 2019-09-24 Hewlett Packard Enterprise Development Lp Memristive control circuits with current control components
CN105825885B (zh) * 2016-03-21 2018-04-10 华中科技大学 基于忆阻器的多值存储单元、读写电路及其操作方法
JP2017199443A (ja) * 2016-04-27 2017-11-02 ソニー株式会社 半導体記憶装置、駆動方法、および電子機器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102169720A (zh) * 2010-02-25 2011-08-31 复旦大学 一种消除过写、误写现象的电阻随机存储器
CN104810049A (zh) * 2015-04-30 2015-07-29 中国科学院微电子研究所 一种脉冲宽度幅度自适应的阻变存储器写驱动电路
CN107195322A (zh) * 2017-07-11 2017-09-22 高科创芯(北京)科技有限公司 一种基于忆阻器的动态电源管理系统

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