WO2021042480A1 - 像素驱动电路、像素驱动方法、显示面板及显示装置 - Google Patents

像素驱动电路、像素驱动方法、显示面板及显示装置 Download PDF

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Publication number
WO2021042480A1
WO2021042480A1 PCT/CN2019/115163 CN2019115163W WO2021042480A1 WO 2021042480 A1 WO2021042480 A1 WO 2021042480A1 CN 2019115163 W CN2019115163 W CN 2019115163W WO 2021042480 A1 WO2021042480 A1 WO 2021042480A1
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Prior art keywords
transistor
electrically connected
driving
electrode
signal terminal
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PCT/CN2019/115163
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English (en)
French (fr)
Inventor
玄明花
齐琪
刘静
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980002266.0A priority Critical patent/CN113168810B/zh
Priority to US17/052,147 priority patent/US11263970B2/en
Publication of WO2021042480A1 publication Critical patent/WO2021042480A1/zh

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Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a pixel driving method, a display panel, and a display device.
  • HDR High-Dynamic Range
  • display devices can improve the picture quality of the display screen, and also put forward higher requirements on the color gamut and brightness of the display device.
  • Micro light emitting diodes The display device is more suitable for realizing the display of high dynamic range images because of its high brightness and wide color gamut.
  • a pixel drive circuit including: a drive signal control sub-circuit and a drive duration control sub-circuit; wherein the drive signal control sub-circuit is related to a first scan signal terminal, a first data signal terminal, and a first voltage
  • the signal terminal, the enable signal terminal, and the driving duration control sub-circuit are electrically connected, and are configured to provide a driving signal to the driving duration control sub-circuit under the control of the first scan signal terminal and the enable signal terminal .
  • the driving signal is related to the first data signal received at the first data signal terminal and the first voltage signal received at the first voltage signal terminal.
  • the driving duration control sub-circuit is also electrically connected to the second scan signal terminal, the second data signal terminal, the enable signal terminal, and the component to be driven, and is configured to be between the second scan signal terminal and the enable signal terminal. Under control, the drive signal is transmitted to the component to be driven. The duration of the transmission of the driving signal to the component to be driven is related to the second data signal received at the second data signal terminal.
  • the driving signal control sub-circuit includes: a first data writing unit, a first driving unit, and a first control unit; wherein, the first data writing unit and the first scan signal terminal , The first data signal terminal and the first driving unit are electrically connected, and are configured to write the first data signal received at the first data signal terminal under the control of the first scan signal terminal To the first drive unit.
  • the first control unit is electrically connected to the enable signal terminal, the first voltage signal terminal, and the first driving unit, and is configured to operate under the control of the enable signal terminal.
  • the first voltage signal received at the voltage signal terminal is input to the first driving unit.
  • the first driving unit is also electrically connected to a third voltage signal terminal, and is configured to be based on the written first data signal and the input first voltage signal, and the first voltage signal received at the third voltage signal terminal. Three voltage signals, generating the driving signal, and transmitting the driving signal to the first control unit.
  • the first control unit is also electrically connected to the driving duration control sub-circuit, and is configured to transmit the driving signal to the driving duration control sub-circuit under the control of the enable signal terminal.
  • the first data writing unit includes: a first transistor and a second transistor.
  • the control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first data signal terminal, and the second electrode of the first transistor is electrically connected to the first scan signal terminal.
  • the first driving unit is electrically connected.
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, and the first electrode and the second electrode of the second transistor are electrically connected to the first driving unit.
  • the first driving unit includes: a first storage capacitor and a third transistor.
  • the first end of the first storage capacitor is electrically connected to the first data writing unit and the first control unit, and the second end of the first storage capacitor is electrically connected to the first data writing unit .
  • the control electrode of the third transistor is electrically connected to the second terminal of the first storage capacitor and the first data writing unit, and the first electrode of the third transistor is electrically connected to the first voltage signal terminal ,
  • the second electrode of the third transistor is electrically connected to the first data writing unit and the first control unit.
  • the first control unit includes: a fourth transistor and a fifth transistor.
  • the control electrode of the fourth transistor is electrically connected to the enable signal terminal, the first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the
  • the first driving unit is electrically connected.
  • the control electrode of the fifth transistor is electrically connected to the enable signal terminal, the first electrode of the fifth transistor is electrically connected to the first driving unit, and the second electrode of the fifth transistor is electrically connected to the driving unit.
  • the duration control sub-circuit is electrically connected.
  • the driving signal control sub-circuit further includes: a first reset unit.
  • the first reset unit is electrically connected to the first voltage signal terminal, the reset signal terminal, the initialization signal terminal, and the first driving unit, and is configured to be controlled by the reset signal terminal according to the The first voltage signal received at the voltage signal terminal and the initialization signal received at the initialization signal terminal reset the voltage of the first driving unit.
  • the first reset unit includes: a sixth transistor and a seventh transistor.
  • the control electrode of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the first voltage signal terminal.
  • a drive unit is electrically connected.
  • the control electrode of the seventh transistor is electrically connected to the reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initialization signal terminal, and the second electrode of the seventh transistor is electrically connected to the first driving unit. connection.
  • the drive signal control sub-circuit further includes: a drive signal stabilization unit; the drive signal stabilization unit is connected to the first drive unit and is configured to enable the drive generated by the first drive unit The signal remains stable.
  • the driving signal stabilizing unit includes: a stabilizing storage capacitor.
  • the first driving unit includes a first storage capacitor and a third transistor
  • the first end of the stabilized storage capacitor is electrically connected to the first end of the first storage capacitor
  • the stabilized storage capacitor The second end of the voltage-stabilizing storage capacitor is electrically connected to the second electrode of the third transistor; or, the first end of the voltage-stabilizing storage capacitor is electrically connected to the second end of the first storage capacitor.
  • the second terminal is electrically connected to the second terminal of the third transistor.
  • the driving signal control sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first storage capacitor, and a voltage regulator Storage capacitor.
  • the control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first data signal terminal, and the second electrode of the first transistor is electrically connected to the first scan signal terminal.
  • the first end of the first storage capacitor is electrically connected.
  • the control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the second transistor is electrically connected. It is electrically connected to the second end of the first storage capacitor and the control electrode of the third transistor.
  • the control electrode of the third transistor is also electrically connected to the second terminal of the first storage capacitor, the first electrode of the third transistor is electrically connected to the first voltage signal terminal, and the first electrode of the third transistor is electrically connected to the first voltage signal terminal.
  • the two poles are also electrically connected to the first pole of the fifth transistor.
  • the control electrode of the fourth transistor is electrically connected to the enable signal terminal, the first electrode of the fourth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the fourth transistor is electrically connected to the The first terminal of the first storage capacitor is electrically connected.
  • the control electrode of the fifth transistor is electrically connected to the enable signal terminal, and the second electrode of the fifth transistor is electrically connected to the driving duration control sub-circuit.
  • the control electrode of the sixth transistor is electrically connected to the reset signal terminal, the first electrode of the sixth transistor is electrically connected to the first voltage signal terminal, and the second electrode of the sixth transistor is electrically connected to the first storage terminal.
  • the first end of the capacitor is electrically connected.
  • the control electrode of the seventh transistor is electrically connected to the reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initialization signal terminal, and the second electrode of the seventh transistor is electrically connected to the first storage capacitor. The second end is electrically connected to the control electrode of the third transistor.
  • the first end of the stabilized storage capacitor is electrically connected to the first end of the first storage capacitor, and the second end of the stabilized storage capacitor is electrically connected to the second electrode of the third transistor; or, The first end of the stabilized storage capacitor is electrically connected with the second end of the first storage capacitor, and the second end of the stabilized storage capacitor is electrically connected with the second electrode of the third transistor.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all P-type transistors Or they are all N-type transistors.
  • the driving duration control sub-circuit includes: a second data writing unit, a second control unit, and a second driving unit; wherein, the second data writing unit and the second scan signal terminal , The second data signal terminal and the second driving unit are electrically connected, and are configured to receive a signal with a set working potential at the second data signal terminal under the control of the second scan signal terminal The second data signal is written to the second driving unit.
  • the second control unit is electrically connected to the enable signal terminal, the second data signal terminal, and the second driving unit, and is configured to operate under the control of the enable signal terminal.
  • the second data signal whose potential changes within a set range received at the data signal terminal is transmitted to the second driving unit.
  • the second driving unit is also electrically connected to the driving signal control sub-circuit, and is configured to be based on the second data signal with a set working potential and a second data signal with the potential changing within a set range,
  • the driving signal is transmitted to the second control unit, and the duration of the transmission of the driving signal to the second control unit is controlled.
  • the second control unit is also electrically connected to the element to be driven, and is also configured to transmit the driving signal to the element to be driven.
  • the second data writing unit includes: an eighth transistor, the control electrode of the eighth transistor is electrically connected to the second scan signal terminal, and the first electrode of the eighth transistor is electrically connected to the second scan signal terminal.
  • the second data signal terminal is electrically connected, and the second electrode of the eighth transistor is electrically connected to the second driving unit.
  • the second control unit includes: a ninth transistor and a tenth transistor, a control electrode of the ninth transistor is electrically connected to the enable signal terminal, and a first electrode of the ninth transistor is connected to the second data signal The terminal is electrically connected, and the second electrode of the ninth transistor is electrically connected to the second driving unit.
  • the control electrode of the tenth transistor is electrically connected to the enable signal terminal, the first electrode of the tenth transistor is electrically connected to the second driving unit, and the second electrode of the tenth transistor is electrically connected to the standby signal terminal.
  • the driving element is electrically connected.
  • the second driving unit includes: a second storage capacitor and an eleventh transistor, a first end of the second storage capacitor is electrically connected to the second data writing unit and the second control unit;
  • the control electrode of the eleventh transistor is electrically connected to the second terminal of the second storage capacitor, the first electrode of the eleventh transistor is electrically connected to the drive signal control sub-circuit, and the second terminal of the eleventh transistor is electrically connected
  • the pole is electrically connected with the second control unit.
  • the driving duration control sub-circuit further includes: a second reset unit; the second reset unit is electrically connected to a reset signal terminal, an initialization signal terminal, and the second driving unit, and is configured to Under the control of the reset signal terminal, the voltage of the second driving unit is reset according to the initialization signal received at the initialization signal terminal.
  • the second reset unit includes: a twelfth transistor and a thirteenth transistor.
  • the control electrode of the twelfth transistor is electrically connected to the reset signal end, the first electrode of the twelfth transistor is electrically connected to the initialization signal end, and the second electrode of the twelfth transistor is electrically connected to the reset signal end.
  • the second driving unit is electrically connected.
  • the control electrode of the thirteenth transistor can be connected to the reset signal terminal, and the first electrode and the second electrode of the thirteenth transistor are electrically connected to the second driving unit.
  • the driving duration control sub-circuit includes: an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a second storage capacitor.
  • the control electrode of the eighth transistor is electrically connected to the second scan signal terminal, the first electrode of the eighth transistor is electrically connected to the second data signal terminal, and the second electrode of the eighth transistor is electrically connected to the second data signal terminal.
  • the first end of the second storage capacitor is electrically connected.
  • the control electrode of the ninth transistor is electrically connected to the enable signal terminal, the first electrode of the ninth transistor is electrically connected to the second data signal terminal, and the second electrode of the ninth transistor is electrically connected to the The first end of the second storage capacitor is electrically connected.
  • the control electrode of the tenth transistor is electrically connected to the enable signal terminal, the first electrode of the tenth transistor is electrically connected to the second electrode of the eleventh transistor, and the second electrode of the tenth transistor is electrically connected. It is electrically connected with the component to be driven.
  • the control electrode of the eleventh transistor is electrically connected to the second terminal of the second storage capacitor, and the first electrode of the eleventh transistor is connected to the driving signal control sub-circuit and the second terminal of the twelfth transistor.
  • the two poles are electrically connected, and the second pole of the eleventh transistor is also electrically connected to the first pole of the thirteenth transistor.
  • the control electrode of the twelve transistor is electrically connected to the reset signal terminal, and the first electrode of the twelve transistor is electrically connected to the initialization signal terminal.
  • the control electrode of the thirteenth transistor is electrically connected to the reset signal terminal, and the second electrode of the thirteenth transistor is electrically connected to the second end of the second storage capacitor and the control electrode of the eleventh transistor. connection.
  • the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, and the thirteenth transistor are all P-type transistors or All are N-type transistors.
  • a pixel driving method which is applied to the pixel driving circuit according to any one of the first aspect, the pixel driving method includes: a frame period includes a scanning phase and a working phase, and the scanning phase includes Multiple line scan periods.
  • Each of the plurality of row scan periods includes: a driving signal control sub-circuit writes the first data signal under the control of the first scan signal terminal; the driving time control sub-circuit is at the second scan signal terminal Under control, a second data signal with a set working potential is written.
  • the working phase includes: the drive signal control sub-circuit provides a drive signal to the drive duration control sub-circuit under the control of the enable signal terminal; the drive signal is connected to the first data signal and the first voltage signal terminal The first voltage signal provided is related.
  • the driving duration control sub-circuit receives a second data signal whose potential changes within a set range, and transmits the driving signal to the component to be driven; the driving signal is transmitted to the The duration of the component to be driven is related to the second data signal with the set working potential and the second data signal with the potential changing within the set range.
  • the absolute value of the set working potential is related to the working time of the corresponding component to be driven.
  • the two end values of the setting range are: the non-working potential of the second data signal and the reference working potential; the absolute value of the reference working potential is greater than or equal to the second data signal The maximum value among the absolute values of all the set working potentials of the signal; the set working potential is within the set range.
  • a display panel including the pixel driving circuit according to any one of the first aspects.
  • the display panel includes a plurality of sub-pixels, each sub-pixel corresponds to one pixel driving circuit, and the plurality of sub-pixels are arranged in an array with multiple rows and multiple columns.
  • the display panel further includes: a plurality of first scan signal lines, a plurality of first data signal lines, a plurality of second scan signal lines, and a plurality of second data signal lines.
  • Each pixel driving circuit corresponding to the same row of sub-pixels is electrically connected to the same first scanning signal line and the same second scanning signal line.
  • Each pixel driving circuit corresponding to the same column of sub-pixels is electrically connected to the same first data signal line and the same second data signal line.
  • the above-mentioned display panel further includes a base substrate on which the pixel driving circuit is disposed, and the base substrate is a glass substrate.
  • a display device including the display panel as described in the third aspect.
  • FIG. 1 is a schematic diagram of a structure of a pixel driving circuit according to some embodiments of the present disclosure
  • FIG. 2A is another structural schematic diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • 2B is a schematic diagram of another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 3A is a schematic diagram of another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 3B is a schematic diagram of another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 5A is a schematic diagram of still another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 5B is a schematic diagram of still another structure of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 6 is a timing diagram of a pixel driving method according to some embodiments of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a display panel according to some embodiments of the present disclosure.
  • FIG. 8 is a schematic diagram of a display device according to some embodiments of the present disclosure.
  • FIG. 9 is a schematic diagram of signal crosstalk according to some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of an I-V characteristic curve of a transistor according to some embodiments.
  • Micro LED (miniature light emitting diode) display devices have high brightness and wide color gamut, which can meet the requirements of the application of HDR (High-Dynamic Range) technology on the brightness and color gamut of display devices. Suitable for HDR display.
  • the pixel drive circuit of the miniature light-emitting diode display device usually adopts current drive control.
  • the light-emitting intensity of the miniature light-emitting diode is controlled by controlling the size of the driving current input to the miniature light-emitting diode, and thus the display of different gray scales is realized. For example, when implementing a lower gray scale display, a smaller driving current will be provided to reduce the light-emitting brightness of the micro light-emitting diode; when a higher gray scale display is achieved, a larger driving current will be provided to make the micro The light-emitting brightness of the light-emitting diode is improved.
  • the inventors of the present disclosure have discovered through research that the miniature light-emitting diode has the characteristics of high luminous efficiency at high current density, low luminous efficiency at low current density, and deviation of the main peak.
  • the specific performance is: when the driving current of the input micro LED reaches a certain value, the luminous efficiency of the micro LED reaches the highest; when the driving current does not reach this value, the luminous efficiency of the micro LED has been in the climbing stage, that is, with With the increase of the driving current provided, the luminous intensity of the miniature light-emitting diode gradually increases, and at the same time the luminous efficiency gradually increases to a certain extent, and the luminous efficiency of the miniature light-emitting diode tends to be stable.
  • the driving current input to the micro light-emitting diode is relatively low, so that the micro light is emitted.
  • the diode is at a low current density, resulting in low luminous efficiency of the miniature light-emitting diode, high energy consumption, and high power consumption when the display device performs display, resulting in energy loss.
  • the pixel driving circuit 100 includes: a driving signal control subcircuit 1 and a driving duration control subcircuit 2.
  • the driving signal control sub-circuit 1 is electrically connected to the first scan signal terminal GATE1, the first data signal terminal DATA1, the first voltage signal terminal VDD, the enable signal terminal EM, and the driving duration control sub-circuit 2.
  • the first scan signal terminal GATE1 is configured to receive the first scan signal Gate1 and input the first scan signal Gate1 to the driving signal control sub-circuit 1
  • the first data signal terminal DATA1 is configured to receive the first data signal Data1, And input the first data signal Data1 to the driving signal control sub-circuit 1
  • the first voltage signal terminal VDD is configured to receive the first voltage signal Vdd, and input the first voltage signal Vdd to the driving signal control sub-circuit 1
  • enable The signal terminal EM is configured to receive the enable signal Em and input the enable signal Em to the driving signal control sub-circuit 1.
  • the driving signal control sub-circuit 1 is configured to provide a driving signal to the driving duration control sub-circuit 2 under the control of the first scan signal terminal GATE1 and the enable signal terminal EM.
  • the driving signal is related to the first data signal Data1 received at the first data signal terminal DATA1 and the first voltage signal Vdd received at the first voltage signal terminal VDD.
  • the driving duration control sub-circuit 2 is also electrically connected to the second scan signal terminal GATE2, the second data signal terminal DATA2, the enable signal terminal EM, and the component 3 to be driven.
  • the second scan signal terminal GATE2 is configured to receive the second scan signal Gate2 and input the second scan signal Gate2 to the driving signal control sub-circuit 1
  • the second data signal terminal DATA2 is configured to receive the second data signal Data2
  • the enable signal terminal EM is configured to receive the enable signal Em, and input the enable signal Em to the driving signal control sub-circuit 1.
  • the driving duration control sub-circuit 2 is configured to transmit the driving signal to the component 3 to be driven under the control of the second scan signal terminal GATE2 and the enable signal terminal EM.
  • the transmission time of the driving signal to the component to be driven 3 is related to the second data signal Data2 received at the second data signal terminal DATA2.
  • the above-mentioned pixel drive circuit 100 includes a drive signal control sub-circuit 1 and a drive duration control sub-circuit 2.
  • the drive signal control sub-circuit 1 is configured to provide a drive signal to the drive duration control sub-circuit 2, and the magnitude of the drive signal is the same as the first A data signal Data1 is related to the first voltage signal Vdd;
  • the driving duration control sub-circuit 2 is configured to transmit the driving signal to the component to be driven 3, and the duration of the transmission of the driving signal to the component to be driven 3 is related to the second data signal Data2,
  • the component to be driven 3 works, that is, the working time of the component to be driven 3 is related to the second data signal Data2.
  • the size of the drive signal of the drive element 3 to be driven is achieved by controlling the size of the drive signal and the length of time the drive signal is transmitted to the element to be driven 3 As well as the control of the working time, the control of the driving element 3 is realized.
  • the component to be driven 3 is a light-emitting device, such as a miniature light-emitting diode.
  • the drive signal control sub-circuit 1 controls the size of the drive signal to control the size of the drive current transmitted to the light-emitting device, and the drive duration control sub-circuit 2 By controlling the transmission time of the driving signal to the light-emitting device, the working time of the light-emitting device is controlled. In this way, when displaying different gray scales, the luminous intensity of the light-emitting device can be changed by controlling the driving current and the light-emitting duration of the light-emitting device, and then Realize the corresponding grayscale display.
  • the inventors of the present disclosure have discovered through research that, when the driving current is large, light-emitting devices such as miniature light-emitting diodes are at high current density, with high luminous efficiency and low energy consumption.
  • the driving current input to the light-emitting device is increased to increase the luminous intensity of the light-emitting device; when a lower gray-scale display is realized, the work of the light-emitting device is shortened.
  • the driving current transmitted to the light-emitting device is always large, the light-emitting device is always at a high current density, and the luminous efficiency is high, thereby achieving the effects of reducing power consumption and saving costs.
  • the first data signal Data1 provided to the first data signal terminal DATA1 may be a fixed high-voltage power supply that enables the element 3 to be driven to have higher luminous efficiency.
  • the pixel driving circuit 100 mainly controls the gray scale through the driving time control sub-circuit 1.
  • the potential of the first data signal Data1 can be changed within a certain voltage interval, and the first data signal Data1 within the voltage interval can ensure that the component 3 to be driven has a high luminous efficiency.
  • the pixel driving circuit 100 controls the gray scale through the joint action of the driving signal control sub-circuit 1 and the driving duration control sub-circuit 2.
  • the above-mentioned driving signal control sub-circuit 1 includes: a first data writing unit 11, a first driving unit 12, and a first control unit 13.
  • the first data writing unit 11 is electrically connected to the first scan signal terminal GATE1, the first data signal terminal DATA1, and the first driving unit 12, and is configured to, under the control of the first scan signal terminal GATE1, change the first data signal
  • the first data signal Data1 received at the terminal DATA1 is written into the first driving unit 12.
  • the first driving unit 12 is also electrically connected to the first voltage signal terminal VDD and the first control unit 13, and is configured to be based on the written first data signal Data1 and the first voltage signal received at the first voltage signal terminal VDD. Vdd, generating a driving signal, and transmitting the driving signal to the first control unit 13.
  • the first control unit 13 is also electrically connected to the enable signal terminal EM, the first voltage signal terminal VDD, and the driving duration control sub-circuit 2, and is configured to, under the control of the enable signal terminal EM, according to the first voltage signal Vdd, The driving signal is transmitted to the driving duration control sub-circuit 2.
  • the first data signal Data1 is written to the first driving unit 12 through the first data writing unit 11, and the first driving unit 12 is based on the first data signal Data1 and the first voltage signal.
  • Vdd generate a driving signal
  • the first control unit 13 transmits the driving signal to the driving duration control sub-circuit 2, so that the driving signal control sub-circuit 1 realizes the driving duration
  • the control sub-circuit 2 provides a driving signal, and the driving signal is related to the first data signal Data1 and the first voltage signal Vdd.
  • the first driving unit 12 is electrically connected to the first voltage signal terminal VDD, that is, both the first driving unit 12 and the first control unit 13 are electrically connected to the first voltage signal terminal VDD.
  • the first control unit 13 inputs the first voltage signal Vdd received at the first voltage signal terminal VDD to the first driving unit 12 under the control of the enable signal terminal EM.
  • the first driving unit 12 is based on the first data signal Data1 written by the first data writing unit 11 and the first voltage signal Vdd input by the first control unit 13, and the first voltage signal received at the first voltage signal terminal VDD.
  • the voltage signal Vdd generates a driving signal, and transmits the driving signal to the first control unit 13.
  • the magnitude of the driving signal is related to the first data signal Data1 and the first voltage signal Vdd.
  • the first driving unit 12 and the first control unit 13 are both electrically connected to the first voltage signal terminal VDD, and receive the first voltage signal Vdd transmitted by the first voltage signal terminal VDD.
  • An additional voltage signal terminal for separately providing a voltage signal to the first driving unit 12 is additionally provided, or there is no need to additionally provide a voltage signal terminal for separately providing a voltage signal to the first control unit 13, so that the circuit structure is simplified.
  • only the first voltage signal line configured to provide the first voltage signal Vdd to the first voltage signal terminal VDD is provided, and other voltage signal lines need not be additionally provided. Can reduce the number of wiring, simplify the circuit structure.
  • the inventors of the present disclosure have discovered through research that the above-mentioned driving signal is used to control the sub-circuit 1.
  • the first driving The driving signal generated by the unit 12 passes through the first voltage signal terminal VDD.
  • the driving current generated by the first driving unit 12 passes through the first voltage signal terminal VDD, and then flows to the first voltage signal line, and since the first voltage signal line has Resistance, when a current flows on the first voltage signal line, a voltage drop may occur.
  • the first voltage signal Vdd received by the first voltage signal terminal VDD in each pixel driving circuit 100 may be inconsistent.
  • the first voltage signal line transmits the first voltage signal Vdd
  • the greater the distance traveled by the first voltage signal Vdd the greater the voltage drop generated, so the distance from the signal source end of the first voltage signal Vdd is greater.
  • the pixel driving circuit 100 that is far away has a lower received first voltage signal Vdd than the pixel driving circuit 100 that is closer to the signal source end of the first voltage signal Vdd.
  • the driving signal generated by the driving signal control sub-circuit 1 is the same as the first data signal Data1 received at the first data signal terminal DATA1 and the first data signal Data1 received at the first voltage signal terminal VDD.
  • the first voltage signal Vdd is related. Therefore, because the first voltage signal Vdd received by each pixel driving circuit 100 is not consistent, the size of the generated driving signal is not consistent, causing the display panel to display unevenness.
  • the above-mentioned driving signal control sub-circuit 1 includes: a first data writing unit 11, a first driving unit 12 and a first control unit 13.
  • the first data writing unit 11 is electrically connected to the first scan signal terminal GATE1, the first data signal terminal DATA1, and the first driving unit 12, and is configured to, under the control of the first scan signal terminal GATE1, change the first data signal
  • the first data signal Data1 received at the terminal DATA1 is written into the first driving unit 12.
  • the first control unit 13 is electrically connected to the enable signal terminal EM, the first voltage signal terminal VDD, and the first driving unit 12, and is configured to receive at the first voltage signal terminal VDD under the control of the enable signal terminal EM
  • the first voltage signal Vdd is input to the first driving unit 12.
  • the first driving unit 12 is also electrically connected to the third voltage signal terminal VREF, and is configured to be based on the written first data signal Data1 and the input first voltage signal Vdd, and the signal received at the third voltage signal terminal VREF.
  • the third voltage signal Vref generates a driving signal, and transmits the driving signal to the first control unit 13.
  • the first control unit 13 is also electrically connected to the driving duration control sub-circuit 2 and is configured to transmit the driving signal to the driving duration control sub-circuit 2 under the control of the enable signal terminal EM.
  • the first data signal Data1 is written to the first driving unit 12 through the first data writing unit 11, and the first driving unit 12 is based on the written first data signal Data1 and
  • the input first voltage signal Vdd and the third voltage signal Vref received at the third voltage signal terminal VREF generate a driving signal, and transmit the driving signal to the first control unit 13, and the first control unit 13 transmits the driving signal It is transmitted to the driving duration control sub-circuit 2, so that the driving signal control sub-circuit 1 provides a driving signal to the driving duration control sub-circuit 2, and the driving signal is related to the first data signal Data1 and the first voltage signal Vdd.
  • the first driving unit 12 is electrically connected to the third voltage signal terminal VREF, and is configured according to the written first data signal Data1 and the input first voltage signal Vdd, and the third voltage signal
  • the third voltage signal Vref received at the terminal VREF generates a driving signal, and transmits the driving signal to the first control unit 13.
  • the third voltage signal terminal VREF is configured to receive the third voltage signal Vref and input the third voltage signal Vref to the driving signal control sub-circuit 1. That is, in the above-mentioned driving signal control sub-circuit 100, a separate At the third voltage signal terminal VREF that provides the third voltage signal Vref to the first driving unit 12.
  • the first voltage signal line configured to provide the first voltage signal Vdd to the first voltage signal terminal VDD and the third voltage signal line configured to provide the third voltage signal Vref to the third voltage signal terminal VREF
  • the voltage signal lines are different signal lines.
  • the driving current generated by the first driving unit 12 will only flow from the third voltage signal terminal VREF to the third voltage signal line without affecting the first voltage signal line, so that the first voltage
  • the signal line can provide a stable first voltage signal Vdd to the first voltage signal terminal VDD of each pixel driving circuit 100, and the size of the driving signal will not be affected, thus avoiding the above-mentioned possible problem of uneven display of the display panel. .
  • the first data writing unit 11 includes: a first transistor M1 and a second transistor M2.
  • the control electrode of the first transistor M1 is electrically connected to the first scan signal terminal GATE1, the first electrode of the first transistor M1 is electrically connected to the first data signal terminal DATA1, and the second electrode of the first transistor M1 is electrically connected to the first driving unit 12 connection.
  • the first transistor M1 is configured to be turned on under the control of the first scan signal Gate1 to transmit the first data signal Data1 to the first driving unit 12.
  • the control electrode of the second transistor M2 is electrically connected to the first scanning signal terminal GATE1, and the first electrode and the second electrode of the second transistor M2 are electrically connected to the first driving unit 12.
  • the first driving unit 12 includes the third transistor M3
  • the second transistor M2 is configured to be turned on under the control of the first scan signal Gate1, so that the third transistor M3 is in a self-saturated state.
  • the above-mentioned first driving unit 12 includes: a first storage capacitor C1 and a third transistor M3.
  • the first end of the first storage capacitor C1 is electrically connected to the first data writing unit 11 and the first control unit 13, and the second end of the first storage capacitor C1 is electrically connected to the first data writing unit 11.
  • the first storage capacitor C1 is configured to receive the first data signal Data1 input by the first data writing unit 11 and store the first data signal Data1.
  • the control electrode of the third transistor M3 is electrically connected to the second terminal of the first storage capacitor C1 and the first data writing unit 11, the first electrode of the third transistor M3 is electrically connected to the third voltage signal terminal VREF, and the third transistor M3 The second pole is electrically connected to the first data writing unit 11 and the first control unit 13.
  • the third transistor M3 is configured to be based on the first data signal Data1 stored in the first storage capacitor C1 and the first voltage signal Vdd input by the first control unit 13, and the third voltage received at the third voltage signal terminal VREF
  • the signal Vref generates a driving signal, and transmits the driving signal to the first control unit 13.
  • the above-mentioned first control unit 13 includes: a fourth transistor M4 and a fifth transistor M5.
  • the control electrode of the fourth transistor M4 is electrically connected to the enable signal terminal EM, the first electrode of the fourth transistor M4 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the fourth transistor M4 is electrically connected to the first driving unit 12 .
  • the fourth transistor M4 is configured to be turned on under the control of the enable signal Em to transmit the first voltage signal Vdd to the first driving unit 12.
  • the control electrode of the fifth transistor M5 is electrically connected to the enable signal terminal EM, the first electrode of the fifth transistor M5 is electrically connected to the first driving unit 12, and the second electrode of the fifth transistor M5 is electrically connected to the driving duration control sub-circuit 2 .
  • the fifth transistor M5 is configured to be turned on under the control of the enable signal Em to transmit the driving signal to the driving duration control sub-circuit 2.
  • the driving signal control sub-circuit 1 further includes a first reset unit 14.
  • the first reset unit 14 is electrically connected to the first voltage signal terminal VDD, the reset signal terminal RESET, the initialization signal terminal VINIT and the first driving unit 12.
  • the reset signal terminal RESET is configured to receive the reset signal Reset and input the reset signal Reset to the first reset unit 14;
  • the initialization signal terminal VINIT is configured to receive the initialization signal Vinit and input the initialization signal Vinit to the first reset unit 14.
  • the first reset unit 14 is configured to, under the control of the reset signal terminal RESET, drive the first drive signal according to the first voltage signal Vdd received at the first voltage signal terminal VDD and the initialization signal Vinit received at the initialization signal terminal VINIT.
  • the voltage of cell 12 is reset.
  • the voltage of the first driving unit 12 is reset by the first reset unit 14, so as to reduce the noise of the signal at the first driving unit 12, so that the first data writing unit 11 will first When the data signal Data1 is written to the first driving unit 12, the input first data signal Data1 is more accurate.
  • the first reset unit 14 includes: a sixth transistor M6 and a seventh transistor M7.
  • the control electrode of the sixth transistor M6 is electrically connected to the reset signal terminal RESET, the first electrode of the sixth transistor M6 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the sixth transistor M6 is electrically connected to the first driving unit 12.
  • the sixth transistor M6 is configured to be turned on under the control of the reset signal Reset to transmit the first voltage signal Vdd to the first driving unit 12.
  • the control electrode of the seventh transistor M7 is electrically connected to the reset signal terminal RESET, the first electrode of the seventh transistor M7 is electrically connected to the initialization signal terminal VINIT, and the second electrode of the seventh transistor M7 is electrically connected to the first driving unit 12.
  • the seventh transistor M7 is configured to be turned on under the control of the reset signal Reset, and transmit the initialization signal Vinit to the first driving unit 12.
  • the first voltage signal Vdd may be affected by other signals and be distorted. Exemplarily, as shown in FIG. 9, the first voltage signal Vdd is affected by the level jump of the first data signal Data1. On the rising edge of the first data signal Data1, the level of the first voltage signal Vdd will increase. Pull transition and then resume.
  • the level of the first voltage signal Vdd will undergo a pull-down transition and then resume, and the recovery time after the transition is determined by the first voltage signal Vdd used to transmit the first voltage signal.
  • the influence of resistive load and capacitive load existing on a voltage signal line When the resistive load and capacitive load of the first voltage signal line are relatively large, the recovery time of the first voltage signal Vdd after a jump occurs is relatively long, resulting in the instability of the first voltage signal Vdd received by the pixel driving circuit 100 The problem is even more pronounced.
  • the fourth transistor M4 is turned on under the control of the enable signal Em to transmit the first voltage signal Vdd to the first driving unit 12
  • the potential of the first end of the first storage capacitor C1 has a pull-down jump.
  • the potential of the second end of the first storage capacitor C1 also has a pull-down jump.
  • the potential of the second terminal of the first storage capacitor C1 is equal to the potential of the control electrode of the third transistor T3, so the potential of the control electrode of the third transistor T3 undergoes a pull-down jump, and the potential of the first electrode of the third transistor T3 is When the potential of the third voltage signal Vref remains unchanged, the gate-source voltage difference of the third transistor T3 decreases.
  • the current generated by the transistor when the gate-source voltage difference of the control electrode of the transistor changes, the current generated by the transistor also changes.
  • the P-type transistor Take the P-type transistor as an example.
  • the absolute value of the gate-source voltage difference of the P-type transistor is greater than the absolute value of its threshold voltage, the P-type transistor is turned on, which in turn generates current.
  • the P-type transistor is turned on, the P-type transistor’s The gate-source voltage difference is less than zero.
  • the relationship between the current Id generated by the P-type transistor and the gate-source voltage difference Vgs of the P-type transistor is as follows: When the voltage is less than 0V (that is, when the P-type transistor is turned on to generate current), as the gate-source voltage difference Vgs of the P-type transistor decreases, the current generated by the P-type transistor increases.
  • the third transistor T3 is a P-type transistor
  • the gate-source voltage difference of the third transistor T3 decreases, which will cause the drive current generated by the third transistor T3 to increase
  • the third transistor T3 With its own resistance, the drive current generated by the third transistor T3 increases, indicating that the resistance of the third transistor T3 decreases, and the resulting voltage drop decreases.
  • the potential at the first pole of the third transistor T3 that is, the third voltage
  • the potential of the signal Vref remains unchanged, the potential of the second electrode of the third transistor T3 rises, and an instantaneous pull-up transition occurs.
  • the driving signal generated by the first driving unit 12 is affected by the pull-down jump of the potential of the first voltage signal Vdd, and will increase instantaneously, so that the potential of the second electrode of the third transistor is pulled up and jumped instantaneously.
  • the drive current generated by the third transistor T3 will be reduced, indicating that the resistance of the third transistor T3 itself increases, resulting in a voltage drop.
  • the potential of the first pole of the third transistor T3 that is, the potential of the third voltage signal Vref
  • the potential of the second pole of the third transistor T3 decreases, and an instant pull-down jump occurs. That is to say, the driving signal generated by the first driving unit 12 is affected by the pull-up jump of the first voltage signal Vdd, and will decrease instantaneously, so that the potential of the second electrode of the third transistor T3 pulls down and jumps instantaneously.
  • the change of the driving signal generated by the first driving unit 12 affects the operation of the component 3 to be driven.
  • the element to be driven 3 is a light emitting device
  • the luminous intensity of the element to be driven 3 is affected by the change of the driving signal and changes, which in turn leads to display failures in the display screen.
  • the driving signal control sub-circuit 1 further includes a driving signal stabilizing unit 15.
  • the driving signal stabilizing unit 15 is electrically connected to the first driving unit 12 and is configured to stabilize the driving signal generated by the first driving unit 12.
  • the driving signal stabilizing unit 15 is used to stabilize the driving signal generated by the first driving unit 12, so as to avoid the interference of the first voltage signal Vdd by other signals.
  • the jump affects the magnitude of the driving signal generated by the first driving unit 12, ensuring that the component to be driven 3 works normally under the action of the driving signal, thereby ensuring the normal display of the display screen.
  • the driving signal stabilizing unit 15 includes: a stabilized storage capacitor C3.
  • the first driving unit 12 includes the first storage capacitor C1 and the third transistor T3, in some examples, as shown in FIG.
  • the second terminal of the voltage stabilizing storage capacitor C3 is electrically connected to the second terminal of the third transistor T3.
  • the node where the second electrode of the first transistor M1 and the first end of the first storage capacitor C1 are electrically connected is equivalent to the first node N1, that is, the potential of the first node N1 and the first storage capacitor C1
  • the potential of the terminal, the potential of the second pole of the first transistor M1, and the potential of the first terminal of the stabilizing storage capacitor C3 are the same.
  • the node where the control electrode of the third transistor M3 and the second end of the first storage capacitor C1 are electrically connected is equivalent to the second node N2, that is, the potential of the second node N2 and the potential of the second end of the first storage capacitor C1, and The potentials of the control electrodes of the third transistor M3 are the same.
  • the node where the second terminal of the stabilized storage capacitor C3 and the second electrode of the third transistor T3 are electrically connected is equivalent to the sixth node N6, that is, the potential of the sixth node N6 and the potential of the second terminal of the stabilized storage capacitor C3, and The potentials of the second electrodes of the third transistor T3 are the same.
  • the above-mentioned stabilized storage capacitor C3 is arranged between the first terminal of the first storage capacitor C1 and the second terminal of the third transistor T3, so that the first voltage signal Vdd is affected by the potential change of the first data signal Data1.
  • potential jumps For example, the potential of the first voltage signal Vdd undergoes a pull-down jump, the potential of the first end of the first storage capacitor C1 (the potential of the first node N1) undergoes a pull-down jump, and the potential of the first end of the stabilized storage capacitor C3 is the same as The potential of the first node N1 is the same, so the potential of the first terminal of the stabilized storage capacitor C3 is also pulled down.
  • the potential of the second terminal of the stabilized storage capacitor C3 (the potential of the sixth node N6) Pull-down changes also occur.
  • the driving signal generated by the first driving unit 12 is affected by the pull-down jump of the potential of the first voltage signal Vdd, and increases instantaneously, so that the third transistor The potential of the second pole (the potential of the sixth node N6) instantly pulls up and jumps.
  • the stabilizing storage capacitor C3 the change in the potential of the second electrode of the third transistor (the potential of the sixth node N6) is cancelled, which is equivalent to that the drive signal generated by the first drive unit 12 does not change or change It is very small and can be ignored, and it will hardly be affected by the jump of the potential of the first voltage signal Vdd.
  • the potential change of each node can refer to the above description, which will not be repeated here.
  • the operation of the component to be driven 3 is hardly affected, and can work normally, ensuring the display The normal display of the screen.
  • the first end of the stabilized storage capacitor C3 is electrically connected to the second end of the first storage capacitor C1
  • the second end of the stabilized storage capacitor C3 is electrically connected to the third end of the first storage capacitor C1.
  • the second electrode of the transistor T3 is electrically connected.
  • the above-mentioned stabilizing storage capacitor C3 is arranged between the second terminal of the first storage capacitor C1 and the second terminal of the third transistor T3, so that the first voltage signal Vdd is affected by the potential change of the first data signal Data1.
  • a potential jump for example, the potential of the first voltage signal Vdd has a pull-down jump, and the potential of the first end of the first storage capacitor C1 (the potential of the first node N1) has a pull-down jump.
  • the potential of the second terminal of the first storage capacitor C1 (the potential of the second node N2) also undergoes a pull-down jump
  • the potential of the first terminal of the regulated storage capacitor C3 is the same as the potential of the second node N2, so the regulated storage
  • the potential of the first terminal of the capacitor C3 also changes in a pull-down.
  • the potential of the second terminal of the stabilized storage capacitor C3 (the potential of the sixth node N6) also changes in the pull-down.
  • the driving signal generated by the first driving unit 12 is affected by the pull-down jump of the potential of the first voltage signal Vdd, and increases instantaneously, so that the third transistor The potential of the second pole (the potential of the sixth node N6) instantly pulls up and jumps.
  • the stabilizing storage capacitor C3 the change in the potential of the second pole of the third transistor (the potential of the sixth node N6) is cancelled, which is equivalent to that the drive signal generated by the first drive unit 12 does not change or change It is very small and can be ignored, and it will hardly be affected by the jump of the potential of the first voltage signal Vdd.
  • the potential change of each node can refer to the above description, which will not be repeated here.
  • the operation of the component 3 to be driven will not be affected, and can work normally, ensuring the display screen The normal display.
  • the driving signal stabilizing unit 15 may also include other devices, and the present disclosure is not limited to this, as long as it can stabilize the driving signal generated by the first driving unit 12.
  • the driving signal control sub-circuit 1 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, the first storage capacitor C1 and the stabilized storage capacitor C3.
  • the control electrode of the first transistor M1 is electrically connected to the first scan signal terminal GATE1, the first electrode of the first transistor M1 is electrically connected to the first data signal terminal DATA1, and the second electrode of the first transistor M1 is electrically connected to the first storage capacitor C1.
  • the first end is electrically connected.
  • the first transistor M1 is configured to be turned on under the control of the first scan signal Gate1 to transmit the first data signal Date1 to the first end of the first storage capacitor C1.
  • the control electrode of the second transistor M2 is electrically connected to the first scan signal terminal GATE1, the first electrode of the second transistor M2 is electrically connected to the second electrode of the third transistor M3, and the second electrode of the second transistor M2 is electrically connected to the first storage capacitor The second end of C1 and the control electrode of the third transistor M3 are electrically connected.
  • the second transistor M2 is configured to be turned on under the control of the first scan signal Gate1, and the control electrode of the third transistor M3 is connected to the second electrode of the third transistor M3, so that the third transistor M3 reaches a self-saturation state.
  • the control electrode of the third transistor M3 is also electrically connected to the second end of the first storage capacitor C1, the first electrode of the third transistor M3 is electrically connected to the third voltage signal terminal VREF, and the second electrode of the third transistor M3 is also electrically connected to the The first pole of the five transistor M5 is electrically connected.
  • the third transistor M3 is configured to generate a driving signal according to the first data signal Date1 stored in the first storage capacitor C1, the first voltage signal Vdd input by the first control unit 13, and the third voltage signal Vref, and to drive The signal is transmitted to the first pole of the fifth transistor M5.
  • the control electrode of the fourth transistor M4 is electrically connected to the enable signal terminal EM, the first electrode of the fourth transistor M4 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the fourth transistor M4 is electrically connected to the first storage capacitor C1. One end is electrically connected.
  • the fourth transistor M4 is configured to be turned on under the control of the enable signal Em to transmit the first voltage signal Vdd to the first end of the first storage capacitor C1.
  • the control electrode of the fifth transistor M5 is electrically connected to the enable signal terminal EM, and the second electrode of the fifth transistor M5 is electrically connected to the driving duration control sub-circuit 2.
  • the fifth transistor M5 is configured to be turned on under the control of the enable signal Em to transmit the driving signal to the driving duration control sub-circuit 2.
  • the control electrode of the sixth transistor M6 is electrically connected to the reset signal terminal RESET, the first electrode of the sixth transistor M6 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the sixth transistor M6 is electrically connected to the first storage capacitor C1. Terminals are electrically connected.
  • the sixth transistor M6 is configured to be turned on under the control of the reset signal Reset, and transmit the first voltage signal Vdd to the first end of the first storage capacitor C1.
  • the control electrode of the seventh transistor M7 is electrically connected to the reset signal terminal RESET, the first electrode of the seventh transistor M7 is electrically connected to the initialization signal terminal VINIT, the second electrode of the seventh transistor M7 is electrically connected to the second end of the first storage capacitor C1 and The control electrode of the third transistor M3 is electrically connected.
  • the seventh transistor M7 is configured to be turned on under the control of the reset signal Reset, and transmit the initialization signal Vinit to the second end of the first storage capacitor C1.
  • the first end of the stabilized storage capacitor C3 is electrically connected with the first end of the first storage capacitor C1, and the second end of the stabilized storage capacitor C1 is electrically connected with the second electrode of the third transistor T3.
  • the first end of the stabilized storage capacitor C3 is electrically connected to the second end of the first storage capacitor C1
  • the second end of the stabilized storage capacitor C3 is electrically connected to the second electrode of the third transistor T3.
  • the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all P-type transistors or all N-type transistors.
  • the driving duration control sub-circuit 2 in the pixel driving circuit 100 provided by the present disclosure includes: a second data writing unit 21, a second control unit 23, and a second driving Unit 22.
  • the second data writing unit 21 is electrically connected to the second scan signal terminal GATE2, the second data signal terminal DATA2, and the second driving unit 22, and is configured to be controlled by the second scan signal terminal GATE2, The second data signal Data2 with the set working potential received at the terminal DATA2 is written to the second driving unit 22.
  • the transmission time of the drive signal to the component 3 to be driven is related to the second data signal Data2 with the set working potential.
  • the drive signal can be changed to be transmitted to the device to be driven.
  • the duration of the driving element 3 changes the working duration of the element 3 to be driven.
  • the second control unit 23 is electrically connected to the enable signal terminal EM, the second data signal terminal DATA2, and the second driving unit 22, and is configured to receive at the second data signal terminal DATA2 under the control of the enable signal terminal EM
  • the second data signal Data2 whose potential changes within a set range is transmitted to the second driving unit 22.
  • the transmission time of the drive signal to the component to be driven 3 is related to the second data signal Data2 whose potential changes within the set range.
  • the second data signal The driving unit 22 is turned on, and the driving signal is transmitted to the second control unit 23 at this time.
  • the second driving unit 22 is also electrically connected to the driving signal control sub-circuit 1, and is configured to transmit the driving signal according to a second data signal Data2 having a set working potential and a second data signal Data2 whose potential changes within a set range. To the second control unit 23 and control the duration of the drive signal transmission to the second control unit 23.
  • the second control unit 23 is also electrically connected to the component 3 to be driven, and is also configured to transmit a driving signal to the component 3 to be driven.
  • the second data signal Data2 with the set working potential is written to the second driving unit 22 through the second data writing unit 21, and the potential is set to the second driving unit 22 through the second control unit 23.
  • the second data signal Data2 that changes within the set range is transmitted to the second drive unit 22, and through the second drive unit 22, according to the second data signal Data2 with the set working potential and the second data signal whose potential changes within the set range
  • the second data signal Data2 transmits the driving signal to the second control unit 23 and controls the duration of the transmission of the driving signal to the second control unit 23. Therefore, the aforementioned driving duration control sub-circuit 2 realizes the effect of controlling the duration of transmission of the driving signal to the second control unit 23 to control the working duration of the component 3 to be driven, and thereby the working state of the component 3 to be driven.
  • the above-mentioned second data writing unit 21 includes: an eighth transistor M8.
  • the control electrode of the eighth transistor M8 is electrically connected to the second scan signal terminal GATE2, the first electrode of the eighth transistor M8 is electrically connected to the second data signal terminal DATA2, and the second electrode of the eighth transistor M8 is electrically connected to the second driving unit 22. connection.
  • the eighth transistor M8 is configured to be turned on under the control of the second scan signal Gate2 to transmit the second data signal Data2 to the second driving unit 22.
  • the above-mentioned second control unit 23 includes: a ninth transistor M9 and a tenth transistor M10.
  • the control electrode of the ninth transistor M9 is electrically connected to the enable signal terminal EM, the first electrode of the ninth transistor M9 is electrically connected to the second data signal terminal DATA2, and the second electrode of the ninth transistor M9 is electrically connected to the second driving unit 22 .
  • the ninth transistor M9 is configured to be turned on under the control of the enable signal Em to transmit the second data signal Data2 to the second driving unit 22.
  • the control electrode of the tenth transistor M10 is electrically connected to the enable signal terminal EM, the first electrode of the tenth transistor M10 is electrically connected to the second driving unit 22, and the second electrode of the tenth transistor M10 is electrically connected to the component 3 to be driven.
  • the tenth transistor M10 is configured to be turned on under the control of the enable signal Em to transmit the driving signal to the element 3 to be driven.
  • the above-mentioned second driving unit 22 includes: a second storage capacitor C2 and an eleventh transistor M11.
  • the first end of the third storage capacitor C3 is electrically connected to the second data writing unit 21 and the second control unit 23, and is configured to receive the second data signal Data2 and store the second data signal Data2.
  • the control electrode of the eleventh transistor M11 is electrically connected to the second end of the third storage capacitor C3, the first electrode of the eleventh transistor M11 is electrically connected to the driving signal control sub-circuit 1, and the second electrode of the eleventh transistor M11 is electrically connected to The second control unit 23 is electrically connected.
  • the eleventh transistor M11 is configured to be turned on under the control of the voltage of the second terminal of the third storage capacitor C3 to transmit the driving signal to the tenth transistor M10.
  • the driving duration control sub-circuit 2 further includes: a second reset unit 24.
  • the second reset unit 24 is electrically connected to the reset signal terminal RESET, the initialization signal terminal VINIT, and the second driving unit 22, and is configured to, under the control of the reset signal terminal RESET, according to the initialization signal Vinit received at the initialization signal terminal VINIT, The voltage of the second driving unit 22 is reset.
  • the second reset unit 24 resets the voltage of the second drive unit 22 to reduce the noise of the signal at the second drive unit 22, so that the second data writing unit 21 will When the data signal Data2 is written to the second driving unit 22, the input second data signal Data2 is more accurate.
  • the second reset unit 24 includes: a twelfth transistor M12 and a thirteenth transistor M13.
  • the control electrode of the twelfth transistor M12 is electrically connected to the reset signal terminal RESET, the first electrode of the twelfth transistor M12 is electrically connected to the initialization signal terminal VINIT, and the second electrode of the twelfth transistor M12 is electrically connected to the second driving unit 22 .
  • the twelfth transistor M12 is configured to be turned on under the control of the reset signal Reset to transmit the initialization signal Vinit to the second driving unit 22.
  • the control electrode of the thirteenth transistor M13 can be connected to the reset signal terminal RESET, and the first electrode and the second electrode of the thirteenth transistor M13 are electrically connected to the second driving unit 22.
  • the thirteenth transistor M13 is configured to be turned on under the control of the reset signal Reset, and the control electrode of the eleventh transistor M11 is connected to the second electrode thereof, so that the eleventh transistor M11 is in a self-saturated state.
  • the driving duration control sub-circuit 2 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and The second storage capacitor C2.
  • the control electrode of the eighth transistor M8 is electrically connected to the second scan signal terminal GATE2, the first electrode of the eighth transistor M8 is electrically connected to the second data signal terminal DATA2, and the second electrode of the eighth transistor M8 is electrically connected to the second storage capacitor C2. The first end is electrically connected.
  • the eighth transistor M8 is configured to be turned on under the control of the second scan signal Gate2 to transmit the second data signal Data2 to the first end of the second storage capacitor C2.
  • the control electrode of the ninth transistor M9 is electrically connected to the enable signal terminal EM, the first electrode of the ninth transistor M9 is electrically connected to the second data signal terminal DATA2, and the second electrode of the ninth transistor M9 is electrically connected to the second storage capacitor C2. One end is electrically connected.
  • the ninth transistor M9 is configured to be turned on under the control of the enable signal Em to transmit the second data signal Data2 to the second storage capacitor C2.
  • the control electrode of the tenth transistor M10 is electrically connected to the enable signal terminal EM, the first electrode of the tenth transistor M10 is electrically connected to the second electrode of the eleventh transistor M11, and the second electrode of the tenth transistor M10 is electrically connected to the component to be driven 3 Electric connection.
  • the tenth transistor M10 is configured to be turned on under the control of the enable signal Em to transmit the driving signal to the element 3 to be driven.
  • the control electrode of the eleventh transistor M11 is electrically connected to the second terminal of the second storage capacitor C2, the first electrode of the eleventh transistor M11 is electrically connected to the driving signal control sub-circuit 1 and the second electrode of the twelfth transistor M12, The second electrode of the eleventh transistor M11 is also electrically connected to the first electrode of the thirteenth transistor M13.
  • the eleventh transistor M11 is configured to be turned on under the control of the voltage of the second terminal of the second storage capacitor C2 to transmit the driving signal to the tenth transistor M10.
  • the control electrode of the twelve transistor is electrically connected to the reset signal terminal RESET, and the first electrode of the twelve transistor is electrically connected to the initialization signal terminal VINIT.
  • the twelfth transistor M12 is configured to be turned on under the control of the reset signal Reset to transmit the initialization signal Vinit to the second driving unit 22.
  • the control electrode of the thirteenth transistor M13 is electrically connected to the reset signal terminal RESET, and the second electrode of the thirteenth transistor M13 is electrically connected to the second end of the second storage capacitor C2 and the control electrode of the eleventh transistor M11.
  • the thirteenth transistor M13 is configured to be turned on under the control of the reset signal Reset, and the control electrode of the eleventh transistor M11 is connected to the second electrode thereof, so that the eleventh transistor M11 is in a self-saturated state.
  • the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all P-type transistors or all N-type transistors. .
  • the specific structures of the driving signal control sub-circuit 1 and the driving duration control sub-circuit 2 have been exemplarily introduced above.
  • some embodiments of the present disclosure provide The driving signal control sub-circuit 1 in the pixel driving circuit 100 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and a first transistor M1.
  • a storage capacitor C1 the connection mode of each component can be referred to the introduction of the corresponding part above.
  • the driving duration control sub-circuit 2 in the pixel driving circuit 100 includes: an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, and a Two storage capacitor C2, the connection mode of each component is as described in the corresponding part above.
  • Each of the above-mentioned transistors may be a P-type transistor or an N-type transistor.
  • the component to be driven 3 includes at least one light emitting diode 31, and the at least one light emitting diode is connected in series in the current path.
  • the anode of one of the light emitting diodes 31 is electrically connected to the second electrode of the tenth transistor M10, and the node at which the anode of the light emitting diode 31 is electrically connected to the second electrode of the tenth transistor M10 is equivalent to the fifth node N5.
  • the cathode of one of the light-emitting diodes 31 is electrically connected to a signal terminal.
  • the signal terminal is the second voltage signal terminal VSS.
  • the tenth transistor M10 is a P-type transistor
  • the second voltage signal terminal VSS may be grounded. , Or 0V.
  • the above-mentioned light-emitting diode 31 is a micro LED, a mini LED or an organic light-emitting diode.
  • Other quantum dot light-emitting diodes have high luminous efficiency at high current density and high luminous efficiency at low current density.
  • the embodiments of the present disclosure are not limited thereto.
  • transistors used in the circuit provided by the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.
  • the control electrode of each transistor used in the pixel driving circuit 100 is the gate of the transistor, one of the source and drain of the transistor at the first pole, and the other of the source and drain of the transistor at the second pole.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable. That is to say, the first and second electrodes of the transistor in the embodiment of the present disclosure The two poles can be indistinguishable in structure.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is a source and the second electrode is a drain; for example, when the transistor is an N-type transistor, the first electrode of the transistor is a drain,
  • the second pole is the source.
  • the specific implementation manners of the drive signal control sub-circuit 1 and the drive duration control sub-circuit 2 are not limited to the manner described above, and they can be implemented arbitrarily, such as those well known to those skilled in the art.
  • Conventional connection mode only needs to ensure that the corresponding function is realized.
  • the above examples do not limit the protection scope of the present disclosure.
  • the skilled person can choose to use or not apply one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the aforementioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • the pixel driving method includes: one frame period (1Frame) includes a scanning phase ts and working phase t-em.
  • the scanning stage t-s includes multiple line scanning periods, for example, (n is greater than or equal to 2), the multiple line scanning periods are n line scanning periods, and the n line scanning periods are t1 to tn, respectively.
  • Each of the multiple line scanning periods t1 to tn includes:
  • the driving signal control sub-circuit 1 writes the first data signal Data1 under the control of the first scan signal terminal GATE1; the driving time control sub-circuit 2 writes the data with the set working potential under the control of the second scan signal terminal GATE2 The second data signal Data2.
  • the driving signal control sub-circuit 1 includes a first data writing unit 11, a first driving unit 12, and a first control unit 13, the first data writing unit 11 is connected to the first scan signal terminal GATE1 It is turned on under control, and the first data signal Data1 received at the first data signal terminal DATA1 is written to the first driving unit 12.
  • the first data writing unit 11 includes a first transistor M1 and a second transistor M2
  • the first driving unit 12 includes a first storage capacitor C1 and a third transistor M3, and the first control unit 13
  • the fourth transistor M4 and the fifth transistor M5 are included:
  • the first transistor M1 is turned on under the control of the first scan signal Gate1, and transmits the first data signal Data1 received at the first data signal terminal DATA1 to the first terminal of the first storage capacitor C1 At this time, the potential of the first terminal of the first storage capacitor C1 is the potential of the first data signal Data1.
  • the second transistor M2 is turned on under the control of the first scan signal Gate1, and the control electrode of the third transistor M3 is connected to the second electrode, so that the third transistor M3 is in a self-saturated state, and the voltage of the control electrode of the third transistor M3 As the sum of the voltage of its first electrode and its threshold voltage, the first electrode of the third transistor M3 is connected to the third voltage signal terminal VREF, so the potential of the first electrode of the third transistor M3 is the potential of the third voltage signal Vref, Then the potential of the control electrode of the third transistor M3 is the sum of the potential of the third voltage signal Vref and the threshold voltage of the third transistor M3.
  • the potential of the second terminal of the first storage capacitor C1 is the same as the potential of the control electrode of the third transistor M3, and the potential of the second terminal of the first storage capacitor C1 is the difference between the potential of the third voltage signal Vref and the threshold voltage of the third transistor M3 with. At this time, there is a potential difference between the first terminal and the second terminal of the first storage capacitor C1, so that the first storage capacitor C1 is charged.
  • the driving duration control sub-circuit 2 includes a second data writing unit 21, a second control unit 23, and a second driving unit 22, the second data writing unit 21 is connected to the second scan signal terminal GATE2. It is turned on under control, and the second data signal Data2 received at the second data signal terminal DATA2 is written into the second driving unit 22.
  • the second data signal Data2 has a set working potential, and the set working potential is related to the working time of the component 3 to be driven, and depends on the working time of the component 3 to be driven.
  • the second data writing unit 21 includes an eighth transistor M8, the second control unit 23 includes a ninth transistor M9 and a tenth transistor M10, and the second driving unit 22 includes a second storage capacitor.
  • the eleventh transistor M11 In the case of C2 and the eleventh transistor M11:
  • the eighth transistor M8 is turned on under the control of the second scan signal Gate2, and transmits the second data signal Data2 to the first end of the second storage capacitor C2 and the first end of the second storage capacitor C2.
  • the potential of is the set working potential of the second data signal Data2, which realizes the charging of the second storage capacitor C2.
  • each of the n line scanning periods includes the above S1 to S2, so that the scanning of the n rows of sub-pixels is realized, and the first data signal Data1 for the n rows of sub-pixels is completed. And the writing of the second data signal Data2, and the first data signal Data1 and the second data signal Data2 are stored in preparation for the output of the driving signal in the working phase t-em.
  • the working phase t-em includes:
  • the driving signal control sub-circuit 1 provides a driving signal to the driving duration control sub-circuit 2 under the control of the enable signal terminal EM.
  • the driving signal is related to the first data signal Data1 and the first voltage signal Vdd provided by the first voltage signal terminal VDD; under the control of the enable signal terminal EM, the driving duration control sub-circuit 2 receives the first voltage signal whose potential changes within the set range.
  • the second data signal Data2 transmits the driving signal to the component 3 to be driven.
  • the duration of the transmission of the driving signal to the component to be driven 3 is related to the second data signal Data2 with the set working potential and the second data signal Data2 with the potential changing within the set range.
  • the drive signal control sub-circuit 1 includes the first data writing unit 11, the first drive unit 12, and the first control unit 13, the first control unit 13 is turned on under the control of the enable signal terminal EM , The drive signal is transmitted to the drive duration control sub-circuit 2.
  • the first data writing unit 11 includes a first transistor M1 and a second transistor M2
  • the first driving unit 12 includes a first storage capacitor C1 and a third transistor M3, and the first control unit 13
  • the fourth transistor M4 and the fifth transistor M5 are included:
  • the fourth transistor M4 is turned on under the control of the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the first terminal of the first storage capacitor C1, The potential of the first terminal of the first storage capacitor C1 becomes the potential of the first voltage signal Vdd.
  • the potential difference between the first terminal and the second terminal of the first storage capacitor C1 remains unchanged. Since the potential of the first terminal of the first storage capacitor C1 jumps from the potential of the first data signal Data1 to the potential of the first voltage signal Vdd, the potential of the first terminal of the first storage capacitor C1 also jumps accordingly.
  • the third transistor M3 is turned on and generates a driving current, which is output from the second pole of the third transistor M3.
  • the fifth transistor M5 is turned on under the control of the enable signal terminal EM, and transmits the driving signal to the driving duration control sub-circuit 2, that is, the driving current generated by the third transistor M3 is transmitted to the driving duration control through the fifth transistor M5 Sub-circuit 2.
  • the driving duration control sub-circuit 2 includes a second data writing unit 21, a second control unit 23, and a second driving unit 22, the second control unit 23 is turned on under the control of the enable signal terminal EM , The second data signal Data2 whose potential changes within the set range is written into the second driving unit 22.
  • the voltage of the second data signal Data2 changes within a set range.
  • the second driving unit 22 is turned on, and the driving signal is transmitted to the second control unit 23, and the The two control units 23 are transmitted to the component to be driven 3, so that the component to be driven 3 starts to work, wherein the above-mentioned specific voltage value is related to the set working potential.
  • the second data writing unit 21 includes an eighth transistor M8, the second control unit 23 includes a ninth transistor M9 and a tenth transistor M10, and the second driving unit 22 includes a second storage capacitor.
  • the ninth transistor M9 is turned on under the control of the enable signal terminal EM, and transmits the second data signal whose potential changes within the set range to the second storage capacitor
  • the potential of the first terminal of C2 and the first terminal of the second storage capacitor C2 is the potential of the second data signal Data2, and the potential changes within a set range.
  • the potential of the second terminal is also Change accordingly.
  • the potential of the control electrode of the eleventh transistor M11 is the same as the potential of the second terminal of the second storage capacitor C2, so that the potential of the control electrode of the eleventh transistor M11 is also changing.
  • the gate-source voltage difference of the eleventh transistor M11 is ( When the absolute value of the potential difference between the control electrode and the first electrode) is greater than its threshold voltage, the eleventh transistor M11 is turned on to transmit the driving signal to the first electrode of the tenth transistor M10.
  • the tenth transistor M10 is turned on under the control of the enable signal terminal EM, and transmits the driving signal to the component 3 to be driven, so that the component 3 to be driven starts to work.
  • the first data signal Data1 and the second data signal Data2 of each row of sub-pixels are written in the scanning phase ts, and the driving signal is generated during the working phase t-em to drive Signal output, and control the duration of the driving signal to the component 3 to be driven.
  • the control of the component 3 to be driven is achieved.
  • the element to be driven 3 is a light-emitting device
  • the pixel driving method described above is used to change the light-emitting intensity of the light-emitting device by controlling the driving current and the light-emitting duration of the light-emitting device, thereby realizing the corresponding grayscale display.
  • the driving current of the device reduces the luminous intensity of the light-emitting device. In this way, the driving current transmitted to the light-emitting device is always large, the light-emitting device is always at a high current density, and the luminous efficiency is high, thereby reducing power consumption and saving costs.
  • the pixel driving method further includes: in each row scanning period, the first reset unit 14 resets the voltage of the first driving unit 12 under the control of the reset signal terminal RESET.
  • the second reset unit 24 resets the voltage of the second driving unit 22 under the control of the reset signal terminal RESET.
  • the sixth transistor M6 is turned on under the control of the reset signal Reset
  • the first reset unit 14 includes the sixth transistor M6 and the seventh transistor M7.
  • the voltage signal Vdd is transmitted to the first driving unit 12
  • the seventh transistor M7 is turned on under the control of the reset signal Reset
  • the initialization signal Vinit is transmitted to the first driving unit 12, thereby resetting the voltage of the first driving unit 12.
  • the second reset unit 24 includes the twelfth transistor M12 and the thirteenth transistor M13
  • the thirteenth transistor M13 is turned on under the control of the reset signal terminal RESET
  • the twelfth transistor M12 is under the control of the reset signal Reset.
  • the initialization signal Vinit is transmitted to the second driving unit 22, so as to reset the voltage of the second driving unit 22.
  • the voltage of the first driving unit 12 is reset by the first reset unit 14 and the voltage of the second driving unit 22 is reset by the second reset unit 24, so that the voltage of the second driving unit 22 is reset.
  • the signals at the first driving unit 12 and the second driving unit 22 are noise-reduced, so that the first data signal Data1 input to the first driving unit 12 and the second data signal Data2 input to the second driving unit 22 are not interfered, and it is more accurate .
  • the absolute value of the set working potential is related to the working duration of the corresponding component 3 to be driven.
  • the absolute value of the set working potential of the second data signal Data2 written by each pixel driving circuit 100 is related to the working time required for the component 3 to be driven by the pixel driving circuit 100 to work.
  • the absolute value of the set working potential of the second data signal Data2 written by each pixel drive circuit 100 is consistent with that the light-emitting device corresponding to the pixel drive circuit 100 needs to emit light.
  • the light-emitting duration is related, and by changing the absolute value of the set working potential, the light-emitting duration of the light-emitting device can be controlled, so as to realize the control of the gray scale of the sub-pixels.
  • the pixel driving circuit 100 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9.
  • the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the first storage capacitor C1, the second storage capacitor C2, and the stabilized storage capacitor C3, and the above-mentioned transistors are all P-type transistors .
  • the component to be driven 3 includes a light emitting diode 31.
  • the pixel driving method includes: a frame period 1Frame includes a scanning stage ts and a working stage t-em, the scanning stage ts includes a plurality of line scanning periods t1 to tn, each of the plurality of line scanning periods t1 to tn
  • the line scanning period includes: a first sub-period and a second sub-period.
  • the first line scanning period t1 includes the first sub-period t1-1 and the second sub-period t1-2
  • the second line scanning period t2 includes the first sub-period t2-1 and the second sub-period t2-2
  • the scanning period tn of the nth row includes a first sub-period tn-1 and a second sub-period tn-2.
  • the display device includes n rows and m columns of sub-pixels, and each sub-pixel corresponds to one pixel driving circuit 100
  • the scanning stage ts the sub-pixels from the first row to the n-th row are scanned row by row.
  • the working phase t-em is entered.
  • the pixel driving circuit 100 corresponding to the sub-pixels in the n rows and m columns simultaneously receives the same second The data signal data2 and the potential of the second data signal data2 written by the pixel driving circuit 100 corresponding to each sub-pixel all change within a set range.
  • m pixel driving circuits 100 corresponding to m sub-pixels in the same row are simultaneously written with different first data signals data1, that is to say, the first data signals data1 are a group of signals; the same row
  • the m pixel driving circuits 100 corresponding to the m sub-pixels are simultaneously written with different second data signals data2, that is, the second data signal data2 is a group of signals.
  • the first data signal data1 and the second data signal data2 written by the m pixel driving circuits 100 corresponding to the m sub-pixels in the same row are related to the gray levels that the corresponding sub-pixels need to display.
  • the pixel driving circuit 100 corresponding to the sub-pixels in the first column is taken as an example for description.
  • the potential of the first data signal data1 transmitted by the first data signal terminal DATA1 is referred to as V1.
  • the potential of the first data signal data1 is V1 (1)
  • the potential of the first data signal data1 is V1 (2)
  • the potential of the first data signal data1 is V1 (n) .
  • the potential of the second data signal data2 transmitted by the second data signal terminal DATA2 is referred to as the set working potential Vs.
  • the set working potential of the second data signal data2 is Vs (1)
  • the second The set working potential of the data signal data2 is Vs (2)
  • the potential of the second data signal data2 is Vs (n) .
  • Vs' the potential of the second data signal data2 transmitted by the second data signal terminal DATA2 is referred to as Vs'.
  • the potential of the second data signal data2 transmitted by the second data signal terminal DATA2 is called Vg, and the potential Vg changes within a set range. From the first row to the nth row, the potential Vg of the written second data signal changes within the setting range, and the setting range corresponding to each row is the same.
  • the pixel driving circuit corresponding to the first sub-pixel of the first line includes the following driving process:
  • the reset signal Reset transmitted by the reset signal terminal RESET and the second scan signal Gate2 transmitted by the second scan signal terminal GATE2 are low-level signals
  • the first scan signal Gate1 transmitted by the first scan signal terminal GATE1 and the enable signal terminal EM are transmitted
  • the enable signal Em is a high-level signal
  • the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are turned on under the control of the reset signal Reset
  • the eighth transistor M8 is turned on under the control of the second scan signal It is turned on under the control of Gate2, and all other transistors are turned off.
  • the sixth transistor M6 transmits the first voltage signal Vdd received at the first voltage signal terminal VDD to the first terminal of the first storage capacitor C1. At this time, the potential of the first terminal of the first storage capacitor C1 (the first node N1 The potential of) is the potential Vd of the first voltage signal Vdd.
  • the seventh transistor M7 transmits the initialization signal Vinit received at the initialization signal terminal VINIT to the second terminal of the first storage capacitor C1. At this time, the potential of the second terminal of the first storage capacitor C1 (the potential of the second node N2) is initialized.
  • the potential of the signal Vinit for example, the potential Vinit of the initialization signal Vinit is 0V.
  • the eighth transistor M8 transmits the second data signal Data2 received at the second data signal terminal DATA2 to the first terminal of the second storage capacitor C2.
  • the potential of the first terminal of the second storage capacitor C2 (the third node N3 The potential of) is the same as the potential of the second data signal Data2, which is the set working potential Vs (1) .
  • the twelfth transistor M12 transmits the initialization signal Vinit received at the initialization signal terminal VINIT to the first pole of the eleventh transistor M11, and the potential of the first pole of the eleventh transistor M11 is the potential of the initialization signal Vinit; Transistor M13 is turned on, connecting the control electrode of the eleventh transistor M11 with the second electrode, so that the eleventh transistor M11 is in a self-saturated state. At this time, the potential of the control electrode of the eleventh transistor M11 is the potential of the first electrode. (The potential of the initialization signal Vinit) and its threshold voltage Vth2.
  • the potential of the initialization signal Vinit is 0V
  • the potential of the control electrode of the eleventh transistor M11 is Vth2
  • the potential of the second end of the second storage capacitor C2 is also Vth2.
  • the pixel driving circuit corresponding to the first sub-pixel of the first line includes the following driving process:
  • the first scan signal Gate1 transmitted by the first scan signal terminal GATE1 and the second scan signal Gate2 transmitted by the second scan signal terminal GATE2 are low-level signals, and the reset signal Reset transmitted by the reset signal terminal RESET and the enable signal terminal EM are transmitted
  • the enable signal Em is a high-level signal.
  • the first transistor M1 and the second transistor M2 are turned on under the control of the first scan signal Gate1, the eighth transistor M8 is turned on under the control of the second scan signal Gate2, and the remaining transistors are all turned on. Shut down.
  • the first transistor M1 transmits the first data voltage Data1 received at the first data signal terminal DATA1 to the first terminal of the first storage capacitor C1.
  • the potential of the first terminal of the first storage capacitor C1 (the first node N1 The potential of) is the potential V1 (1) of the first data signal Data1.
  • the second transistor M2 is turned on, connecting the control electrode of the third transistor M3 to its second electrode, so that the third transistor M3 is in a self-saturated state, and the potential of the control electrode of the third transistor M3 is equal to that of the first electrode of the third transistor M3.
  • the sum of the electric potential and its threshold voltage Vth1 the electric potential of the first electrode of the third transistor M3 is the electric potential Vre of the third voltage signal Vref, the electric potential of the control electrode of the third transistor M3 is Vre+Vth1, and the electric potential of the first storage capacitor C1
  • the potential of the two terminals (the potential of the second node N2) is also Vre+Vth1.
  • the eighth transistor M8 transmits the second data signal Data2 received at the second data signal terminal DATA2 to the first terminal of the second storage capacitor C2.
  • the potential of the first terminal of the second storage capacitor C2 (the third node N3
  • the potential of the second data signal Data2 is the same as the potential Vs' of the second data signal Data2.
  • the potential Vs' of the second data signal is 0V.
  • the potential of the first terminal of the second storage capacitor C2 is the set working potential Vs (1)
  • the potential of the second terminal of the second storage capacitor C2 is Vth2.
  • Vs (1) the potential of the first terminal of the second storage capacitor C2
  • Vth2 the potential of the second terminal of the second storage capacitor C2
  • the potential difference between the first terminal and the second terminal of the second storage capacitor C2 remains unchanged, then in the second sub-period t1-2, the potential of the first terminal of the second storage capacitor C2 jumps to 0V, then the first The potential of the second terminal of the second storage capacitor C2 jumps to Vth2-Vs (1) .
  • the driving process of the pixel driving circuit 100 corresponding to the sub-pixels in the second row to the nth row is consistent with the driving process of the pixel driving circuit 100 corresponding to the sub-pixels in the first row.
  • the scanning period tn of the nth row refer to the description of the scanning period t1 of the first row.
  • each row of the sub-pixels of the display device enters the working stage t-em.
  • the working stage t-em of the first sub-pixel in the first row includes the following process:
  • the enable signal Em transmitted by the enable signal terminal EM is a low-level signal
  • the first scan signal Gate1 transmitted by the first scan signal terminal GATE1, the second scan signal Gate2 transmitted by the second scan signal terminal GATE2, and the reset signal terminal RESET are transmitted
  • the reset signal Reset is a high-level signal
  • the fourth transistor M4, the fifth transistor M5, and the tenth transistor M10 are turned on under the control of the enable signal Em, and the remaining transistors are all turned off.
  • the fourth transistor M4 transmits the first voltage signal Vdd received at the first voltage signal terminal VDD to the first terminal of the first storage capacitor C1. At this time, the potential of the first terminal of the first storage capacitor C1 (the first node N1 The potential of) is the potential Vd of the first voltage signal Vdd.
  • the potential of the first terminal of the first storage capacitor C1 is the potential V1 of the first data signal Data1 (1) , and the potential of the second terminal of the first storage capacitor C1 Is Vd+Vth1. According to the law of charge retention of the capacitor, the potential difference between the first terminal and the second terminal of the first storage capacitor C1 remains unchanged. Then in the working phase t-em, the first storage capacitor C1 The potential of the terminal becomes Vd, and the potential of the second terminal of the first storage capacitor C1 becomes Vd+Vre-V1 (1) +Vth1.
  • the third transistor M3 generates a driving current according to the first voltage signal Vdd and the potential of the second terminal of the second storage capacitor C2.
  • the fifth transistor M5 is turned on and transmits the driving current generated by the third transistor M3 to the first pole of the eleventh transistor M11.
  • the ninth transistor M9 transmits the second data signal Data2 received at the second data signal terminal DATA2 to the first terminal of the second storage capacitor C2.
  • the potential of the first terminal of the second storage capacitor C2 (the third node N3 The potential of) is the potential Vg of the second data signal Data2, and the potential Vg of the second data signal Data2 changes within a set range.
  • the two end values of the setting range are respectively: the non-operating potential Vgf of the second data signal Data2 and the reference operating potential Vgc.
  • the absolute value of the reference working potential Vgc is greater than or equal to the maximum value among the absolute values of all the set working potentials Vs of the second data signal Data2. Set the working potential Vs within the set range.
  • the non-working potential Vgf of the second data signal Data2 is 0V.
  • the potential Vg of the second data signal gradually changes from the non-working potential Vgf (0V) to the reference working potential Vgc, and the second storage
  • the potential of the first terminal of the capacitor C2 (the potential of the third node N3) also gradually changes from the non-operating potential Vgf (0V) to the reference operating potential Vgc.
  • the potential difference between the first terminal and the second terminal of the second storage capacitor C2 remains unchanged.
  • the second storage capacitor C2 The potential of the first terminal of the second storage capacitor C2 becomes 0V, the potential of the second terminal of the second storage capacitor C2 is Vth2-Vs (1) , and the potential difference between the first terminal and the second terminal of the second storage capacitor C2 is Vs (1 ) -Vth2, then in the working phase t-em, the potential of the second end of the second storage capacitor C2 (the potential of the fourth node N4 ) gradually changes from Vth2-Vs (1) to Vth2-Vs (1) +Vgc.
  • the potential of the control electrode of the eleventh transistor M11 (the potential of the fourth node N4) also gradually changes from Vth2-Vs (1) to Vth2-Vs ( 1) +Vgc.
  • the eleventh transistor M11 can be turned on.
  • V k the turn-on potential
  • Vd(1) is the potential of the first voltage signal Vdd after passing through the third transistor M3.
  • the eleventh transistor M11 When the gate voltage difference of the eleventh transistor M11 is When the absolute value is greater than or equal to the absolute value of its threshold voltage Vth2, the eleventh transistor M11 is turned on, that is, when the turn-on potential V k satisfies ⁇ V k -Vd(1) ⁇ Vth2 ⁇ , V k ⁇ Vth2+Vd (1) When the eleventh transistor M11 is turned on, the driving signal is passed through. Before that, the eleventh transistor M11 is turned off, and the driving signal cannot pass.
  • Vg of the second data signal Data2 changes from the non-operating potential Vgf (0V) to the set operating potential in the first sub-period t1-1 of the first line scanning period t1
  • Vs (1) the potential of the first terminal of the second storage capacitor C2 is Vs (1)
  • the potential of the second terminal of the second storage capacitor C2 is Vth2
  • the potential of the control electrode of the eleventh transistor M11 is Vth2 is, since Vth2 ⁇ Vth2 + Vd (1), the potential V k oN condition is satisfied, so the eleventh transistor M11 is turned on.
  • Vd(1) 0.
  • the eleventh transistor M11 keeps conducting, and the driving signal Transfer to the tenth transistor M10 until the end of the working phase.
  • the absolute value of the reference working potential Vgc is greater than or equal to the maximum value of the absolute values of all the set working potentials Vs of the second data signal Data2. For example, as shown in FIG. 6, refer to the above for the sub-pixels in the first row.
  • the absolute value of the reference working potential Vgc is greater than the absolute value of the set working potential Vs (1) of the second data signal Data2 in the first sub-period t1-1 of the first line scanning period t1, so It can be ensured that in the working phase t-em, when the potential Vg of the second data signal Data2 gradually changes from the non-working potential Vgf to the reference working potential Vgc, the turn-on potential V k is reached (for example, the working potential Vs (1) ), the eleventh transistor M11 can be turned on, so that the driving signal can be transmitted.
  • the absolute value of the reference working potential Vgc of the second data signal Data2 in the working phase t-em is greater than or equal to the set working potential Vs (2 ) , Vs (3) ... the absolute value of Vs (n) , so that the eleventh transistor M11 can be turned on.
  • the eleventh transistor M11 transmits the driving signal to the tenth transistor M10, and the tenth transistor M10 is turned on under the control of the enable signal Em to transmit the driving signal to the element to be driven 3, so that the component to be driven 3 works.
  • the driving process of the pixel driving circuit 100 corresponding to the sub-pixels in the second row to the nth row in the working phase t-em please refer to the pixel driving circuit 100 corresponding to the sub-pixels in the first row in the working phase t-em above.
  • the description of the driving process of the driving process please refer to the pixel driving circuit 100 corresponding to the sub-pixels in the first row in the working phase t-em above.
  • the potential V1 of the first data signal Data1 written by the pixel driving circuit 100 corresponding to each row of sub-pixels is working, and the pixel driving circuit 100 corresponding to the sub-pixels of the row is working.
  • the size of the drive signal generated during the t-em phase is related.
  • the potential of the second end of the first storage capacitor C1 of the pixel driving circuit 100 corresponding to each row of sub-pixels is Vd+Vre-V1+Vth1
  • the control electrode of the third transistor is The potential is Vd+Vre-V1+Vth1
  • the potential of the first electrode of the third transistor is Vre
  • I ds is the saturation current of the third transistor M3, that is, the operating current input to the light-emitting diode 31;
  • W/L is the channel width-to-length ratio of the third transistor M3;
  • ⁇ is the carrier mobility;
  • C ox is The channel capacitance per unit area of the third transistor M3;
  • V gs is the gate-source voltage difference of the third transistor M3;
  • Vth1 is the threshold voltage of the third transistor M3.
  • the drive current generated by the third transistor M3 is only related to the potential Vd of the first voltage signal Vdd and the potential V1 of the written first data signal Data1, and has nothing to do with the threshold voltage Vth1 of the third transistor M3, so the third The magnitude of the driving current generated by the transistor M3 is not affected by the threshold voltage, which avoids the difference in the threshold voltage of the third transistor M3 caused by the manufacturing process from affecting the driving current, thereby affecting the display effect.
  • the drive current generated by the third transistor M3 has nothing to do with the potential of the third voltage signal Vref, so the drive current generated by the third transistor M3 will not be affected by the voltage drop of the third voltage signal line, thereby avoiding the
  • the third voltage signal Vref received by each pixel driving circuit 100 is inconsistent due to the drop, and the size of the generated driving signal is inconsistent, causing the display panel to display unevenness.
  • the absolute value of the set operating potential Vs of the second data signal data2 is related to the operating duration of the corresponding component 3 to be driven.
  • the set working potential of the second data signal data2 written by the pixel driving circuit 100 corresponding to the sub-pixels in the first row is Vs (1)
  • the set working potential of the second data signal data2 written by the pixel driving circuit 100 corresponding to the sub-pixels in the second row is Vs (2)
  • the set working potential of the second data signal data2 written by the pixel driving circuit 100 corresponding to the sub-pixel of the nth row is Vs (n) , where the absolute values of Vs (1) , Vs (2) and Vs (n) decrease in order.
  • the potential of the second data signal data2 written by the pixel driving circuit 100 corresponding to each row of sub-pixels changes within a set range, and the potential of the second data signal data2 changes from the non-operating potential
  • Vgf (0V) changes to the set working potential Vs
  • the eleventh transistor M11 is turned on to transmit the driving signal to the component to be driven.
  • the potential of the second data signal data2 changes from the non-working potential Vgf (0V) to the set working potential Vs, the smaller the absolute value of the set working potential Vs, the first 2.
  • the anode of the light-emitting diode 31 is electrically connected to the second electrode of the tenth transistor M10, the node electrically connected between the two is equivalent to the fifth node N5, and the cathode of the light-emitting diode 31 is grounded.
  • the potential of the fifth node N5 is at a high level, the light emitting diode 31 starts to emit light. It can be seen from FIG.
  • Vs (1) , Vs (2), and Vs (n) decrease in order, and the corresponding light emitting diodes 31 emit light for t N5(1) , t N5(2) , t N5(n) increases in sequence, so that different gray scales can be displayed.
  • the control of the magnitude of the generated driving signal can be achieved, and the control of the driving signal can be achieved by controlling the scanning phase.
  • the absolute value of the set working potential of the second data signal Data2 of the drive duration control sub-circuit 2 is written, which can realize the control of the working duration of the drive element 3, so that under the cooperation of different drive signals and different working durations, Realize the display of different gray scales.
  • the magnitude of the driving signal can be maintained in a higher value range, which improves the working efficiency of the components to be driven and saves energy consumption.
  • control of the driving signal and the control of the working time are independent of the threshold voltage of the transistor, which avoids the unstable threshold voltage of the transistor caused by process defects and affects the display effect.
  • Some embodiments of the present disclosure also provide a display panel including the pixel driving circuit described above.
  • the display panel provided by the present disclosure adopts the above-mentioned pixel driving circuit.
  • the element to be driven is a micro light emitting diode
  • the micro light emitting diode has the characteristics of high luminous efficiency at high current density and low luminous efficiency at low current density.
  • the combination of current control and light-emitting duration control is adopted.
  • the light-emitting duration of the micro-light-emitting diode is controlled to realize the control of its light-emitting intensity, so that the current value of the input micro-light-emitting diode is kept in a relatively high range. In this way, the miniature light-emitting diode is always at a high current density, and the luminous efficiency is high, thereby reducing power consumption and saving costs.
  • the display panel 200 includes a plurality of sub-pixels 101, and each sub-pixel 101 corresponds to a pixel driving circuit 100, and the plurality of sub-pixels 101 are arranged in an array of multiple rows and multiple columns.
  • the plurality of sub-pixels 101 are arranged in an array of n rows and m columns.
  • the display panel 200 further includes: a plurality of first scan signal lines G1(1) to G1(n), a plurality of first data signal lines D1(1) to D1(m), and a plurality of second scan signal lines G2(1) ) To G2(n), and a plurality of second data signal lines D2(1) to D2(m).
  • Each pixel driving circuit 100 corresponding to the same row of sub-pixels 101 is electrically connected to the same first scanning signal line and the same second scanning signal line.
  • Each pixel driving circuit 100 corresponding to the same column of sub-pixels 101 is electrically connected to the same first data signal line and the same second data signal line.
  • the pixel driving circuit 100 corresponding to the first row of sub-pixels 101 is electrically connected to the first scanning signal line G1(1) and the second scanning signal line G2(1)
  • the pixel driving circuit corresponding to the first column of sub-pixels 101 100 is electrically connected to the first data signal line D1(1) and the second data signal line D2(1).
  • the plurality of first scan signal lines provide the first scan signal terminal GATE1 with the first scan signal Gate1
  • the plurality of second scan signal lines provide the second scan signal terminal GATE2 with the second scan signal Gate2
  • the plurality of first data signals The line provides the first data signal Data1 for the first data signal terminal DATA1
  • the plurality of second data signal lines provide the second data signal Data2 for the second data signal terminal DATA2, thereby providing the pixel driving circuit 100 with the first scan signal Gate1 and the first scan signal.
  • the display panel 200 further includes: multiple reset signal lines R(1) to R(n), multiple enable signal lines E1(1) to E1(n), multiple initialization signal lines VN, and multiple first voltage signals Line L VDD and a plurality of third voltage signal lines L VREF .
  • Each pixel driving circuit 100 corresponding to the same row of sub-pixels 101 is electrically connected to the same reset signal line, the same enable signal line, and the same third voltage signal line L VREF .
  • Each pixel driving circuit 100 corresponding to the sub-pixels 101 in the same column is electrically connected to the same initialization signal line.
  • the plurality of first voltage signal lines L VDD are respectively arranged in a grid shape along the row direction and along the column direction.
  • Each pixel driving circuit 100 corresponding to the sub-pixels 101 in the same column is connected to the same first voltage signal line arranged in the column direction.
  • L VDD is electrically connected.
  • a plurality of row direction are arranged along a first signal line L VDD voltage are a first voltage signal line L VDD electrically plurality of column direction of the arrangement is connected to a plurality of the row direction are arranged a first voltage signal line L VDD It is configured to reduce the resistance of the plurality of first voltage signal lines L VDD arranged in the column direction, and reduce the RC load and IR drop of the first voltage signal Vdd.
  • multiple reset signal lines provide reset signal Reset for the reset signal terminal RESET
  • multiple enable signal lines provide the enable signal Em for the enable signal terminal EM
  • multiple initialization signal lines provide the initialization signal Vinit for the initialization signal terminal VINIT.
  • the plurality of third voltage signal lines L VREF provide the third voltage signal terminal VREF with the third voltage signal Vref
  • the plurality of first voltage signal lines arranged along the column direction provide the first voltage signal terminal VDD with the s-th voltage signal Vdd .
  • the display panel 200 further includes:
  • the base substrate, the pixel driving circuit is arranged on the base substrate, and the base substrate is a glass substrate.
  • the above-mentioned display panel is a Micro LED display panel, and each sub-pixel of the plurality of sub-pixels included in the display panel corresponds to at least one micro light-emitting diode.
  • the pixel driving circuit 100 provided by the present disclosure aims at the characteristics of high luminous efficiency at high current density and low luminous efficiency at low current densities of miniature light-emitting diodes, the current control and light-emitting duration control are combined with each other to achieve different Gray-scale display, so when performing a lower gray-scale display, by shortening the light-emitting time of the micro-light-emitting diode, the current input to the micro-light-emitting diode is kept in a higher range, so that the micro-light-emitting diode is always at a high current density , The luminous efficiency is high, and the power consumption of the display panel is reduced, and the cost is saved. Therefore, the display panel provided in the present disclosure can be applied to an active driving mode.
  • the display panel provided by the present disclosure adopts an active driving method.
  • the pixel driving circuit 100 can be arranged on a base substrate made of glass. Since the splicing process of the glass substrate is relatively mature, the display panel can be spliced according to the display size. , A display panel with a larger display size is obtained, which is suitable for viewing at a medium distance.
  • the above-mentioned display panel is a TV screen.
  • the pixel driving circuit can be prepared by the processes of exposure, development, and etching with high preparation process accuracy, and the obtained pixel driving
  • the accuracy of the circuit 100 is high, and the size of the sub-pixels can be reduced.
  • the size of the sub-pixels can be 400 ⁇ m or less, which improves the resolution of the display panel and the image quality of the display screen is better.
  • the display panel is a Micro LED display panel
  • the color gamut and brightness of the display panel can be improved, enabling HDR display and improving the display effect of the display screen of the display panel.
  • the transistors in the pixel driving circuit 100 included in the display panel 200 adopt the LTPS (Low Temperature Poly-silicon, low temperature polysilicon) process and are prepared on a glass substrate. Because low temperature polysilicon has a high mobility, The characteristic of better stability can improve the response speed of the prepared transistor. Therefore, the LTPS process is more suitable for the pixel driving circuit 100 provided in the present disclosure that uses driving current and driving duration for control.
  • the threshold voltage of the third transistor M3 and the eleventh transistor M11 has been compensated in the driving method of the pixel driving circuit 100, the display effect of the display panel 200 will not be affected by transistors caused by defects in the LTPS process. The effect of threshold voltage shift.
  • some embodiments of the present disclosure further provide a display device 300 including the display panel 200 as described above.
  • the display device 300 provided by the present disclosure includes the above-mentioned display panel 200. Therefore, the display device 300 has the characteristics of large display size, high pixel resolution, suitable for HDR display, and excellent display effect.
  • the above-mentioned display device 300 is a product with a display function, such as a TV, a mobile phone, a tablet computer, a notebook computer, a display, a digital photo frame, or a navigator, and the present disclosure is not limited thereto.

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Abstract

一种像素驱动电路（100），包括：驱动信号控制子电路（1）和驱动时长控制子电路（2）；其中，驱动信号控制子电路（1）与第一扫描信号端（GATE1）、第一数据信号端（DATA1）、第一电压信号端（VDD）、使能信号端（EM）及驱动时长控制子电路（2）电连接，被配置为在第一扫描信号端（GATE1）和使能信号端（EM）的控制下，向驱动时长控制子电路（2）提供驱动信号；驱动信号与在第一数据信号端（DATA1）处接收的第一数据信号（Data1）和在第一电压信号端（VDD）处接收的第一电压信号（Vdd）有关；驱动时长控制子电路（2）还与第二扫描信号端（GATE2）、第二数据信号端（DATA2）、使能信号端（EM）及待驱动元件（3）电连接，被配置为在第二扫描信号端（GATE2）和使能信号端（EM）的控制下，将驱动信号传输至待驱动元件（3）；驱动信号传输至待驱动元件（3）的时长与在第二数据信号端（DATA2）处接收的第二数据信号（Data2）有关。

Description

像素驱动电路、像素驱动方法、显示面板及显示装置
本公开要求于2019年09月03日提交的申请号为PCT/CN2019/104235的国际申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、像素驱动方法、显示面板及显示装置。
背景技术
在显示技术领域，显示装置中应用HDR(高动态范围图像，High-Dynamic Range)技术能够实现显示画面的画质提升，同时也对显示装置的色域和亮度提出更高的要求，微型发光二极管显示装置因其亮度高，色域广的特点，更适合实现高动态范围图像的显示。
发明内容
第一方面，提供一种像素驱动电路，包括：驱动信号控制子电路和驱动时长控制子电路；其中，所述驱动信号控制子电路与第一扫描信号端、第一数据信号端、第一电压信号端、使能信号端及所述驱动时长控制子电路电连接，被配置为在所述第一扫描信号端和所述使能信号端的控制下，向所述驱动时长控制子电路提供驱动信号。所述驱动信号与在所述第一数据信号端处接收的第一数据信号和在所述第一电压信号端处接收的第一电压信号有关。所述驱动时长控制子电路还与第二扫描信号端、第二数据信号端、使能信号端及待驱动元件电连接，被配置为在所述第二扫描信号端和所述使能信号端的控制下，将所述驱动信号传输至所述待驱动元件。所述驱动信号传输至所述待驱动元件的时长与在所述第二数据信号端处接收的第二数据信号有关。
在一些实施例中，所述驱动信号控制子电路包括：第一数据写入单元、第一驱动单元及第一控制单元；其中，所述第一数据写入单元与所述第一扫描信号端、所述第一数据信号端及所述第一驱动单元电连接，被配置为在所述第一扫描信号端的控制下，将在所述第一数据信号端处接收的第一数据信 号写入至所述第一驱动单元。所述第一控制单元与所述使能信号端、所述第一电压信号端及所述第一驱动单元电连接，被配置为在所述使能信号端的控制下，将在所述第一电压信号端处接收的第一电压信号输入至所述第一驱动单元。所述第一驱动单元还与第三电压信号端电连接，被配置为根据所写入的第一数据信号和所输入的第一电压信号，及在所述第三电压信号端处接收的第三电压信号，产生所述驱动信号，并将所述驱动信号传输至所述第一控制单元。所述第一控制单元还与所述驱动时长控制子电路电连接，被配置为在所述使能信号端的控制下，将所述驱动信号传输至所述驱动时长控制子电路。
在一些实施例中，所述第一数据写入单元包括：第一晶体管和第二晶体管。所述第一晶体管的控制极与所述第一扫描信号端电连接，所述第一晶体管的第一极与所述第一数据信号端电连接，所述第一晶体管的第二极与所述第一驱动单元电连接。所述第二晶体管的控制极与所述第一扫描信号端电连接，所述第二晶体管的第一极和第二极与所述第一驱动单元电连接。
所述第一驱动单元包括：第一存储电容器和第三晶体管。所述第一存储电容器的第一端与所述第一数据写入单元及所述第一控制单元电连接，所述第一存储电容器的第二端与所述第一数据写入单元电连接。所述第三晶体管的控制极与所述第一存储电容器的第二端及所述第一数据写入单元电连接，所述第三晶体管的第一极与所述第一电压信号端电连接，所述第三晶体管的第二极与所述第一数据写入单元及所述第一控制单元电连接。
所述第一控制单元包括：第四晶体管和第五晶体管。所述第四晶体管的控制极与所述使能信号端电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第一驱动单元电连接。所述第五晶体管的控制极与所述使能信号端电连接，所述第五晶体管的第一极与所述第一驱动单元电连接，所述第五晶体管的第二极与所述驱动时长控制子电路电连接。
在一些实施例中，所述驱动信号控制子电路还包括：第一复位单元。所 述第一复位单元与所述第一电压信号端、复位信号端、初始化信号端及所述第一驱动单元电连接，被配置为在所述复位信号端的控制下，根据在所述第一电压信号端处接收的第一电压信号和在所述初始化信号端处接收的初始化信号，对所述第一驱动单元的电压进行复位。
在一些实施例中，所述第一复位单元包括：第六晶体管和第七晶体管。所述第六晶体管的控制极与所述复位信号端电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一驱动单元电连接。第七晶体管的控制极与所述复位信号端电连接，所述第七晶体管的第一极与所述初始化信号端电连接，所述第七晶体管的第二极与所述第一驱动单元电连接。
在一些实施例中，所述驱动信号控制子电路还包括：驱动信号稳定单元；所述驱动信号稳定单元与所述第一驱动单元连接，被配置为使所述第一驱动单元所产生的驱动信号保持稳定。
在一些实施例中，所述驱动信号稳定单元包括：稳压存储电容器。在所述第一驱动单元包括第一存储电容器和第三晶体管的情况下，所述稳压存储电容器的第一端与所述第一存储电容器的第一端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接；或者，所述稳压存储电容器的第一端与所述第一存储电容器的第二端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接。
在一些实施例中，所述驱动信号控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一存储电容器及稳压存储电容器。所述第一晶体管的控制极与所述第一扫描信号端电连接，所述第一晶体管的第一极与所述第一数据信号端电连接，所述第一晶体管的第二极与所述第一存储电容器的第一端电连接。所述第二晶体管的控制极与所述第一扫描信号端电连接，所述第二晶体管的第一极与所述第三晶体管的第二极电连接，所述第二晶体管的第二极与所述第一存储电容器的第二端及所述第三晶体管的控制极电连接。
所述第三晶体管的控制极还与所述第一存储电容器的第二端电连接，所述第三晶体管的第一极与所述第一电压信号端电连接，所述第三晶体管的第二极还与所述第五晶体管的第一极电连接。所述第四晶体管的控制极与所述使能信号端电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第一存储电容器的第一端电连接。
所述第五晶体管的控制极与所述使能信号端电连接，所述第五晶体管的第二极与所述驱动时长控制子电路电连接。所述第六晶体管的控制极与复位信号端电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一存储电容器的第一端电连接。所述第七晶体管的控制极与所述复位信号端电连接，所述第七晶体管的第一极与初始化信号端电连接，所述第七晶体管的第二极与所述第一存储电容器的第二端及所述第三晶体管的控制极电连接。
所述稳压存储电容器的第一端与所述第一存储电容器的第一端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接；或者，所述稳压存储电容器的第一端与所述第一存储电容器的第二端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接。
在一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及第七晶体管均为P型晶体管或者均为N型晶体管。
在一些实施例中，所述驱动时长控制子电路包括：第二数据写入单元、第二控制单元及第二驱动单元；其中，所述第二数据写入单元与所述第二扫描信号端、所述第二数据信号端及所述第二驱动单元电连接，被配置为在所述第二扫描信号端的控制下，将在所述第二数据信号端处接收的具有设定工作电位的第二数据信号写入至所述第二驱动单元。
所述第二控制单元与所述使能信号端、所述第二数据信号端及所述第二驱动单元电连接，被配置为在所述使能信号端的控制下，将在所述第二数据信号端处接收的电位在设定范围内变化的第二数据信号传输至所述第二驱动 单元。
所述第二驱动单元还与所述驱动信号控制子电路电连接，被配置为根据所述具有设定工作电位的第二数据信号和所述电位在设定范围内变化的第二数据信号，将所述驱动信号传输至所述第二控制单元，并控制所述驱动信号传输至所述第二控制单元的时长。所述第二控制单元还与所述待驱动元件电连接，还被配置为将所述驱动信号传输至所述待驱动元件。
在一些实施例中，所述第二数据写入单元包括：第八晶体管，所述第八晶体管的控制极与所述第二扫描信号端电连接，所述第八晶体管的第一极与所述第二数据信号端电连接，所述第八晶体管的第二极与所述第二驱动单元电连接。
所述第二控制单元包括：第九晶体管和第十晶体管，所述第九晶体管的控制极与所述使能信号端电连接，所述第九晶体管的第一极与所述第二数据信号端电连接，所述第九晶体管的第二极与所述第二驱动单元电连接。所述第十晶体管的控制极与所述使能信号端电连接，所述第十晶体管的第一极与所述第二驱动单元电连接，所述第十晶体管的第二极与所述待驱动元件电连接。
所述第二驱动单元包括：第二存储电容器和第十一晶体管，所述第二存储电容器的第一端与所述第二数据写入单元及所述第二控制单元电连接；所述第十一晶体管的控制极与所述第二存储电容器的第二端电连接，所述第十一晶体管的第一极与所述驱动信号控制子电路电连接，所述第十一晶体管的第二极与所述第二控制单元电连接。
在一些实施例中，所述驱动时长控制子电路还包括：第二复位单元；所述第二复位单元与复位信号端、初始化信号端及所述第二驱动单元电连接，被配置为在所述复位信号端的控制下，根据在所述初始化信号端处接收的初始化信号，对所述第二驱动单元的电压进行复位。
在一些实施例中，所述第二复位单元包括：第十二晶体管和第十三晶体管。所述第十二晶体管的控制极与所述复位信号端电连接，所述第十二晶体 管的第一极与所述初始化信号端电连接，所述第十二晶体管的第二极与所述第二驱动单元电连接。所述第十三晶体管的控制极与所述复位信号端能接，所述第十三晶体管的第一极和第二极与所述第二驱动单元电连接。
在一些实施例中，所述驱动时长控制子电路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第二存储电容器。所述第八晶体管的控制极与所述第二扫描信号端电连接，所述第八晶体管的第一极与所述第二数据信号端电连接，所述第八晶体管的第二极与所述第二存储电容器的第一端电连接。所述第九晶体管的控制极与所述使能信号端电连接，所述第九晶体管的第一极与所述第二数据信号端电连接，所述第九晶体管的第二极与所述第二存储电容器的第一端电连接。
所述第十晶体管的控制极与所述使能信号端电连接，所述第十晶体管的第一极与所述第十一晶体管的第二极电连接，所述第十晶体管的第二极与所述待驱动元件电连接。所述第十一晶体管的控制极与所述第二存储电容器的第二端电连接，所述第十一晶体管的第一极与所述驱动信号控制子电路及所述第十二晶体管的第二极电连接，所述第十一晶体管的第二极还与所述第十三晶体管的第一极电连接。
所述十二晶体管的控制极与复位信号端电连接，所述十二晶体管的第一极与初始化信号端电连接。所述第十三晶体管的控制极与所述复位信号端电连接，所述第十三晶体管的第二极与所述第二存储电容器的第二端及所述第十一晶体管的控制极电连接。
在一些实施例中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管及所述第十三晶体管均为P型晶体管或者均为N型晶体管。
第二方面，提供一种像素驱动方法，应用于如第一方面中任选一项所述像素驱动电路，所述像素驱动方法包括：一个帧周期包括扫描阶段和工作阶段，所述扫描阶段包括多个行扫描时段。所述多个行扫描时段中的每个行扫描时段包括：驱动信号控制子电路在第一扫描信号端的控制下，写入第一数 据信号；驱动时长控制子电路在所述第二扫描信号端的控制下，写入具有设定工作电位的第二数据信号。
所述工作阶段包括：所述驱动信号控制子电路在使能信号端的控制下，向所述驱动时长控制子电路提供驱动信号；所述驱动信号与所述第一数据信号和第一电压信号端提供的第一电压信号有关。所述驱动时长控制子电路在所述使能信号端的控制下，接收电位在设定范围内变化的第二数据信号，将所述驱动信号传输至待驱动元件；所述驱动信号传输至所述待驱动元件的时长与所述具有设定工作电位的第二数据信号和所述电位在设定范围内变化的第二数据信号有关。
在一些实施例中，设定工作电位的绝对值与相应的待驱动元件需要工作的工作时长相关。
在一些实施例中，所述设定范围的两个端点值分别为：所述第二数据信号的非工作电位和参考工作电位；所述参考工作电位的绝对值大于或等于所述第二数据信号的全部设定工作电位的绝对值中的最大值；所述设定工作电位在所述设定范围之内。
第三方面，提供一种显示面板，包括如第一方面中任一项所述的像素驱动电路。
在一些实施例中，所述显示面板包括多个亚像素，每个亚像素对应一个所述像素驱动电路，所述多个亚像素呈多行多列的阵列式布置。所述显示面板还包括：多条第一扫描信号线、多条第一数据信号线、多条第二扫描信号线、及多条第二数据信号线。同一行亚像素对应的各像素驱动电路与同一条第一扫描信号线及同一条第二扫描信号线电连接。同一列亚像素对应的各像素驱动电路与同一条第一数据信号线及同一条第二数据信号线电连接。
在一些实施例中，上述显示面板还包括：衬底基板，所述像素驱动电路设置于所述衬底基板上，所述衬底基板为玻璃基板。
第四方面，提供一种显示装置，包括如第三方面所述的显示面板。
附图说明
为了更清楚地说明本公开一些实施例中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。
图1为根据本公开的一些实施例的一种像素驱动电路的一种结构示意图；
图2A为根据本公开的一些实施例的一种像素驱动电路的另一种结构示意图；
图2B为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图3A为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图3B为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图4为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图5A为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图5B为根据本公开的一些实施例的一种像素驱动电路的又一种结构示意图；
图6为根据本公开的一些实施例的像素驱动方法的时序图；
图7为根据本公开的一些实施例的显示面板的结构示意图；
图8为根据本公开的一些实施例的显示装置的示意图；
图9为根据本公开的一些实施例的信号串扰的示意图；
图10为根据一些实施例的晶体管的I-V特性曲线的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而 不是全部的实施例。基于本公开中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在显示技术领域，Micro LED(微型发光二极管)显示装置的亮度高，色域广，能够满足应用HDR(高动态范围图像，High-Dynamic Range)技术对显示装置的亮度和色域的要求，更适合实现HDR的显示。
在相关技术中，微型发光二极管显示装置的像素驱动电路通常采用电流驱动控制，通过控制输入微型发光二极管的驱动电流的大小来实现控制微型发光二极管的发光强度，进而实现不同灰阶的显示。例如，在实现较低的灰阶的显示时，会提供较小的驱动电流，使微型发光二极管的发光亮度降低；在实现较高的灰阶的显示时，提供较大的驱动电流，使微型发光二极管的发光亮度提高。
本公开的发明人经研究发现，微型发光二极管具有在高电流密度下发光效率高，在低电流密度下发光效率低且主波峰偏移的特性。具体表现为：在输入微型发光二极管的驱动电流达到一定值时，微型发光二极管的发光效率达到最高；在驱动电流没有达到该值时，微型发光二极管的发光效率一直处于爬坡阶段，即随着所提供的驱动电流的增大，微型发光二极管的发光强度逐渐增大，同时发光效率逐渐增大，增大到一定程度，微型发光二极管的发光效率趋于稳定。
这样，在采用相关技术中通过驱动电流幅值大小控制微型发光二极管的发光强度的驱动方式的情况下，在实现较低灰阶的显示时，输入微型发光二极管的驱动电流较低，这样微型发光二极管就处于低电流密度下，造成微型发光二极管的发光效率较低，能耗较高，显示装置进行显示时功耗较大，造成能源损耗。
本公开的一些实施例提供了一种像素驱动电路100，如图1所示，该像素驱动电路100包括：驱动信号控制子电路1和驱动时长控制子电路2。
驱动信号控制子电路1与第一扫描信号端GATE1、第一数据信号端DATA1、第一电压信号端VDD、使能信号端EM及驱动时长控制子电路2电 连接。其中，第一扫描信号端GATE1被配置为接收第一扫描信号Gate1，并向驱动信号控制子电路1输入该第一扫描信号Gate1；第一数据信号端DATA1被配置为接收第一数据信号Data1，并向驱动信号控制子电路1输入该第一数据信号Data1；第一电压信号端VDD被配置为接收第一电压信号Vdd，并向驱动信号控制子电路1输入该第一电压信号Vdd；使能信号端EM被配置为接收使能信号Em，并向驱动信号控制子电路1输入该使能信号Em。
驱动信号控制子电路1被配置为在第一扫描信号端GATE1和使能信号端EM的控制下，向驱动时长控制子电路2提供驱动信号。该驱动信号与在第一数据信号端DATA1处接收的第一数据信号Data1和在第一电压信号端VDD处接收的第一电压信号Vdd有关。
驱动时长控制子电路2还与第二扫描信号端GATE2、第二数据信号端DATA2、使能信号端EM及待驱动元件3电连接。其中，第二扫描信号端GATE2被配置为接收第二扫描信号Gate2，并向驱动信号控制子电路1输入该第二扫描信号Gate2；第二数据信号端DATA2被配置为接收第二数据信号Data2，并向驱动时长控制子电路2输入该第二数据信号Data2；使能信号端EM被配置为接收使能信号Em，并向驱动信号控制子电路1输入该使能信号Em。
驱动时长控制子电路2被配置为在第二扫描信号端GATE2和使能信号端EM的控制下，将驱动信号传输至待驱动元件3。该驱动信号传输至待驱动元件3的时长与在第二数据信号端DATA2处接收的第二数据信号Data2有关。
由此，上述像素驱动电路100包括驱动信号控制子电路1和驱动时长控制子电路2，驱动信号控制子电路1被配置为向驱动时长控制子电路2提供驱动信号，并且驱动信号的大小与第一数据信号Data1和第一电压信号Vdd有关；驱动时长控制子电路2被配置为将驱动信号传输至待驱动元件3，且驱动信号传输至待驱动元件3的时长与第二数据信号Data2有关，在驱动信号传输至待驱动元件3的情况下，待驱动元件3工作，也就是待驱动元件3的工作时长与第二数据信号Data2有关。
这样，在驱动信号控制子电路1和驱动时长控制子电路2的共同作用下，通过控制驱动信号的大小，以及驱动信号传输至待驱动元件3的时长，实现对待驱动元件3的驱动信号的大小以及工作时长的控制，进而实现对待驱动元件3的控制。
在一些实施例中，待驱动元件3为发光器件，例如，微型发光二极管，驱动信号控制子电路1通过控制驱动信号的大小，从而控制传输至发光器件的驱动电流的大小，驱动时长控制子电路2通过控制驱动信号传输至发光器件的时长，从而控制发光器件的工作时长，这样在进行不同灰阶的显示时，通过控制发光器件的驱动电流大小以及发光时长实现改变发光器件的发光强度，进而实现对应的灰阶显示。
本公开的发明人经研究发现，在驱动电流较大时，微型发光二极管等发光器件处于高电流密度下，发光效率较高，能耗较低。利用上述像素驱动电路100，在实现较高灰阶的显示时，通过增大输入发光器件的驱动电流，提高发光器件的发光强度；在实现较低灰阶的显示时，通过缩短发光器件的工作时长，不需要降低输入发光器件的驱动电流，使得发光器件的发光强度降低。这样，传输至发光器件的驱动电流始终较大，发光器件始终处于高电流密度下，发光效率较高，进而实现了降低功耗，节约成本的效果。
在一些实施例中，在待驱动元件3微型发光二极管的情况下，为第一数据信号端DATA1提供的第一数据信号Data1可以为使待驱动元件3能够具有较高的发光效率的固定高电平信号，在此情况下，像素驱动电路100主要通过驱动时长控制子电路1来控制灰阶。在另一些实施例中，第一数据信号Data1的电位可以在一定的电压区间范围内变化，在该电压区间范围内的第一数据信号Data1能够保证待驱动元件3具有较高的发光效率，在此情况下，像素驱动电路100通过驱动信号控制子电路1和驱动时长控制子电路2的共同作用来控制灰阶。通过这样设置，在上述两种情况下，待驱动元件3均能够具有较高的发光效率，从而功耗得以降低。
在一些实施例中，如图2A和图3A所示，上述驱动信号控制子电路1包 括：第一数据写入单元11、第一驱动单元12及第一控制单元13。
第一数据写入单元11与第一扫描信号端GATE1、第一数据信号端DATA1及第一驱动单元12电连接，被配置为在第一扫描信号端GATE1的控制下，将在第一数据信号端DATA1处接收的第一数据信号Data1写入至第一驱动单元12。
第一驱动单元12还与第一电压信号端VDD及第一控制单元13电连接，被配置为根据所写入的第一数据信号Data1和在第一电压信号端VDD处接收的第一电压信号Vdd，产生驱动信号，并将驱动信号传输至第一控制单元13。
第一控制单元13还与使能信号端EM、第一电压信号端VDD及驱动时长控制子电路2电连接，被配置为在使能信号端EM的控制下，根据第一电压信号Vdd，将驱动信号传输至驱动时长控制子电路2。
在上述驱动信号控制子电路1中，通过第一数据写入单元11，将第一数据信号Data1写入至第一驱动单元12，第一驱动单元12根据第一数据信号Data1和第一电压信号Vdd，产生驱动信号，并将驱动信号传输至第一控制单元13，第一控制单元13将驱动信号传输至所述驱动时长控制子电路2，从而上述驱动信号控制子电路1实现了向驱动时长控制子电路2提供驱动信号，且驱动信号与第一数据信号Data1和第一电压信号Vdd有关。
在上述实施例中，第一驱动单元12与第一电压信号端VDD电连接，也就是说，第一驱动单元12和第一控制单元13均与第一电压信号端VDD电连接。这样，第一控制单元13在使能信号端EM的控制下，将在第一电压信号端VDD处接收的第一电压信号Vdd输入至第一驱动单元12。第一驱动单元12根据第一数据写入单元11所写入的第一数据信号Data1和第一控制单元13所输入的第一电压信号Vdd，及在第一电压信号端VDD处接收的第一电压信号Vdd，产生驱动信号，并将驱动信号传输至第一控制单元13。且驱动信号的大小与第一数据信号Data1和第一电压信号Vdd有关。
在上述驱动信号控制子电路1中，第一驱动单元12和第一控制单元13均与第一电压信号端VDD电连接，接收第一电压信号端VDD所传输的第一 电压信号Vdd，不需要额外设置单独向第一驱动单元12提供电压信号的电压信号端，或者，不需要额外设置单独向第一控制单元13提供电压信号的电压信号端，这样电路结构得以简化。且在像素驱动电路100所应用的显示面板上，只需要设置被配置为向第一电压信号端VDD提供第一电压信号Vdd的第一电压信号线，不需要额外设置其他的电压信号线，这样可以减少布线数量，简化电路结构。
本公开的发明人经研究发现：采用上述驱动信号控制子电路1，在一些情况下，由于第一驱动单元12和第一控制单元13均与第一电压信号端VDD电连接，因此第一驱动单元12产生的驱动信号会经过第一电压信号端VDD，例如，第一驱动单元12产生的驱动电流经过第一电压信号端VDD，进而流向第一电压信号线，而由于第一电压信号线具有电阻，在第一电压信号线上有电流流过时，可能会产生压降。
这样，就有可能造成各个像素驱动电路100中第一电压信号端VDD所接收的第一电压信号Vdd不一致。示例性地，第一电压信号线在传输第一电压信号Vdd时，第一电压信号Vdd所经过的距离越大，所产生的压降越大，因此距离第一电压信号Vdd的信号源端较远的像素驱动电路100，相比距离第一电压信号Vdd的信号源端较近的像素驱动电路100，所接收的第一电压信号Vdd降低。而本公开所提供的像素驱动电路100中，驱动信号控制子电路1所产生的驱动信号与在第一数据信号端DATA1处接收的第一数据信号Data1和在第一电压信号端VDD处接收的第一电压信号Vdd有关，因此由于各个像素驱动电路100所接收的第一电压信号Vdd不一致会导致所产生的驱动信号的大小不一致，使得显示面板出现显示不均匀的现象。
针对上述问题，在一些实施例中，如图2B和图3B所示，上述驱动信号控制子电路1包括：第一数据写入单元11、第一驱动单元12及第一控制单元13。
第一数据写入单元11与第一扫描信号端GATE1、第一数据信号端DATA1及第一驱动单元12电连接，被配置为在第一扫描信号端GATE1的控 制下，将在第一数据信号端DATA1处接收的第一数据信号Data1写入至第一驱动单元12。
第一控制单元13与使能信号端EM、第一电压信号端VDD及第一驱动单元12电连接，被配置为在使能信号端EM的控制下，将在第一电压信号端VDD处接收的第一电压信号Vdd输入至第一驱动单元12。
第一驱动单元12还与第三电压信号端VREF电连接，被配置为根据所写入的第一数据信号Data1和所输入的第一电压信号Vdd，及在第三电压信号端VREF处接收的第三电压信号Vref，产生驱动信号，并将驱动信号传输至第一控制单元13。
第一控制单元13还与驱动时长控制子电路2电连接，被配置为在使能信号端EM的控制下，将驱动信号传输至驱动时长控制子电路2。
在上述驱动信号控制子电路1中，通过第一数据写入单元11，将第一数据信号Data1写入至第一驱动单元12，第一驱动单元12根据所写入的第一数据信号Data1和所输入的第一电压信号Vdd，及在第三电压信号端VREF处接收的第三电压信号Vref，产生驱动信号，并将驱动信号传输至第一控制单元13，第一控制单元13将驱动信号传输至所述驱动时长控制子电路2，从而上述驱动信号控制子电路1实现了向驱动时长控制子电路2提供驱动信号，且驱动信号与第一数据信号Data1和第一电压信号Vdd有关。
在上述实施例中，第一驱动单元12与第三电压信号端VREF电连接，被配置为根据所写入的第一数据信号Data1和所输入的第一电压信号Vdd，及在第三电压信号端VREF处接收的第三电压信号Vref，产生驱动信号，并将驱动信号传输至第一控制单元13。其中第三电压信号端VREF被配置为接收第三电压信号Vref，并向驱动信号控制子电路1输入该第三电压信号Vref，也就是说，在上述驱动信号控制子电路100中，单独设置用于向第一驱动单元12提供第三电压信号Vref的第三电压信号端VREF。
这样，在显示面板中，被配置为向第一电压信号端VDD提供第一电压信号Vdd的第一电压信号线，与被配置为向第三电压信号端VREF提供第三电 压信号Vref的第三电压信号线为不同的信号线，第一驱动单元12所产生的驱动电流仅会由第三电压信号端VREF流经第三电压信号线，而不会影响第一电压信号线，从而第一电压信号线能够向各个像素驱动电路100的第一电压信号端VDD提供稳定的第一电压信号Vdd，驱动信号的大小不会受到影响，因此就避免了上述可能出现的显示面板的显示不均匀的问题。
示例性地，如图3B所示，第一数据写入单元11包括：第一晶体管M1和第二晶体管M2。
第一晶体管M1的控制极与第一扫描信号端GATE1电连接，第一晶体管M1的第一极与第一数据信号端DATA1电连接，第一晶体管M1的第二极与第一驱动单元12电连接。第一晶体管M1被配置为在第一扫描信号Gate1的控制下导通，将第一数据信号Data1传输至第一驱动单元12。
第二晶体管M2的控制极与第一扫描信号端GATE1电连接，第二晶体管M2的第一极和第二极与第一驱动单元12电连接。在第一驱动单元12包括第三晶体管M3的情况下，第二晶体管M2被配置为在第一扫描信号Gate1的控制下导通，使第三晶体管M3处于自饱和状态。
上述第一驱动单元12包括：第一存储电容器C1和第三晶体管M3。
第一存储电容器C1的第一端与第一数据写入单元11及第一控制单元13电连接，第一存储电容器C1的第二端与第一数据写入单元11电连接。第一存储电容器C1被配置为接收第一数据写入单元11所输入的第一数据信号Data1，并存储该第一数据信号Data1。
第三晶体管M3的控制极与第一存储电容器C1的第二端及第一数据写入单元11电连接，第三晶体管M3的第一极与第三电压信号端VREF电连接，第三晶体管M3的第二极与所述第一数据写入单元11及第一控制单元13电连接。第三晶体管M3被配置为根据第一存储电容器C1所存储的第一数据信号Data1和第一控制单元13所输入的第一电压信号Vdd，及在第三电压信号端VREF处接收的第三电压信号Vref，产生驱动信号，并将驱动信号传输至所述第一控制单元13。
上述第一控制单元13包括：第四晶体管M4和第五晶体管M5。
第四晶体管M4的控制极与使能信号端EM电连接，第四晶体管M4的第一极与第一电压信号端VDD电连接，第四晶体管M4的第二极与第一驱动单元12电连接。第四晶体管M4被配置为在使能信号Em的控制下导通，将第一电压信号Vdd传输至第一驱动单元12。
第五晶体管M5的控制极与使能信号端EM电连接，第五晶体管M5的第一极与第一驱动单元12电连接，第五晶体管M5的第二极与驱动时长控制子电路2电连接。第五晶体管M5被配置为在使能信号Em的控制下导通，将驱动信号传输至驱动时长控制子电路2。
在一些实施例中，如图4所示，驱动信号控制子电路1还包括第一复位单元14。
第一复位单元14与第一电压信号端VDD、复位信号端RESET、初始化信号端VINIT及第一驱动单元12电连接。复位信号端RESET被配置为接收复位信号Reset，并向第一复位单元14输入该复位信号Reset；初始化信号端VINIT被配置为接收初始化信号Vinit，并向第一复位单元14输入该初始化信号Vinit。
第一复位单元14被配置为在复位信号端RESET的控制下，根据在第一电压信号端VDD处接收的第一电压信号Vdd和在初始化信号端VINIT处接收的初始化信号Vinit，对第一驱动单元12的电压进行复位。
在上述实施例中，通过第一复位单元14，对第一驱动单元12的电压进行复位，以对第一驱动单元12处的信号进行降噪，而使得第一数据写入单元11将第一数据信号Data1写入至第一驱动单元12时，所输入的第一数据信号Data1更加准确。
示例性的，如图5A和图5B所示，第一复位单元14包括：第六晶体管M6和第七晶体管M7。
第六晶体管M6的控制极与复位信号端RESET电连接，第六晶体管M6的第一极与第一电压信号端VDD电连接，第六晶体管M6的第二极与第一驱 动单元12电连接。第六晶体管M6被配置为在复位信号Reset的控制下导通，将第一电压信号Vdd传输至第一驱动单元12。
第七晶体管M7的控制极与复位信号端RESET电连接，第七晶体管M7的第一极与初始化信号端VINIT电连接，第七晶体管M7的第二极与第一驱动单元12电连接。第七晶体管M7被配置为在复位信号Reset的控制下导通，将初始化信号Vinit传输至第一驱动单元12。
由于显示面板中存在很多的信号线，在一些情况下，在显示面板中位置临近的两条信号线(例如，相邻两条信号线，或者相隔距离较近的两条信号线，或者在显示面板的衬底基板上的正投影存在交叉的两条信号线)之间，由于存在耦合电容、信号线之间存在互感等，可能会产生串扰现象。在本公开所提供的像素驱动电路100中，第一电压信号Vdd可能会受到其他信号的影响，而发生畸变。示例性地，如图9所示，第一电压信号Vdd受第一数据信号Data1的电平跳变的影响，在第一数据信号Data1的上升沿，第一电压信号Vdd的电平会发生上拉跳变再恢复，在第一数据信号Data1的下降沿，第一电压信号Vdd的电平会发生下拉跳变再恢复，且发生跳变后恢复的时间受用于传输第一电压信号Vdd的第一电压信号线存在的电阻负载和电容负载的影响。在第一电压信号线存在的电阻负载和电容负载较大的情况下，第一电压信号Vdd发生跳变后恢复的时间较长，导致像素驱动电路100所接收的第一电压信号Vdd的不稳定问题更加显著。
这样，请参见图3B，在第一电压信号Vdd的电位发生下拉跳变时，在第四晶体管M4在使能信号Em的控制下导通，将第一电压信号Vdd传输至第一驱动单元12中的第一存储电容器C1的情况下，第一存储电容器C1的第一端的电位发生下拉跳变，根据电容的电荷保持定律，第一存储电容器C1的第二端的电位也发生下拉跳变，而第一存储电容器C1的第二端的电位与第三晶体管T3的控制极的电位相等，因此第三晶体管T3的控制极的电位发生下拉跳变，而第三晶体管T3的第一极的电位为第三电压信号Vref的电位，在该电位不变的情况下，第三晶体管T3的栅源电压差减小。
而根据晶体管的I-V特性，在晶体管的控制极的栅源电压差发生变化的情况下，晶体管产生的电流也会随之变化。以P型晶体管为例，当P型晶体管的栅源电压差的绝对值大于其阈值电压的绝对值时，P型晶体管导通，进而产生电流，在P型晶体管导通时，P型晶体管的栅源电压差小于0。如图10所示，由P型晶体管的I-V特性曲线可知，P型晶体管所产生的电流Id与P型晶体管的栅源电压差Vgs之间的关系为，在P型晶体管的栅源电压差Vgs小于0V的情况下(即P型晶体管导通，进而产生电流的情况下)，随着P型晶体管的栅源电压差Vgs减小，P型晶体管所产生的电流增大。
因此，请参见图3B，在第三晶体管T3为P型晶体管的情况下，第三晶体管T3的栅源电压差减小，会导致第三晶体管T3所产生的驱动电流增大，第三晶体管T3自身具有电阻，第三晶体管T3所产生的驱动电流增大，说明第三晶体管T3阻值减小，从而产生的压降减小，在第三晶体管T3的第一极的电位(即第三电压信号Vref的电位)不变的情况下，第三晶体管T3的第二极的电位升高，发生瞬间上拉跳变。也就是说，第一驱动单元12所产生的驱动信号受第一电压信号Vdd的电位的下拉跳变影响，会瞬间增大，从而第三晶体管的第二极的电位瞬间上拉跳变。
同理，在第一电压信号Vdd的电位发生上拉跳变时，会使得第三晶体管T3所产生的驱动电流变小，说明第三晶体管T3自身所具有的电阻增大，从而产生的压降增大，在第三晶体管T3的第一极的电位(即第三电压信号Vref的电位)不变的情况下，第三晶体管T3的第二极的电位降低，发生瞬间下拉跳变。也就是说，第一驱动单元12所产生的驱动信号受第一电压信号Vdd的上拉跳变影响，会瞬间减小，从而第三晶体管T3的第二极的电位瞬间下拉跳变。
这样，第一驱动单元12所产生的驱动信号的变化使得待驱动元件3的工作受到影响。示例性地，在待驱动元件3为发光器件的情况下，待驱动元件3的发光强度受驱动信号的变化影响而发生变化，进而导致显示画面出现显示不良现象。
针对上述可能出现的由于信号串扰导致的显示不良的问题，在一些实施例中，如图4所示，驱动信号控制子电路1还包括：驱动信号稳定单元15。驱动信号稳定单元15与第一驱动单元12电连接，被配置为使第一驱动单元12所产生的驱动信号保持稳定。
上述实施例所提供的驱动信号控制子电路1中，通过驱动信号稳定单元15，使第一驱动单元12所产生的驱动信号保持稳定，从而避免由于第一电压信号Vdd受到其他信号的干扰而发生跳变，而影响第一驱动单元12所产生的驱动信号的大小，保证了待驱动元件3在驱动信号的作用下正常工作，从而保证显示画面的正常显示。
示例性地，如图5A和5B所示，驱动信号稳定单元15包括：稳压存储电容器C3。
在第一驱动单元12包括第一存储电容器C1和第三晶体管T3的情况下，在一些示例中，如图5A所示，稳压存储电容器C3的第一端与第一存储电容器C1的第一端电连接，稳压存储电容器C3的第二端与第三晶体管T3的第二极电连接。
为了方便说明，第一晶体管M1的第二极与第一存储电容器C1的第一端电连接的节点等效为第一节点N1，即第一节点N1的电位与第一存储电容器C1的第一端的电位、第一晶体管M1的第二极的电位以及稳压存储电容器C3的第一端的电位相同。第三晶体管M3的控制极与第一存储电容器C1的第二端电连接的节点等效为第二节点N2，即第二节点N2的电位与第一存储电容器C1的第二端的电位，以及与第三晶体管M3的控制极的电位相同。稳压存储电容器C3的第二端与第三晶体管T3的第二极电连接的节点等效为第六节点N6，即第六节点N6的电位与稳压存储电容器C3的第二端的电位，以及第三晶体管T3的第二极的电位相同。
上述稳压存储电容器C3设置于第一存储电容器C1的第一端和第三晶体管T3的第二极之间，这样在第一电压信号Vdd受到第一数据信号Data1的电位变化的影响，而发生电位跳变的情况下。例如，第一电压信号Vdd的电位 发生下拉跳变，第一存储电容器C1的第一端的电位(第一节点N1的电位)发生下拉跳变，稳压存储电容器C3的第一端的电位与第一节点N1的电位相同，因此稳压存储电容器C3的第一端的电位也发生下拉变化，根据电容的电荷保持定律，稳压存储电容器C3的第二端的电位(第六节点N6的电位)也发生下拉变化。
而根据上面对信号串扰导致的显示不良现象的分析可知，第一驱动单元12所产生的驱动信号受第一电压信号Vdd的电位的下拉跳变影响，而有瞬间增大，从而第三晶体管的第二极的电位(第六节点N6的电位)瞬间上拉跳变。在稳压存储电容器C3的作用下，第三晶体管的第二极的电位(第六节点N6的电位)变化被抵消，从而相当于第一驱动单元12所产生的驱动信号没有发生变化，或者变化很小可以忽略不计，几乎不会受到第一电压信号Vdd的电位的跳变的影响。同样的，在第一电压信号Vdd的电位发生上拉跳变时，各节点的电位变化可参考上面的描述，此处不再赘述。
因此，在第一驱动单元12所产生的驱动信号不受第一电压信号Vdd的电位的跳变的影响的情况下，待驱动元件3的工作几乎不会受到影响，能够正常工作，保证了显示画面的正常显示。
在另一些示例中，如图5B所示，稳压存储电容器C3的第一端与所述第一存储电容器C1的第二端电连接，稳压存储电容器C3的第二端与所述第三晶体管T3的第二极电连接。
上述稳压存储电容器C3设置于第一存储电容器C1的第二端和第三晶体管T3的第二极之间，这样在第一电压信号Vdd受到第一数据信号Data1的电位变化的影响，而发生电位跳变的情况下，例如，第一电压信号Vdd的电位发生下拉跳变，第一存储电容器C1的第一端的电位(第一节点N1的电位)发生下拉跳变，根据电容的电荷保持定律，第一存储电容器C1的第二端的电位(第二节点N2的电位)也发生下拉跳变，稳压存储电容器C3的第一端的电位与第二节点N2的电位相同，因此稳压存储电容器C3的第一端的电位也发生下拉变化，根据电容的电荷保持定律，稳压存储电容器C3的第二端的电 位(第六节点N6的电位)同样发生下拉变化。
而根据上面对信号串扰导致的显示不良现象的分析可知，第一驱动单元12所产生的驱动信号受第一电压信号Vdd的电位的下拉跳变影响，而有瞬间增大，从而第三晶体管的第二极的电位(第六节点N6的电位)瞬间上拉跳变。在稳压存储电容器C3的作用下，第三晶体管的第二极的电位(第六节点N6的电位)变化被抵消，从而相当于第一驱动单元12所产生的驱动信号没有发生变化，或者变化很小可以忽略不计，几乎不会受到第一电压信号Vdd的电位的跳变的影响。同样的，在第一电压信号Vdd的电位发生上拉跳变时，各节点的电位变化可参考上面的描述，此处不再赘述。
因此，在第一驱动单元12所产生的驱动信号不受第一电压信号Vdd的电位的跳变的影响的情况下，待驱动元件3的工作不会受到影响，能够正常工作，保证了显示画面的正常显示。
在一些实施例中，驱动信号稳定单元15还可以包括其他的器件，本公开对此并不设限，只要能起到使第一驱动单元12所产生的驱动信号保持稳定的作用即可。
在此基础上，下面对本公开实施例所提供的像素驱动电路100所包括的驱动信号控制子电路1的具体电路结构进行整体性的、示例性的介绍。
如图5A和图5B所示，驱动信号控制子电路1包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第一存储电容器C1及稳压存储电容器C3。
第一晶体管M1的控制极与第一扫描信号端GATE1电连接，第一晶体管M1的第一极与第一数据信号端DATA1电连接，第一晶体管M1的第二极与第一存储电容器C1的第一端电连接。第一晶体管M1被配置为在第一扫描信号Gate1的控制下导通，将第一数据信号Date1传输至第一存储电容器C1的第一端。
第二晶体管M2的控制极与第一扫描信号端GATE1电连接，第二晶体管M2的第一极与第三晶体管M3的第二极电连接，第二晶体管M2的第二极与 第一存储电容器C1的第二端及第三晶体管M3的控制极电连接。第二晶体管M2被配置为在第一扫描信号Gate1的控制下导通，将第三晶体管M3的控制极与第三晶体管M3的第二极相连，使第三晶体管M3达到自饱和状态。
第三晶体管M3的控制极还与第一存储电容器C1的第二端电连接，第三晶体管M3的第一极与第三电压信号端VREF电连接，第三晶体管M3的第二极还与第五晶体管M5的第一极电连接。第三晶体管M3被配置为根据第一存储电容器C1所存储的第一数据信号Date1和第一控制单元13所输入的第一电压信号Vdd，以及第三电压信号Vref，产生驱动信号，并将驱动信号传输至第五晶体管M5的第一极。
第四晶体管M4的控制极与使能信号端EM电连接，第四晶体管M4的第一极与第一电压信号端VDD电连接，第四晶体管M4的第二极与第一存储电容器C1的第一端电连接。第四晶体管M4被配置为在使能信号Em的控制下导通，将第一电压信号Vdd传输至第一存储电容器C1的第一端。
第五晶体管M5的控制极与使能信号端EM电连接，第五晶体管M5的第二极与驱动时长控制子电路2电连接。第五晶体管M5被配置为在使能信号Em的控制下导通，将驱动信号传输至驱动时长控制子电路2。
第六晶体管M6的控制极与复位信号端RESET电连接，第六晶体管M6的第一极与第一电压信号端VDD电连接，第六晶体管M6的第二极与第一存储电容器C1的第一端电连接。第六晶体管M6被配置为在复位信号Reset的控制下导通，将第一电压信号Vdd传输至第一存储电容器C1的第一端。
第七晶体管M7的控制极与复位信号端RESET电连接，第七晶体管M7的第一极与初始化信号端VINIT电连接，第七晶体管M7的第二极与第一存储电容器C1的第二端及第三晶体管M3的控制极电连接。第七晶体管M7被配置为在复位信号Reset的控制下导通，将初始化信号Vinit传输至第一存储电容器C1的第二端。
稳压存储电容器C3的第一端与第一存储电容器C1的第一端电连接，稳压存储电容器C1的第二端与第三晶体管T3的第二极电连接。或者，稳压存 储电容器C3的第一端与第一存储电容器C1的第二端电连接，稳压存储电容器C3的第二端与第三晶体管T3的第二极电连接。
在一些实施例中，本公开所提供的像素驱动电路100中，第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6及第七晶体管M7均为P型晶体管或者均为N型晶体管。
在一些实施例中，如图2A和图2B所示，本公开所提供的像素驱动电路100中驱动时长控制子电路2包括：第二数据写入单元21、第二控制单元23及第二驱动单元22。
第二数据写入单元21与第二扫描信号端GATE2、第二数据信号端DATA2及第二驱动单元22电连接，被配置为在第二扫描信号端GATE2的控制下，将在第二数据信号端DATA2处接收的具有设定工作电位的第二数据信号Data2写入至第二驱动单元22。
需要说明的是，驱动信号传输至待驱动元件3的时长与上述具有设定工作电位的第二数据信号Data2有关，通过控制第二数据信号Data2的设定工作电位，可以改变驱动信号传输至待驱动元件3的时长，进而改变待驱动元件3的工作时长。
第二控制单元23与使能信号端EM、第二数据信号端DATA2及第二驱动单元22电连接，被配置为在使能信号端EM的控制下，将在第二数据信号端DATA2处接收的电位在设定范围内变化的第二数据信号Data2传输至第二驱动单元22。
需要说明的是，驱动信号传输至待驱动元件3的时长与上述电位在设定范围内变化的第二数据信号Data2有关，在第二数据信号Data2的电位变化至一定值时，会使第二驱动单元22打开，此时驱动信号传输至第二控制单元23。
第二驱动单元22还与驱动信号控制子电路1电连接，被配置为根据具有设定工作电位的第二数据信号Data2和电位在设定范围内变化的第二数据信号Data2，将驱动信号传输至第二控制单元23，并控制驱动信号传输至第二控制单元23的时长。
第二控制单元23还与待驱动元件3电连接，还被配置为将驱动信号传输至待驱动元件3。
在上述驱动时长控制子电路2中，通过第二数据写入单元21，将具有设定工作电位的第二数据信号Data2写入至第二驱动单元22，通过第二控制单元23，将电位在设定范围内变化的第二数据信号Data2传输至所述第二驱动单元22，通过第二驱动单元22，根据具有设定工作电位的第二数据信号Data2和电位在设定范围内变化的第二数据信号Data2，将驱动信号传输至第二控制单元23，并控制驱动信号传输至第二控制单元23的时长。从而上述驱动时长控制子电路2实现了控制驱动信号传输至第二控制单元23的时长，以控制待驱动元件3的工作时长，进而控制待驱动元件3的工作状态的效果。
示例性地，如图3A和图3B所示，上述第二数据写入单元21包括：第八晶体管M8。
第八晶体管M8的控制极与第二扫描信号端GATE2电连接，第八晶体管M8的第一极与第二数据信号端DATA2电连接，第八晶体管M8的第二极与第二驱动单元22电连接。第八晶体管M8被配置为在第二扫描信号Gate2的控制下导通，将第二数据信号Data2传输至第二驱动单元22。
上述第二控制单元23包括：第九晶体管M9和第十晶体管M10。
第九晶体管M9的控制极与使能信号端EM电连接，第九晶体管M9的第一极与第二数据信号端DATA2电连接，第九晶体管M9的第二极与第二驱动单元22电连接。第九晶体管M9被配置为在使能信号Em的控制下导通，将第二数据信号Data2传输至第二驱动单元22。
第十晶体管M10的控制极与使能信号端EM电连接，第十晶体管M10的第一极与第二驱动单元22电连接，第十晶体管M10的第二极与待驱动元件3电连接。第十晶体管M10被配置为在使能信号Em的控制下导通，将驱动信号传输至待驱动元件3。
上述第二驱动单元22包括：第二存储电容器C2和第十一晶体管M11。
第三存储电容器C3的第一端与第二数据写入单元21及第二控制单元23 电连接，被配置为接收第二数据信号Data2，并存储该第二数据信号Data2。
第十一晶体管M11的控制极与第三存储电容器C3的第二端电连接，第十一晶体管M11的第一极与驱动信号控制子电路1电连接，第十一晶体管M11的第二极与第二控制单元23电连接。第十一晶体管M11被配置为在第三存储电容器C3的第二端的电压的控制下导通，将驱动信号传输至第十晶体管M10。
在一些实施例中，如图4所示，驱动时长控制子电路2还包括：第二复位单元24。
第二复位单元24与复位信号端RESET、初始化信号端VINIT及第二驱动单元22电连接，被配置为在复位信号端RESET的控制下，根据在初始化信号端VINIT处接收的初始化信号Vinit，对第二驱动单元22的电压进行复位。
在上述实施例中，通过第二复位单元24，对第二驱动单元22的电压进行复位，以对第二驱动单元22处的信号进行降噪，而使得第二数据写入单元21将第二数据信号Data2写入至第二驱动单元22时，所输入的第二数据信号Data2更加准确。
示例性地，如图5A和图5B所示，第二复位单元24包括：第十二晶体管M12和第十三晶体管M13。
第十二晶体管M12的控制极与复位信号端RESET电连接，第十二晶体管M12的第一极与初始化信号端VINIT电连接，第十二晶体管M12的第二极与第二驱动单元22电连接。第十二晶体管M12被配置为在复位信号Reset的控制下导通，将初始化信号Vinit传输至第二驱动单元22。
第十三晶体管M13的控制极与复位信号端RESET能接，第十三晶体管M13的第一极和第二极与第二驱动单元22电连接。第十三晶体管M13被配置为在复位信号Reset的控制下导通，将第十一晶体管M11的控制极与其第二极相连，使第十一晶体管M11处于自饱和状态。
在此基础上，下面对本公开实施例所提供的像素驱动电路100所包括的 驱动时长控制子电路2的具体电路结构进行整体性的、示例性的介绍。
如图5A和图5B所示，驱动时长控制子电路2包括：第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13及第二存储电容器C2。
第八晶体管M8的控制极与第二扫描信号端GATE2电连接，第八晶体管M8的第一极与第二数据信号端DATA2电连接，第八晶体管M8的第二极与第二存储电容器C2的第一端电连接。第八晶体管M8被配置为在第二扫描信号Gate2的控制下导通，将第二数据信号Data2传输至第二存储电容器C2的第一端。
第九晶体管M9的控制极与使能信号端EM电连接，第九晶体管M9的第一极与第二数据信号端DATA2电连接，第九晶体管M9的第二极与第二存储电容器C2的第一端电连接。第九晶体管M9被配置为在使能信号Em的控制下导通，将将第二数据信号Data2传输至第二存储电容器C2。
第十晶体管M10的控制极与使能信号端EM电连接，第十晶体管M10的第一极与第十一晶体管M11的第二极电连接，第十晶体管M10的第二极与待驱动元件3电连接。第十晶体管M10被配置为在使能信号Em的控制下导通，将驱动信号传输至待驱动元件3。
第十一晶体管M11的控制极与第二存储电容器C2的第二端电连接，第十一晶体管M11的第一极与驱动信号控制子电路1及第十二晶体管M12的第二极电连接，第十一晶体管M11的第二极还与第十三晶体管M13的第一极电连接。第十一晶体管M11被配置为在第二存储电容器C2的第二端的电压的控制下导通，将驱动信号传输至第十晶体管M10。
十二晶体管的控制极与复位信号端RESET电连接，十二晶体管的第一极与初始化信号端VINIT电连接。第十二晶体管M12被配置为在复位信号Reset的控制下导通，将初始化信号Vinit传输至第二驱动单元22。
第十三晶体管M13的控制极与复位信号端RESET电连接，第十三晶体管M13的第二极与第二存储电容器C2的第二端及第十一晶体管M11的控制 极电连接。第十三晶体管M13被配置为在复位信号Reset的控制下导通，将第十一晶体管M11的控制极与其第二极相连，使第十一晶体管M11处于自饱和状态。
在一些实施例中，上述第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12及第十三晶体管M13均为P型晶体管或者均为N型晶体管。
上面已经驱动信号控制子电路1和驱动时长控制子电路2的具体结构分别进行了示例性的介绍，在一些实施例中，如图5A和图5B所示，本公开的一些实施例所提供的像素驱动电路100中的驱动信号控制子电路1包括：第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7及第一存储电容器C1，各元件的连接方式可参见上面相应部分的介绍。并且，像素驱动电路100中的驱动时长控制子电路2包括:第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12及第十三晶体管M13及第二存储电容器C2，各元件的连接方式如上面相应部分的介绍。上述各晶体管可均为P型晶体管或N型晶体管。
在一些实施例中，如图3B、图5A和图5B所示，待驱动元件3包括至少一个发光二极管31，所述至少一个发光二极管串联在电流通路中。其中一个发光二极管31的阳极与第十晶体管M10的第二极电连接，该发光二极管31的阳极与第十晶体管M10的第二极电连接的节点等效为第五节点N5。其中一个发光二极管31的阴极与一个信号端电连接，示例性地，该信号端为第二电压信号端VSS，在第十晶体管M10为P型晶体管的情况下，第二电压信号端VSS可以接地，或者为0V。
在一些实施例中，上述发光二极管31为微型发光二极管(micro LED)、迷你发光二极管(mini LED)或者有机发光二极管，量子点发光二极管其他具有在高电流密度下发光效率高，在低电流密度下发光效率低的特性的发光器件，本公开的实施例对此并不设限。
需要说明的是，本公开的实施例提供的电路中所采用的晶体管可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例对此并不设限。
在一些实施例中，像素驱动电路100所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性的，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例中，驱动信号控制子电路1和驱动时长控制子电路2的具体实现方式不局限于上面描述的方式，其可以为任意使用的实现方式，例如为本领域技术人员熟知的常规连接方式，只需保证实现相应功能即可。上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不适用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
本公开的一些实施例还提供了一种像素驱动方法，该像素驱动方法应用于如上所述像素驱动电路100，如图6所示，该像素驱动方法包括：一个帧周期(1Frame)包括扫描阶段t-s和工作阶段t-em。其中，扫描阶段t-s包括多个行扫描时段，例如，(n大于或等于2)，所述多个行扫描时段为n个行扫描时段，n个行扫描时段分别为t1～tn。
所述多个行扫描时段t1～tn中的每个行扫描时段包括:
驱动信号控制子电路1在第一扫描信号端GATE1的控制下，写入第一数据信号Data1；驱动时长控制子电路2在第二扫描信号端GATE2的控制下，写入具有设定工作电位的第二数据信号Data2。
结合图2B，在驱动信号控制子电路1包括第一数据写入单元11、第一驱动单元12及第一控制单元13的情况下，第一数据写入单元11在第一扫描信 号端GATE1的控制下打开，将在第一数据信号端DATA1处接收的第一数据信号Data1写入至第一驱动单元12。
示例性地，如图3B所示，在第一数据写入单元11包括第一晶体管M1和第二晶体管M2，第一驱动单元12包括第一存储电容器C1和第三晶体管M3，第一控制单元13包括第四晶体管M4和第五晶体管M5的情况下：
在每个行扫描时段，第一晶体管M1在第一扫描信号Gate1的控制下导通，将在第一数据信号端DATA1处接收的第一数据信号Data1传输至第一存储电容器C1的第一端，此时第一存储电容器C1的第一端的电位为第一数据信号Data1的电位。
第二晶体管M2在第一扫描信号Gate1的控制下导通，将第三晶体管M3的控制极与其第二极相连，使第三晶体管M3处于自饱和状态，则第三晶体管M3的控制极的电压为其第一极的电压与其阈值电压之和，第三晶体管M3的第一极与第三电压信号端VREF相连，因此第三晶体管M3的第一极的电位为第三电压信号Vref的电位，则第三晶体管M3的控制极的电位为第三电压信号Vref的电位与第三晶体管M3的阈值电压之和。
第一存储电容器C1的第二端的电位与第三晶体管M3的控制极的电位相同，则第一存储电容器C1的第二端的电位为第三电压信号Vref的电位与第三晶体管M3的阈值电压之和。此时，第一存储电容器C1的第一端和第二端存在电位差，实现了对第一存储电容器C1的充电。
结合图2B，在驱动时长控制子电路2包括第二数据写入单元21、第二控制单元23及第二驱动单元22的情况下，第二数据写入单元21在第二扫描信号端GATE2的控制下打开，将在第二数据信号端DATA2处接收的第二数据信号Data2写入第二驱动单元22。第二数据信号Data2具有设定工作电位，该设定工作电位与待驱动元件3的工作时长有关，依待驱动元件3的工作时长而定。
示例性地，如图3B所示，在第二数据写入单元21包括第八晶体管M8，第二控制单元23包括第九晶体管M9和第十晶体管M10，第二驱动单元22 包括第二存储电容器C2和第十一晶体管M11的情况下：
在每个行扫描时段，第八晶体管M8在第二扫描信号Gate2的控制下导通，将第二数据信号Data2传输至第二存储电容器C2的第一端，第二存储电容器C2的第一端的电位为第二数据信号Data2的设定工作电位，实现了对第二存储电容器C2的充电。
在整个扫描时段t-s，n个行扫描时段中的每个行扫描时段均包括上述S1～S2，这样就实现了对n行亚像素进行扫描，完成了对n行亚像素的第一数据信号Data1和第二数据信号Data2的写入，并将第一数据信号Data1和第二数据信号Data2进行存储，为工作阶段t-em的驱动信号的输出做准备。
工作阶段t-em包括：
驱动信号控制子电路1在使能信号端EM的控制下，向驱动时长控制子电路2提供驱动信号。驱动信号与第一数据信号Data1和第一电压信号端VDD提供的第一电压信号Vdd有关；驱动时长控制子电路2在使能信号端EM的控制下，接收电位在设定范围内变化的第二数据信号Data2，将驱动信号传输至待驱动元件3。驱动信号传输至待驱动元件3的时长与具有设定工作电位的第二数据信号Data2和电位在设定范围内变化的第二数据信号Data2有关。
结合图2B，在驱动信号控制子电路1包括第一数据写入单元11、第一驱动单元12及第一控制单元13的情况下，第一控制单元13在使能信号端EM的控制下打开，将驱动信号传输至驱动时长控制子电路2。
示例性的，如图3B所示，在第一数据写入单元11包括第一晶体管M1和第二晶体管M2，第一驱动单元12包括第一存储电容器C1和第三晶体管M3，第一控制单元13包括第四晶体管M4和第五晶体管M5的情况下：
在工作阶段t-em，第四晶体管M4在使能信号端EM的控制下导通，将在第一电压信号端VDD处接收的第一电压信号传输至第一存储电容器C1的第一端，第一存储电容器C1的第一端的电位变为第一电压信号Vdd的电位。
根据电容的电荷保持定律，第一存储电容器C1的第一端和第二端的电位差保持不变。由于第一存储电容器C1的第一端的电位由第一数据信号Data1 的电位跳变为第一电压信号Vdd的电位，第一存储电容器C1的第一端的电位也会随之发生跳变。
第三晶体管M3导通，并产生驱动电流，该驱动电流从第三晶体管M3的第二极输出。第五晶体管M5在使能信号端EM的控制下导通，将驱动信号传输至驱动时长控制子电路2，也就是将第三晶体管M3产生的驱动电流经过第五晶体管M5，传输至驱动时长控制子电路2。
结合图2B，在驱动时长控制子电路2包括第二数据写入单元21、第二控制单元23及第二驱动单元22的情况下，第二控制单元23在使能信号端EM的控制下打开，将电位在设定范围内变化的第二数据信号Data2写入第二驱动单元22。第二数据信号Data2的电压在设定范围内变化，在第二数据信号Data2的电压变化至特定电压值时，第二驱动单元22打开，将驱动信号传输至第二控制单元23，并由第二控制单元23传输至待驱动元件3，进而使得待驱动元件3开始工作，其中，上述特定电压值与设定工作电位有关。
示例性地，如图3B所示，在第二数据写入单元21包括第八晶体管M8，第二控制单元23包括第九晶体管M9和第十晶体管M10，第二驱动单元22包括第二存储电容器C2和第十一晶体管M11的情况下：在工作阶段，第九晶体管M9在使能信号端EM的控制下导通，将电位在设定范围内变化的第二数据信号传输至第二存储电容器C2的第一端，第二存储电容器C2的第一端的电位为第二数据信号Data2的电位，且电位在设定范围内变化。
根据电容的电荷保持定律，为保持第二存储电容器C2的第一端和第二端的电位差不变，在第二存储电容器C2的第一端的电位发生变化时，其第二端的电位也在随之变化。第十一晶体管M11的控制极的电位与第二存储电容器C2的第二端的电位相同，从而第十一晶体管M11的控制极的电位也在变化，当第十一晶体管M11的栅源电压差(控制极与第一极之间的电位差)的绝对值大于其阈值电压时，第十一晶体管M11打开，将驱动信号传输至第十晶体管M10的第一极。
第十晶体管M10在使能信号端EM的控制下导通，将驱动信号传输至待 驱动元件3，从而待驱动元件3开始工作。
上述像素驱动方法，在一个帧周期(1Frame)内，在扫描阶段t-s实现各行亚像素的第一数据信号Data1和第二数据信号Data2的写入，在工作阶段t-em产生驱动信号，将驱动信号输出，并控制驱动信号传输至待驱动元件3的时长，这样，通过控制驱动信号的大小，以及通过控制待驱动元件3的工作时长，实现对待驱动元件3的控制。
在一些实施例中，待驱动元件3为发光器件，采用上述像素驱动方法，通过控制发光器件的驱动电流大小以及发光时长实现改变发光器件的发光强度，进而实现对应的灰阶显示。在实现较高灰阶的显示时，通过增大输入发光器件的驱动电流，提高发光器件的发光强度；在实现较低灰阶的显示时，通过缩短发光器件的工作时长，不需要降低输入发光器件的驱动电流，使得发光器件的发光强度降低，这样，传输至发光器件的驱动电流始终较大，发光器件始终处于高电流密度下，发光效率较高，进而降低功耗，节约成本。
在一些实施例中，像素驱动方法还包括：在每个行扫描时段，第一复位单元14在复位信号端RESET的控制下，对第一驱动单元12的电压进行复位。第二复位单元24在复位信号端RESET的控制下，对第二驱动单元22的电压进行复位。
示例性地，如图5A和图5B所示，在第一复位单元14包括第六晶体管M6和第七晶体管M7的情况下，第六晶体管M6在复位信号Reset的控制下导通，将第一电压信号Vdd传输至第一驱动单元12，第七晶体管M7在复位信号Reset的控制下导通，将初始化信号Vinit传输至第一驱动单元12，从而对第一驱动单元12的电压进行复位。
在第二复位单元24包括第十二晶体管M12和第十三晶体管M13的情况下，第十三晶体管M13在复位信号端RESET的控制下导通，第十二晶体管M12在复位信号Reset的控制下导通，将初始化信号Vinit传输至第二驱动单元22，从而对第二驱动单元22的电压进行复位。
在上述实施例中，在每个行扫描时段，通过第一复位单元14对第一驱动 单元12的电压进行复位，通过第二复位单元24对第二驱动单元22的电压进行复位，实现了对第一驱动单元12与第二驱动单元22处的信号进行降噪，使输入第一驱动单元12的第一数据信号Data1和输入第二驱动单元22的第二数据信号Data2不受干扰，更加准确。
在一些实施例中，设定工作电位的绝对值与相应的待驱动元件3需要工作的工作时长相关。每个像素驱动电路100被写入的第二数据信号Data2所具有的设定工作电位的绝对值与该像素驱动电路100所驱动的待驱动元件3需要工作的工作时长相关。在待驱动元件3为发光器件的情况下，每个像素驱动电路100被写入的第二数据信号Data2所具有的设定工作电位的绝对值与该像素驱动电路100对应的发光器件需要发光的发光时长相关，通过改变设定工作电位的绝对值，可以实现对发光器件的发光时长的控制，从而实现对亚像素的灰阶的控制。
在此基础上，下面对本公开实施例所提供的像素驱动方法进行整体性、示例性的介绍。以下的介绍，以图5A所示出的像素驱动电路100为例，结合图6所示出的时序信号图进行描述。该像素驱动电路100包括第一晶体管M1、第二晶体管M2、第三晶体管M3、第四晶体管M4、第五晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11、第十二晶体管M12、第十三晶体管M13、第一存储电容器C1、第二存储电容器C2及稳压存储电容器C3，且上述晶体管均为P型晶体管，待驱动元件3包括发光二极管31。
如图6所示，像素驱动方法包括：一个帧周期1Frame包括扫描阶段t-s和工作阶段t-em，扫描阶段t-s包括多个行扫描时段t1～tn，多个行扫描时段t1～tn中的每个行扫描时段包括：第一子时段和第二子时段。例如：第一行扫描时段t1包括第一子时段t1-1和第二子时段t1-2，第二行扫描时段t2包括第一子时段t2-1和第二子时段t2-2，依次类推，第n行扫描时段tn包括第一子时段tn-1和第二子时段tn-2。
需要说明的是，在显示装置包括n行m列亚像素，每个亚像素对应一个 像素驱动电路100的情况下，在扫描阶段t-s，对第一行至第n行的亚像素进行逐行扫描，依次将第一数据信号data1和不同的第二数据信号data2写入每一行亚像素对应的像素驱动电路100。在对第一行至第n行的亚像素逐行扫描完毕后，进入工作阶段t-em，在工作阶段t-em，n行m列亚像素对应的像素驱动电路100同时接收相同的第二数据信号data2，每个亚像素对应的像素驱动电路100所写入的第二数据信号data2的电位均在设定范围内变化。
在每个行扫描时段，同一行的m个亚像素所对应的m个像素驱动电路100同时被写入不同的第一数据信号data1，也就是说第一数据信号data1为一组信号；同一行的m个亚像素所对应的m个像素驱动电路100同时被写入不同的第二数据信号data2，也就是说第二数据信号data2为一组信号。同一行的m个亚像素所对应的m个像素驱动电路100所写入的第一数据信号data1和第二数据信号data2与对应亚像素需要显示的灰阶有关。以下以第一列亚像素所对应的像素驱动电路100为例，进行说明。
在扫描阶段t-s，称第一数据信号端DATA1所传输的第一数据信号data1的电位为V1。在第一行扫描时段t1，第一数据信号data1的电位为V1 (1)，在第二行扫描时段t2，第一数据信号data1的电位为V1 (2)，依次类推，在第n行扫描时段tn，第一数据信号data1的电位为V1 (n)。
在每个行扫描时段的第一子时段，称第二数据信号端DATA2所传输的第二数据信号data2的电位为设定工作电位Vs。在第一行扫描时段t1的第一子时段t1-1，第二数据信号data2的设定工作电位为Vs (1)，在第二行扫描时段t2的第一子时段t2-1，第二数据信号data2的设定工作电位为Vs (2)，依次类推，在第二行扫描时段tn的第一子时段tn-1，第二数据信号data2的电位为Vs (n)。
在每个行扫描时段的第二子时段，称第二数据信号端DATA2所传输的第二数据信号data2的电位为Vs’。
在工作阶段t-em，称第二数据信号端DATA2所传输的第二数据信号data2的电位为Vg，且该电位Vg在设定范围内变化。从第一行至第n行，所写入 的第二数据信号的电位Vg均在设定范围内变化，且各行对应的设定范围均相同。
在扫描阶段t-s中的第一行扫描时段t1，第一行扫描时段t1的第一子时段t1-1，第一行的第一个亚像素对应的像素驱动电路包括如下驱动过程：
复位信号端RESET传输的复位信号Reset和第二扫描信号端GATE2传输的第二扫描信号Gate2为低电平信号，第一扫描信号端GATE1传输的第一扫描信号Gate1和使能信号端EM传输的使能信号Em为高电平信号，第六晶体管M6、第七晶体管M7、第十二晶体管M12以及第十三晶体管M13在复位信号Reset的控制下导通，第八晶体管M8在第二扫描信号Gate2的控制下导通，其余晶体管均关断。
第六晶体管M6将在第一电压信号端VDD处接收的第一电压信号Vdd传输至第一存储电容器C1的第一端，此时第一存储电容器C1的第一端的电位(第一节点N1的电位)为第一电压信号Vdd的电位Vd。
第七晶体管M7将在初始化信号端VINIT处接收的初始化信号Vinit传输至第一存储电容器C1的第二端，此时第一存储电容器C1的第二端的电位(第二节点N2的电位)为初始化信号Vinit的电位，示例性的，初始化信号Vinit的电位Vinit为0V。
第八晶体管M8将在第二数据信号端DATA2处接收的第二数据信号Data2传输至第二存储电容器C2的第一端，此时第二存储电容器C2的第一端的电位(第三节点N3的电位)与第二数据信号Data2的电位相同，为设定工作电位Vs (1)。
第十二晶体管M12将在初始化信号端VINIT处接收的初始化信号Vinit传输至第十一晶体管M11的第一极，第十一晶体管M11的第一极的电位为初始化信号Vinit的电位；第十三晶体管M13导通，将第十一晶体管M11的控制极和第二极相连，使第十一晶体管M11处于自饱和状态，此时第十一晶体管M11的控制极的电位为其第一极的电位(初始化信号Vinit的电位)与其阈值电压Vth2之和，示例性地，初始化信号Vinit的电位为0V，则第十一晶 体管M11的控制极的电位为Vth2，第二存储电容器C2的第二端的电位(第四节点N4的电位)也为Vth2。
在扫描阶段t-s的第一行扫描时段t1，第一行扫描时段t1的第二子时段t1-2，第一行的第一个亚像素对应的像素驱动电路包括如下驱动过程：
第一扫描信号端GATE1传输的第一扫描信号Gate1和第二扫描信号端GATE2传输的第二扫描信号Gate2为低电平信号，复位信号端RESET传输的复位信号Reset和使能信号端EM传输的使能信号Em为高电平信号，第一晶体管M1、第二晶体管M2在第一扫描信号Gate1的控制下导通，第八晶体管M8在第二扫描信号Gate2的控制下导通，其余晶体管均关断。
第一晶体管M1将在第一数据信号端DATA1处接收的第一数据电压Data1传输至第一存储电容器C1的第一端，此时第一存储电容器C1的第一端的电位(第一节点N1的电位)为第一数据信号Data1的电位V1 (1)。
第二晶体管M2导通，将第三晶体管M3的控制极与其第二极相连，使第三晶体管M3处于自饱和状态，第三晶体管M3的控制极的电位为第三晶体管M3的第一极的电位与其阈值电压Vth1之和，第三晶体管M3的第一极的电位为第三电压信号Vref的电位Vre，则第三晶体管M3的控制极的电位为Vre+Vth1，第一存储电容器C1的第二端的电位(第二节点N2的电位)也为Vre+Vth1。
第八晶体管M8将在第二数据信号端DATA2处接收的第二数据信号Data2传输至第二存储电容器C2的第一端，此时第二存储电容器C2的第一端的电位(第三节点N3的电位)与第二数据信号Data2的电位Vs’相同。示例性的，此时第二数据信号的电位Vs’为0V。
在第一子时段t1-1，第二存储电容器C2的第一端的电位为设定工作电位Vs (1)，第二存储电容器C2的第二端的电位为Vth2，根据电容的电荷保持定律，第二存储电容器C2的第一端和第二端之间的电位差保持不变，则在第二子时段t1-2，第二存储电容器C2的第一端的电位跳变为0V，则第二存储电容器C2的第二端的电位跳变为Vth2-Vs (1)。
第二行至第n行的亚像素对应的像素驱动电路100的驱动过程与第一行的亚像素对应的像素驱动电路100的驱动过程一致，对于在扫描阶段t-s的第二行扫描时段t2～第n行扫描时段tn的说明均参见对第一行扫描时段t1的说明。
在对第一行至第n行的亚像素逐行扫描完毕后，显示装置的各行亚像素进入工作阶段t-em。第一行的第一个亚像素的工作阶段t-em包括如下过程：
使能信号端EM传输的使能信号Em为低电平信号，第一扫描信号端GATE1传输的第一扫描信号Gate1、第二扫描信号端GATE2传输的第二扫描信号Gate2和复位信号端RESET传输的复位信号Reset为高电平信号，第四晶体管M4、第五晶体管M5和第十晶体管M10在使能信号Em的控制下导通，其余晶体管均关断。
第四晶体管M4将在第一电压信号端VDD处接收的第一电压信号Vdd传输至第一存储电容器C1的第一端，此时第一存储电容器C1的第一端的电位(第一节点N1的电位)为第一电压信号Vdd的电位Vd。
在第一行扫描时段t1的第二子时段t1-2，第一存储电容器C1的第一端的电位为第一数据信号Data1的电位V1 (1)，第一存储电容器C1的第二端的电位为Vd+Vth1，根据电容的电荷保持定律，第一存储电容器C1的第一端和第二端之间的电位差保持不变，则在工作阶段t-em，第一存储电容器C1的第一端的电位变为Vd，则第一存储电容器C1的第二端的电位变为Vd+Vre-V1 (1)+Vth1。
第三晶体管M3根据第一电压信号Vdd和第二存储电容器C2的第二端的电位，产生驱动电流。
第五晶体管M5导通，将第三晶体管M3产生的驱动电流传输至第十一晶体管M11的第一极。
第九晶体管M9将在第二数据信号端DATA2处接收的第二数据信号Data2传输至第二存储电容器C2的第一端，此时第二存储电容器C2的第一端的电位(第三节点N3的电位)为第二数据信号Data2的电位Vg，第二数 据信号Data2的电位Vg在设定范围内变化。
在一些实施例中，设定范围的两个端点值分别为：第二数据信号Data2的非工作电位Vgf和参考工作电位Vgc。参考工作电位Vgc的绝对值大于或等于第二数据信号Data2的全部设定工作电位Vs的绝对值中的最大值。设定工作电位Vs在设定范围之内。
示例性的，第二数据信号Data2的非工作电位Vgf为0V，在工作阶段t-em，第二数据信号的电位Vg由非工作电位Vgf(0V)逐渐变化至参考工作电位Vgc，第二存储电容器C2的第一端的电位(第三节点N3的电位)也为由非工作电位Vgf(0V)逐渐变化至参考工作电位Vgc。
根据电容的电荷保持定律，第二存储电容器C2的第一端和第二端之间的电位差保持不变，在第一行扫描时段t1的第二子时段t1-2，第二存储电容器C2的第一端的电位变为0V，第二存储电容器C2的第二端的电位为Vth2-Vs (1)，第二存储电容器C2的第一端和第二端之间的电位差为Vs (1)-Vth2，则在工作阶段t-em，第二存储电容器C2的第二端的电位(第四节点N4的电位)由Vth2-Vs (1)逐渐变化至Vth2-Vs (1)+Vgc。
在第二存储电容器C2的第二端的电位发生变化的过程中，第十一晶体管M11的控制极的电位(第四节点N4的电位)也从Vth2-Vs (1)逐渐变化至Vth2-Vs (1)+Vgc。在第十一晶体管M11的控制极的电位变化至某一电位时，第十一晶体管M11可以导通，设该电位为开启电位V k，开启电位V k所满足的条件如下：第十一晶体管M11的栅源电压差Vgs＝V k-Vd(1)，其中，Vd(1)为经过第三晶体管M3后的第一电压信号Vdd的电位，当第十一晶体管M11的栅极电压差的绝对值大于或者等于其阈值电压Vth2的绝对值时，第十一晶体管M11导通，也就是当开启电位V k满足│V k-Vd(1)│≥│Vth2│，V k≤Vth2+Vd(1)时，第十一晶体管M11导通，从而使驱动信号通过。在此之前，第十一晶体管M11关断，驱动信号无法通过。
示例性地，请参见图6，当第二数据信号Data2的电位Vg由非工作电位Vgf(0V)变化至在第一行扫描时段t1的第一子时段t1-1所具有的设定工作 电位Vs (1)时，此时第二存储电容器C2的第一端的电位为Vs (1)，第二存储电容器C2的第二端的电位为Vth2，即第十一晶体管M11的控制极的电位为Vth2，由于Vth2≤Vth2+Vd(1)，满足开启电位V k的条件，因此第十一晶体管M11导通。通常情况下，如果忽略第三晶体管M3的组织，则Vd(1)＝0。故可以理解为，s第二数据信号Data2的电位Vg由设定工作电位Vs (1)变化至参考工作电位Vgc的这一时间段内，第十一晶体管M11一直保持导通状态，将驱动信号传输至第十晶体管M10，直到工作阶段结束。
参考工作电位Vgc的绝对值大于或等于第二数据信号Data2的全部设定工作电位Vs的绝对值中的最大值，示例性地，如图6所示，参照以上对第一行的亚像素在工作阶段t-em的描述，参考工作电位Vgc的绝对值大于在第一行扫描时段t1的第一子时段t1-1第二数据信号Data2的设定工作电位Vs (1)的绝对值，这样可以保证在工作阶段t-em，在第二数据信号Data2的电位Vg由非工作电位Vgf逐渐变化至参考工作电位Vgc的过程中，在达到开启电位V k(例如设定工作电位Vs (1))时，第十一晶体管M11能够导通，使驱动信号得以传输。同样，对于第二行～第n行的亚像素，在工作阶段t-em第二数据信号Data2的参考工作电位Vgc的绝对值大于或等于在第二数据信号Data2的设定工作电位Vs (2)、Vs (3)…Vs (n)的绝对值，以使第十一晶体管M11能够导通。
在第十一晶体管M11导通的时段内，第十一晶体管M11将驱动信号传输至第十晶体管M10，第十晶体管M10在使能信号Em的控制下导通，将驱动信号传输至待驱动元件3，从而使待驱动元件3工作。
对于第二行至第n行的亚像素对应的像素驱动电路100在工作阶段t-em的驱动过程，可参见上面对第一行的亚像素对应的像素驱动电路100在工作阶段t-em的驱动过程的驱动过程的描述。
在一些实施例中，在扫描阶段t-s，对每一行的亚像素对应的像素驱动电路100所写入的第一数据信号Data1的电位V1，与该行的亚像素对应的像素驱动电路100在工作阶段t-em所产生的驱动信号的大小有关。
由上面可知，在工作阶段t-em，每一行的亚像素对应的像素驱动电路100的第一存储电容器C1的第二端的电位为Vd+Vre-V1+Vth1，则第三晶体管的控制极的电位为Vd+Vre-V1+Vth1，第三晶体管的第一极的电位为Vre，因此第三晶体管M3的栅源电压差V gs为Vd+Vre-V1+Vth1-Vre＝Vd-V1+Vth1。因此在工作阶段t-em，根据电流饱和公式，第三晶体管M3产生的驱动电流为：
Figure PCTCN2019115163-appb-000001
其中，其中I ds为第三晶体管M3的饱和电流，也就是输入发光二极管31的工作电流；W/L为第三晶体管M3的沟道宽长比；μ为载流子迁移率；C ox为第三晶体管M3的单位面积沟道电容；V gs为第三晶体管M3的栅源电压差；Vth1为第三晶体管M3的阈值电压。
可见，第三晶体管M3所产生的驱动电流仅与第一电压信号Vdd的电位Vd和所写入的第一数据信号Data1的电位V1有关，与第三晶体管M3的阈值电压Vth1无关，因此第三晶体管M3所产生的驱动电流的大小不受阈值电压的影响，避免了因制备工艺引起的第三晶体管M3的阈值电压的不同影响驱动电流，进而影响显示效果。并且，第三晶体管M3所产生的驱动电流与第三电压信号Vref的电位无关，因此第三晶体管M3所产生的驱动电流不会受到第三电压信号线的压降的影响，从而避免了由于压降导致的各个像素驱动电路100所接收的第三电压信号Vref不一致，所产生的驱动信号的大小不一致，使得显示面板出现显示不均匀的现象的发生。
通过控制在第一行扫描时段t1～第n行扫描时段tn对每行亚像素多对应的像素驱动电路100所写入的第一数据信号Data1的电位V1 (1)～V1 (n)，控制每一行的像素驱动电路100所产生的驱动电流的大小，从而实现控制发光二极管31的发光强度。
在一些实施例中，每个行扫描时段的第一子时段，第二数据信号data2的所具有的设定工作电位Vs的绝对值与相应的待驱动元件3需要工作的工作时长相关。
如图6所示，在第一行扫描时段t1的第一子时段t1-1中，第一行的亚像素对应的像素驱动电路100所写入的第二数据信号data2的设定工作电位为Vs (1)，在第二行扫描时段t2的第一子时段t2-1中，第二行的亚像素对应的像素驱动电路100所写入的第二数据信号data2的设定工作电位为Vs (2)…，在第n行扫描时段tn的第一子时段tn-1中，第n行的亚像素对应的像素驱动电路100所写入的第二数据信号data2的设定工作电位为Vs (n)，其中，Vs (1)、Vs (2)和Vs (n)的绝对值的大小依次减小。
在进入工作阶段t-em之后，每一行的亚像素对应的像素驱动电路100所写入的第二数据信号data2的电位在设定范围内变化，在第二数据信号data2的电位由非工作电位Vgf(0V)变化至设定工作电位Vs时，第十一晶体管M11导通，将驱动信号传输至待驱动元件。
再次参见图6，在工作阶段t-em，第二数据信号data2的电位由非工作电位Vgf(0V)变化至设定工作电位Vs的过程中，设定工作电位Vs的绝对值越小，第二数据信号data2的电位由非工作电位(0V)变化至设定工作电位Vs所需要的时长越短，从而在工作阶段t-em，第十一晶体管M11导通的时间越长，将驱动信号传输至待发光二极管31的时长越长，发光二极管31在一个帧周期1Frame工作时长越长，其发光强度越强。
示例性的，如图5A所示，在发光二极管31的阳极与第十晶体管M10的第二极电连接，二者电连接的节点等效为第五节点N5，发光二极管31的阴极接地的情况下：在第五节点N5的电位为高电平时，发光二极管31开始发光。从图6中可知，Vs (1)、Vs (2)和Vs (n)的绝对值的大小依次减小，所对应的发光二极管31的发光时长t N5(1)、t N5(2)、t N5(n)依次增大，从而可以实现不同灰阶的显示。
综上，本公开提供的像素驱动方法，通过控制在扫描阶段t-s写入驱动信 号控制子电路的第一数据信号Data1的电位，可以实现对所产生的驱动信号的大小的控制，通过控制在扫描阶段t-s写入驱动时长控制子路2的第二数据信号Data2的设定工作电位的绝对值，可以实现对待驱动元件3的工作时长的控制，从而在不同驱动信号与不同工作时长的配合下，可以实现不同灰阶的显示。并且，通过缩短待驱动元件的工作时长，可以使驱动信号的大小维持在较高值范围内，提高待驱动元件的工作效率，节省能耗。
再者，上述对驱动信号的控制以及对工作时长的控制均与晶体管的阈值电压无关，避免了因工艺缺陷导致的晶体管的阈值电压不稳定而影响显示效果。
本公开的一些实施例还提供一种显示面板，包括如上所述的像素驱动电路。
本公开所提供的显示面板采用上述像素驱动电路，在待驱动元件为微型发光二极管的情况下，根据微型发光二极管具有在高电流密度下发光效率高，在低电流密度下发光效率低的特性，采用电流控制和发光时长的控制相互结合方式，在实现不同灰阶的显示时，通过控制微型发光二极管的发光时长实现对其发光强度的控制，使得输入微型发光二极管的电流值保持在较高范围内，从而使微型发光二极管始终处于高电流密度下，发光效率较高，进而降低功耗，节约成本。
在一些实施例中，如图7所示，显示面板200包括多个亚像素101，每个亚像素101对应一个像素驱动电路100，所述多个亚像素101呈多行多列的阵列式布置，示例性地，多个亚像素101呈n行m列的阵列式布置。
显示面板200还包括：多条第一扫描信号线G1(1)～G1(n)、多条第一数据信号线D1(1)～D1(m)、多条第二扫描信号线G2(1)～G2(n)、及多条第二数据信号线D2(1)～D2(m)。
同一行亚像素101对应的各像素驱动电路100与同一条第一扫描信号线及同一条第二扫描信号线电连接。同一列亚像素101对应的各像素驱动电路100与同一条第一数据信号线及同一条第二数据信号线电连接。示例性地，第 一行亚像素101对应的像素驱动电路100与第一扫描信号线G1(1)及第二扫描信号线G2(1)电连接，第一列亚像素101对应的像素驱动电路100与第一数据信号线D1(1)及第二数据信号线D2(1)电连接。
这样，多条第一扫描信号线为第一扫描信号端GATE1提供第一扫描信号Gate1，多条第二扫描信号线为第二扫描信号端GATE2提供第二扫描信号Gate2，多条第一数据信号线为第一数据信号端DATA1提供第一数据信号Data1，多条第二数据信号线为第二数据信号端DATA2提供第二数据信号Data2，从而为像素驱动电路100提供第一扫描信号Gate1、第二扫描信号Gate2、第一数据信号Data1和第二数据信号Data2。
显示面板200还包括：多条复位信号线R(1)～R(n)、多条使能信号线E1(1)～E1(n)、多条初始化信号线VN、多条第一电压信号线L VDD、及多条第三电压信号线L VREF。
同一行亚像素101对应的各像素驱动电路100与同一条复位信号线、同一条使能信号线及同一条第三电压信号线L VREF电连接。同一列亚像素101对应的各像素驱动电路100与同一条初始化信号线电连接。
多条第一电压信号线L VDD分别沿行方向且沿列方向呈网格状排布，同一列亚像素101对应的各像素驱动电路100与同一条沿列方向排布的第一电压信号线L VDD电连接。多条沿行方向排布的第一电压信号线L VDD分别与多条沿列方向排布的第一电压信号线L VDD电连接，多条沿行方向排布的第一电压信号线L VDD被配置为降低多条沿列方向排布的第一电压信号线L VDD的电阻，减少第一电压信号Vdd的RC负载和IR压降(IR Drop)。
这样，多条复位信号线为复位信号端RESET提供复位信号Reset，多条使能信号线为使能信号端EM提供使能信号Em，多条初始化信号线为初始化信号端VINIT提供初始化信号Vinit，多条第三电压信号线L VREF为第三电压信号端VREF提供第三电压信号Vref；多条沿列方向排布的第一电压信号线为第一电压信号端VDD提供第s一电压信号Vdd，从而为像素驱动电路100提供复位信号Reset、使能信号Em、初始化信号Vinit、第一电压信号Vdd和 第三电压信号Vref。其中，第一电压信号Vdd和第三电压信号Vref均为高电平恒压信号，二者的幅值可以相同也可以不同。
需要说明的是，以上所述的显示面板200所包括的多条信号线的排布，以及图7示出的显示面板200的布线图仅是一种示例，并不构成对显示面板的结构的限制。
在一些实施例中，显示面板200还包括：
衬底基板，所述像素驱动电路设置于衬底基板上，该衬底基板为玻璃基板。
在一些实施例中，上述显示面板为Micro LED显示面板，显示面板所包括的多个亚像素中的每个亚像素均对应至少一个微型发光二极管。
由于本公开提供的像素驱动电路100针对微型发光二极管所具有的在高电流密度下发光效率高，在低电流密度下发光效率低的特性，采用电流控制和发光时长的控制相互结合方式，实现不同灰阶的显示，因此在进行较低灰阶的显示时，通过缩短微型发光二极管的发光时长，使输入微型发光二极管的电流保持在较高范围内，从而使微型发光二极管始终处于高电流密度下，发光效率较高，进而降低显示面板的功耗，节约成本，从而本公开提供的显示面板能够适用于有源驱动的方式。
本公开提供的显示面板采用有源驱动的方式，像素驱动电路100可以设置于以玻璃为材料的衬底基板上，由于玻璃基板的拼接工艺较成熟，因此可以根据显示尺寸，将显示面板进行拼接，得到具有较大显示尺寸的显示面板，适用于中等距离观看，示例性地，上述显示面板为电视屏幕。并且，由于上述显示面板采用有源驱动的方式，并采用玻璃基板作为衬底基板，可以采用制备工艺精度较高的曝光、显影、刻蚀等工艺进行像素驱动电路的制备，从而得到的像素驱动电路100的精度较高，亚像素的尺寸得以减小，例如，亚像素的尺寸可以做到400μm甚至更小，这样就使得显示面板的分辨率得以提升，显示画面的画质细腻度较好。在显示面板为Micro LED显示面板的情况下，显示面板的色域和亮度得以提升，能够实现HDR显示，提高显示面板的 显示画面的显示效果。
在一些实施例中，显示面板200所包括的像素驱动电路100中的晶体管采用LTPS(Low Temperature Poly-silicon，低温多晶硅)工艺，在玻璃基板上进行制备得到，由于低温多晶硅具有迁移率较高，稳定性较好的特点，可以提高所制备得到的晶体管的响应速度，因此LTPS工艺更加适用于本公开所提供的采用驱动电流和驱动时长进行控制的像素驱动电路100。并且由于对像素驱动电路100的驱动方法中已进行了对第三晶体管M3和第十一晶体管M11的阈值电压的补偿，因此显示面板200的显示效果不会受到因LTPS工艺的缺陷造成的晶体管的阈值电压偏移的影响。
如图8所示，本公开的一些实施例还提供一种显示装置300，包括如上所述的显示面板200。
本公开提供的显示装置300包括上述显示面板200，因此该显示装置300具有显示尺寸较大，像素分辨率高，适用于HDR显示，显示效果优良等特点。
在一些示例中，上述显示装置300为电视机、手机、平板电脑、笔记本电脑、显示器、数码相框或导航仪等具有显示功能的产品，本公开对此并不设限。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (22)

  1. 一种像素驱动电路，包括：驱动信号控制子电路和驱动时长控制子电路；其中，
    所述驱动信号控制子电路与第一扫描信号端、第一数据信号端、第一电压信号端、使能信号端及所述驱动时长控制子电路电连接，被配置为在所述第一扫描信号端和所述使能信号端的控制下，向所述驱动时长控制子电路提供驱动信号；所述驱动信号与在所述第一数据信号端处接收的第一数据信号和在所述第一电压信号端处接收的第一电压信号有关；
    所述驱动时长控制子电路还与第二扫描信号端、第二数据信号端、使能信号端及待驱动元件电连接，被配置为在所述第二扫描信号端和所述使能信号端的控制下，将所述驱动信号传输至所述待驱动元件；所述驱动信号传输至所述待驱动元件的时长与在所述第二数据信号端处接收的第二数据信号有关。
  2. 根据权利要求1所述的像素驱动电路，其中，所述驱动信号控制子电路包括：第一数据写入单元、第一驱动单元及第一控制单元；其中，
    所述第一数据写入单元与所述第一扫描信号端、所述第一数据信号端及所述第一驱动单元电连接，被配置为在所述第一扫描信号端的控制下，将在所述第一数据信号端处接收的第一数据信号写入至所述第一驱动单元；
    所述第一控制单元与所述使能信号端、所述第一电压信号端及所述第一驱动单元电连接，被配置为在所述使能信号端的控制下，将在所述第一电压信号端处接收的第一电压信号输入至所述第一驱动单元；
    所述第一驱动单元还与第三电压信号端电连接，被配置为根据所写入的第一数据信号和所输入的第一电压信号，及在所述第三电压信号端处接收的第三电压信号，产生所述驱动信号，并将所述驱动信号传输至所述第一控制单元；
    所述第一控制单元还与所述驱动时长控制子电路电连接，被配置为在所述使能信号端的控制下，将所述驱动信号传输至所述驱动时长控制子电路。
  3. 根据权利要求2所述的像素驱动电路，其中，
    所述第一数据写入单元包括：
    第一晶体管，所述第一晶体管的控制极与所述第一扫描信号端电连接，所述第一晶体管的第一极与所述第一数据信号端电连接，所述第一晶体管的第二极与所述第一驱动单元电连接；
    第二晶体管，所述第二晶体管的控制极与所述第一扫描信号端电连接，所述第二晶体管的第一极和第二极与所述第一驱动单元电连接；
    所述第一驱动单元包括：
    第一存储电容器，所述第一存储电容器的第一端与所述第一数据写入单元及所述第一控制单元电连接，所述第一存储电容器的第二端与所述第一数据写入单元电连接；
    第三晶体管，所述第三晶体管的控制极与所述第一存储电容器的第二端及所述第一数据写入单元电连接，所述第三晶体管的第一极与所述第三电压信号端电连接，所述第三晶体管的第二极与所述第一数据写入单元及所述第一控制单元电连接；
    所述第一控制单元包括：
    第四晶体管，所述第四晶体管的控制极与所述使能信号端电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第一驱动单元电连接；
    第五晶体管，所述第五晶体管的控制极与所述使能信号端电连接，所述第五晶体管的第一极与所述第一驱动单元电连接，所述第五晶体管的第二极与所述驱动时长控制子电路电连接。
  4. 根据权利要求2所述的像素驱动电路，其中，所述驱动信号控制子电路还包括：第一复位单元；
    所述第一复位单元与所述第一电压信号端、复位信号端、初始化信号端及所述第一驱动单元电连接，被配置为在所述复位信号端的控制下，根据在所述第一电压信号端处接收的第一电压信号和在所述初始化信号端处接收的 初始化信号，对所述第一驱动单元的电压进行复位。
  5. 根据权利要求4所述的像素驱动电路，其中，所述第一复位单元包括：
    第六晶体管，所述第六晶体管的控制极与所述复位信号端电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一驱动单元电连接；
    第七晶体管，所述第七晶体管的控制极与所述复位信号端电连接，所述第七晶体管的第一极与所述初始化信号端电连接，所述第七晶体管的第二极与所述第一驱动单元电连接。
  6. 根据权利要求2～5中任一项所述的像素驱动电路，其中，所述驱动信号控制子电路还包括：驱动信号稳定单元；
    所述驱动信号稳定单元与所述第一驱动单元电连接，被配置为使所述第一驱动单元所产生的驱动信号保持稳定。
  7. 根据权利要求6所述的像素驱动电路，其中，所述驱动信号稳定单元包括：稳压存储电容器；
    在所述第一驱动单元包括第一存储电容器和第三晶体管的情况下，
    所述稳压存储电容器的第一端与所述第一存储电容器的第一端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接；
    或者，所述稳压存储电容器的第一端与所述第一存储电容器的第二端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接。
  8. 根据权利要求1～7中任一项所述的像素驱动电路，其中，所述驱动信号控制子电路包括：第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管、第一存储电容器及稳压存储电容器；
    所述第一晶体管的控制极与所述第一扫描信号端电连接，所述第一晶体管的第一极与所述第一数据信号端电连接，所述第一晶体管的第二极与所述第一存储电容器的第一端电连接；
    所述第二晶体管的控制极与所述第一扫描信号端电连接，所述第二晶体管的第一极与所述第三晶体管的第二极电连接，所述第二晶体管的第二极与 所述第一存储电容器的第二端及所述第三晶体管的控制极电连接；
    所述第三晶体管的控制极还与所述第一存储电容器的第二端电连接，所述第三晶体管的第一极与所述第三电压信号端电连接，所述第三晶体管的第二极还与所述第五晶体管的第一极电连接；
    所述第四晶体管的控制极与所述使能信号端电连接，所述第四晶体管的第一极与所述第一电压信号端电连接，所述第四晶体管的第二极与所述第一存储电容器的第一端电连接；
    所述第五晶体管的控制极与所述使能信号端电连接，所述第五晶体管的第二极与所述驱动时长控制子电路电连接；
    所述第六晶体管的控制极与复位信号端电连接，所述第六晶体管的第一极与所述第一电压信号端电连接，所述第六晶体管的第二极与所述第一存储电容器的第一端电连接；
    所述第七晶体管的控制极与所述复位信号端电连接，所述第七晶体管的第一极与初始化信号端电连接，所述第七晶体管的第二极与所述第一存储电容器的第二端及所述第三晶体管的控制极电连接；
    所述稳压存储电容器的第一端与所述第一存储电容器的第一端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接；或者，所述稳压存储电容器的第一端与所述第一存储电容器的第二端电连接，所述稳压存储电容器的第二端与所述第三晶体管的第二极电连接。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管、所述第六晶体管及第七晶体管均为P型晶体管或者均为N型晶体管。
  10. 根据权利要求1所述的像素驱动电路，其中，所述驱动时长控制子电路包括：第二数据写入单元、第二控制单元及第二驱动单元；其中，
    所述第二数据写入单元与所述第二扫描信号端、所述第二数据信号端及所述第二驱动单元电连接，被配置为在所述第二扫描信号端的控制下，将在所述第二数据信号端处接收的具有设定工作电位的第二数据信号写入至所述 第二驱动单元；
    所述第二控制单元与所述使能信号端、所述第二数据信号端及所述第二驱动单元电连接，被配置为在所述使能信号端的控制下，将在所述第二数据信号端处接收的电位在设定范围内变化的第二数据信号传输至所述第二驱动单元；
    所述第二驱动单元还与所述驱动信号控制子电路电连接，被配置为根据所述具有设定工作电位的第二数据信号和所述电位在设定范围内变化的第二数据信号，将所述驱动信号传输至所述第二控制单元，并控制所述驱动信号传输至所述第二控制单元的时长；
    所述第二控制单元还与所述待驱动元件电连接，还被配置为将所述驱动信号传输至所述待驱动元件。
  11. 根据权利要求10所述的像素驱动电路，其中，
    所述第二数据写入单元包括：
    第八晶体管，所述第八晶体管的控制极与所述第二扫描信号端电连接，所述第八晶体管的第一极与所述第二数据信号端电连接，所述第八晶体管的第二极与所述第二驱动单元电连接；
    所述第二控制单元包括：
    第九晶体管，所述第九晶体管的控制极与所述使能信号端电连接，所述第九晶体管的第一极与所述第二数据信号端电连接，所述第九晶体管的第二极与所述第二驱动单元电连接；
    第十晶体管，所述第十晶体管的控制极与所述使能信号端电连接，所述第十晶体管的第一极与所述第二驱动单元电连接，所述第十晶体管的第二极与所述待驱动元件电连接；
    所述第二驱动单元包括：
    第二存储电容器，所述第二存储电容器的第一端与所述第二数据写入单元及所述第二控制单元电连接；
    第十一晶体管，所述第十一晶体管的控制极与所述第二存储电容器的第 二端电连接，所述第十一晶体管的第一极与所述驱动信号控制子电路电连接，所述第十一晶体管的第二极与所述第二控制单元电连接。
  12. 根据权利要求10所述的像素驱动电路，其中，所述驱动时长控制子电路还包括：第二复位单元；
    所述第二复位单元与复位信号端、初始化信号端及所述第二驱动单元电连接，被配置为在所述复位信号端的控制下，根据在所述初始化信号端处接收的初始化信号，对所述第二驱动单元的电压进行复位。
  13. 根据权利要求12所述的像素驱动电路，其中，所述第二复位单元包括：
    第十二晶体管，所述第十二晶体管的控制极与所述复位信号端电连接，所述第十二晶体管的第一极与所述初始化信号端电连接，所述第十二晶体管的第二极与所述第二驱动单元电连接；
    第十三晶体管，所述第十三晶体管的控制极与所述复位信号端能接，所述第十三晶体管的第一极和第二极与所述第二驱动单元电连接。
  14. 根据权利要求1、10～13中任一项所述的像素驱动电路，其中，所述驱动时长控制子电路包括：第八晶体管、第九晶体管、第十晶体管、第十一晶体管、第十二晶体管、第十三晶体管及第二存储电容器；
    所述第八晶体管的控制极与所述第二扫描信号端电连接，所述第八晶体管的第一极与所述第二数据信号端电连接，所述第八晶体管的第二极与所述第二存储电容器的第一端电连接；
    所述第九晶体管的控制极与所述使能信号端电连接，所述第九晶体管的第一极与所述第二数据信号端电连接，所述第九晶体管的第二极与所述第二存储电容器的第一端电连接；
    所述第十晶体管的控制极与所述使能信号端电连接，所述第十晶体管的第一极与所述第十一晶体管的第二极电连接，所述第十晶体管的第二极与所述待驱动元件电连接；
    所述第十一晶体管的控制极与所述第二存储电容器的第二端电连接，所 述第十一晶体管的第一极与所述驱动信号控制子电路及所述第十二晶体管的第二极电连接，所述第十一晶体管的第二极还与所述第十三晶体管的第一极电连接；
    所述十二晶体管的控制极与复位信号端电连接，所述十二晶体管的第一极与初始化信号端电连接；
    所述第十三晶体管的控制极与所述复位信号端电连接，所述第十三晶体管的第二极与所述第二存储电容器的第二端及所述第十一晶体管的控制极电连接。
  15. 根据权利要求14所述的像素驱动电路，其中，所述第八晶体管、所述第九晶体管、所述第十晶体管、所述第十一晶体管、所述第十二晶体管及所述第十三晶体管均为P型晶体管或者均为N型晶体管。
  16. 一种像素驱动方法，应用于如权利要求1～15中任选一项所述像素驱动电路，所述像素驱动方法包括：一个帧周期包括扫描阶段和工作阶段，所述扫描阶段包括多个行扫描时段，
    所述多个行扫描时段中的每个行扫描时段包括：
    驱动信号控制子电路在第一扫描信号端的控制下，写入第一数据信号；
    驱动时长控制子电路在所述第二扫描信号端的控制下，写入具有设定工作电位的第二数据信号；
    所述工作阶段包括：
    所述驱动信号控制子电路在使能信号端的控制下，向所述驱动时长控制子电路提供驱动信号；所述驱动信号与所述第一数据信号和第一电压信号端提供的第一电压信号有关；
    所述驱动时长控制子电路在所述使能信号端的控制下，接收电位在设定范围内变化的第二数据信号，将所述驱动信号传输至待驱动元件；所述驱动信号传输至所述待驱动元件的时长与所述具有设定工作电位的第二数据信号和所述电位在设定范围内变化的第二数据信号有关。
  17. 根据权利要求16所述的像素驱动方法，其中，设定工作电位的绝对 值与相应的待驱动元件需要工作的工作时长相关。
  18. 根据权利要求17所述的像素驱动方法，其中，所述设定范围的两个端点值分别为：所述第二数据信号的非工作电位和参考工作电位；
    所述参考工作电位的绝对值大于或等于所述第二数据信号的全部工作电位的绝对值中的最大值；
    所述设定工作电位在所述设定范围之内。
  19. 一种显示面板，包括如权利要求1～15中任一项所述的像素驱动电路。
  20. 根据权利要求19所述的显示面板，所述显示面板包括多个亚像素，每个亚像素对应一个所述像素驱动电路，所述多个亚像素呈多行多列的阵列式布置；
    所述显示面板还包括：多条第一扫描信号线、多条第一数据信号线、多条第二扫描信号线、及多条第二数据信号线；
    同一行亚像素对应的各像素驱动电路与同一条第一扫描信号线及同一条第二扫描信号线电连接；
    同一列亚像素对应的各像素驱动电路与同一条第一数据信号线及同一条第二数据信号线电连接。
  21. 根据权利要求19所述的显示面板，还包括：衬底基板，所述像素驱动电路设置于所述衬底基板上，所述衬底基板为玻璃基板。
  22. 一种显示装置，包括如权利要求19～21中任一项所述的显示面板。
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