WO2021039047A1

WO2021039047A1 - Chip-like electronic component jig

Info

Publication number: WO2021039047A1
Application number: PCT/JP2020/023938
Authority: WO
Inventors: 雄太田中
Original assignee: 株式会社村田製作所
Priority date: 2019-08-23
Filing date: 2020-06-18
Publication date: 2021-03-04
Also published as: CN114245926B; KR20220028100A; JPWO2021039047A1; KR102554646B1; JP7193001B2; CN114245926A

Abstract

A chip-like electronic component jig (10) is provided with a first layer (11), a second layer (12), a third layer (13), and at least one of a fourth layer (14) and a fifth layer (15). The fourth layer (14) is positioned over the first layer (11). The fourth layer (14), when viewed from a stacking direction, is composed of a plurality of fourth linear members (14L) extending so as to overlap with a plurality of third linear members (13L), the number of the fourth linear members (14L) being not less than two and less than the number of the plurality of third linear members (13L). The fifth layer (15) is positioned over the first layer (11). The fifth layer (15), when viewed from the stacking direction, is composed of a plurality of fifth linear members (15L) extending so as to overlap with a plurality of second linear members (12L), the number of the fifth linear members (15L) being not less than two and less than the number of the plurality of second linear members (12L).

Description

Jig for chip-shaped electronic parts

The present invention relates to a jig for chip-shaped electronic parts.

As documents disclosing the configuration of jigs for chip-shaped electronic components, Japanese Patent Application Laid-Open No. 2008-177188 (Patent Document 1), Japanese Patent No. 6259943 (Patent Document 2), and Japanese Patent Application Laid-Open No. 2018-193287 (Patent Document 3). There is.

The jig for chip-shaped electronic components described in Patent Document 1 is a jig used for processing chip-shaped electronic components, and includes a support member and a receiving member. The support member is made of a metal material. The support member is flat as a whole and has a large number of penetrating tip insertion holes in the plane. The receiving member is a net-like body in which a metal meridian and a metal parallel are woven. The receiving member is joined to one surface of the support member, and at least one intersection exists in the opening surface of the chip insertion hole.

The jig for chip-shaped electronic parts described in Patent Document 2 is a ceramic lattice. The ceramic lattice body includes a plurality of first streaks made of ceramics extending in one direction and a plurality of second streaks made of ceramics extending in a direction intersecting the first streaks. And have. At the intersection of the first line portion and the second line portion, the second line portion is arranged on the first line portion at any of the intersections. At the intersection, the first linear portion has a shape in which the cross section is composed of a straight portion and a convex curved portion having both ends of the straight portion as ends. At the intersection, the second striation has a circular or elliptical cross section. In the vertical cross-sectional view of the intersection, the first streak and the second streak are the top of the convex curve in the first streak and the circle or ellipse in the second streak. Only the downwardly convex top of the shape is in contact.

The jig for chip-shaped electronic parts described in Patent Document 3 is a ceramic lattice. The ceramic lattice body includes a plurality of first streaks made of ceramics extending in one direction and a plurality of second streaks made of ceramics extending in a direction intersecting the first streaks. And have. At the intersection of the first line portion and the second line portion, the second line portion is arranged on the first line portion at any of the intersections. When the straight portion of the first streak portion is placed on a plane as a mounting surface, the second striation portion has a shape separated from the plane between two adjacent intersections. There is. The ceramic lattice body further has a plurality of third linear portions made of ceramics extending in the same direction as the extending direction of the first linear portion. The third streak intersects the second streak. At the intersection of the third line portion and the second line portion, the third line portion is arranged on the second line portion at any of the intersections. The third streak is arranged half a pitch off the pitch of the first streak.

Japanese Unexamined Patent Publication No. 2008-177188 Japanese Patent No. 6259943 JP-A-2018-193287

When processing a plurality of chip-shaped electronic components with a reaction gas using a conventional chip-shaped electronic component jig, a plurality of chips are inserted into each of the plurality of chip insertion holes formed in the chip-shaped electronic component jig. Insert electronic components. At this time, as the distance between the chip-shaped electronic component and the peripheral wall portion of the chip insertion hole increases, the reaction gas easily flows into the periphery of the chip-shaped electronic component, and the reaction efficiency of the chip-shaped electronic component increases. However, as the separation distance becomes longer, the number of chip-shaped electronic components that can be arranged in one jig for chip-shaped electronic components decreases. As a result, the productivity of the chip-shaped electronic component in the processing step may decrease.

The present invention has been made in view of the above problems, and provides a jig for chip-shaped electronic components capable of improving the reaction efficiency of the chip-shaped electronic components while maintaining the number of chip-shaped electronic components that can be arranged. With the goal.

The jig for a chip-shaped electronic component based on the present invention is for a chip-shaped electronic component, which is composed of a plurality of layers in which a plurality of layers formed by extending a plurality of linear members in parallel with each other are laminated. The jig includes a first layer, a second layer, and a third layer, and includes at least one of the fourth layer and the fifth layer. The first layer contains a plurality of first linear members extending at equal intervals. The second layer is located above the first layer. The second layer is composed of a plurality of second linear members extending side by side at equal intervals so as to be staggered with the first linear member when viewed from the stacking direction of the plurality of layers. The third layer is located above the first layer. The third layer is composed of a plurality of third linear members that are arranged at equal intervals and extend in a direction intersecting with the second linear member when viewed from the stacking direction. The fourth layer is located above the first layer. The fourth layer is composed of a plurality of fourth linear members extending so as to overlap the plurality of third linear members when viewed from the stacking direction, and having two or more and less than the number of the plurality of third linear members. It is configured. The fifth layer is located above the first layer. The fifth layer is a plurality of fifth linear members extending so as to overlap the plurality of second linear members when viewed from the stacking direction, and having two or more and less than the number of the plurality of second linear members. It is configured.

According to the present invention, it is possible to improve the reaction efficiency of chip-shaped electronic components while maintaining the number of chip-shaped electronic components that can be arranged.

It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 1 of this invention. It is a front view which saw the jig for chip-shaped electronic parts of FIG. 1 from the direction of arrow II. It is a side view which saw the jig for chip-shaped electronic parts of FIG. 1 from the direction of arrow III. It is a front view which shows the structure of the chip-shaped electronic component which concerns on a comparative example. It is a side view which shows the structure of the chip-shaped electronic component which concerns on a comparative example. It is a front view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 2 of this invention. It is a side view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 2 of this invention. It is a front view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 3 of this invention. It is a side view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 3 of this invention.

Hereinafter, jigs for chip-shaped electronic components according to each embodiment of the present invention will be described. In the following description of the embodiment, the same or corresponding parts in the drawings are designated by the same reference numerals, and the description will not be repeated.

(Embodiment 1)
FIG. 1 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the first embodiment of the present invention. FIG. 2 is a front view of the jig for chip-shaped electronic components of FIG. 1 as viewed from the direction of arrow II. FIG. 3 is a side view of the jig for chip-shaped electronic components of FIG. 1 as viewed from the direction of arrow III.

As shown in FIGS. 1 to 3, the jig 10 for a chip-shaped electronic component according to the first embodiment of the present invention is composed of a plurality of layers, and in the plurality of layers, a plurality of linear members are formed. A plurality of layers formed by extending in parallel with each other are laminated. The jig 10 for chip-shaped electronic components includes a first layer 11, a second layer 12, a third layer 13, a fourth layer 14, a fifth layer 15, a sixth layer 16, and a seventh layer 17. And have.

As shown in FIG. 1, the jig 10 for a chip-shaped electronic component according to the first embodiment of the present invention has a substantially rectangular outer shape as a whole when viewed from the stacking direction of the plurality of layers. .. The jig 10 for a chip-shaped electronic component may have an outer shape of another polygon such as a triangle, a pentagon, or a hexagon when viewed from the stacking direction of the plurality of layers. Seen from the stacking direction, the overall outer shape of the jig for chip-shaped electronic components according to the present embodiment has sides parallel to the extending direction of a plurality of linear members described later. In addition, when viewed from the stacking direction, the outer shape may have a side inclined by 45 degrees with respect to the extending direction of the plurality of linear members.

As shown in FIGS. 1 to 3, the first layer 11 includes a plurality of first linear members 11L extending side by side at equal intervals. The distance between the adjacent first linear members 11L is, for example, 0.1 mm or more and 5.0 mm or less. The first layer 11 may include another linear member on the outer side of the plurality of first linear members 11L when viewed from the stacking direction. The first linear member 11L and other linear members described later may be made by cutting a plate-shaped member in one direction and processing it into a long and thin shape.

As shown in FIGS. 2 and 3, the second layer 12 is located above the first layer 11. As shown in FIGS. 1 and 3, the second layer 12 is composed of a plurality of second linear members 12L. The plurality of second linear members 12L extend side by side at equal intervals so as to be staggered with the first linear member 11L when viewed from the stacking direction of the plurality of layers. In the chip-shaped electronic component jig 10 according to the first embodiment of the present invention, the side having the entrance of the insertion hole described later is the upper side.

In the present embodiment, when viewed from the stacking direction, the two second linear members 12L arranged on the outermost side of the plurality of second linear members 12L are outside the plurality of first linear members 11L. Is located in. When viewed from the stacking direction, each of the plurality of first linear members 11L is located at the center of the plurality of second linear members 12L adjacent to each other among the plurality of second linear members 12L. Each of the plurality of first linear members 11L may be located at a position deviated from the center of the plurality of second linear members 12L adjacent to each other when viewed from the stacking direction, but is viewed from the stacking direction. Occasionally, since each of the plurality of first linear members 11L is located in the center of the above, the plurality of chip-shaped electronic components 1 inserted into each of the plurality of chip insertion ports can be stably inserted as described later. Can be held. The first layer 11 may include other linear members located outside the plurality of second linear members 12L when viewed from the stacking direction.

As shown in FIGS. 2 and 3, the third layer 13 is located above the first layer 11. As shown in FIGS. 1 and 2, the third layer 13 is composed of a plurality of third linear members 13L. When viewed from the stacking direction, the plurality of third linear members 13L are arranged at equal intervals and extend in a direction intersecting with the second linear member 12L. In the present embodiment, the separation distance between the plurality of third linear members 13L adjacent to each other is the same as the separation distance between the plurality of second linear members 12L adjacent to each other. In the present embodiment, the plurality of third linear members 13L are arranged at equal intervals and extend in a direction orthogonal to the second linear member 12L when viewed from the stacking direction.

The second layer 12 and the third layer 13 are located above the first layer 11. In the present embodiment, one of the second layer 12 and the third layer 13 is located on the uppermost side of the plurality of layers, and the other layer of the second layer 12 and the third layer 13 is located. However, it is located directly under one layer. Specifically, the third layer 13 is located on the uppermost side of the plurality of layers. The second layer 12 and the third layer 13 are laminated so as to be adjacent to each other. A fourth layer or the like, which will be described later, may be located between the second layer 12 and the third layer 13.

As shown in FIGS. 1 to 3, the jig 10 for a chip-shaped electronic component according to the first embodiment of the present invention is provided with a plurality of insertion holes into which the chip-shaped electronic component 1 can be inserted. Specifically, as shown in FIG. 1, a plurality of second linear members 12L adjacent to each other and two third linear members 13L adjacent to each other when viewed from the stacking direction. The jig 10 for a chip-shaped electronic component according to the present embodiment is configured so that the chip-shaped electronic component 1 can be inserted into each of the plurality of insertion holes, each of which is an insertion hole. In other words, the two insertion holes adjacent to each other are separated by one second linear member 12L or one third linear member 13L. Further, in the fourth layer 14, the fifth layer and the seventh layer 17, each of the plurality of linear members described later located in each layer separates two insertion holes adjacent to each other, but the fourth layer 14 In the 5th layer 15 and the 7th layer 17, the insertion holes adjacent to each other may not be separated by a linear member. Further, as shown in FIG. 2, the chip-shaped electronic component 1 inserted into the insertion hole is held by the first layer 11 composed of a plurality of first linear members 11L.

As shown in FIGS. 1 to 3, the chip-shaped electronic component 1 has, for example, a rectangular parallelepiped outer shape. The chip-shaped electronic component jig 10 according to the present embodiment has a dimension T in the thickness direction, a dimension W in the width direction orthogonal to the thickness direction, and a length direction orthogonal to both the thickness direction and the width direction. A rectangular parallelepiped chip-shaped electronic component 1 having a W = T <L relationship with each other can be inserted into the insertion hole. In the present embodiment, the plurality of insertion holes are configured so that the rectangular parallelepiped chip-shaped electronic component 1 can be inserted in a direction parallel to the length direction. The chip-shaped electronic component 1 can be used, for example, in a multilayer ceramic capacitor, a multilayer ceramic inductor, a multilayer ceramic piezoelectric element, a multilayer ceramic module substrate, or the like. It should be noted that the dimensions W and T of the chip-shaped electronic component 1 that can actually be inserted into the insertion hole are not exactly the same as each other, and may differ within a certain range. For example, each of the dimensions W and T designed to be the same as each other may be within plus or minus 5% of the value at the time of design.

As shown in FIGS. 2 and 3, in the present embodiment, the fourth layer 14 is located above the first layer 11 and below the third layer 13. The fourth layer 14 may be located above the third layer.

The fourth layer 14 is composed of a plurality of fourth linear members 14L having two or more and less than the number of the plurality of third linear members 13L. Each of the plurality of fourth linear members 14L extends so as to overlap the plurality of third linear members 13L when viewed from the stacking direction. Further, between the fourth layer 14 and the third layer 13, other than that, a linear member extending so as to intersect each of the plurality of third linear members 13L when viewed from the stacking direction is formed. Layer is at least located. In the present embodiment, the fifth layer 15, the seventh layer 17, and the second layer 12, which will be described later, are located between the fourth layer 14 and the third layer 13.

As shown in FIG. 2, in the fourth layer 14, the plurality of fourth linear members 14L are not located at a part of the positions where they overlap with the plurality of third linear members 13L when viewed from the stacking direction. The void portion 19 is formed. When the chip-shaped electronic component 1 is inserted into each of the plurality of insertion holes, the gap portion 19 in the fourth layer 14 allows the reaction gas to flow in the extending direction of each of the plurality of fourth linear members 14L. Functions as a possible gas flow path.

In the present embodiment, the fourth layer 14 is configured such that a plurality of fourth linear members 14L and a plurality of gap portions 19 are alternately positioned when viewed from the stacking direction. As a result, all the chip-shaped electronic components 1 inserted into each of the plurality of insertion holes can be adjacent to the gap 19 in the fourth layer 14. Further, when the chip-shaped electronic component 1 inserted into the chip-shaped electronic component jig 10 is fired, the chip-shaped electronic component 1 is inserted into the insertion hole by the plurality of fourth linear members 14L in the fourth layer 14. It is possible to suppress the movement around and maintain the strength of the chip-shaped electronic component jig 10. Further, by changing the number of the fourth linear members 14L in the fourth layer 14, the movement prevention effect of the chip-shaped electronic component 1 and the gas flow improving effect can be adjusted.

In the present embodiment, the chip-shaped electronic component jig 10 further includes a seventh layer 17 located parallel to the fourth layer 14. The seventh layer 17 also has a plurality of seventh wires extending so as to overlap the plurality of third linear members 13L when viewed from the stacking direction, and having two or more and less than the number of the plurality of third linear members 13L. It is composed of a shape member 17L. In the present embodiment, the second layer 12 is located between the seventh layer 17 and the third layer 13.

Also in the seventh layer 17, a gap 19 in which the plurality of seventh linear members 17L are not located is formed at a part of the positions where the plurality of third linear members 13L overlap when viewed from the stacking direction. There is. The seventh layer 17 is configured such that a plurality of seventh linear members 17L and a plurality of gap portions 19 are alternately positioned when viewed from the stacking direction. Further, each of the plurality of seventh linear members 17L constituting the seventh layer 17 is located at a position overlapping each of the plurality of gaps 19 in the fourth layer 14 when viewed from the stacking direction. The chip-shaped electronic component jig 10 does not have to include the seventh layer 17.

The fifth layer 15 is located above the first layer 11 and below the second layer 12. The fifth layer 15 may be located above the second layer 12.

The fifth layer 15 has a plurality of fifth lines extending so as to overlap the plurality of second linear members 12L when viewed from the stacking direction, and the number of the fifth layer 15 is less than the number of the plurality of second linear members 12L. It is composed of a shape member 15L. Therefore, between the fifth layer 15 and the second layer 12, at least a linear member extending so as to be orthogonal to each of the plurality of second linear members 12L when viewed from the stacking direction is formed. The other layers that have been made are located. In the present embodiment, the seventh layer 17 is located between the fifth layer 15 and the second layer.

As shown in FIG. 3, in the fifth layer 15, the plurality of fifth linear members 15L are not located at a part of the positions where they overlap with the plurality of second linear members 12L when viewed from the stacking direction. The void portion 19 is formed. When the chip-shaped electronic component 1 is inserted into each of the plurality of insertion holes, the gap portion 19 in the fifth layer 15 allows the reaction gas to flow in each extending direction of the plurality of fifth linear members 15L. Functions as a possible gas flow path.

In the present embodiment, the fifth layer 15 is configured such that a plurality of fifth linear members 15L and a plurality of gap portions 19 are alternately positioned when viewed from the stacking direction. As a result, all the chip-shaped electronic components 1 inserted into each of the insertion holes can be adjacent to the gap 19 in the fifth layer 15.

In the present embodiment, the jig 10 for chip-shaped electronic components may include an additional layer corresponding to the fifth layer 15 in the same manner as the correspondence between the fourth layer 14 and the seventh layer 17. The jig 10 for chip-shaped electronic components does not have to include the additional layer.

As described above, the chip-shaped electronic component jig 10 always includes at least one of the fourth layer 14 and the fifth layer 15, and in the present embodiment, the chip-shaped electronic component jig 10 is It includes both the fourth layer 14 and the fifth layer 15. When the chip-shaped electronic component jig 10 includes the fourth layer 14, the jig 10 does not have to include the fifth layer 15. When the chip-shaped electronic component jig 10 includes the fifth layer 15, the jig 10 does not have to include the fourth layer 14.

Further, as shown in FIGS. 2 and 3, in the present embodiment, all of the plurality of layers are above the first layer 11 and below the second layer 12 when viewed from the stacking direction. A plurality of linear members extending so as to overlap each of the plurality of second linear members 12L, and all the plurality of third linear members above the first layer 11 and below the third layer 13. It includes at least one of a plurality of linear members extending so as to overlap each of the 13 Ls. As shown in FIG. 2, specifically, when viewed from the stacking direction, a plurality of fourth linear members 14L of the fourth layer 14 and a plurality of seventh linear members 17L of the seventh layer 17 are formed. The linear members are overlapped with all the third linear members 13L of the third layer 13 in a one-to-one correspondence. That is, in the portion above the first layer 11 of the plurality of layers, the plurality of linear members of the other layers extending in the same direction as the third linear member 13L of the third layer 13 are the third layer. It overlaps with all the third linear members 13L in a one-to-one correspondence. Further, as shown in FIG. 3, some of the second linear members 12L of the plurality of second linear members 12L of the second layer 12 are in the same direction as the second linear members 12L when viewed from the stacking direction. It does not have to overlap with a plurality of linear members of other layers extending in.

As shown in FIGS. 2 and 3, the sixth layer 16 is located below the first layer 11. The sixth layer 16 is composed of a plurality of sixth linear members 16L.

As shown in FIGS. 1 and 2, each of the plurality of sixth linear members 16L extends side by side at equal intervals so as to be staggered with the plurality of third linear members 13L when viewed from the stacking direction. Exists. When viewed from the stacking direction, the two third linear members 13L arranged on the outermost side of the plurality of third linear members 13L are located outside the plurality of sixth linear members 16L.

By providing the plurality of sixth linear members 16L, the strength of the chip-shaped electronic component jig 10 is improved. Since the plurality of sixth linear members 16L do not constitute the inner surface of the chip insertion hole in the chip-shaped electronic component 1, the number, arrangement intervals, orientations, and the like of the plurality of sixth linear members 16L are appropriate. It can be changed. An embodiment in which the number of the plurality of sixth linear members 16L is changed will be described later.

Further, when viewed from the stacking direction, each of the plurality of sixth linear members 16L is located at the center of the plurality of third linear members 13L adjacent to each other among the plurality of third linear members 13L. There is. That is, as shown in FIGS. 1 to 3, in the present embodiment, the intersection with each of the plurality of first linear members 11L and each of the plurality of sixth linear members 16L when viewed from the stacking direction. Reference numeral 18 denotes approximately the center of the insertion slot. When viewed from the stacking direction, each of the plurality of sixth linear members 16L is displaced from the center of the plurality of third linear members 13L adjacent to each other among the plurality of third linear members 13L. It may be located in a place.

In the present embodiment, a plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, Each of the plurality of sixth linear members 16L and the plurality of seventh linear members 17L is substantially linear. A plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, a plurality of sixth wires. Each of the shaped member 16L and the plurality of seventh linear members 17L has a substantially circular outer shape when viewed from the extending direction. Each of these plurality of linear members may have a rectangular, semicircular or non-rectangular polygonal outer shape when viewed from the extending direction. A plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, a plurality of sixth wires. The wire diameter of each of the shape member 16L and the plurality of seventh linear members 17L is, for example, 0.1 mm or more and 2.0 mm or less. The wire diameters of these linear members may be the same as or different from each other, but in the present embodiment, they are the same as each other.

A plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, a plurality of sixth wires. Each of the shape member 16L and the plurality of seventh linear members 17L may be made of the same material as each other, or may be made of different materials from each other. A plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, a plurality of sixth wires. Each of the shape member 16L and the plurality of seventh linear members 17L is, for example, ceramics such as SiC, zirconia, ittria-stabilized zirconia, alumina or mulite, metals such as nickel, aluminum, inconel (registered trademark) or SUS, and poly. A resin material such as tetrafluoroethylene (PTFE: polytetrafluoroethylene), polypropylene (PP: polypropylene), acrylic resin, ABS (Acrylonitrile butadiene styrene) -like resin or other heat-resistant resin, carbon, or a composite material consisting of metal and ceramics. It is made of ceramics in this embodiment. Further, a plurality of first linear members 11L, a plurality of second linear members 12L, a plurality of third linear members 13L, a plurality of fourth linear members 14L, a plurality of fifth linear members 15L, and a plurality of first linear members. The surfaces of the 6-linear member 16L and the plurality of 7th linear members 17L are further coated with ceramics such as SiC, zirconia, yttria, yttria-stabilized zirconia, alumina or mullite, or metals such as nickel. May be good.

In the present embodiment, each of the first layer 11, the second layer 12, the third layer 13, the fourth layer 14, the fifth layer 15, the sixth layer 16 and the seventh layer 17 is connected to each other with other adjacent layers. It is joined. The jig 10 for chip-shaped electronic components according to the present embodiment can be obtained, for example, by firing a lattice body formed of a plurality of linear members made of ceramics before firing.

Here, a jig for chip-shaped electronic parts according to a comparative example will be described. FIG. 4 is a front view showing the configuration of the chip-shaped electronic component according to the comparative example. FIG. 5 is a side view showing the configuration of the chip-shaped electronic component according to the comparative example. In FIG. 4, it is shown when viewed from the same direction as in FIG. In FIG. 5, it is shown when viewed from the same direction as in FIG.

As shown in FIG. 4, in the chip-shaped electronic component jig 90 according to the comparative example, the number of the fourth layer 94 is the same as the number of the plurality of third linear members 13L when viewed from the stacking direction. It is composed of a plurality of fourth linear members 94L. The seventh layer 97 is composed of a plurality of seventh linear members 97L in the same number as the number of the plurality of third linear members 13L when viewed from the stacking direction. As shown in FIG. 5, the fifth layer 95 is composed of a plurality of fifth linear members 95L in the same number as the number of the plurality of second linear members 12L when viewed from the stacking direction. Therefore, in the chip-shaped electronic component jig 90 according to the comparative example, the gaps such as the plurality of gaps 19 formed by the chip-shaped electronic component jig 10 according to the first embodiment of the present invention are formed. Not formed.

On the other hand, the jig 10 for chip-shaped electronic components according to the first embodiment of the present invention includes at least one of the fourth layer 14 and the fifth layer 15. The fourth layer 14 has a plurality of fourth wires extending so as to overlap the plurality of third linear members 13L when viewed from the stacking direction, and the number of the fourth layer 14 is less than the number of the two or more and the plurality of third linear members 13L. It is composed of a shape member 14L. The fifth layer 15 has a plurality of fifth lines extending so as to overlap the plurality of second linear members 12L when viewed from the stacking direction, and the number of the fifth layer 15 is less than the number of the two or more and the plurality of second linear members 12L. It is composed of a shape member 15L.

As a result, in the chip-shaped electronic component jig 10 according to the present embodiment, the gap portion 19 is formed without expanding the size of the insertion hole of the chip-shaped electronic component 1 when viewed from the stacking direction. .. Therefore, when the plurality of chip-shaped electronic components 1 are treated with the reaction gas by using the jig 10 for the chip-shaped electronic components, the reaction gas is passed through the gaps 19 to allow the plurality of chip-shaped electronic components 1 to pass through the gaps 19. The reaction gas can be supplied to each peripheral portion of the chip-shaped electronic component 1. That is, in the chip-shaped electronic component jig 10 according to the present embodiment, the reaction efficiency of the chip-shaped electronic component 1 can be improved while maintaining the number in which the chip-shaped electronic component 1 can be arranged.

Further, the chip-shaped electronic component jig 10 according to the first embodiment of the present invention has a smaller number of wires than the plurality of linear members constituting the chip-shaped electronic component jig 90 according to the comparative example due to the above configuration. It can be composed of a shape member. As a result, the chip-shaped electronic component jig 10 according to the first embodiment of the present invention can have a smaller heat capacity than the chip-shaped electronic component jig 90 according to the comparative example. Therefore, when a plurality of chip-shaped electronic components 1 are fired using the chip-shaped electronic component jig 10, the chip-shaped electronic component 1 is formed by reducing the heat capacity of the chip-shaped electronic component jig 90. Since heat is easily transferred, the heating load in firing can be reduced.

Further, in the present embodiment, one of the second layer 12 and the third layer 13 is located on the uppermost side of the plurality of layers, and the other of the second layer 12 and the third layer 13 is located. Layer is located directly below one layer.

As a result, the chip-shaped electronic component 1 is inserted by the plurality of second linear members 12L constituting the second layer 12 and the plurality of third linear members 13L constituting the third layer 13 when viewed from the stacking direction. An open end of each of the plurality of tip insertion openings is formed. Therefore, the plurality of chip-shaped electronic components 1 can be easily arranged so as to correspond to each of the plurality of chip insertion ports.

In the present embodiment, when viewed from the stacking direction, each of the plurality of first linear members 11L is the center of the plurality of second linear members 12L adjacent to each other among the plurality of second linear members 12L. Is located in.

As a result, it is possible to stably hold the plurality of chip-shaped electronic components 1 inserted into each of the plurality of chip insertion ports.

The jig 10 for chip-shaped electronic components according to this embodiment includes both the fourth layer 14 and the fifth layer 15.

As a result, the number of the plurality of voids 19 through which the reaction gas can pass can be increased, so that the number of reaction gas supply paths increases, and the peripheral portion of the chip-shaped electronic component 1 inserted into the chip insertion hole is increased. The flow rate of the flowing reaction gas is further increased. As a result, the reaction efficiency of the chip-shaped electronic component 1 can be further improved.

The jig 10 for chip-shaped electronic components according to this embodiment further includes a sixth layer 16. The sixth layer 16 is located below the first layer 11. The sixth layer 16 is composed of a plurality of sixth linear members 16L. Each of the plurality of sixth linear members 16L extends side by side at equal intervals so as to be staggered with the plurality of third linear members 13L when viewed from the stacking direction.

As a result, the first linear member 11L is reinforced, and the first linear member 11L and the sixth linear member 16L intersect at the bottom side of each of the plurality of chip insertion ports, whereby the chip-shaped electronic component is formed. 1 can be held more stably.

In the present embodiment, the plurality of layers are overlapped with each of the plurality of second linear members 12L above the first layer 11 and below the second layer 12 when viewed from the stacking direction. A plurality of linear members extending, and a plurality of linear members extending above the first layer 11 and below the third layer 13 so as to overlap each of the plurality of third linear members 13L. , Has at least one.

As a result, a plurality of gaps 19 in which the linear member is not located can be arranged evenly, so that the reaction gas can flow while suppressing the local decrease in the strength of the jig 10 for the chip-shaped electronic component. The gap portion 19 can be formed.

(Embodiment 2)
Hereinafter, the jig for chip-shaped electronic components according to the second embodiment of the present invention will be described. In the jig for chip-shaped electronic components according to the second embodiment of the present invention, the number of the fourth linear member and the number of the fifth linear member are each different from the jig for the chip-shaped electronic component according to the first embodiment of the present invention. It is different from the tool 10. Therefore, the description of the configuration similar to that of the jig 10 for chip-shaped electronic components according to the first embodiment of the present invention will not be repeated.

FIG. 6 is a front view showing the configuration of a jig for chip-shaped electronic components according to the second embodiment of the present invention. FIG. 7 is a side view showing the configuration of the jig for chip-shaped electronic components according to the second embodiment of the present invention. In FIG. 6, it is shown when viewed from the same direction as in FIG. In FIG. 7, it is shown when viewed from the same direction as in FIG.

As shown in FIG. 6, in the chip-shaped electronic component jig 20 according to the second embodiment of the present invention, the fourth layer 24 is composed of two fourth linear members 24L. As a result, the number of voids 29 through which the reaction gas can pass is larger than that of the jig 10 for the chip-shaped electronic component according to the first embodiment of the present invention, so that the reaction efficiency of the chip-shaped electronic component 1 can be improved. It can be further improved.

Each of the two fourth linear members 24L constituting the fourth layer 24 overlaps the two outermost third linear members 13L in the third layer 13 when viewed from the stacking direction. positioned. As a result, the strength of the chip-shaped electronic component jig 10 can be improved. Further, since the number of the fourth linear member 24L constituting the fourth layer is two, another layer is laminated and held on the upper side of the fourth layer by the minimum required number of the fourth linear member 24L. can do.

The 7th layer 27 is also composed of two 7th linear members 27L, like the 4th layer 24. Each of the two seventh linear members 27L constituting the seventh layer 27 overlaps the two outermost third linear members 13L in the third layer 13 when viewed from the stacking direction. positioned.

As shown in FIG. 7, the fifth layer 25 is composed of two fifth linear members 25L. Each of the two fifth linear members 25L constituting the fifth layer 25 overlaps the two outermost second linear members 12L in the second layer 12 when viewed from the stacking direction. positioned.

(Embodiment 3)
Hereinafter, the jig for chip-shaped electronic components according to the third embodiment of the present invention will be described. In the jig for chip-shaped electronic components according to the third embodiment of the present invention, the number of the first linear member and the number of the sixth linear member are the same for the chip-shaped electronic component according to the first embodiment of the present invention. It is different from the tool 10. Therefore, the description of the configuration similar to that of the jig 10 for chip-shaped electronic components according to the first embodiment of the present invention will not be repeated.

FIG. 8 is a front view showing the configuration of a jig for chip-shaped electronic components according to the third embodiment of the present invention. FIG. 9 is a side view showing the configuration of the jig for chip-shaped electronic components according to the third embodiment of the present invention. In FIG. 8, it is shown when viewed from the same direction as in FIG. In FIG. 9, it is shown when viewed from the same direction as in FIG.

As shown in FIG. 9, in the chip-shaped electronic component jig 30 according to the third embodiment of the present invention, the first layer 11 overlaps with a plurality of second linear members 12L when viewed from the stacking direction. It further includes a plurality of additional linear members 31L extending so as to. As a result, the strength of the chip-shaped electronic component jig 30 can be improved.

Further, as shown in FIG. 8, in the present embodiment, the sixth layer 16 is a plurality of additional linear members extending so as to overlap the plurality of third linear members 13L when viewed from the stacking direction. It further contains 36L. As a result, the strength of the chip-shaped electronic component jig 30 can be improved.

In the description of the above-described embodiment, "the plurality of linear members are lined up at equal intervals" means that the plurality of linear members are lined up at substantially equal intervals. The members may be separated from each other within a certain range, not exactly at equal intervals. For example, the separation distance between the plurality of linear members may be within plus or minus 5% of the value at the time of design.

Further, in the above description of the embodiment, even when a plurality of linear members are lined up at equal intervals in a specific layer, the end portion of the jig for chip-shaped electronic components or the end portion when viewed from the stacking direction The specific layer may partially include a portion where the linear members are not evenly spaced, as long as the number of chip-shaped electronic components is not significantly affected, such as in a part of the center.

Further, in the description of the above-described embodiment, the plurality of layers constituting the jig for chip-shaped electronic components may include linear members having partially different shapes. The jig for chip-shaped electronic components may include a plate-shaped member. The plurality of linear members included in the plurality of layers may be made of materials different from each other.

Further, in the description of the above-described embodiment, each of the plurality of linear members is provided as long as the insertion and holding of the chip-shaped electronic component is not significantly affected and the shape of the jig for the chip-shaped electronic component is maintained. , It may be interrupted in the extension direction.

In the description of the above-described embodiment, the configurations that can be combined may be combined with each other.

The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the claims.

1 Chip-shaped electronic component, 10, 20, 30, 90 Chip-shaped electronic component jig, 11 1st layer, 11L 1st linear member, 12 2nd layer, 12L 2nd linear member, 13 3rd layer, 13L 3rd linear member, 14, 24,94 4th layer, 14L, 24L, 94L 4th linear member, 15, 25, 95 5th layer, 15L, 25L, 95L 5th linear member, 16 6th Layer, 16L 6th linear member, 17, 27, 97 7th layer, 17L, 27L, 97L 7th linear member, 18 intersection, 19, 29 void, 31L, 36L additional linear member.

Claims

A jig for chip-shaped electronic components, which is composed of a plurality of layers in which a plurality of layers formed by extending a plurality of linear members in parallel with each other are laminated.
A first layer containing a plurality of first linear members extending at equal intervals,
A plurality of second linear members located above the first layer and extending side by side at equal intervals so as to be staggered with the first linear member when viewed from the stacking direction of the plurality of layers. The second layer composed of
A second layer located above the first layer and composed of a plurality of third linear members that are arranged at equal intervals and extend in a direction intersecting with the second linear member when viewed from the stacking direction. 3 layers and
Two or more and less than the number of the plurality of third linear members located above the first layer and extending so as to overlap the plurality of third linear members when viewed from the stacking direction. A fourth layer composed of a plurality of fourth linear members, located above the first layer, and extending so as to overlap the plurality of second linear members when viewed from the stacking direction. A jig for chip-shaped electronic components including at least one layer out of a fifth layer composed of a plurality of fifth linear members having two or more and less than the number of the plurality of second linear members. ..
One of the second layer and the third layer is located on the uppermost side of the plurality of layers, and the other layer of the second layer and the third layer is the one layer. The jig for chip-shaped electronic components according to claim 1, which is located directly below.
When viewed from the stacking direction, each of the plurality of first linear members is located at the center of the plurality of second linear members adjacent to each other among the plurality of second linear members. The jig for chip-shaped electronic components according to claim 1 or 2.
The jig for chip-shaped electronic components according to any one of claims 1 to 3, further comprising both the fourth layer and the fifth layer.
Claims 1 to 4, wherein the first layer further includes a plurality of additional linear members extending so as to overlap the plurality of second linear members when viewed from the stacking direction. The jig for chip-shaped electronic parts according to any one of the items.
A plurality of sixth linear members located below the first layer and extending side by side at equal intervals so as to be staggered with the plurality of third linear members when viewed from the stacking direction. The jig for a chip-shaped electronic component according to any one of claims 1 to 5, further comprising a configured sixth layer.
The plurality of layers extend so as to overlap each of the plurality of second linear members above the first layer and below the second layer when viewed from the stacking direction. A linear member and at least one of a plurality of linear members extending above the first layer and below the third layer so as to overlap each of the plurality of third linear members. The jig for chip-shaped electronic components according to claim 2.