WO2021039048A1 - Jig for chip-like electronic component - Google Patents

Jig for chip-like electronic component Download PDF

Info

Publication number
WO2021039048A1
WO2021039048A1 PCT/JP2020/023940 JP2020023940W WO2021039048A1 WO 2021039048 A1 WO2021039048 A1 WO 2021039048A1 JP 2020023940 W JP2020023940 W JP 2020023940W WO 2021039048 A1 WO2021039048 A1 WO 2021039048A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
shaped electronic
jig
electronic component
linear members
Prior art date
Application number
PCT/JP2020/023940
Other languages
French (fr)
Japanese (ja)
Inventor
雄太 田中
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to KR1020227003848A priority Critical patent/KR102587640B1/en
Priority to CN202080058002.XA priority patent/CN114402408A/en
Priority to JP2021542034A priority patent/JP7327489B2/en
Publication of WO2021039048A1 publication Critical patent/WO2021039048A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Definitions

  • the present invention relates to a jig for chip-shaped electronic parts.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2008-177188
  • Patent Document 2 Japanese Patent No. 6259943
  • the jig for chip-shaped electronic components described in Patent Document 1 includes a support member and a receiving member, and is a jig used for processing chip-shaped electronic components.
  • the support member is made of a metal material.
  • the support member is flat as a whole and has a large number of penetrating tip insertion holes in the plane.
  • the receiving member is a net-like body in which a metal meridian and a metal parallel are woven.
  • the receiving member is joined to one surface of the support member, and at least one intersection exists in the opening surface of the chip insertion hole.
  • the jig for chip-shaped electronic components described in Patent Document 2 is a ceramic lattice body, and has a plurality of first streaks and a plurality of second streaks.
  • Each of the plurality of first streaks is made of ceramic and extends in one direction.
  • Each of the plurality of second streaks is made of ceramic and extends in a direction intersecting the first streak.
  • the second line portion is arranged on the first line portion at each intersection.
  • the first linear portion has a shape in which the cross section is composed of a straight portion and a convex curved portion having both ends of the straight portion as ends.
  • the second striation has a circular or elliptical cross section. In the vertical cross-sectional view of the intersection, the first streak and the second streak are the top of the convex curve in the first streak and the circle or ellipse in the second streak. Only the downwardly convex top of the shape is in contact.
  • the jig for chip-shaped electronic components In the conventional jig for chip-shaped electronic components, after the plurality of chip-shaped electronic components are scattered on the jig for chip-shaped electronic components from the opening side of the plurality of chip storage portions, the jig for chip-shaped electronic components is used. Swing. As a result, the chip-shaped electronic component is inserted into each of the plurality of chip accommodating portions. The remaining chip-shaped electronic components on the chip-shaped electronic component jig that cannot fit in the chip storage portion are shaken off by tilting the chip-shaped electronic component jig.
  • the chip-shaped electronic components stored in the chip storage portion may also be shaken off when the surplus chip-shaped electronic components are shaken off. Further, if the depth dimension of the chip storage portion is too large, when two chip-shaped electronic components are inserted side by side in the depth direction, it may not be possible to shake off only the upper chip-shaped electronic component. ..
  • the present invention has been made in view of the above problems, and provides a jig for chip-shaped electronic parts capable of easily inserting one chip-shaped electronic component into one chip storage portion in a plurality of chip storage portions.
  • the purpose is.
  • the jig for chip-shaped electronic parts based on the present invention includes a plurality of chip storage portions for storing chip-shaped electronic parts.
  • Each of the plurality of chip accommodating portions includes a bottom portion and a side wall portion.
  • the bottom supports chip electronic components.
  • the side wall portion is open so that a chip-shaped electronic component can be inserted.
  • the dimension of the diameter D of the inscribed circle of the side wall portion when viewed from the direction orthogonal to the bottom portion and the dimension of the depth Z of each of the plurality of chip storage portions are as follows. The relationship (1) is satisfied.
  • one chip-shaped electronic component can be easily inserted into one chip storage unit in a plurality of chip storage units.
  • FIG. 1 It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 1 of this invention. It is a figure which looked at the jig for chip-shaped electronic parts shown in FIG. 1 from the direction of arrow II. It is a top view which shows the structure of the chip accommodating part in the jig for chip-shaped electronic parts which concerns on Embodiment 1 of this invention. It is sectional drawing which saw the chip accommodating part shown in FIG. 3 from the direction of the arrow of line IV-IV. It is a front view which shows the structure of a part of the jig for a chip-shaped electronic component which concerns on a comparative example.
  • FIG. 6 is a view of the jig for chip-shaped electronic components shown in FIG. 6 as viewed from the direction of arrow VII. It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 3 of this invention.
  • FIG. 1 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the first embodiment of the present invention.
  • FIG. 2 is a view of the jig for chip-shaped electronic components shown in FIG. 1 as viewed from the direction of arrow II.
  • FIG. 3 is a plan view showing a configuration of a chip accommodating portion in the jig for chip-shaped electronic components according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the chip accommodating portion shown in FIG. 3 as viewed from the direction of the arrow along line IV-IV.
  • the jig 100 for a chip-shaped electronic component according to the first embodiment of the present invention is configured by laminating a plurality of linear members 110 on each other.
  • each of the plurality of linear members 110 is linear.
  • the jig 100 for a chip-shaped electronic component has a plurality of linear members 110, a plurality of first linear members 111, and a plurality of second linear members 112. , A plurality of third linear members 113, a plurality of fourth linear members 114, a plurality of fifth linear members 115, a plurality of sixth linear members 116, and a plurality of seventh linear members 117.
  • the plurality of first linear members 111 are arranged on substantially the same plane to form a layer made of linear members.
  • the plurality of second linear members 112 to the plurality of seventh linear members 117 each form a layer composed of the plurality of linear members. Details of the plurality of linear members 110 will be described later.
  • the jig 100 for a chip-shaped electronic component includes a plurality of chip accommodating portions 140 for accommodating the chip-shaped electronic component 10.
  • Each of the plurality of chip accommodating portions 140 includes a bottom portion 120 and a side wall portion 130.
  • the bottom 120 supports the chip-shaped electronic component 10.
  • the side wall portion 130 is open so that the chip-shaped electronic component 10 can be inserted.
  • the bottom portion 120 has a first linear member 111 and a second linear member 112.
  • the bottom portion 120 may have at least a second linear member 112 that directly supports the chip-shaped electronic component 10, and may not have a first linear member 111.
  • the bottom portion 120 may further have an additional layer on the side wall 130 side of the second linear member 112 or on the side opposite to the second linear member 112 side of the first linear member 111.
  • the bottom 120 may have one additional layer or a plurality of additional layers as additional layers.
  • the side wall portion 130 includes two third linear members 113, two fourth linear members 114, two fifth linear members 115, two sixth linear members 116, and two. It has a seventh linear member 117 of a book.
  • the side wall portion 130 has two third linear members 113 and two from the viewpoint of forming an opening of the chip accommodating portion 140 when viewed from a side opposite to the bottom portion 120 side in a direction orthogonal to the bottom portion 120. It suffices to have at least the fourth linear member 114 of the above.
  • the side wall portion 130 does not have to have the fifth linear member 115, the sixth linear member 116, and the seventh linear member 117.
  • the chip-shaped electronic component jig 100 may be entirely composed of a plate-shaped member instead of the plurality of linear members 110.
  • the plurality of holes are formed by forming a plurality of holes from one side of the plate-shaped member. May be a plurality of chip storage units 140.
  • each of the plurality of holes on the bottom surface side constitutes the bottom portion 120
  • each of the plurality of holes on the peripheral side surface side constitutes the side wall portion 130.
  • a plurality of linear members 110 constituting the chip-shaped electronic component jig 100 according to the present embodiment will be described.
  • each of the plurality of first linear members 111 extends side by side at equal intervals in one direction.
  • Each of the plurality of second linear members 112 extends orthogonally to each other at equal intervals while being orthogonal to each of the plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. ..
  • Each of the plurality of second linear members 112 is located above the plurality of first linear members 111.
  • one second linear member 112 directly supports one chip-shaped electronic component 10 housed in one chip accommodating portion 140.
  • one second linear member 112 is located at the center between the sixth linear members 116 adjacent to each other, and one first linear member 111. Is located in the center between the seventh linear members 117 adjacent to each other. That is, at the substantially center of the chip accommodating portion 140, one first linear member 111 and one second linear member 112 are orthogonal to each other.
  • a plurality of second linear members 112 may be located between the sixth linear members 116 adjacent to each other, and the sixth linear members 112 adjacent to each other may be present. It may be located in a place other than the center between the 116s.
  • the plurality of third linear members 113 are located above the plurality of second linear members 112. Each of the plurality of third linear members 113 intersects each of the plurality of second linear members 112 at right angles when viewed from a direction orthogonal to the bottom portion 120, and is arranged at equal intervals from each other. It is postponed. That is, each of the plurality of third linear members 113 extends parallel to the extending direction of the plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. In the present embodiment, each of the plurality of third linear members 113 is positioned so as to overlap each of the plurality of plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. There is.
  • the layer composed of the plurality of second linear members 112 is between the layer composed of the plurality of first linear members 111 and the layer composed of the plurality of third linear members 113. Since it is located at, the position where the second linear member 112 does not exist between the first linear member 111 and the third linear member 113 which overlap each other when viewed from the direction orthogonal to the bottom 120. , A gap is formed.
  • the plurality of fourth linear members 114 are located above the plurality of third linear members 113. Each of the plurality of fourth linear members 114 is arranged at equal intervals from each other while intersecting each of the plurality of third linear members 113 at right angles when viewed from a direction orthogonal to the bottom portion 120. It is postponed. That is, each of the plurality of fourth linear members 114 extends parallel to the extending direction of the plurality of second linear members 112 when viewed from a direction orthogonal to the bottom portion 120. In the present embodiment, each of the plurality of fourth linear members 114 is positioned so as to partially overlap each of the plurality of second linear members 112 when viewed from a direction orthogonal to the bottom portion 120. ..
  • a layer composed of a plurality of third linear members 113 is between a layer composed of a plurality of second linear members 112 and a layer composed of a plurality of fourth linear members 114. Since it is located at, the position where the third linear member 113 does not exist between the second linear member 112 and the fourth linear member 114 which overlap each other when viewed from the direction orthogonal to the bottom 120. , A gap is formed.
  • the plurality of fifth linear members 115 are located above the plurality of fourth linear members 114.
  • the plurality of fifth linear members 115 are positioned so as to correspond one-to-one with the plurality of third linear members 113 when viewed from a direction orthogonal to the bottom portion 120.
  • the plurality of sixth linear members 116 are located above the plurality of fifth linear members 115.
  • the plurality of sixth linear members 116 are positioned so as to correspond one-to-one with the plurality of fourth linear members 114 when viewed from a direction orthogonal to the bottom portion 120.
  • the plurality of seventh linear members 117 are located above the plurality of sixth linear members 116.
  • the plurality of seventh linear members 117 are positioned so as to correspond one-to-one with the plurality of fifth linear members 115 when viewed from a direction orthogonal to the bottom portion 120.
  • the jig 100 for chip-shaped electronic components according to the present embodiment may further include additional linear members on the upper side of the plurality of seventh linear members 117 as the plurality of linear members 110.
  • the additional linear members may be laminated according to the regularity shown in the description of the fifth linear member 115, the sixth linear member 116, and the seventh linear member 117 described above.
  • a plurality of linear linear members 110 are parallel to each other and separated from each other on each surface of the plurality of virtual planes. By arranging them, a plurality of layers composed of a plurality of linear members 110 are formed. These plurality of layers are laminated with each other, and in these plurality of layers, each of the linear members 110 included in a certain layer and each of the linear members 110 included in the layer adjacent to the layer are , Cross each other when viewed from the stacking direction.
  • the length of the separation distance X between the third linear members 113 is equal to the length of the separation distance Y between the fourth linear members 114.
  • each of the length of the separation distance X and the length of the separation distance Y is, for example, 0.1 mm or more and 5.0 mm or less.
  • the separation distance X between the third linear members 113 and the separation distance Y between the fourth linear members 114 may be different from each other.
  • each of the plurality of linear members 110 has a substantially circular outer shape when viewed from the extending direction.
  • Each of these plurality of linear members may have a rectangular, semicircular or non-rectangular polygonal outer shape when viewed from the extending direction.
  • the wire diameter R of each of the plurality of linear members 110 is the same among the plurality of linear members 110 arranged in a direction parallel to the bottom portion 120.
  • the wire diameters R of each of the plurality of linear members 110 may be the same as or different from each other among the linear members 110 that are not aligned in the direction parallel to the bottom portion 120.
  • the wire diameters R of the plurality of linear members 110 are all the same as each other, for example, 0.3 mm.
  • the wire diameter R of the linear member located farthest from the bottom 120 among the plurality of linear members 110 may be, for example, 0.2 mm.
  • the thickness of the bottom portion 120 is, for example, 0.2 mm or more and 2.0 mm or less
  • the height of the side wall portion 130 is, for example, It is 0.1 mm or more and 8.0 mm or less.
  • each of the plurality of linear members 110 is, for example, a ceramic such as SiC, zirconia, ittria-stabilized zirconia, alumina or mulite, a metal such as nickel, aluminum, inconel (registered trademark) or SUS, and polytetra.
  • Consists of resin materials such as fluoroethylene (PTFE: polytetrafluoroethylene), polypropylene (PP: polypropylene), acrylic resin, ABS (Acrylonitrile butadiene styrene) -like resin or other heat-resistant resin, carbon, or a composite material consisting of metal and ceramics. In this embodiment, it is made of ceramics.
  • a plurality of linear members 110 are joined to each other by sintering or the like.
  • the surface of each of the plurality of linear members 110 may be further coated with a ceramic such as SiC, zirconia, yttria, yttria-stabilized zirconia, alumina or mullite, or a metal such as nickel.
  • a ceramic such as SiC, zirconia, yttria, yttria-stabilized zirconia, alumina or mullite, or a metal such as nickel.
  • the open ends of the plurality of chip accommodating portions 140 are two sixth linear members 116 adjacent to each other and two seventh linear members adjacent to each other. It is composed of member 117.
  • the two chip accommodating portions 140 adjacent to each other are separated by one sixth linear member 116 or one seventh linear member 117.
  • one linear member separates two chip accommodating portions 140 adjacent to each other in the layer corresponding to each linear member. ing.
  • the opening shape of each of the plurality of chip storage portions 140 is rectangular. , Specifically, it has a square shape. In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shapes of the plurality of chip storage portions 140 are polygonal. There may be.
  • the inner surface of each opening of the plurality of chip accommodating portions 140 is formed by the plurality of linear members 110. Specifically, two third linear members 113 adjacent to each other, two fourth linear members 114 adjacent to each other, two fifth linear members 115 adjacent to each other, and two second linear members adjacent to each other. It is formed by a 6-linear member 116 and two 7th linear members 117 adjacent to each other.
  • each of the plurality of chip accommodating portions 140 is composed of the second linear member 112. Further, as shown in FIG. 3, when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120, the first linear member 111 and the center of the bottom surface of each of the plurality of chip storage portions 140 The second linear member 112 intersects with each other.
  • the chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment will be described. As shown in FIGS. 1 and 2, the chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment has a substantially rectangular parallelepiped shape.
  • the chip-shaped electronic component 10 can be used, for example, in a multilayer ceramic capacitor.
  • the chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment has a longitudinal direction, a width direction, and a thickness direction.
  • the chip-shaped electronic component 10 is housed in each of the plurality of chip storage portions 140 so that the direction orthogonal to the bottom portion 120 and the longitudinal direction of the chip-shaped electronic component 10 are parallel to each other.
  • the chip-shaped electronic component that can be stored in the chip-shaped electronic component jig 100 according to the present embodiment is not limited to the chip-shaped electronic component 10 having each of the above dimensional relationships.
  • the length L in the longitudinal direction of the chip-shaped electronic component 10 that can be stored in the jig 100 for the chip-shaped electronic component according to the present embodiment is, for example, 0.6 mm or more and 3.8 mm or less
  • the width W in the width direction is For example, it is 0.3 mm or more and 3.0 mm or less
  • the thickness T in the thickness direction is, for example, 0.3 mm or more and 3.0 mm or less.
  • each dimension related to the shape of each opening of the plurality of chip accommodating portions 140 is the length L in the longitudinal direction of the chip-shaped electronic component 10 according to the present embodiment.
  • the diameter D of each inscribed circle 141 of the plurality of chip storage portions 140 when viewed from a direction orthogonal to the bottom portion 120 is a plurality.
  • the chip-shaped electronic component 10 is housed in each of the chip accommodating portions 140, the chip-shaped electronic component 10 is set so as to be rotatable about an axis along the longitudinal direction as a central axis.
  • the diameter D of the inscribed circle 141 is the width direction of the chip-shaped electronic component 10.
  • the diameter D of the inscribed circle 141 is set to be larger than about ⁇ (W 2 + T 2). ..
  • the diameter D of the inscribed circle 141 is set to be less than 2a (D ⁇ 2a).
  • the opening shape of the plurality of chip accommodating portions 140 is a square shape having a side length of D.
  • the height dimension of the side wall portion 130 that is, the dimension of the depth Z of each of the plurality of chip storage portions 140
  • the chip-shaped electronic component 10 that does not fit in the chip-shaped electronic component 140 and remains on the chip-shaped electronic component jig 100 is a chip-shaped electronic component. Tilt the component jig 100 and shake it off. Therefore, the depth Z of each of the plurality of chip accommodating portions 140 can shake off the chip-shaped electronic component 10 stored in the chip accommodating portion 140, and the surplus chip-shaped electronic component 10 can be reliably shaken off. It needs to be set so that it can be dropped.
  • the depth Z of each of the plurality of chip accommodating portions 140 is set to be larger than half of 2a when the dimension of the length L of the chip-shaped electronic component 10 is 2a.
  • Set (a ⁇ Z) By setting in this way, if the center of gravity of the chip-shaped electronic component 10 is located substantially at the center in the longitudinal direction of the chip-shaped electronic component 10, the center of gravity of the chip-shaped electronic component 10 housed in the chip accommodating portion 140 will be. , Located in the chip storage unit 140. As a result, when the chip-shaped electronic component 10 is tilted and shaken off from the chip-shaped electronic component jig 100, the chip-shaped electronic component 10 stored in the chip storage unit 140 falls from the chip storage unit 140. Can be suppressed.
  • the depth Z of each of the plurality of chip accommodating portions 140 is set to be smaller than 3a when the dimension of the length L of the chip-shaped electronic component 10 is 2a. Set (Z ⁇ 3a).
  • the chip-shaped electronic component 10 is scattered on the chip-shaped electronic component jig 100 and inserted into the chip-shaped electronic component 140, the chip-shaped electronic component 10 is placed on the chip-shaped electronic component 10 stored in the chip-shaped electronic component 140. Even if the component 10 is further positioned, only the chip-shaped electronic component 10 on the upper side can be screened off. This is because the height dimension of the center of gravity of the upper chip-shaped electronic component 10 is 3a with respect to the bottom portion 120, and the center of gravity of the upper chip-shaped electronic component 10 is located outside the chip accommodating portion 140.
  • each of the plurality of chip storage portions 140 the size of the diameter D of the inscribed circle of the side wall portion 130 when viewed from the direction orthogonal to the bottom portion 120, and the plurality of chip storage portions 140.
  • the dimension of each depth Z of the above satisfies the relationship of the following equation (1).
  • the depth Z of each of the plurality of chip accommodating portions 140 is set to be smaller than 2a when the dimension of the length L of the chip-shaped electronic component 10 is 2a (Z ⁇ 2a). .. That is, when the chip-shaped electronic component 10 is stored in the chip accommodating portion 140, it is preferable that a part of the chip-shaped electronic component 10 is located outside the chip accommodating portion 140. As a result, when the chip-shaped electronic component 10 stored in the chip accommodating portion 140 is taken out, the plurality of corner portions of the chip-shaped electronic component 10 are caught on the side wall portion 130, and the plurality of corner portions are fixed. This makes it possible to prevent the chip-shaped electronic component 10 from being locked to the side wall portion 130.
  • the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip storage portions 240 are further expressed by the following equation (2). It is preferable that the relationship of
  • the diameter D of the inscribed circle 141 is, for example, 0.1 mm or more and 5.0 mm or less.
  • the depth Z is, for example, 0.1 mm or more and 8.0 mm.
  • the dimension of each wire diameter R of the plurality of linear members 110 is less than 1/2 of the dimension of each depth Z of the plurality of chip accommodating portions 140. Is.
  • the relationship between the dimension of the wire diameter R of each of the plurality of linear members and the dimension of the depth Z of each of the plurality of chip accommodating portions is the relationship between the jig 100 for chip-shaped electronic components according to the present embodiment.
  • a different jig for chip-shaped electronic components according to a comparative example will be described.
  • FIG. 5 is a front view showing a partial configuration of a jig for chip-shaped electronic parts according to a comparative example.
  • the dimension of the wire diameter R of each of the plurality of linear members is the depth Z of each of the plurality of chip accommodating portions 940. It is 1/2 of the size.
  • the bottom portion 120 is composed of a first linear member 911 and a second linear member 912.
  • the side wall portion 130 is composed of two third linear members 913 and two fourth linear members 914.
  • the dimension of the wire diameter R of each of the plurality of linear members is relatively large.
  • the other chip-shaped electronic components 10 are inserted between the chip-shaped electronic components 10 adjacent to each other. , It is possible to be located above the third linear member 913.
  • the wire diameter R of each of the plurality of linear members is relatively small. Suppressing that other chip-shaped electronic components enter between the chip-shaped electronic components 10 adjacent to each other among the plurality of chip-shaped electronic components 10 housed in each of the plurality of chip storage units 140. Can be done.
  • the chip-shaped electronic component jig 100 according to the first embodiment of the present invention is specifically a chip-shaped electronic component firing jig.
  • the chip-shaped electronic component jig 100 containing the plurality of chip-shaped electronic components 10 in a firing atmosphere, the plurality of chip-shaped electronic components 10 can be fired.
  • the jig 100 for chip-shaped electronic components according to the first embodiment of the present invention has a plurality of chips by immersing the jig 100 for chip-shaped electronic components containing a plurality of chip-shaped electronic components 10 in a plating solution.
  • the electronic component 10 can also be plated with a metal such as Cu, Ni, Sn, Ag, Au or Pd.
  • a jig 100 for chip-shaped electronic components containing such a plurality of chip-shaped electronic components 10 is used as a plating solution. By immersing the base electrode, the base electrode can be plated.
  • the jig 100 for chip-shaped electronic components includes a plurality of chip accommodating portions 140 for accommodating chip-shaped electronic components.
  • Each of the plurality of chip accommodating portions 140 includes a bottom portion 120 and a side wall portion 130.
  • the bottom 120 supports a chip-shaped electronic component.
  • the side wall portion 130 is open so that a chip-shaped electronic component can be inserted.
  • the size of the diameter D of the inscribed circle of each side wall portion 130 of the plurality of chip storage portions 140 when viewed from the direction orthogonal to the bottom portion 120, and the plurality of chip storage portions 140 is the dimension of each depth Z of the above satisfies the relationship of the following equation (1).
  • the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip accommodating portions 140 are expressed by the following equations ( It is more preferable that the relationship of 2) is satisfied.
  • the opening shapes of the plurality of chip storage portions 140 are polygonal. is there.
  • the filling rate of the chip-shaped electronic component 10 per the jig 100 for the chip-shaped electronic component can be improved by storing the chip-shaped electronic component 10 in each of the plurality of aligned chip storage portions 140.
  • the jig 100 for chip-shaped electronic components according to the present embodiment is configured by stacking a plurality of linear linear members 110 on each other.
  • gas or liquid can flow through the gap formed between the linear members 110, so that the air permeability of the chip accommodating portion 140 or the passage of liquid can be improved.
  • the dimension of the wire diameter R of each of the plurality of linear members 110 is less than 1/2 of the dimension of the depth Z of each of the plurality of chip accommodating portions 140.
  • the chip-shaped electronic component jig 100 according to this embodiment is made of ceramics. As a result, the heat resistance of the chip-shaped electronic component jig 100 can be improved as compared with the case where the chip-shaped electronic component jig 100 is made of metal.
  • the jig for chip-shaped electronic components according to the second embodiment of the present invention will be described.
  • the opening shape of each of the plurality of chip accommodating portions is mainly different from the jig 100 for the chip-shaped electronic components according to the first embodiment of the present invention. .. Therefore, the description of the configuration similar to that of the chip-shaped electronic component jig 100 according to the first embodiment of the present invention will not be repeated.
  • FIG. 6 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the second embodiment of the present invention.
  • FIG. 7 is a view of the jig for chip-shaped electronic components shown in FIG. 6 as viewed from the direction of arrow VII. In FIG. 6, it is shown when viewed from the same direction as in FIG. In FIG. 6, the plurality of first linear members 111 and the plurality of second linear members 112 are not shown.
  • the jig 200 for chip-shaped electronic components according to the second embodiment of the present invention is composed of a plurality of linear members 210.
  • the bottom portion 120 has a plurality of first linear members 111 and a plurality of second linear members 112.
  • the side wall portion 130 has a plurality of annular eighth linear members 218 and a plurality of annular ninth linear members 219.
  • each of the plurality of annular eighth linear members 218 is positioned so as to form an end portion of the side wall portion 130 opposite to the bottom portion 120 side. As shown in FIG. 6, each of the plurality of annular eighth linear members 218 overlaps with the adjacent eighth linear member 218. Each of the plurality of annular eighth linear members 218 is positioned so that the inner portions of the annulus do not overlap each other when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120. There is.
  • each of the plurality of annular ninth linear members 219 is positioned so as to overlap each of the plurality of annular eighth linear members 218 when viewed from a direction orthogonal to the bottom 120. doing.
  • Each of the plurality of annular ninth linear members 219 overlaps with the adjacent ninth linear member 219.
  • Each of the plurality of annular ninth linear members 219 is located on the side opposite to the first linear member 111 side of the plurality of second linear members 112, and is located at the bottom of the plurality of eighth linear members 218. It is located on the 120 side.
  • the dimension of the depth Z of each of the plurality of chip accommodating portions 240 is from the end portion of the second linear member 112 on the eighth linear member 218 side in the direction orthogonal to the bottom portion 120. , The dimension of the distance to the end of the eighth linear member 218 opposite to the second linear member 112 side.
  • the openings of the plurality of chip accommodating portions 240 are the inner portions of each of the plurality of eighth linear members 218 and the plurality of openings. It is composed of each inner portion of the ninth linear member 219.
  • a plurality of jigs 200 when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120.
  • the inner portion of each of the eighth linear member 218 and each of the plurality of ninth linear members 219 is circular. That is, when the plurality of chip storage portions 240 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 240 is circular.
  • the plurality of chip storage portions 240 can be densely arranged when viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120. As a result, the filling rate of the chip-shaped electronic component 10 per the chip-shaped electronic component jig 200 can be improved.
  • one chip-shaped electronic component 10 can be easily inserted into one chip storage unit 240 in the plurality of chip storage units 240. it can.
  • the inscribed circles 241 of the plurality of chip accommodating portions 240 when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120 are the bottom 120 in the direction orthogonal to the bottom 120. It is composed of an inner side surface portion of each of the plurality of eighth linear members 218 or each inner side surface portion of the ninth linear member 219 when viewed from the side opposite to the side.
  • the jig for chip-shaped electronic components according to the third embodiment of the present invention will be described.
  • the feature related to the opening size of each of the plurality of chip storage portions is mainly the jig for the chip-shaped electronic parts according to the first embodiment of the present invention. Different from 100. Therefore, the description of the configuration similar to that of the chip-shaped electronic component jig 100 according to the first embodiment of the present invention will not be repeated.
  • FIG. 8 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the third embodiment of the present invention.
  • each of the plurality of chip accommodating portions 340 is oriented from the bottom 120 side to the bottom in a direction orthogonal to the bottom 120.
  • the opening size increases toward the side opposite to the 120 side.
  • the chip-shaped electronic component 10 can be easily slid into each of the plurality of chip accommodating portions 340.
  • one chip-shaped electronic component 10 can be easily inserted into one chip storage unit 340 in the plurality of chip storage units 340. it can.
  • the opening dimension is the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom 120.
  • the wire diameters of the plurality of linear members 310 are different from each other for some of the plurality of linear members 310.
  • the wire diameters of the plurality of linear members 310 are the 7th linear member 317, the 6th linear member 316, the 5th linear member 315, the 4th linear member 314, and the 3rd linear member 313. It is increasing in the order of.
  • the dimension of the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom 120 is the seventh linear member.
  • the size decreases in the order of 317, the sixth linear member 316, the fifth linear member 315, the fourth linear member 314, and the third linear member 313.
  • the diameter D of the inscribed circle 141 is set so that the above equation (1) is always satisfied at any position in the direction orthogonal to the bottom portion 120.
  • the jig for chip-shaped electronic components according to each embodiment of the present invention may include a chip accommodating portion that does not satisfy the above formula (1).
  • the chip accommodating portion that does not satisfy the above formula (1) the flow of gas flowing between the linear members can be controlled.
  • the linear members forming the side wall portion may be densely arranged. As a result, the strength of the jig for chip-shaped electronic parts can be increased.
  • the jig for a chip-shaped electronic component according to each embodiment of the present invention may have a mere gap having a size in which the chip-shaped electronic component cannot be inserted.
  • a jig for a chip-shaped electronic component may be formed by combining a bottom portion made of a plate-shaped member and a side wall portion made of a plurality of linear members. That is, the shape of the bottom and the relative position of the bottom with respect to the linear member are not particularly limited as long as the bottom can prevent the chip-shaped electronic component in the chip storage portion from falling off.
  • the linear member constitutes the bottom, the extending direction in each plane of the plurality of first linear members and the plurality of second linear members is not particularly limited.
  • the plurality of linear members may be configured such that a plurality of first linear members or a plurality of second linear members form a bottom portion per chip accommodating portion.
  • the cross-sectional shape of the linear member may be polygonal.
  • the jig for a chip-shaped electronic component may have side wall portions that are open on both sides of the bottom portion so that the chip-shaped electronic component can be inserted.
  • Chip-shaped electronic components 100, 200, 300, 900 Chip-shaped electronic component jigs, 110, 210, 310 Linear members, 111,911 1st linear member, 112,912 2nd linear member, 113, 313,913 3rd linear member, 114,314,914 4th linear member, 115,315 5th linear member, 116,316 6th linear member 117,317 7th linear member, 120 bottom, 130 side wall, 140, 240, 340, 940 chip storage, 141,241 inscribed circles, 218 8th linear member, 219 9th linear member.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Packaging Frangible Articles (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

A jig (100) for a chip-like electronic component is provided with a plurality of chip storage parts (140) that store chip-like electronic components. Each of the chip storage parts (140) includes a bottom section (120) and a side wall section (130). The bottom section (120) supports a corresponding one of the chip-like electronic components. The side wall section (130) is opened so as to enable insertion of a chip-like electronic component. In each of the chip storage parts (140) , the relationship between the size of the diameter D of an inscribed circle of the side wall section (130) and the size of the depth Z of each of the chip storage parts (140) seen from a direction orthogonal to the bottom section (120) satisfy formula (1).　(1): (D/2) < Z < (3√2/2)D

Description

チップ状電子部品用治具Jig for chip-shaped electronic parts
　本発明は、チップ状電子部品用治具に関する。 The present invention relates to a jig for chip-shaped electronic parts.
　チップ状電子部品用治具を開示した先行文献として、特開２００８－１７７１８８号公報(特許文献１)および特許第６２５９９４３号(特許文献２)がある。 Prior documents disclosing jigs for chip-shaped electronic components include Japanese Patent Application Laid-Open No. 2008-177188 (Patent Document 1) and Japanese Patent No. 6259943 (Patent Document 2).
　特許文献１に記載のチップ状電子部品用治具は、支持部材と、受け部材とを含み、チップ状電子部品の処理に用いられる治具である。支持部材は、金属材料からなる。支持部材は、全体として平面状であって、その面内に多数の貫通するチップ挿入孔を有している。受け部材は、金属経線と金属緯線とを織り込んだ網状体である。受け部材は、支持部材の一面に接合され、チップ挿入孔の開口面内に、少なくとも１つの交差部が存在している。 The jig for chip-shaped electronic components described in Patent Document 1 includes a support member and a receiving member, and is a jig used for processing chip-shaped electronic components. The support member is made of a metal material. The support member is flat as a whole and has a large number of penetrating tip insertion holes in the plane. The receiving member is a net-like body in which a metal meridian and a metal parallel are woven. The receiving member is joined to one surface of the support member, and at least one intersection exists in the opening surface of the chip insertion hole.
　特許文献２に記載のチップ状電子部品用治具は、セラミックス格子体であり、複数の第１の線条部と、複数の第２の線条部とを有している。複数の第１の線条部の各々は、セラミックス製であり、一方向に向けて延びている。複数の第２の線条部の各々は、セラミックス製であり、第１の線条部と交差する方向に向けて延びている。第１の線条部と第２の線条部との交差部は、いずれの交差部においても、第１の線条部上に第２の線条部が配されている。交差部において、第１の線条部は、その断面が、直線部と、直線部の両端部を端部とする凸形の曲線部とから構成される形状を有している。交差部において、第２の線条部は、その断面が、円形又は楕円形の形状を有している。交差部の縦断面視において、第１の線条部と第２の線条部とは、第１の線条部における凸形の曲線部の頂部と、第２の線条部における円形または楕円形における下向きに凸の頂部のみが接触している。 The jig for chip-shaped electronic components described in Patent Document 2 is a ceramic lattice body, and has a plurality of first streaks and a plurality of second streaks. Each of the plurality of first streaks is made of ceramic and extends in one direction. Each of the plurality of second streaks is made of ceramic and extends in a direction intersecting the first streak. At the intersection of the first line portion and the second line portion, the second line portion is arranged on the first line portion at each intersection. At the intersection, the first linear portion has a shape in which the cross section is composed of a straight portion and a convex curved portion having both ends of the straight portion as ends. At the intersection, the second striation has a circular or elliptical cross section. In the vertical cross-sectional view of the intersection, the first streak and the second streak are the top of the convex curve in the first streak and the circle or ellipse in the second streak. Only the downwardly convex top of the shape is in contact.
特開２００８－１７７１８８号公報Japanese Unexamined Patent Publication No. 2008-177188 特許第６２５９９４３号公報Japanese Patent No. 6259943
　従来のチップ状電子部品用治具においては、複数のチップ収納部の開口側から、チップ状電子部品用治具上に複数のチップ状電子部品をばらまいた後、チップ状電子部品用治具を揺動させる。これにより、複数のチップ収納部の各々に、チップ状電子部品が挿入される。チップ収納部に入りきらず、チップ状電子部品用治具上の余ったチップ状電子部品は、チップ状電子部品用治具を傾けて振るい落とす。 In the conventional jig for chip-shaped electronic components, after the plurality of chip-shaped electronic components are scattered on the jig for chip-shaped electronic components from the opening side of the plurality of chip storage portions, the jig for chip-shaped electronic components is used. Swing. As a result, the chip-shaped electronic component is inserted into each of the plurality of chip accommodating portions. The remaining chip-shaped electronic components on the chip-shaped electronic component jig that cannot fit in the chip storage portion are shaken off by tilting the chip-shaped electronic component jig.
　このため、複数のチップ収納部において、１つのチップ収納部に１つのチップ状電子部品を挿入するためには、チップ収納部の深さの寸法および開口面積を適切に設定する必要がある。たとえば、チップ状電子部品の開口面積が小さすぎると、チップ収納部にチップ状電子部品を挿入するのに時間がかかる。また、チップ状電子部品の開口面積が大きすぎると、１つのチップ収納部に２つのチップ状電子部品が入る。これにより、チップ状電子部品用治具を用いたチップ状電子部品の焼成においては、焼成ムラが発生するおそれがある。また、チップ収納部の深さの寸法が小さすぎると、余ったチップ状電子部品を振るい落とす際に、チップ収納部に収納されたチップ状電子部品も振るい落とされるおそれがある。さらに、チップ収納部の深さの寸法が大き過ぎると、深さ方向に２つのチップ状電子部品が並んで挿入されたときに、上側のチップ状電子部品のみを振るい落とすことができないおそれがある。 Therefore, in order to insert one chip-shaped electronic component into one chip storage unit in a plurality of chip storage units, it is necessary to appropriately set the depth dimension and the opening area of the chip storage unit. For example, if the opening area of the chip-shaped electronic component is too small, it takes time to insert the chip-shaped electronic component into the chip storage portion. Further, if the opening area of the chip-shaped electronic component is too large, two chip-shaped electronic components are accommodated in one chip storage portion. As a result, in firing of chip-shaped electronic components using a jig for chip-shaped electronic components, firing unevenness may occur. Further, if the depth dimension of the chip storage portion is too small, the chip-shaped electronic components stored in the chip storage portion may also be shaken off when the surplus chip-shaped electronic components are shaken off. Further, if the depth dimension of the chip storage portion is too large, when two chip-shaped electronic components are inserted side by side in the depth direction, it may not be possible to shake off only the upper chip-shaped electronic component. ..
　本発明は上記の課題に鑑みてなされたものであり、複数のチップ収納部において、１つのチップ収納部に１つのチップ状電子部品を容易に挿入できる、チップ状電子部品用治具を提供することを目的とする。 The present invention has been made in view of the above problems, and provides a jig for chip-shaped electronic parts capable of easily inserting one chip-shaped electronic component into one chip storage portion in a plurality of chip storage portions. The purpose is.
　本発明に基づくチップ状電子部品用治具は、チップ状電子部品を収納する複数のチップ収納部を備えている。複数のチップ収納部の各々は、底部と、側壁部とを含んでいる。底部は、チップ状電子部品を支持する。側壁部は、チップ状電子部品を挿入可能に開口している。複数のチップ収納部の各々において、底部と直交する方向から見たときの側壁部の内接円の直径Ｄの寸法と、複数のチップ収納部の各々の深さＺの寸法とが、下記式(１)の関係を満たしている。 The jig for chip-shaped electronic parts based on the present invention includes a plurality of chip storage portions for storing chip-shaped electronic parts. Each of the plurality of chip accommodating portions includes a bottom portion and a side wall portion. The bottom supports chip electronic components. The side wall portion is open so that a chip-shaped electronic component can be inserted. In each of the plurality of chip storage portions, the dimension of the diameter D of the inscribed circle of the side wall portion when viewed from the direction orthogonal to the bottom portion and the dimension of the depth Z of each of the plurality of chip storage portions are as follows. The relationship (1) is satisfied.
　(Ｄ／２）＜Ｚ＜（３√２／２）Ｄ　・・・（１） (D / 2) <Z <(3√2 / 2) D ... (1)
　本発明によれば、複数のチップ収納部において、１つのチップ収納部に１つのチップ状電子部品を容易に挿入することができる。 According to the present invention, one chip-shaped electronic component can be easily inserted into one chip storage unit in a plurality of chip storage units.
本発明の実施形態１に係るチップ状電子部品用治具の構成を示す平面図である。It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 1 of this invention. 図１に示すチップ状電子部品用治具を矢印ＩＩ方向から見た図である。It is a figure which looked at the jig for chip-shaped electronic parts shown in FIG. 1 from the direction of arrow II. 本発明の実施形態１に係るチップ状電子部品用治具におけるチップ収納部の構成を示す平面図である。It is a top view which shows the structure of the chip accommodating part in the jig for chip-shaped electronic parts which concerns on Embodiment 1 of this invention. 図３に示すチップ収納部をＩＶ－ＩＶ線矢印方向から見た断面図である。It is sectional drawing which saw the chip accommodating part shown in FIG. 3 from the direction of the arrow of line IV-IV. 比較例に係るチップ状電子部品用治具の一部の構成を示す正面図である。It is a front view which shows the structure of a part of the jig for a chip-shaped electronic component which concerns on a comparative example. 本発明の実施形態２に係るチップ状電子部品用治具の構成を示す平面図である。It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 2 of this invention. 図６に示すチップ状電子部品用治具を矢印ＶＩＩ方向から見た図である。6 is a view of the jig for chip-shaped electronic components shown in FIG. 6 as viewed from the direction of arrow VII. 本発明の実施形態３に係るチップ状電子部品用治具の構成を示す平面図である。It is a top view which shows the structure of the jig for chip-shaped electronic parts which concerns on Embodiment 3 of this invention.
　以下、本発明の各実施形態に係るチップ状電子部品用治具について説明する。以下の実施形態の説明においては、図中の同一または相当部分には同一符号を付して、その説明は繰り返さない。 Hereinafter, jigs for chip-shaped electronic components according to each embodiment of the present invention will be described. In the following description of the embodiment, the same or corresponding parts in the drawings are designated by the same reference numerals, and the description will not be repeated.
　(実施形態１)
　図１は、本発明の実施形態１に係るチップ状電子部品用治具の構成を示す平面図である。図２は、図１に示すチップ状電子部品用治具を矢印ＩＩ方向から見た図である。図３は、本発明の実施形態１に係るチップ状電子部品用治具におけるチップ収納部の構成を示す平面図である。図４は、図３に示すチップ収納部をＩＶ－ＩＶ線矢印方向から見た断面図である。 (Embodiment 1)
FIG. 1 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the first embodiment of the present invention. FIG. 2 is a view of the jig for chip-shaped electronic components shown in FIG. 1 as viewed from the direction of arrow II. FIG. 3 is a plan view showing a configuration of a chip accommodating portion in the jig for chip-shaped electronic components according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view of the chip accommodating portion shown in FIG. 3 as viewed from the direction of the arrow along line IV-IV.
　図１および図２に示すように、本発明の実施形態１に係るチップ状電子部品用治具１００は、複数の線状部材１１０が互いに積層されることで構成されている。本実施形態において、複数の線状部材１１０の各々は直線状である。 As shown in FIGS. 1 and 2, the jig 100 for a chip-shaped electronic component according to the first embodiment of the present invention is configured by laminating a plurality of linear members 110 on each other. In the present embodiment, each of the plurality of linear members 110 is linear.
　図１および図２に示すように、本実施形態に係るチップ状電子部品用治具１００は、複数の線状部材１１０として、複数の第１線状部材１１１、複数の第２線状部材１１２、複数の第３線状部材１１３、複数の第４線状部材１１４、複数の第５線状部材１１５、複数の第６線状部材１１６および複数の第７線状部材１１７を備えている。複数の第１線状部材１１１は、略同一平面上に配置されることで、線状部材からなる層を構成している。複数の第１線状部材１１１と同様に、複数の第２線状部材１１２から複数の第７線状部材１１７も、それぞれ、複数の線状部材からなる層を構成している。複数の線状部材１１０の詳細については後述する。 As shown in FIGS. 1 and 2, the jig 100 for a chip-shaped electronic component according to the present embodiment has a plurality of linear members 110, a plurality of first linear members 111, and a plurality of second linear members 112. , A plurality of third linear members 113, a plurality of fourth linear members 114, a plurality of fifth linear members 115, a plurality of sixth linear members 116, and a plurality of seventh linear members 117. The plurality of first linear members 111 are arranged on substantially the same plane to form a layer made of linear members. Like the plurality of first linear members 111, the plurality of second linear members 112 to the plurality of seventh linear members 117 each form a layer composed of the plurality of linear members. Details of the plurality of linear members 110 will be described later.
　本発明の実施形態１に係るチップ状電子部品用治具１００は、チップ状電子部品１０を収納する複数のチップ収納部１４０を備えている。複数のチップ収納部１４０の各々は、底部１２０と、側壁部１３０とを含んでいる。底部１２０は、チップ状電子部品１０を支持する。側壁部１３０は、チップ状電子部品１０を挿入可能に開口している。 The jig 100 for a chip-shaped electronic component according to the first embodiment of the present invention includes a plurality of chip accommodating portions 140 for accommodating the chip-shaped electronic component 10. Each of the plurality of chip accommodating portions 140 includes a bottom portion 120 and a side wall portion 130. The bottom 120 supports the chip-shaped electronic component 10. The side wall portion 130 is open so that the chip-shaped electronic component 10 can be inserted.
　図２に示すように、複数のチップ収納部１４０の各々において、底部１２０は、第１線状部材１１１と、第２線状部材１１２とを有している。底部１２０は、チップ状電子部品１０を直接支持する第２線状部材１１２を少なくとも有していればよく、第１線状部材１１１を有していなくてもよい。底部１２０は、第２線状部材１１２の側壁部１３０側、または、第１線状部材１１１の第２線状部材１１２側とは反対側に、追加の層をさらに有していてもよい。底部１２０は、追加の層として、１層の追加の層または複数の追加の層を有していてもよい。側壁部１３０は、２本の第３線状部材１１３と、２本の第４線状部材１１４と、２本の第５線状部材１１５と、２本の第６線状部材１１６と、２本の第７線状部材１１７とを有している。側壁部１３０は、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、チップ収納部１４０の開口を形成するという観点から、２本の第３線状部材１１３および２本の第４線状部材１１４を少なくとも有していればよい。側壁部１３０は、第５線状部材１１５、第６線状部材１１６および第７線状部材１１７を有していなくてもよい。 As shown in FIG. 2, in each of the plurality of chip accommodating portions 140, the bottom portion 120 has a first linear member 111 and a second linear member 112. The bottom portion 120 may have at least a second linear member 112 that directly supports the chip-shaped electronic component 10, and may not have a first linear member 111. The bottom portion 120 may further have an additional layer on the side wall 130 side of the second linear member 112 or on the side opposite to the second linear member 112 side of the first linear member 111. The bottom 120 may have one additional layer or a plurality of additional layers as additional layers. The side wall portion 130 includes two third linear members 113, two fourth linear members 114, two fifth linear members 115, two sixth linear members 116, and two. It has a seventh linear member 117 of a book. The side wall portion 130 has two third linear members 113 and two from the viewpoint of forming an opening of the chip accommodating portion 140 when viewed from a side opposite to the bottom portion 120 side in a direction orthogonal to the bottom portion 120. It suffices to have at least the fourth linear member 114 of the above. The side wall portion 130 does not have to have the fifth linear member 115, the sixth linear member 116, and the seventh linear member 117.
　なお、チップ状電子部品用治具１００は、複数の線状部材１１０に代えて、全体が板状部材で構成されていてもよい。チップ状電子部品用治具１００の全体が板状部材で構成される場合には、上記板状部材に対して、一方側の面から複数の孔部を形成することにより、当該複数の孔部を複数のチップ収納部１４０としてもよい。この場合、当該板状部材において、複数の孔部の各々の底面側の部分が底部１２０を構成し、複数の孔部の各々の周側面側の部分が側壁部１３０を構成する。 The chip-shaped electronic component jig 100 may be entirely composed of a plate-shaped member instead of the plurality of linear members 110. When the entire jig 100 for chip-shaped electronic components is composed of a plate-shaped member, the plurality of holes are formed by forming a plurality of holes from one side of the plate-shaped member. May be a plurality of chip storage units 140. In this case, in the plate-shaped member, each of the plurality of holes on the bottom surface side constitutes the bottom portion 120, and each of the plurality of holes on the peripheral side surface side constitutes the side wall portion 130.
　本実施形態に係るチップ状電子部品用治具１００を構成する複数の線状部材１１０について説明する。 A plurality of linear members 110 constituting the chip-shaped electronic component jig 100 according to the present embodiment will be described.
　図１および図２に示すように、複数の第１線状部材１１１の各々は、互いに等間隔に１方向に並んで延在している。複数の第２線状部材１１２の各々は、底部１２０に直交する方向から見たときに、複数の第１線状部材１１１の各々と直交しつつ、互いに等間隔に並んで延在している。複数の第２線状部材１１２の各々は、複数の第１線状部材１１１の上側に位置している。 As shown in FIGS. 1 and 2, each of the plurality of first linear members 111 extends side by side at equal intervals in one direction. Each of the plurality of second linear members 112 extends orthogonally to each other at equal intervals while being orthogonal to each of the plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. .. Each of the plurality of second linear members 112 is located above the plurality of first linear members 111.
　本実施形態においては、１本の第２線状部材１１２が、１つのチップ収納部１４０に収容された１つのチップ状電子部品１０を直接支持する。底部１２０に直交する方向から見たときに、１本の第２線状部材１１２が、互いに隣り合う第６線状部材１１６同士の間の中央に位置し、１本の第１線状部材１１１が、互いに隣り合う第７線状部材１１７同士の間の中央に位置する。つまり、チップ収納部１４０の略中央において、１本の第１線状部材１１１と１本の第２線状部材１１２とが互いに直交している。なお、底部１２０に直交する方向から見たときに、第２線状部材１１２は、互いに隣り合う第６線状部材１１６同士の間に複数本あってもよく、互いに隣り合う第６線状部材１１６同士の間の中央ではない場所に位置してもよい。 In the present embodiment, one second linear member 112 directly supports one chip-shaped electronic component 10 housed in one chip accommodating portion 140. When viewed from a direction orthogonal to the bottom portion 120, one second linear member 112 is located at the center between the sixth linear members 116 adjacent to each other, and one first linear member 111. Is located in the center between the seventh linear members 117 adjacent to each other. That is, at the substantially center of the chip accommodating portion 140, one first linear member 111 and one second linear member 112 are orthogonal to each other. When viewed from a direction orthogonal to the bottom portion 120, a plurality of second linear members 112 may be located between the sixth linear members 116 adjacent to each other, and the sixth linear members 112 adjacent to each other may be present. It may be located in a place other than the center between the 116s.
　複数の第３線状部材１１３は、複数の第２線状部材１１２の上側に位置している。複数の第３線状部材１１３の各々は、底部１２０に直交する方向から見たときに、複数の第２線状部材１１２の各々と直角に交差しつつ、互いに等間隔に離間して並んで延在している。すなわち、複数の第３線状部材１１３の各々は、底部１２０に直交する方向から見たときに、複数の第１線状部材１１１の延在方向と平行に延在している。本実施形態においては、底部１２０に直交する方向から見たときに、複数の第３線状部材１１３の各々は、一部の複数の第１線状部材１１１の各々と重なるように位置している。底部１２０に平行な方向から見ると、複数の第２線状部材１１２からなる層が、複数の第１線状部材１１１からなる層と、複数の第３線状部材１１３からなる層との間に位置しているため、底部１２０に直交する方向から見たときに互いに重なり合う第１線状部材１１１と第３線状部材１１３との間において、第２線状部材１１２が存在しない位置には、隙間が形成されている。 The plurality of third linear members 113 are located above the plurality of second linear members 112. Each of the plurality of third linear members 113 intersects each of the plurality of second linear members 112 at right angles when viewed from a direction orthogonal to the bottom portion 120, and is arranged at equal intervals from each other. It is postponed. That is, each of the plurality of third linear members 113 extends parallel to the extending direction of the plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. In the present embodiment, each of the plurality of third linear members 113 is positioned so as to overlap each of the plurality of plurality of first linear members 111 when viewed from a direction orthogonal to the bottom portion 120. There is. Seen from a direction parallel to the bottom 120, the layer composed of the plurality of second linear members 112 is between the layer composed of the plurality of first linear members 111 and the layer composed of the plurality of third linear members 113. Since it is located at, the position where the second linear member 112 does not exist between the first linear member 111 and the third linear member 113 which overlap each other when viewed from the direction orthogonal to the bottom 120. , A gap is formed.
　複数の第４線状部材１１４は、複数の第３線状部材１１３の上側に位置している。複数の第４線状部材１１４の各々は、底部１２０に直交する方向から見たときに、複数の第３線状部材１１３の各々と直角に交差しつつ、互いに等間隔に離間して並んで延在している。すなわち、複数の第４線状部材１１４の各々は、底部１２０に直交する方向から見たときに、複数の第２線状部材１１２の延在方向と平行に延在している。本実施形態においては、底部１２０に直交する方向から見たときに、複数の第４線状部材１１４の各々は、一部複数の第２線状部材１１２の各々と重なるように位置している。底部１２０に平行な方向から見ると、複数の第３線状部材１１３からなる層が、複数の第２線状部材１１２からなる層と、複数の第４線状部材１１４からなる層との間に位置しているため、底部１２０に直交する方向から見たときに互いに重なり合う第２線状部材１１２と第４線状部材１１４との間において、第３線状部材１１３が存在しない位置には、隙間が形成されている。 The plurality of fourth linear members 114 are located above the plurality of third linear members 113. Each of the plurality of fourth linear members 114 is arranged at equal intervals from each other while intersecting each of the plurality of third linear members 113 at right angles when viewed from a direction orthogonal to the bottom portion 120. It is postponed. That is, each of the plurality of fourth linear members 114 extends parallel to the extending direction of the plurality of second linear members 112 when viewed from a direction orthogonal to the bottom portion 120. In the present embodiment, each of the plurality of fourth linear members 114 is positioned so as to partially overlap each of the plurality of second linear members 112 when viewed from a direction orthogonal to the bottom portion 120. .. When viewed from a direction parallel to the bottom portion 120, a layer composed of a plurality of third linear members 113 is between a layer composed of a plurality of second linear members 112 and a layer composed of a plurality of fourth linear members 114. Since it is located at, the position where the third linear member 113 does not exist between the second linear member 112 and the fourth linear member 114 which overlap each other when viewed from the direction orthogonal to the bottom 120. , A gap is formed.
　複数の第５線状部材１１５は、複数の第４線状部材１１４の上側に位置している。複数の第５線状部材１１５は、底部１２０に直交する方向から見たときに、複数の第３線状部材１１３と１対１で対応して重なるように位置している。複数の第６線状部材１１６は、複数の第５線状部材１１５の上側に位置している。複数の第６線状部材１１６は、底部１２０に直交する方向から見たときに、複数の第４線状部材１１４と１対１で対応して重なるように位置している。複数の第７線状部材１１７は、複数の第６線状部材１１６の上側に位置している。複数の第７線状部材１１７は、底部１２０に直交する方向から見たときに、複数の第５線状部材１１５と１対１で対応して重なるように位置している。 The plurality of fifth linear members 115 are located above the plurality of fourth linear members 114. The plurality of fifth linear members 115 are positioned so as to correspond one-to-one with the plurality of third linear members 113 when viewed from a direction orthogonal to the bottom portion 120. The plurality of sixth linear members 116 are located above the plurality of fifth linear members 115. The plurality of sixth linear members 116 are positioned so as to correspond one-to-one with the plurality of fourth linear members 114 when viewed from a direction orthogonal to the bottom portion 120. The plurality of seventh linear members 117 are located above the plurality of sixth linear members 116. The plurality of seventh linear members 117 are positioned so as to correspond one-to-one with the plurality of fifth linear members 115 when viewed from a direction orthogonal to the bottom portion 120.
　本実施形態に係るチップ状電子部品用治具１００は、複数の線状部材１１０として、複数の第７線状部材１１７の上側にさらに追加の線状部材を備えていてもよい。このとき、追加の線状部材は、上述した第５線状部材１１５、第６線状部材１１６および第７線状部材１１７の説明で示した規則性に従って積層すればよい。 The jig 100 for chip-shaped electronic components according to the present embodiment may further include additional linear members on the upper side of the plurality of seventh linear members 117 as the plurality of linear members 110. At this time, the additional linear members may be laminated according to the regularity shown in the description of the fifth linear member 115, the sixth linear member 116, and the seventh linear member 117 described above.
　このように、本実施形態に係るチップ状電子部品用治具１００においては、複数の仮想平面のそれぞれの面上に、直線状の複数の線状部材１１０が互いに平行に、かつ、離間して配置されることで、複数の線状部材１１０からなる層が複数形成されている。これらの複数の層は互いに積層されており、これらの複数の層においては、ある層に含まれる線状部材１１０の各々と、当該層に隣接する層に含まれる線状部材１１０の各々とが、積層方向から見て互いに交差する。 As described above, in the jig 100 for chip-shaped electronic components according to the present embodiment, a plurality of linear linear members 110 are parallel to each other and separated from each other on each surface of the plurality of virtual planes. By arranging them, a plurality of layers composed of a plurality of linear members 110 are formed. These plurality of layers are laminated with each other, and in these plurality of layers, each of the linear members 110 included in a certain layer and each of the linear members 110 included in the layer adjacent to the layer are , Cross each other when viewed from the stacking direction.
　図３に示すように、本実施形態において、第３線状部材１１３同士の離間距離Ｘの長さは、第４線状部材１１４同士の離間距離Ｙの長さと等しい。本実施形態において、上記離間距離Ｘの長さおよび上記離間距離Ｙの長さの各々は、たとえば０．１ｍｍ以上５．０ｍｍ以下である。なお、第３線状部材１１３同士の離間距離Ｘと、第４線状部材１１４同士の離間距離Ｙとは、互いに異なっていてもよい。 As shown in FIG. 3, in the present embodiment, the length of the separation distance X between the third linear members 113 is equal to the length of the separation distance Y between the fourth linear members 114. In the present embodiment, each of the length of the separation distance X and the length of the separation distance Y is, for example, 0.1 mm or more and 5.0 mm or less. The separation distance X between the third linear members 113 and the separation distance Y between the fourth linear members 114 may be different from each other.
　図２に示すように、本実施形態において、複数の線状部材１１０の各々は、延在方向から見たときに略円形状の外形を有している。これらの複数の線状部材の各々は、延在方向から見たときに、矩形状、半円状または矩形状以外の多角形状の外形を有していてもよい。図４に示すように、複数の線状部材１１０の各々の線径Ｒは、底部１２０と平行な方向に並んでいる複数の線状部材１１０同士においては、互いに同一となっている。複数の線状部材１１０の各々の線径Ｒは、底部１２０と平行な方向に並んでいない線状部材１１０同士においては、互いに同一となっていてもよいし、互いに異なっていてもよい。本実施形態において、複数の線状部材１１０の各々の線径Ｒは、互いに全て同一であり、たとえば０．３ｍｍである。複数の線状部材１１０のうち底部１２０から最も離れて位置する線状部材の線径Ｒは、たとえば０．２ｍｍであってもよい。 As shown in FIG. 2, in the present embodiment, each of the plurality of linear members 110 has a substantially circular outer shape when viewed from the extending direction. Each of these plurality of linear members may have a rectangular, semicircular or non-rectangular polygonal outer shape when viewed from the extending direction. As shown in FIG. 4, the wire diameter R of each of the plurality of linear members 110 is the same among the plurality of linear members 110 arranged in a direction parallel to the bottom portion 120. The wire diameters R of each of the plurality of linear members 110 may be the same as or different from each other among the linear members 110 that are not aligned in the direction parallel to the bottom portion 120. In the present embodiment, the wire diameters R of the plurality of linear members 110 are all the same as each other, for example, 0.3 mm. The wire diameter R of the linear member located farthest from the bottom 120 among the plurality of linear members 110 may be, for example, 0.2 mm.
　チップ状電子部品用治具１００の全体が板状部材で構成される場合には、底部１２０の厚さは、たとえば０．２ｍｍ以上２．０ｍｍ以下であり、側壁部１３０の高さは、たとえば０．１ｍｍ以上８．０ｍｍ以下である。 When the entire jig 100 for chip-shaped electronic components is composed of a plate-shaped member, the thickness of the bottom portion 120 is, for example, 0.2 mm or more and 2.0 mm or less, and the height of the side wall portion 130 is, for example, It is 0.1 mm or more and 8.0 mm or less.
　本実施形態において、複数の線状部材１１０の各々は、たとえば、ＳｉＣ、ジルコニア、イットリア安定化ジルコニア、アルミナもしくはムライト等のセラミックス、ニッケル、アルミニウム、インコネル(登録商標)もしくはＳＵＳなどの金属、ポリテトラフルオロエチレン(PTFE:polytetrafluoroethylene)、ポリプロピレン(PP:polypropylene)、アクリル樹脂、ＡＢＳ(Acrylonitrile　butadiene　styrene)ライク樹脂もしくはその他の耐熱樹脂などの樹脂材料、カーボン、または、金属とセラミックスとからなる複合材料で構成されており、本実施形態においては、セラミックスで構成されている。本実施形態においては、焼結などにより、複数の線状部材１１０同士が互いに接合されている。複数の線状部材１１０の各々の表面は、ＳｉＣ、ジルコニア、イットリア、イットリア安定化ジルコニア、アルミナもしくはムライト等のセラミックス、または、ニッケルなどの金属によってさらにコーティングされていてもよい。なお、チップ状電子部品用治具１００の全体が、板状部材で構成されている場合であっても、チップ状電子部品用治具１００は、複数の線状部材１１０を構成し得る上記の材料で構成することができる。 In the present embodiment, each of the plurality of linear members 110 is, for example, a ceramic such as SiC, zirconia, ittria-stabilized zirconia, alumina or mulite, a metal such as nickel, aluminum, inconel (registered trademark) or SUS, and polytetra. Consists of resin materials such as fluoroethylene (PTFE: polytetrafluoroethylene), polypropylene (PP: polypropylene), acrylic resin, ABS (Acrylonitrile butadiene styrene) -like resin or other heat-resistant resin, carbon, or a composite material consisting of metal and ceramics. In this embodiment, it is made of ceramics. In the present embodiment, a plurality of linear members 110 are joined to each other by sintering or the like. The surface of each of the plurality of linear members 110 may be further coated with a ceramic such as SiC, zirconia, yttria, yttria-stabilized zirconia, alumina or mullite, or a metal such as nickel. Even when the entire chip-shaped electronic component jig 100 is composed of plate-shaped members, the chip-shaped electronic component jig 100 can form a plurality of linear members 110 as described above. It can be composed of materials.
　次に、複数のチップ収納部１４０について説明する。図３および図４に示すように、本実施形態において、複数のチップ収納部１４０の各々の開口端は、互いに隣り合う２つの第６線状部材１１６と、互いに隣り合う２つの第７線状部材１１７で構成されている。一方、互いに隣り合う２つのチップ収納部１４０は、１本の第６線状部材１１６あるいは１本の第７線状部材１１７によって区切られている。複数の第３線状部材１１３から複数の第５線状部材１１５についても、それぞれの線状部材に対応する層において、１本の線状部材が、互いに隣り合う２つのチップ収納部１４０を区切っている。 Next, a plurality of chip storage units 140 will be described. As shown in FIGS. 3 and 4, in the present embodiment, the open ends of the plurality of chip accommodating portions 140 are two sixth linear members 116 adjacent to each other and two seventh linear members adjacent to each other. It is composed of member 117. On the other hand, the two chip accommodating portions 140 adjacent to each other are separated by one sixth linear member 116 or one seventh linear member 117. Regarding the plurality of third linear members 113 to the plurality of fifth linear members 115, one linear member separates two chip accommodating portions 140 adjacent to each other in the layer corresponding to each linear member. ing.
　本実施形態においては、複数のチップ収納部１４０を底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部１４０の各々の開口形状が、矩形状であり、具体的には、正方形状である。本実施形態においては、複数のチップ収納部１４０を、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部１４０の各々の開口形状が、多角形状であってもよい。 In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 140 is rectangular. , Specifically, it has a square shape. In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shapes of the plurality of chip storage portions 140 are polygonal. There may be.
　本実施形態において、複数のチップ収納部１４０の各々の開口の内側面は、複数の線状部材１１０によって形成される。具体的には、互いに隣り合う２つの第３線状部材１１３と、互いに隣り合う２つの第４線状部材１１４と、互いに隣り合う２つの第５線状部材１１５と、互いに隣り合う２つの第６線状部材１１６と、互いに隣り合う２つの第７線状部材１１７とによって形成されている。 In the present embodiment, the inner surface of each opening of the plurality of chip accommodating portions 140 is formed by the plurality of linear members 110. Specifically, two third linear members 113 adjacent to each other, two fourth linear members 114 adjacent to each other, two fifth linear members 115 adjacent to each other, and two second linear members adjacent to each other. It is formed by a 6-linear member 116 and two 7th linear members 117 adjacent to each other.
　図４に示すように、本実施形態において、複数のチップ収納部１４０の各々の底面は、第２線状部材１１２によって構成されている。また、図３に示すように、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部１４０の各々の底面の中心において、第１線状部材１１１と第２線状部材１１２とが互いに交差している。 As shown in FIG. 4, in the present embodiment, the bottom surface of each of the plurality of chip accommodating portions 140 is composed of the second linear member 112. Further, as shown in FIG. 3, when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120, the first linear member 111 and the center of the bottom surface of each of the plurality of chip storage portions 140 The second linear member 112 intersects with each other.
　ここで、本実施形態における複数のチップ収納部１４０に収納可能なチップ状電子部品１０について説明する。図１および図２に示すように、本実施形態における複数のチップ収納部１４０に収納可能なチップ状電子部品１０は、略直方体の形状を有している。チップ状電子部品１０は、たとえば積層セラミックコンデンサに用いることができる。 Here, the chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment will be described. As shown in FIGS. 1 and 2, the chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment has a substantially rectangular parallelepiped shape. The chip-shaped electronic component 10 can be used, for example, in a multilayer ceramic capacitor.
　本実施形態における複数のチップ収納部１４０に収納可能なチップ状電子部品１０は、長手方向と、幅方向と、厚さ方向とを有している。チップ状電子部品１０は、底部１２０と直交する方向とチップ状電子部品１０の長手方向とが互いに平行となるように、複数のチップ収納部１４０の各々に収納される。 The chip-shaped electronic component 10 that can be stored in the plurality of chip storage units 140 in the present embodiment has a longitudinal direction, a width direction, and a thickness direction. The chip-shaped electronic component 10 is housed in each of the plurality of chip storage portions 140 so that the direction orthogonal to the bottom portion 120 and the longitudinal direction of the chip-shaped electronic component 10 are parallel to each other.
　図１および図２に示すように、チップ状電子部品１０の長手方向の長さＬ、幅方向の幅Ｗ、および、厚さ方向の厚さＴの各々の寸法は、Ｌ：Ｗ：Ｔ＝２：１：１の関係と同等の関係を有している。当該同等の関係とは、Ｌ：Ｗ：Ｔ＝２：１：１の関係に対して、長さＬ、幅方向の幅Ｗ、および、厚さ方向の厚さＴの各々の寸法が寸法差５％以内の範囲を含むことを意味している。なお、本実施形態に係るチップ状電子部品用治具１００に収納可能なチップ状電子部品は、上記の各寸法関係を有するチップ状電子部品１０に限定されるものではない。たとえば、本実施形態に係るチップ状電子部品用治具１００には、Ｌ：Ｗ：Ｔ＝２：１．２５：１．２５の関係と同等の関係を有するチップ状電子部品を収納してもよい。 As shown in FIGS. 1 and 2, the dimensions of the length L in the longitudinal direction, the width W in the width direction, and the thickness T in the thickness direction of the chip-shaped electronic component 10 are L: W: T =. It has a relationship equivalent to the 2: 1: 1 relationship. The equivalent relationship is that the dimensions of the length L, the width W in the width direction, and the thickness T in the thickness direction are dimensional differences with respect to the relationship of L: W: T = 2: 1: 1. It means that it includes the range within 5%. The chip-shaped electronic component that can be stored in the chip-shaped electronic component jig 100 according to the present embodiment is not limited to the chip-shaped electronic component 10 having each of the above dimensional relationships. For example, the jig 100 for chip-shaped electronic components according to the present embodiment may accommodate chip-shaped electronic components having a relationship equivalent to the relationship of L: W: T = 2: 1.25: 1.25. Good.
　本実施形態に係るチップ状電子部品用治具１００に収納可能なチップ状電子部品１０の長手方向の長さＬは、たとえば０．６ｍｍ以上３．８ｍｍ以下であり、幅方向の幅Ｗは、たとえば０．３ｍｍ以上３．０ｍｍ以下であり、厚さ方向の厚さＴは、たとえば０．３ｍｍ以上３．０ｍｍ以下である。チップ状電子部品１０をチップ状電子部品用治具１００を用いて焼成する場合には、焼成後のチップ状電子部品１０の上記長さＬ、上記幅Ｗ、上記厚さＴの各寸法が、たとえば積層セラミックコンデンサの積層体などの電子部品に用いられる際に適切な寸法となるように、焼成前において、チップ状電子部品１０に係る各寸法が上記の範囲内で適宜設定される。 The length L in the longitudinal direction of the chip-shaped electronic component 10 that can be stored in the jig 100 for the chip-shaped electronic component according to the present embodiment is, for example, 0.6 mm or more and 3.8 mm or less, and the width W in the width direction is For example, it is 0.3 mm or more and 3.0 mm or less, and the thickness T in the thickness direction is, for example, 0.3 mm or more and 3.0 mm or less. When the chip-shaped electronic component 10 is fired using the chip-shaped electronic component jig 100, the dimensions of the length L, the width W, and the thickness T of the chip-shaped electronic component 10 after firing are determined. For example, each dimension of the chip-shaped electronic component 10 is appropriately set within the above range before firing so as to have an appropriate dimension when used for an electronic component such as a laminate of a multilayer ceramic capacitor.
　本実施形態に係るチップ状電子部品用治具１００においては、複数のチップ収納部１４０の各々の開口の形状に係る各寸法は、本実施形態におけるチップ状電子部品１０の長手方向の長さＬ、幅方向の幅Ｗ、および、厚さ方向の厚さＴの各々が、上述のＬ：Ｗ：Ｔ＝２：１：１の関係を有していることを考慮して、設定される。以下、本実施形態における複数のチップ収納部１４０の各々の開口の形状に係る各寸法について説明する。 In the chip-shaped electronic component jig 100 according to the present embodiment, each dimension related to the shape of each opening of the plurality of chip accommodating portions 140 is the length L in the longitudinal direction of the chip-shaped electronic component 10 according to the present embodiment. , The width W in the width direction and the thickness T in the thickness direction are set in consideration of the above-mentioned relationship of L: W: T = 2: 1: 1. Hereinafter, each dimension related to the shape of each opening of the plurality of chip accommodating portions 140 in the present embodiment will be described.
　図１および図３に示すように、複数のチップ収納部１４０の各々において、底部１２０と直交する方向から見たときの複数のチップ収納部１４０の各々の内接円１４１の直径Ｄは、複数のチップ収納部１４０の各々にチップ状電子部品１０が収納されたときに、チップ状電子部品１０が、長手方向に沿った軸を中心軸として回転可能となるように、設定される。たとえば、本実施形態において、幅方向の幅Ｗおよび厚さ方向の厚さＴの各々の長さがaである場合、上記内接円１４１の直径Ｄは、チップ状電子部品１０の幅方向の稜線および厚さ方向の稜線で構成される矩形形状の対角線の長さである(√２)ａより大きくなるように設定される(Ｄ＞(√２)ａ)。これにより、チップ状電子部品１０に対して十分な大きさの複数のチップ収納部１４０が確保でき、チップ状電子部品１０をチップ収納部に挿入するときにかかる時間を短縮できる。なお、上記幅方向の幅Ｗおよび上記厚さ方向の厚さＴが互いに異なる場合においては、上記内接円１４１の直径Ｄは、およそ√(Ｗ2＋Ｔ2)より大きくなるように設定される。 As shown in FIGS. 1 and 3, in each of the plurality of chip storage portions 140, the diameter D of each inscribed circle 141 of the plurality of chip storage portions 140 when viewed from a direction orthogonal to the bottom portion 120 is a plurality. When the chip-shaped electronic component 10 is housed in each of the chip accommodating portions 140, the chip-shaped electronic component 10 is set so as to be rotatable about an axis along the longitudinal direction as a central axis. For example, in the present embodiment, when the lengths of the width W in the width direction and the thickness T in the thickness direction are a, the diameter D of the inscribed circle 141 is the width direction of the chip-shaped electronic component 10. It is set to be larger than (√2) a, which is the length of the diagonal line of the rectangular shape composed of the ridge line and the ridge line in the thickness direction (D> (√2) a). As a result, a plurality of chip accommodating portions 140 having a sufficient size for the chip-shaped electronic component 10 can be secured, and the time required for inserting the chip-shaped electronic component 10 into the chip accommodating portion can be shortened. When the width W in the width direction and the thickness T in the thickness direction are different from each other, the diameter D of the inscribed circle 141 is set to be larger than about √ (W 2 + T 2). ..
　次に、複数のチップ収納部１４０の各々においては、底部１２０と直交する方向から見たときに、１つのチップ収納部１４０に２つ以上のチップ状電子部品１０が入らないようにするために、上記内接円１４１の直径Ｄが、２ａ未満となるように設定される（Ｄ＜２ａ）。たとえば、図３に示すように、本実施形態においては、複数のチップ収納部１４０の開口形状が、１辺の長さをＤとする正方形状である。チップ状電子部品１０の幅Ｗおよび厚さＴをａとしたときに、Ｄが２ａ以上であると、１つのチップ収納部１４０にチップ状電子部品１０が２つ入る可能性がある。よって、上記内接円１４１の直径Ｄは、２ａ未満となるように設定される。 Next, in each of the plurality of chip accommodating portions 140, in order to prevent two or more chip-shaped electronic components 10 from entering one chip accommodating portion 140 when viewed from a direction orthogonal to the bottom portion 120. , The diameter D of the inscribed circle 141 is set to be less than 2a (D <2a). For example, as shown in FIG. 3, in the present embodiment, the opening shape of the plurality of chip accommodating portions 140 is a square shape having a side length of D. When the width W and the thickness T of the chip-shaped electronic component 10 are a, and if D is 2a or more, there is a possibility that two chip-shaped electronic components 10 may be inserted in one chip accommodating portion 140. Therefore, the diameter D of the inscribed circle 141 is set to be less than 2a.
　次に、側壁部１３０の高さの寸法、すなわち、複数のチップ収納部１４０の各々の深さＺの寸法について説明する。複数のチップ収納部１４０に各々にチップ状電子部品１０を挿入した際に、チップ収納部１４０に入りきらず、チップ状電子部品用治具１００上に余ったチップ状電子部品１０は、チップ状電子部品用治具１００を傾けて振るい落とす。このため、複数のチップ収納部１４０の各々の深さＺは、チップ収納部１４０に収納されたチップ状電子部品１０を振るい落とすことができ、かつ、余ったチップ状電子部品１０を確実に振るい落とすことができるように設定する必要がある。 Next, the height dimension of the side wall portion 130, that is, the dimension of the depth Z of each of the plurality of chip storage portions 140 will be described. When the chip-shaped electronic component 10 is inserted into each of the plurality of chip-shaped electronic components 140, the chip-shaped electronic component 10 that does not fit in the chip-shaped electronic component 140 and remains on the chip-shaped electronic component jig 100 is a chip-shaped electronic component. Tilt the component jig 100 and shake it off. Therefore, the depth Z of each of the plurality of chip accommodating portions 140 can shake off the chip-shaped electronic component 10 stored in the chip accommodating portion 140, and the surplus chip-shaped electronic component 10 can be reliably shaken off. It needs to be set so that it can be dropped.
　図２および図４に示すように、複数のチップ収納部１４０の各々の深さＺは、チップ状電子部品１０の長さＬの寸法が２ａであるときに、２ａの半分より大きくなるように設定する（ａ＜Ｚ）。このように設定することで、チップ状電子部品１０の重心がチップ状電子部品１０の長手方向の略中心に位置していれば、チップ収納部１４０に収納されたチップ状電子部品１０の重心は、チップ収納部１４０内に位置する。これにより、余ったチップ状電子部品１０は、チップ状電子部品用治具１００を傾けて振るい落とすときに、チップ収納部１４０に収納されたチップ状電子部品１０がチップ収納部１４０から落ちることを抑制できる。 As shown in FIGS. 2 and 4, the depth Z of each of the plurality of chip accommodating portions 140 is set to be larger than half of 2a when the dimension of the length L of the chip-shaped electronic component 10 is 2a. Set (a <Z). By setting in this way, if the center of gravity of the chip-shaped electronic component 10 is located substantially at the center in the longitudinal direction of the chip-shaped electronic component 10, the center of gravity of the chip-shaped electronic component 10 housed in the chip accommodating portion 140 will be. , Located in the chip storage unit 140. As a result, when the chip-shaped electronic component 10 is tilted and shaken off from the chip-shaped electronic component jig 100, the chip-shaped electronic component 10 stored in the chip storage unit 140 falls from the chip storage unit 140. Can be suppressed.
　さらに、図２および図４に示すように、複数のチップ収納部１４０の各々の深さＺは、チップ状電子部品１０の長さＬの寸法が２ａであるときに、３ａより小さくなるように設定する（Ｚ＜３ａ）。これにより、チップ状電子部品１０をチップ状電子部品用治具１００上にばらまいてチップ収納部１４０に挿入したときに、チップ収納部１４０に収納されたチップ状電子部品１０の上にチップ状電子部品１０がさらに位置しても、この上側のチップ状電子部品１０のみをふるい落とすことができる。上側のチップ状電子部品１０の重心位置の高さの寸法は、底部１２０を基準として３ａであり、上側のチップ状電子部品１０の重心は、チップ収納部１４０の外側に位置するからである。 Further, as shown in FIGS. 2 and 4, the depth Z of each of the plurality of chip accommodating portions 140 is set to be smaller than 3a when the dimension of the length L of the chip-shaped electronic component 10 is 2a. Set (Z <3a). As a result, when the chip-shaped electronic component 10 is scattered on the chip-shaped electronic component jig 100 and inserted into the chip-shaped electronic component 140, the chip-shaped electronic component 10 is placed on the chip-shaped electronic component 10 stored in the chip-shaped electronic component 140. Even if the component 10 is further positioned, only the chip-shaped electronic component 10 on the upper side can be screened off. This is because the height dimension of the center of gravity of the upper chip-shaped electronic component 10 is 3a with respect to the bottom portion 120, and the center of gravity of the upper chip-shaped electronic component 10 is located outside the chip accommodating portion 140.
　以上より、チップ状電子部品１０の長さＬ方向の寸法が２ａ、幅Ｗ方向および厚さＴ方向の各々の寸法がａであるとき、ＤとＺとの関係は、上記式（Ｄ＜２ａ）と上記式（ａ＜Ｚ）とに基づき、(Ｄ／２)＜ａ＜Ｚとなるから、(Ｄ／２)＜Ｚとなる。さらに、ＤとＺとの関係は、上記式(Ｄ＞(√２)ａ)と上記式（Ｚ＜３ａ）とに基づき、Ｚ＜３ａ＜(３√２／２)Ｄとなるから、Ｚ＜(３√２／２)Ｄとなる。 From the above, when the dimension of the chip-shaped electronic component 10 in the length L direction is 2a and the respective dimensions in the width W direction and the thickness T direction are a, the relationship between D and Z is based on the above equation (D <2a). ) And the above equation (a <Z), (D / 2) <a <Z, so (D / 2) <Z. Further, the relationship between D and Z is Z <3a <(3√2 / 2) D based on the above equation (D> (√2) a) and the above equation (Z <3a). <(3√2 / 2) D.
　以上により、本実施形態においては、複数のチップ収納部１４０の各々において、底部１２０と直交する方向から見たときの側壁部１３０の内接円の直径Ｄの寸法と、複数のチップ収納部１４０の各々の深さＺの寸法とが、下記式(１)の関係を満たしている。 Based on the above, in the present embodiment, in each of the plurality of chip storage portions 140, the size of the diameter D of the inscribed circle of the side wall portion 130 when viewed from the direction orthogonal to the bottom portion 120, and the plurality of chip storage portions 140. The dimension of each depth Z of the above satisfies the relationship of the following equation (1).
　(Ｄ／２）＜Ｚ＜（３√２／２）Ｄ　・・・（１）
　さらに、複数のチップ収納部１４０の各々の深さＺは、チップ状電子部品１０の長さＬの寸法が２ａであるときに、２ａより小さくなるように設定することが好ましい（Ｚ＜２ａ）。すなわち、チップ状電子部品１０をチップ収納部１４０に収納したときに、チップ状電子部品１０の一部がチップ収納部１４０の外側に位置していることが好ましい。これにより、チップ収納部１４０の中に収納されたチップ状電子部品１０を取り出すときに、側壁部１３０にチップ状電子部品１０の複数の角部が引っかかって、これら複数の角部が固定されることで、チップ状電子部品１０が側壁部１３０にロックされることを防ぐことができる。 (D / 2) <Z <(3√2 / 2) D ... (1)
Further, it is preferable that the depth Z of each of the plurality of chip accommodating portions 140 is set to be smaller than 2a when the dimension of the length L of the chip-shaped electronic component 10 is 2a (Z <2a). .. That is, when the chip-shaped electronic component 10 is stored in the chip accommodating portion 140, it is preferable that a part of the chip-shaped electronic component 10 is located outside the chip accommodating portion 140. As a result, when the chip-shaped electronic component 10 stored in the chip accommodating portion 140 is taken out, the plurality of corner portions of the chip-shaped electronic component 10 are caught on the side wall portion 130, and the plurality of corner portions are fixed. This makes it possible to prevent the chip-shaped electronic component 10 from being locked to the side wall portion 130.
　よって、深さが（Ｚ＜２ａ）と設定されるときは、ＤとＺとの関係は、当該式（Ｚ＜２ａ）と、上記式(Ｄ＞(√２)ａ)とに基づき、Ｚ＜２ａ＜(√２)Ｄとなるから、Ｚ＜(√２)Ｄとなる。 Therefore, when the depth is set to (Z <2a), the relationship between D and Z is based on the equation (Z <2a) and the above equation (D> (√2) a). Since <2a <(√2) D, Z <(√2) D.
　以上により、複数のチップ収納部１４０の各々において、側壁部１３０の内接円の直径Ｄの寸法と、複数のチップ収納部２４０の各々の深さＺの寸法とは、さらに下記式(２)の関係を満たしていることが好ましい。 Based on the above, in each of the plurality of chip storage portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip storage portions 240 are further expressed by the following equation (2). It is preferable that the relationship of
　(Ｄ／２）＜Ｚ＜（√２）Ｄ　・・・（２）
　本実施形態において、上記内接円１４１の直径Ｄの寸法は、たとえば０．１ｍｍ以上５．０ｍｍ以下である。上記深さＺは、たとえば０．１ｍｍ以上８．０ｍｍである。 (D / 2) <Z <(√2) D ... (2)
In the present embodiment, the diameter D of the inscribed circle 141 is, for example, 0.1 mm or more and 5.0 mm or less. The depth Z is, for example, 0.1 mm or more and 8.0 mm.
　また、図４に示すように、本実施形態においては、複数の線状部材１１０の各々の線径Ｒの寸法が、複数のチップ収納部１４０の各々の深さＺの寸法の１／２未満である。 Further, as shown in FIG. 4, in the present embodiment, the dimension of each wire diameter R of the plurality of linear members 110 is less than 1/2 of the dimension of each depth Z of the plurality of chip accommodating portions 140. Is.
　ここで、複数の線状部材の各々の線径Ｒの寸法と、複数のチップ収納部の各々の深さＺの寸法との関係が、本実施形態に係るチップ状電子部品用治具１００と異なる、比較例に係るチップ状電子部品用治具について説明する。 Here, the relationship between the dimension of the wire diameter R of each of the plurality of linear members and the dimension of the depth Z of each of the plurality of chip accommodating portions is the relationship between the jig 100 for chip-shaped electronic components according to the present embodiment. A different jig for chip-shaped electronic components according to a comparative example will be described.
　図５は、比較例に係るチップ状電子部品用治具の一部の構成を示す正面図である。図５においては、図４と同一の方向から見た断面視にて図示している。図５に示すように、比較例に係るチップ状電子部品用治具９００においては、複数の線状部材の各々の線径Ｒの寸法が、複数のチップ収納部９４０の各々の深さＺの寸法の１／２である。 FIG. 5 is a front view showing a partial configuration of a jig for chip-shaped electronic parts according to a comparative example. In FIG. 5, it is shown in a cross-sectional view seen from the same direction as in FIG. As shown in FIG. 5, in the chip-shaped electronic component jig 900 according to the comparative example, the dimension of the wire diameter R of each of the plurality of linear members is the depth Z of each of the plurality of chip accommodating portions 940. It is 1/2 of the size.
　このような比較例に係るチップ状電子部品用治具９００においては、底部１２０が、第１線状部材９１１と、第２線状部材９１２とで構成されている。側壁部１３０は、２本の第３線状部材９１３と、２本の第４線状部材９１４とで構成されている。 In the chip-shaped electronic component jig 900 according to such a comparative example, the bottom portion 120 is composed of a first linear member 911 and a second linear member 912. The side wall portion 130 is composed of two third linear members 913 and two fourth linear members 914.
　図５に示すように、比較例に係るチップ状電子部品用治具９００においては、複数の線状部材の各々の線径Ｒの寸法が比較的大きい。これにより、複数のチップ収納部９４０の各々に収納された複数のチップ状電子部品１０のうち、互いに隣り合っているチップ状電子部品１０同士の間に、他のチップ状電子部品１０が入り込んで、第３線状部材９１３の上側に位置することが可能となっている。 As shown in FIG. 5, in the jig 900 for chip-shaped electronic parts according to the comparative example, the dimension of the wire diameter R of each of the plurality of linear members is relatively large. As a result, among the plurality of chip-shaped electronic components 10 housed in each of the plurality of chip accommodating portions 940, the other chip-shaped electronic components 10 are inserted between the chip-shaped electronic components 10 adjacent to each other. , It is possible to be located above the third linear member 913.
　一方、図２および図４に示すように、本発明の実施形態１に係るチップ状電子部品用治具１００においては、複数の線状部材の各々の線径Ｒの寸法が比較的小さいため、複数のチップ収納部１４０の各々に収納された複数のチップ状電子部品１０のうち、互いに隣り合っているチップ状電子部品１０同士の間に、他のチップ状電子部品が入り込むことを抑制することができる。 On the other hand, as shown in FIGS. 2 and 4, in the chip-shaped electronic component jig 100 according to the first embodiment of the present invention, the wire diameter R of each of the plurality of linear members is relatively small. Suppressing that other chip-shaped electronic components enter between the chip-shaped electronic components 10 adjacent to each other among the plurality of chip-shaped electronic components 10 housed in each of the plurality of chip storage units 140. Can be done.
　本発明の実施形態１に係るチップ状電子部品用治具１００は、具体的には、チップ状電子部品焼成用治具である。複数のチップ状電子部品１０が収納されたチップ状電子部品用治具１００を焼成雰囲気下に配置することで、複数のチップ状電子部品１０を焼成することができる。また、本発明の実施形態１に係るチップ状電子部品用治具１００は、複数のチップ状電子部品１０が収納されたチップ状電子部品用治具１００をめっき液につけることで、複数のチップ状電子部品１０に、Ｃｕ、Ｎｉ、Ｓｎ、Ａｇ、ＡｕまたはＰｄなどの金属をめっきすることもできる。さらに、端部にＡｇなどからなる下地電極が形成された複数のチップ状電子部品１０について、このような複数のチップ状電子部品１０が収納されたチップ状電子部品用治具１００をめっき液に浸すことで、上記下地電極に、めっきすることもできる。 The chip-shaped electronic component jig 100 according to the first embodiment of the present invention is specifically a chip-shaped electronic component firing jig. By arranging the chip-shaped electronic component jig 100 containing the plurality of chip-shaped electronic components 10 in a firing atmosphere, the plurality of chip-shaped electronic components 10 can be fired. Further, the jig 100 for chip-shaped electronic components according to the first embodiment of the present invention has a plurality of chips by immersing the jig 100 for chip-shaped electronic components containing a plurality of chip-shaped electronic components 10 in a plating solution. The electronic component 10 can also be plated with a metal such as Cu, Ni, Sn, Ag, Au or Pd. Further, with respect to a plurality of chip-shaped electronic components 10 having base electrodes made of Ag or the like formed at the ends, a jig 100 for chip-shaped electronic components containing such a plurality of chip-shaped electronic components 10 is used as a plating solution. By immersing the base electrode, the base electrode can be plated.
　上記のように、本発明の実施形態１に係るチップ状電子部品用治具１００は、チップ状電子部品を収納する複数のチップ収納部１４０を備えている。複数のチップ収納部１４０の各々は、底部１２０と、側壁部１３０とを含んでいる。底部１２０は、チップ状電子部品を支持する。側壁部１３０は、チップ状電子部品を挿入可能に開口している。複数のチップ収納部１４０の各々において、底部１２０と直交する方向から見たときの複数のチップ収納部１４０の各々の側壁部１３０の内接円の直径Ｄの寸法と、複数のチップ収納部１４０の各々の深さＺの寸法とが、下記式(１)の関係を満たしている。 As described above, the jig 100 for chip-shaped electronic components according to the first embodiment of the present invention includes a plurality of chip accommodating portions 140 for accommodating chip-shaped electronic components. Each of the plurality of chip accommodating portions 140 includes a bottom portion 120 and a side wall portion 130. The bottom 120 supports a chip-shaped electronic component. The side wall portion 130 is open so that a chip-shaped electronic component can be inserted. In each of the plurality of chip storage portions 140, the size of the diameter D of the inscribed circle of each side wall portion 130 of the plurality of chip storage portions 140 when viewed from the direction orthogonal to the bottom portion 120, and the plurality of chip storage portions 140. The dimension of each depth Z of the above satisfies the relationship of the following equation (1).
　(Ｄ／２）＜Ｚ＜（３√２／２）Ｄ　・・・（１）
　これにより、複数のチップ収納部１４０において、１つのチップ収納部１４０に１つのチップ状電子部品１０を容易に挿入することができる。 (D / 2) <Z <(3√2 / 2) D ... (1)
As a result, in the plurality of chip storage units 140, one chip-shaped electronic component 10 can be easily inserted into one chip storage unit 140.
　本実施形態においては、複数のチップ収納部１４０の各々において、側壁部１３０の内接円の直径Ｄの寸法と、複数のチップ収納部１４０の各々の深さＺの寸法とが、下記式(２)の関係を満たしていることがより好ましい。 In the present embodiment, in each of the plurality of chip accommodating portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip accommodating portions 140 are expressed by the following equations ( It is more preferable that the relationship of 2) is satisfied.
　(Ｄ／２）＜Ｚ＜（√２）Ｄ　・・・（２）
　これにより、複数のチップ収納部１４０に１つずつ挿入されたチップ状電子部品１０を、容易に取り出すことができる。 (D / 2) <Z <(√2) D ... (2)
As a result, the chip-shaped electronic components 10 inserted into the plurality of chip accommodating portions 140 one by one can be easily taken out.
　本実施形態においては、複数のチップ収納部１４０を、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部１４０の各々の開口形状が、多角形状である。 In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shapes of the plurality of chip storage portions 140 are polygonal. is there.
　これにより、複数のチップ収納部１４０を整列させやすくなる。ひいては、整列された複数のチップ収納部１４０の各々にチップ状電子部品１０を収納することにより、チップ状電子部品用治具１００あたりのチップ状電子部品１０の充填率を向上させることができる。 This makes it easier to align the plurality of chip storage units 140. As a result, the filling rate of the chip-shaped electronic component 10 per the jig 100 for the chip-shaped electronic component can be improved by storing the chip-shaped electronic component 10 in each of the plurality of aligned chip storage portions 140.
　本実施形態に係るチップ状電子部品用治具１００は、直線状の複数の線状部材１１０が互いに積層されることで構成されている。 The jig 100 for chip-shaped electronic components according to the present embodiment is configured by stacking a plurality of linear linear members 110 on each other.
　これにより、線状部材１１０同士の間に形成された隙間においてガスまたは液体が通流可能となるため、チップ収納部１４０の通気性または液体の通過性を向上させることができる。 As a result, gas or liquid can flow through the gap formed between the linear members 110, so that the air permeability of the chip accommodating portion 140 or the passage of liquid can be improved.
　本実施形態においては、複数の線状部材１１０の各々の線径Ｒの寸法が、複数のチップ収納部１４０の各々の深さＺの寸法の１／２未満である。 In the present embodiment, the dimension of the wire diameter R of each of the plurality of linear members 110 is less than 1/2 of the dimension of the depth Z of each of the plurality of chip accommodating portions 140.
　これにより、複数のチップ収納部１４０の各々に収納されたチップ状電子部品１０のうち、互いに隣り合うチップ状電子部品１０同士の間に、さらに他のチップ状電子部品１０が入り込むことを抑制できる。 As a result, among the chip-shaped electronic components 10 stored in each of the plurality of chip accommodating portions 140, it is possible to prevent another chip-shaped electronic component 10 from entering between the chip-shaped electronic components 10 adjacent to each other. ..
　本実施形態に係るチップ状電子部品用治具１００は、セラミックスで構成されている。
　これにより、チップ状電子部品用治具１００が金属で構成されている場合と比較して、チップ状電子部品用治具１００の耐熱性を向上させることができる。 The chip-shaped electronic component jig 100 according to this embodiment is made of ceramics.
As a result, the heat resistance of the chip-shaped electronic component jig 100 can be improved as compared with the case where the chip-shaped electronic component jig 100 is made of metal.
　(実施形態２)
　以下、本発明の実施形態２に係るチップ状電子部品用治具について説明する。本発明の実施形態２に係るチップ状電子部品用治具においては、複数のチップ収納部の各々の開口形状が主に、本発明の実施形態１に係るチップ状電子部品用治具１００と異なる。よって、本発明の実施形態１に係るチップ状電子部品用治具１００と同様である構成については説明を繰り返さない。 (Embodiment 2)
Hereinafter, the jig for chip-shaped electronic components according to the second embodiment of the present invention will be described. In the jig for chip-shaped electronic components according to the second embodiment of the present invention, the opening shape of each of the plurality of chip accommodating portions is mainly different from the jig 100 for the chip-shaped electronic components according to the first embodiment of the present invention. .. Therefore, the description of the configuration similar to that of the chip-shaped electronic component jig 100 according to the first embodiment of the present invention will not be repeated.
　図６は、本発明の実施形態２に係るチップ状電子部品用治具の構成を示す平面図である。図７は、図６に示すチップ状電子部品用治具を矢印ＶＩＩ方向から見た図である。図６においては、図１と同一の方向から見て図示している。なお、図６においては、複数の第１線状部材１１１および複数の第２線状部材１１２は図示していない。 FIG. 6 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the second embodiment of the present invention. FIG. 7 is a view of the jig for chip-shaped electronic components shown in FIG. 6 as viewed from the direction of arrow VII. In FIG. 6, it is shown when viewed from the same direction as in FIG. In FIG. 6, the plurality of first linear members 111 and the plurality of second linear members 112 are not shown.
　図６および図７に示すように、本発明の実施形態２に係るチップ状電子部品用治具２００は、複数の線状部材２１０で構成されている。具体的には、本実施形態において、底部１２０は、複数の第１線状部材１１１と、複数の第２線状部材１１２とを有している。側壁部１３０は、複数の環状の第８線状部材２１８と、複数の環状の第９線状部材２１９とを有している。 As shown in FIGS. 6 and 7, the jig 200 for chip-shaped electronic components according to the second embodiment of the present invention is composed of a plurality of linear members 210. Specifically, in the present embodiment, the bottom portion 120 has a plurality of first linear members 111 and a plurality of second linear members 112. The side wall portion 130 has a plurality of annular eighth linear members 218 and a plurality of annular ninth linear members 219.
　図７に示すように、複数の環状の第８線状部材２１８の各々は、側壁部１３０において底部１２０側とは反対側の端部を構成するように位置している。図６に示すように、複数の環状の第８線状部材２１８の各々は、隣接する第８線状部材２１８と互いに重なり合っている。複数の環状の第８線状部材２１８の各々は、底部１２０に直交する方向において底部１２０側とは反対側から見たときに、環状の内側部分同士が互いに重なり合わないように、位置している。 As shown in FIG. 7, each of the plurality of annular eighth linear members 218 is positioned so as to form an end portion of the side wall portion 130 opposite to the bottom portion 120 side. As shown in FIG. 6, each of the plurality of annular eighth linear members 218 overlaps with the adjacent eighth linear member 218. Each of the plurality of annular eighth linear members 218 is positioned so that the inner portions of the annulus do not overlap each other when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120. There is.
　図７に示すように、複数の環状の第９線状部材２１９の各々は、底部１２０に直交する方向から見たときに、複数の環状の第８線状部材２１８の各々と重なるように位置している。複数の環状の第９線状部材２１９の各々は、隣接する第９線状部材２１９と互いに重なり合っている。複数の環状の第９線状部材２１９の各々は、複数の第２線状部材１１２の第１線状部材１１１側とは反対側に位置し、かつ、複数の第８線状部材２１８より底部１２０側に位置している。 As shown in FIG. 7, each of the plurality of annular ninth linear members 219 is positioned so as to overlap each of the plurality of annular eighth linear members 218 when viewed from a direction orthogonal to the bottom 120. doing. Each of the plurality of annular ninth linear members 219 overlaps with the adjacent ninth linear member 219. Each of the plurality of annular ninth linear members 219 is located on the side opposite to the first linear member 111 side of the plurality of second linear members 112, and is located at the bottom of the plurality of eighth linear members 218. It is located on the 120 side.
　本発明の実施形態２において、複数のチップ収納部２４０の各々の深さＺの寸法は、底部１２０に直交する方向において、第２線状部材１１２の第８線状部材２１８側の端部から、第８線状部材２１８の第２線状部材１１２側とは反対側の端部までの距離の寸法である。 In the second embodiment of the present invention, the dimension of the depth Z of each of the plurality of chip accommodating portions 240 is from the end portion of the second linear member 112 on the eighth linear member 218 side in the direction orthogonal to the bottom portion 120. , The dimension of the distance to the end of the eighth linear member 218 opposite to the second linear member 112 side.
　本実施形態に係るチップ状電子部品用治具２００は上記のように構成されているため、複数のチップ収納部２４０の開口は、複数の第８線状部材２１８の各々の内側部分および複数の第９線状部材２１９の各々の内側部分で構成されている。 Since the jig 200 for chip-shaped electronic components according to the present embodiment is configured as described above, the openings of the plurality of chip accommodating portions 240 are the inner portions of each of the plurality of eighth linear members 218 and the plurality of openings. It is composed of each inner portion of the ninth linear member 219.
　図６および図７に示すように、本発明の実施形態２に係るチップ状電子部品用治具２００においては、底部１２０に直交する方向において底部１２０側とは反対側から見たときに、複数の第８線状部材２１８の各々および複数の第９線状部材２１９の各々の内側部分は、円形状である。すなわち、複数のチップ収納部２４０を、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部２４０の各々の開口形状が、円形状である。 As shown in FIGS. 6 and 7, in the jig 200 for chip-shaped electronic components according to the second embodiment of the present invention, a plurality of jigs 200 when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120. The inner portion of each of the eighth linear member 218 and each of the plurality of ninth linear members 219 is circular. That is, when the plurality of chip storage portions 240 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 240 is circular.
　これにより、底部１２０と直交する方向において底部１２０側とは反対側から見たときに、複数のチップ収納部２４０を密に配置することができる。ひいては、チップ状電子部品用治具２００あたりのチップ状電子部品１０の充填率を向上させることできる。 As a result, the plurality of chip storage portions 240 can be densely arranged when viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120. As a result, the filling rate of the chip-shaped electronic component 10 per the chip-shaped electronic component jig 200 can be improved.
　また、本実施形態においても、上記式(１)の関係を満たしているため、複数のチップ収納部２４０において、１つのチップ収納部２４０に１つのチップ状電子部品１０を容易に挿入することができる。 Further, also in the present embodiment, since the relationship of the above formula (1) is satisfied, one chip-shaped electronic component 10 can be easily inserted into one chip storage unit 240 in the plurality of chip storage units 240. it can.
　なお、本実施形態において、底部１２０に直交する方向において底部１２０側とは反対側から見たときの複数のチップ収納部２４０の各々の内接円２４１は、底部１２０に直交する方向において底部１２０側とは反対側から見たときの複数の第８線状部材２１８の各々の内側面部または第９線状部材２１９の各々の内側面部で構成される。 In the present embodiment, the inscribed circles 241 of the plurality of chip accommodating portions 240 when viewed from the side opposite to the bottom 120 side in the direction orthogonal to the bottom 120 are the bottom 120 in the direction orthogonal to the bottom 120. It is composed of an inner side surface portion of each of the plurality of eighth linear members 218 or each inner side surface portion of the ninth linear member 219 when viewed from the side opposite to the side.
　(実施形態３)
　以下、本発明の実施形態３に係るチップ状電子部品用治具について説明する。本発明の実施形態３に係るチップ状電子部品用治具においては、複数のチップ収納部の各々の開口寸法に係る特徴が主に、本発明の実施形態１に係るチップ状電子部品用治具１００と異なる。よって、本発明の実施形態１に係るチップ状電子部品用治具１００と同様である構成については説明を繰り返さない。 (Embodiment 3)
Hereinafter, the jig for chip-shaped electronic components according to the third embodiment of the present invention will be described. In the jig for chip-shaped electronic parts according to the third embodiment of the present invention, the feature related to the opening size of each of the plurality of chip storage portions is mainly the jig for the chip-shaped electronic parts according to the first embodiment of the present invention. Different from 100. Therefore, the description of the configuration similar to that of the chip-shaped electronic component jig 100 according to the first embodiment of the present invention will not be repeated.
　図８は、本発明の実施形態３に係るチップ状電子部品用治具の構成を示す平面図である。 FIG. 8 is a plan view showing the configuration of a jig for chip-shaped electronic components according to the third embodiment of the present invention.
　図８に示すように、本発明の実施形態３に係るチップ状電子部品用治具３００においては、複数のチップ収納部３４０の各々が、底部１２０と直交する方向において、底部１２０側から、底部１２０側とは反対側に向かうにしたがって、開口寸法が大きくなっている。 As shown in FIG. 8, in the chip-shaped electronic component jig 300 according to the third embodiment of the present invention, each of the plurality of chip accommodating portions 340 is oriented from the bottom 120 side to the bottom in a direction orthogonal to the bottom 120. The opening size increases toward the side opposite to the 120 side.
　これにより、チップ状電子部品用治具３００を揺動させたときに、複数のチップ収納部３４０の各々に、チップ状電子部品１０を滑り込ませやすくすることができる。 Thereby, when the jig 300 for the chip-shaped electronic component is swung, the chip-shaped electronic component 10 can be easily slid into each of the plurality of chip accommodating portions 340.
　また、本実施形態においても、上記式(１)の関係を満たしているため、複数のチップ収納部３４０において、１つのチップ収納部３４０に１つのチップ状電子部品１０を容易に挿入することができる。 Further, also in the present embodiment, since the relationship of the above formula (1) is satisfied, one chip-shaped electronic component 10 can be easily inserted into one chip storage unit 340 in the plurality of chip storage units 340. it can.
　なお、本発明の実施形態３において、上記開口寸法とは、底部１２０に平行な方向において互いに隣り合う線状部材３１０同士の距離の寸法である。 In the third embodiment of the present invention, the opening dimension is the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom 120.
　本発明の実施形態３に係るチップ状電子部品用治具３００においては、複数の線状部材３１０の一部について、複数の線状部材３１０の各々の線径が互いに異なっている。具体的には、複数の線状部材３１０の線径は、第７線状部材３１７、第６線状部材３１６、第５線状部材３１５、第４線状部材３１４、第３線状部材３１３の順に大きくなっている。 In the chip-shaped electronic component jig 300 according to the third embodiment of the present invention, the wire diameters of the plurality of linear members 310 are different from each other for some of the plurality of linear members 310. Specifically, the wire diameters of the plurality of linear members 310 are the 7th linear member 317, the 6th linear member 316, the 5th linear member 315, the 4th linear member 314, and the 3rd linear member 313. It is increasing in the order of.
　複数の線状部材３１０の各々の線径が上記のように順に大きくなっていることにより、底部１２０に平行な方向において互いに隣り合う線状部材３１０同士の距離の寸法は、第７線状部材３１７、第６線状部材３１６、第５線状部材３１５、第４線状部材３１４、第３線状部材３１３の順に小さくなっている。 Since the wire diameters of the plurality of linear members 310 are gradually increased as described above, the dimension of the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom 120 is the seventh linear member. The size decreases in the order of 317, the sixth linear member 316, the fifth linear member 315, the fourth linear member 314, and the third linear member 313.
　また、本実施形態においては、内接円１４１の直径Ｄは、底部１２０に直交する方向におけるどの位置においても、常に上記式(１)が満たされるように、設定されている。 Further, in the present embodiment, the diameter D of the inscribed circle 141 is set so that the above equation (1) is always satisfied at any position in the direction orthogonal to the bottom portion 120.
　なお、本発明の各実施形態に係るチップ状電子部品用治具は、上記式(１)を満たさないチップ収納部を含んでいてもよい。上記式(１)を満たさないチップ収納部においては、線状部材同士の間を流れるガスの流れを制御することができる。また、側壁部を構成する線状部材を密に配置してもよい。これにより、チップ状電子部品用治具の強度を高めることができる。さらには、本発明の各実施形態に係るチップ状電子部品用治具は、チップ状電子部品を挿入できない大きさの、単なる隙間を有していてもよい。 Note that the jig for chip-shaped electronic components according to each embodiment of the present invention may include a chip accommodating portion that does not satisfy the above formula (1). In the chip accommodating portion that does not satisfy the above formula (1), the flow of gas flowing between the linear members can be controlled. Further, the linear members forming the side wall portion may be densely arranged. As a result, the strength of the jig for chip-shaped electronic parts can be increased. Further, the jig for a chip-shaped electronic component according to each embodiment of the present invention may have a mere gap having a size in which the chip-shaped electronic component cannot be inserted.
　上述した実施形態の説明において、組み合わせ可能な構成を相互に組み合わせてもよい。たとえば、板状部材で構成された底部と、複数の線状部材で構成された側壁部とを組み合わることでチップ状電子部品用治具を構成してもよい。すなわち、底部は、チップ収納部内のチップ状電子部品が抜け落ちることを防止できるものであれば、底部の形状、底部の線状部材に対する相対的な位置は、特に限定されるものではない。線状部材が底部を構成する場合、複数の第１線状部材および複数の第２線状部材の各々の面内における延在方向は、特に限定されない。複数の線状部材は、１つのチップ収納部あたり複数の第１線状部材または複数の第２線状部材が底部を形成するように構成されていてもよい。線状部材の断面形状は、多角形でもよい。チップ状電子部品用治具は、底部を挟んで、底部の両側に前記チップ状電子部品を挿入可能に開口している側壁部を有していてもよい。 In the description of the above-described embodiment, the configurations that can be combined may be combined with each other. For example, a jig for a chip-shaped electronic component may be formed by combining a bottom portion made of a plate-shaped member and a side wall portion made of a plurality of linear members. That is, the shape of the bottom and the relative position of the bottom with respect to the linear member are not particularly limited as long as the bottom can prevent the chip-shaped electronic component in the chip storage portion from falling off. When the linear member constitutes the bottom, the extending direction in each plane of the plurality of first linear members and the plurality of second linear members is not particularly limited. The plurality of linear members may be configured such that a plurality of first linear members or a plurality of second linear members form a bottom portion per chip accommodating portion. The cross-sectional shape of the linear member may be polygonal. The jig for a chip-shaped electronic component may have side wall portions that are open on both sides of the bottom portion so that the chip-shaped electronic component can be inserted.
　今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the claims.
　１０　チップ状電子部品、１００，２００，３００，９００　チップ状電子部品用治具、１１０，２１０，３１０　線状部材、１１１，９１１　第１線状部材、１１２，９１２　第２線状部材、１１３，３１３，９１３　第３線状部材、１１４，３１４，９１４　第４線状部材、１１５，３１５　第５線状部材、１１６，３１６　第６線状部材、１１７，３１７　第７線状部材、１２０　底部、１３０　側壁部、１４０，２４０，３４０，９４０　チップ収納部、１４１，２４１　内接円、２１８　第８線状部材、２１９　第９線状部材。 10 Chip-shaped electronic components, 100, 200, 300, 900 Chip-shaped electronic component jigs, 110, 210, 310 Linear members, 111,911 1st linear member, 112,912 2nd linear member, 113, 313,913 3rd linear member, 114,314,914 4th linear member, 115,315 5th linear member, 116,316 6th linear member 117,317 7th linear member, 120 bottom, 130 side wall, 140, 240, 340, 940 chip storage, 141,241 inscribed circles, 218 8th linear member, 219 9th linear member.

Claims (8)

  1. 　チップ状電子部品を収納する複数のチップ収納部を備え、
    　前記複数のチップ収納部の各々は、
    　前記チップ状電子部品を支持する底部と、
    　前記チップ状電子部品を挿入可能に開口している側壁部とを含み、
    　前記複数のチップ収納部の各々において、前記底部と直交する方向から見たときの前記側壁部の内接円の直径Ｄの寸法と、前記複数のチップ収納部の各々の深さＺの寸法とが、下記式(１)の関係を満たす、チップ状電子部品用治具。
    　(Ｄ／２）＜Ｚ＜（３√２／２）Ｄ　・・・（１）     Equipped with multiple chip storage units for storing chip-shaped electronic components
    Each of the plurality of chip storage units
    The bottom that supports the chip-shaped electronic component and
    Including a side wall portion that is open so that the chip-shaped electronic component can be inserted.
    In each of the plurality of chip storage portions, the dimension of the diameter D of the inscribed circle of the side wall portion when viewed from the direction orthogonal to the bottom portion and the dimension of the depth Z of each of the plurality of chip storage portions. However, a jig for chip-shaped electronic parts that satisfies the relationship of the following formula (1).
    (D / 2) <Z <(3√2 / 2) D ... (1)
  2. 　前記複数のチップ収納部の各々において、前記側壁部の内接円の直径Ｄの寸法と、前記複数のチップ収納部の各々の深さＺの寸法とが、下記式(２)の関係を満たす、請求項１に記載のチップ状電子部品用治具。
    　(Ｄ／２）＜Ｚ＜（√２）Ｄ　・・・（２）     In each of the plurality of chip storage portions, the dimension of the diameter D of the inscribed circle of the side wall portion and the dimension of the depth Z of each of the plurality of chip storage portions satisfy the relationship of the following formula (2). , The jig for chip-shaped electronic parts according to claim 1.
    (D / 2) <Z <(√2) D ... (2)
  3. 　前記複数のチップ収納部を、前記底部と直交する方向において底部側とは反対側から見たときに、前記複数のチップ収納部の各々の開口形状が、多角形状である、請求項１または請求項２に記載のチップ状電子部品用治具。 1 or claim 1, wherein each of the plurality of chip storage portions has a polygonal opening shape when viewed from a side opposite to the bottom side in a direction orthogonal to the bottom portion. Item 2. The jig for chip-shaped electronic parts according to item 2.
  4. 　前記複数のチップ収納部を、前記底部と直交する方向において底部側とは反対側から見たときに、前記複数のチップ収納部の各々の開口形状が、円形状である、請求項１または請求項２に記載のチップ状電子部品用治具。 1 or claim 1, wherein when the plurality of chip storage portions are viewed from a side opposite to the bottom side in a direction orthogonal to the bottom portion, the opening shape of each of the plurality of chip storage portions is circular. Item 2. The jig for chip-shaped electronic parts according to item 2.
  5. 　前記複数のチップ収納部の各々が、前記底部と直交する方向において、底部側から、底部側とは反対側に向かうにしたがって、開口寸法が大きくなっている、請求項１から請求項４のいずれか１項に記載のチップ状電子部品用治具。 Any of claims 1 to 4, wherein each of the plurality of chip accommodating portions has an opening size that increases from the bottom side to the side opposite to the bottom side in a direction orthogonal to the bottom portion. The jig for chip-shaped electronic parts according to item 1.
  6. 　直線状の複数の線状部材が互いに積層されることで構成されている、請求項１から請求項５のいずれか１項に記載のチップ状電子部品用治具。 The jig for chip-shaped electronic components according to any one of claims 1 to 5, wherein a plurality of linear linear members are laminated on each other.
  7. 　前記複数の線状部材の各々の線径Ｒの寸法が、前記複数のチップ収納部の各々の深さＺの寸法の１／２未満である、請求項６に記載のチップ状電子部品用治具。 The jig for chip-shaped electronic components according to claim 6, wherein the dimension of the wire diameter R of each of the plurality of linear members is less than 1/2 of the dimension of the depth Z of each of the plurality of chip accommodating portions. Ingredients.
  8. 　セラミックスで構成されている、請求項１から請求項７のいずれか１項に記載のチップ状電子部品用治具。 The jig for chip-shaped electronic components according to any one of claims 1 to 7, which is made of ceramics.
PCT/JP2020/023940 2019-08-23 2020-06-18 Jig for chip-like electronic component WO2021039048A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020227003848A KR102587640B1 (en) 2019-08-23 2020-06-18 Jig for chip-shaped electronic components
CN202080058002.XA CN114402408A (en) 2019-08-23 2020-06-18 Clip for chip electronic component
JP2021542034A JP7327489B2 (en) 2019-08-23 2020-06-18 Jigs for chip-shaped electronic components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019152874 2019-08-23
JP2019-152874 2019-08-23

Publications (1)

Publication Number Publication Date
WO2021039048A1 true WO2021039048A1 (en) 2021-03-04

Family

ID=74685826

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/023940 WO2021039048A1 (en) 2019-08-23 2020-06-18 Jig for chip-like electronic component

Country Status (4)

Country Link
JP (1) JP7327489B2 (en)
KR (1) KR102587640B1 (en)
CN (1) CN114402408A (en)
WO (1) WO2021039048A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06290916A (en) * 1993-03-31 1994-10-18 Taiyo Yuden Co Ltd Holder for heat treatment of electronic component and heat treatment
JP3062441U (en) * 1999-02-25 1999-10-08 コーア株式会社 Transfer jig
JP2007194510A (en) * 2006-01-20 2007-08-02 Tdk Corp Ceramic electronic part jig, and method for manufacturing ceramic electronic part using same
JP2008053327A (en) * 2006-08-23 2008-03-06 Hirai Seimitsu Kogyo Corp Holding jig
JP2008177188A (en) * 2007-01-16 2008-07-31 Tdk Corp Tool for chip electronic component
JP2012144433A (en) * 2012-04-20 2012-08-02 Tdk Corp Degreasing tool

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612154A (en) 1979-07-10 1981-02-06 Tamura Electric Works Ltd Answer signal transmission system
JPS60243483A (en) * 1984-05-17 1985-12-03 三菱電機株式会社 Bedplate for baking
JPS6290916A (en) * 1985-08-16 1987-04-25 旭硝子株式会社 Electrode for electric double-layer capacitor
JP6462102B2 (en) * 2017-12-11 2019-01-30 三井金属鉱業株式会社 Ceramic lattice

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06290916A (en) * 1993-03-31 1994-10-18 Taiyo Yuden Co Ltd Holder for heat treatment of electronic component and heat treatment
JP3062441U (en) * 1999-02-25 1999-10-08 コーア株式会社 Transfer jig
JP2007194510A (en) * 2006-01-20 2007-08-02 Tdk Corp Ceramic electronic part jig, and method for manufacturing ceramic electronic part using same
JP2008053327A (en) * 2006-08-23 2008-03-06 Hirai Seimitsu Kogyo Corp Holding jig
JP2008177188A (en) * 2007-01-16 2008-07-31 Tdk Corp Tool for chip electronic component
JP2012144433A (en) * 2012-04-20 2012-08-02 Tdk Corp Degreasing tool

Also Published As

Publication number Publication date
JPWO2021039048A1 (en) 2021-03-04
KR102587640B1 (en) 2023-10-11
KR20220027240A (en) 2022-03-07
CN114402408A (en) 2022-04-26
JP7327489B2 (en) 2023-08-16

Similar Documents

Publication Publication Date Title
US9947476B2 (en) Multilayer ceramic capacitor, multilayer ceramic capacitor series including the same, and multilayer ceramic capacitor mount body including the same
US9941052B2 (en) Multilayer ceramic capacitor
JP4941585B2 (en) Ceramic electronic component, method for manufacturing ceramic electronic component, and method for packing ceramic electronic component
US20120297608A1 (en) Component aligning apparatus and electronic component manufacturing method
JP4737440B2 (en) Chip electronic component jig
JP2019179778A (en) Multilayer ceramic capacitor and mounting structure of the same
BRPI0722314A2 (en) SINTERED POROS STRUCTURE AND METHOD
KR101218985B1 (en) Chip-type coil component
CN105869886A (en) MULTILAYER CERAMIC COMPONENT and plate having the MULTILAYER CERAMIC COMPONENT
JP6801641B2 (en) Inductor parts
JP6569451B2 (en) Multilayer coil parts
WO2021039048A1 (en) Jig for chip-like electronic component
WO2021039047A1 (en) Chip-like electronic component jig
WO2021075357A1 (en) Chip-shaped electronic component jig
JP2009065004A (en) Arraying method for chip type electronic component and arraying device for chip type electronic component
CN114503230B (en) Setter for chip electronic component
JP2005276513A (en) Manufacturing method for surge absorber
JP2021068771A (en) Jig for chip-shaped electronic component
JP2007194510A (en) Ceramic electronic part jig, and method for manufacturing ceramic electronic part using same
JP2006310762A (en) Tool and process for manufacturing chip electronic component
WO2022176297A1 (en) Jig for manufacturing electronic component and method for manufacturing electronic component
WO2021140775A1 (en) Ceramic structure
JP2021068769A (en) Chip-like electronic component jig
JP3692920B2 (en) Parts sorting method, parts sorting jig and parts sorting apparatus
JP2003124007A (en) Ntc thermistor element

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20855989

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20227003848

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2021542034

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20855989

Country of ref document: EP

Kind code of ref document: A1