JP7327489B2 - Jigs for chip-shaped electronic components - Google Patents

Jigs for chip-shaped electronic components Download PDF

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JP7327489B2
JP7327489B2 JP2021542034A JP2021542034A JP7327489B2 JP 7327489 B2 JP7327489 B2 JP 7327489B2 JP 2021542034 A JP2021542034 A JP 2021542034A JP 2021542034 A JP2021542034 A JP 2021542034A JP 7327489 B2 JP7327489 B2 JP 7327489B2
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chip
linear members
shaped electronic
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jig
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JPWO2021039048A5 (en
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雄太 田中
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Murata Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G13/00Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Packaging Frangible Articles (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

本発明は、チップ状電子部品用治具に関する。 The present invention relates to a jig for chip-shaped electronic components.

チップ状電子部品用治具を開示した先行文献として、特開2008-177188号公報(特許文献1)および特許第6259943号(特許文献2)がある。 Japanese Patent Application Laid-Open No. 2008-177188 (Patent Document 1) and Japanese Patent No. 6259943 (Patent Document 2) are prior art documents that disclose jigs for chip-shaped electronic components.

特許文献1に記載のチップ状電子部品用治具は、支持部材と、受け部材とを含み、チップ状電子部品の処理に用いられる治具である。支持部材は、金属材料からなる。支持部材は、全体として平面状であって、その面内に多数の貫通するチップ挿入孔を有している。受け部材は、金属経線と金属緯線とを織り込んだ網状体である。受け部材は、支持部材の一面に接合され、チップ挿入孔の開口面内に、少なくとも1つの交差部が存在している。 A jig for chip-shaped electronic components described in Patent Document 1 includes a support member and a receiving member, and is a jig used for processing chip-shaped electronic components. The support member is made of metal material. The support member has a planar shape as a whole and has a large number of chip insertion holes penetrating therethrough. The receiving member is a net-like body in which metal meridians and metal wefts are woven. The receiving member is joined to one surface of the supporting member, and has at least one intersection within the opening surface of the chip insertion hole.

特許文献2に記載のチップ状電子部品用治具は、セラミックス格子体であり、複数の第1の線条部と、複数の第2の線条部とを有している。複数の第1の線条部の各々は、セラミックス製であり、一方向に向けて延びている。複数の第2の線条部の各々は、セラミックス製であり、第1の線条部と交差する方向に向けて延びている。第1の線条部と第2の線条部との交差部は、いずれの交差部においても、第1の線条部上に第2の線条部が配されている。交差部において、第1の線条部は、その断面が、直線部と、直線部の両端部を端部とする凸形の曲線部とから構成される形状を有している。交差部において、第2の線条部は、その断面が、円形又は楕円形の形状を有している。交差部の縦断面視において、第1の線条部と第2の線条部とは、第1の線条部における凸形の曲線部の頂部と、第2の線条部における円形または楕円形における下向きに凸の頂部のみが接触している。 The jig for chip-shaped electronic components described in Patent Document 2 is a ceramic lattice body and has a plurality of first filamentary portions and a plurality of second filamentary portions. Each of the plurality of first filaments is made of ceramics and extends in one direction. Each of the plurality of second filamentary portions is made of ceramics and extends in a direction intersecting with the first filamentary portions. The second filamentary portion is arranged on the first filamentary portion at any intersection of the first filamentary portion and the second filamentary portion. At the crossing portion, the first filamentary portion has a shape whose cross section is composed of a linear portion and a convex curved portion having ends at both ends of the linear portion. At the intersection, the second filaments have a circular or elliptical shape in cross section. In a vertical cross-sectional view of the crossing portion, the first filament portion and the second filament portion are the top of the convex curved portion of the first filament portion and the circular or elliptical shape of the second filament portion. Only the downwardly convex tops of the shapes are in contact.

特開2008-177188号公報JP 2008-177188 A 特許第6259943号公報Japanese Patent No. 6259943

従来のチップ状電子部品用治具においては、複数のチップ収納部の開口側から、チップ状電子部品用治具上に複数のチップ状電子部品をばらまいた後、チップ状電子部品用治具を揺動させる。これにより、複数のチップ収納部の各々に、チップ状電子部品が挿入される。チップ収納部に入りきらず、チップ状電子部品用治具上の余ったチップ状電子部品は、チップ状電子部品用治具を傾けて振るい落とす。 In the conventional chip-shaped electronic component jig, after scattering a plurality of chip-shaped electronic components on the chip-shaped electronic component jig from the opening side of the plurality of chip storage portions, the chip-shaped electronic component jig is removed. oscillate. Thereby, a chip-like electronic component is inserted into each of the plurality of chip storage portions. The chip-shaped electronic components that do not fit in the chip storage section and remain on the chip-shaped electronic component jig are shaken off by tilting the chip-shaped electronic component jig.

このため、複数のチップ収納部において、1つのチップ収納部に1つのチップ状電子部品を挿入するためには、チップ収納部の深さの寸法および開口面積を適切に設定する必要がある。たとえば、チップ状電子部品の開口面積が小さすぎると、チップ収納部にチップ状電子部品を挿入するのに時間がかかる。また、チップ状電子部品の開口面積が大きすぎると、1つのチップ収納部に2つのチップ状電子部品が入る。これにより、チップ状電子部品用治具を用いたチップ状電子部品の焼成においては、焼成ムラが発生するおそれがある。また、チップ収納部の深さの寸法が小さすぎると、余ったチップ状電子部品を振るい落とす際に、チップ収納部に収納されたチップ状電子部品も振るい落とされるおそれがある。さらに、チップ収納部の深さの寸法が大き過ぎると、深さ方向に2つのチップ状電子部品が並んで挿入されたときに、上側のチップ状電子部品のみを振るい落とすことができないおそれがある。 For this reason, in order to insert one chip-like electronic component into one of the plurality of chip housings, it is necessary to appropriately set the depth dimension and opening area of the chip housing. For example, if the opening area of the chip-shaped electronic component is too small, it will take time to insert the chip-shaped electronic component into the chip storage portion. Also, if the opening area of the chip-shaped electronic component is too large, two chip-shaped electronic components can be accommodated in one chip storage portion. As a result, uneven firing may occur in the firing of chip-shaped electronic components using the chip-shaped electronic component jig. Further, if the depth of the chip storage portion is too small, there is a risk that the electronic chip components stored in the chip storage portion may also be shaken off when the surplus chip-shaped electronic components are shaken off. Furthermore, if the depth dimension of the chip storage portion is too large, when two chip-like electronic components are inserted side by side in the depth direction, there is a possibility that only the upper chip-like electronic component cannot be shaken off. .

本発明は上記の課題に鑑みてなされたものであり、複数のチップ収納部において、1つのチップ収納部に1つのチップ状電子部品を容易に挿入できる、チップ状電子部品用治具を提供することを目的とする。 SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a jig for chip-shaped electronic components that allows one chip-shaped electronic component to be easily inserted into one of a plurality of chip housings. for the purpose.

本発明に基づくチップ状電子部品用治具は、チップ状電子部品を収納する複数のチップ収納部を備えている。複数のチップ収納部の各々は、底部と、側壁部とを含んでいる。底部は、チップ状電子部品を支持する。側壁部は、チップ状電子部品を挿入可能に開口している。複数のチップ収納部の各々において、底部と直交する方向から見たときの側壁部の内接円の直径Dの寸法と、複数のチップ収納部の各々の深さZの寸法とが、下記式(1)の関係を満たしている。 A jig for chip-shaped electronic components according to the present invention includes a plurality of chip storage units for storing chip-shaped electronic components. Each of the plurality of chip storages includes a bottom and side walls. The bottom supports chip-like electronic components. The side wall is open so that the chip-like electronic component can be inserted. In each of the plurality of chip storage portions, the dimension of the diameter D of the inscribed circle of the side wall when viewed from the direction orthogonal to the bottom and the dimension of the depth Z of each of the plurality of chip storage portions are calculated by the following formula. It satisfies the relationship of (1).

(D/2)<Z<(3√2/2)D ・・・(1) (D/2)<Z<(3√2/2)D (1)

本発明によれば、複数のチップ収納部において、1つのチップ収納部に1つのチップ状電子部品を容易に挿入することができる。 According to the present invention, one chip-shaped electronic component can be easily inserted into one chip storage portion among a plurality of chip storage portions.

本発明の実施形態1に係るチップ状電子部品用治具の構成を示す平面図である。1 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 1 of the present invention; FIG. 図1に示すチップ状電子部品用治具を矢印II方向から見た図である。It is the figure which looked at the jig|tool for chip-shaped electronic components shown in FIG. 1 from the arrow II direction. 本発明の実施形態1に係るチップ状電子部品用治具におけるチップ収納部の構成を示す平面図である。FIG. 3 is a plan view showing the configuration of a chip storage portion in the chip-shaped electronic component jig according to Embodiment 1 of the present invention; 図3に示すチップ収納部をIV-IV線矢印方向から見た断面図である。FIG. 4 is a cross-sectional view of the chip storage portion shown in FIG. 3 as viewed from the direction of the arrows on line IV-IV. 比較例に係るチップ状電子部品用治具の一部の構成を示す正面図である。FIG. 5 is a front view showing a configuration of a part of a jig for chip-like electronic components according to a comparative example; 本発明の実施形態2に係るチップ状電子部品用治具の構成を示す平面図である。FIG. 5 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 2 of the present invention; 図6に示すチップ状電子部品用治具を矢印VII方向から見た図である。It is the figure which looked at the jig|tool for chip-shaped electronic components shown in FIG. 6 from the arrow VII direction. 本発明の実施形態3に係るチップ状電子部品用治具の構成を示す平面図である。FIG. 10 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 3 of the present invention;

以下、本発明の各実施形態に係るチップ状電子部品用治具について説明する。以下の実施形態の説明においては、図中の同一または相当部分には同一符号を付して、その説明は繰り返さない。 Hereinafter, jigs for chip-shaped electronic components according to respective embodiments of the present invention will be described. In the following description of the embodiments, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated.

(実施形態1)
図1は、本発明の実施形態1に係るチップ状電子部品用治具の構成を示す平面図である。図2は、図1に示すチップ状電子部品用治具を矢印II方向から見た図である。図3は、本発明の実施形態1に係るチップ状電子部品用治具におけるチップ収納部の構成を示す平面図である。図4は、図3に示すチップ収納部をIV-IV線矢印方向から見た断面図である。
(Embodiment 1)
FIG. 1 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 1 of the present invention. FIG. 2 is a view of the chip-shaped electronic component jig shown in FIG. 1 as viewed in the direction of arrow II. FIG. 3 is a plan view showing the configuration of a chip storage portion in the chip-shaped electronic component jig according to Embodiment 1 of the present invention. FIG. 4 is a cross-sectional view of the chip storage portion shown in FIG. 3 as viewed in the direction of arrows IV-IV.

図1および図2に示すように、本発明の実施形態1に係るチップ状電子部品用治具100は、複数の線状部材110が互いに積層されることで構成されている。本実施形態において、複数の線状部材110の各々は直線状である。 As shown in FIGS. 1 and 2, a chip-shaped electronic component jig 100 according to Embodiment 1 of the present invention is configured by stacking a plurality of linear members 110 on each other. In this embodiment, each of the plurality of linear members 110 is linear.

図1および図2に示すように、本実施形態に係るチップ状電子部品用治具100は、複数の線状部材110として、複数の第1線状部材111、複数の第2線状部材112、複数の第3線状部材113、複数の第4線状部材114、複数の第5線状部材115、複数の第6線状部材116および複数の第7線状部材117を備えている。複数の第1線状部材111は、略同一平面上に配置されることで、線状部材からなる層を構成している。複数の第1線状部材111と同様に、複数の第2線状部材112から複数の第7線状部材117も、それぞれ、複数の線状部材からなる層を構成している。複数の線状部材110の詳細については後述する。 As shown in FIGS. 1 and 2, the chip-shaped electronic component jig 100 according to the present embodiment includes a plurality of first linear members 111 and a plurality of second linear members 112 as the plurality of linear members 110. , a plurality of third linear members 113 , a plurality of fourth linear members 114 , a plurality of fifth linear members 115 , a plurality of sixth linear members 116 and a plurality of seventh linear members 117 . The plurality of first linear members 111 constitute a layer of linear members by being arranged on substantially the same plane. As with the plurality of first linear members 111, the plurality of second linear members 112 to the plurality of seventh linear members 117 also form a layer made up of a plurality of linear members. Details of the plurality of linear members 110 will be described later.

本発明の実施形態1に係るチップ状電子部品用治具100は、チップ状電子部品10を収納する複数のチップ収納部140を備えている。複数のチップ収納部140の各々は、底部120と、側壁部130とを含んでいる。底部120は、チップ状電子部品10を支持する。側壁部130は、チップ状電子部品10を挿入可能に開口している。 The chip-shaped electronic component jig 100 according to Embodiment 1 of the present invention includes a plurality of chip storage sections 140 that store the chip-shaped electronic components 10 . Each of the plurality of chip storage portions 140 includes a bottom portion 120 and side wall portions 130 . The bottom part 120 supports the chip-like electronic component 10 . The side wall portion 130 is open so that the chip-like electronic component 10 can be inserted.

図2に示すように、複数のチップ収納部140の各々において、底部120は、第1線状部材111と、第2線状部材112とを有している。底部120は、チップ状電子部品10を直接支持する第2線状部材112を少なくとも有していればよく、第1線状部材111を有していなくてもよい。底部120は、第2線状部材112の側壁部130側、または、第1線状部材111の第2線状部材112側とは反対側に、追加の層をさらに有していてもよい。底部120は、追加の層として、1層の追加の層または複数の追加の層を有していてもよい。側壁部130は、2本の第3線状部材113と、2本の第4線状部材114と、2本の第5線状部材115と、2本の第6線状部材116と、2本の第7線状部材117とを有している。側壁部130は、底部120と直交する方向において底部120側とは反対側から見たときに、チップ収納部140の開口を形成するという観点から、2本の第3線状部材113および2本の第4線状部材114を少なくとも有していればよい。側壁部130は、第5線状部材115、第6線状部材116および第7線状部材117を有していなくてもよい。 As shown in FIG. 2 , in each of the plurality of chip storage portions 140 , the bottom portion 120 has a first linear member 111 and a second linear member 112 . The bottom portion 120 may have at least the second linear members 112 that directly support the chip-like electronic component 10 , and may not have the first linear members 111 . The bottom portion 120 may further have an additional layer on the side wall portion 130 side of the second linear member 112 or on the side of the first linear member 111 opposite to the second linear member 112 side. The bottom 120 may have one additional layer or multiple additional layers as the additional layers. The side wall portion 130 includes two third linear members 113, two fourth linear members 114, two fifth linear members 115, two sixth linear members 116, and two linear members 116. It has a book seventh linear member 117 . Side wall portion 130 has two third linear members 113 and two linear members 113 and 2 linear members 113 from the viewpoint of forming an opening of chip storage portion 140 when viewed from the side opposite to bottom portion 120 in a direction perpendicular to bottom portion 120 . at least the fourth linear member 114 . Side wall portion 130 may not have fifth linear member 115 , sixth linear member 116 and seventh linear member 117 .

なお、チップ状電子部品用治具100は、複数の線状部材110に代えて、全体が板状部材で構成されていてもよい。チップ状電子部品用治具100の全体が板状部材で構成される場合には、上記板状部材に対して、一方側の面から複数の孔部を形成することにより、当該複数の孔部を複数のチップ収納部140としてもよい。この場合、当該板状部材において、複数の孔部の各々の底面側の部分が底部120を構成し、複数の孔部の各々の周側面側の部分が側壁部130を構成する。 Note that the chip-shaped electronic component jig 100 may be entirely composed of a plate-shaped member instead of the plurality of linear members 110 . When the chip-shaped electronic component jig 100 is entirely composed of a plate-shaped member, a plurality of holes are formed in the plate-shaped member from one side surface, thereby forming the plurality of holes. may be used as a plurality of chip storage units 140 . In this case, in the plate-shaped member, the bottom portion 120 of each of the plurality of holes constitutes the bottom portion, and the peripheral side portion of each of the plurality of holes constitutes the side wall portion 130 .

本実施形態に係るチップ状電子部品用治具100を構成する複数の線状部材110について説明する。 A plurality of linear members 110 constituting the chip-shaped electronic component jig 100 according to the present embodiment will be described.

図1および図2に示すように、複数の第1線状部材111の各々は、互いに等間隔に1方向に並んで延在している。複数の第2線状部材112の各々は、底部120に直交する方向から見たときに、複数の第1線状部材111の各々と直交しつつ、互いに等間隔に並んで延在している。複数の第2線状部材112の各々は、複数の第1線状部材111の上側に位置している。 As shown in FIGS. 1 and 2, each of the plurality of first linear members 111 extends in one direction at equal intervals. When viewed from the direction perpendicular to the bottom portion 120, each of the plurality of second linear members 112 extends perpendicular to each of the plurality of first linear members 111 and is aligned with each other at equal intervals. . Each of the plurality of second linear members 112 is positioned above the plurality of first linear members 111 .

本実施形態においては、1本の第2線状部材112が、1つのチップ収納部140に収容された1つのチップ状電子部品10を直接支持する。底部120に直交する方向から見たときに、1本の第2線状部材112が、互いに隣り合う第6線状部材116同士の間の中央に位置し、1本の第1線状部材111が、互いに隣り合う第7線状部材117同士の間の中央に位置する。つまり、チップ収納部140の略中央において、1本の第1線状部材111と1本の第2線状部材112とが互いに直交している。なお、底部120に直交する方向から見たときに、第2線状部材112は、互いに隣り合う第6線状部材116同士の間に複数本あってもよく、互いに隣り合う第6線状部材116同士の間の中央ではない場所に位置してもよい。 In this embodiment, one second linear member 112 directly supports one chip-like electronic component 10 housed in one chip housing portion 140 . When viewed from the direction orthogonal to the bottom portion 120 , one second linear member 112 is positioned in the center between the mutually adjacent sixth linear members 116 and one first linear member 111 . is located at the center between the seventh linear members 117 adjacent to each other. In other words, one first linear member 111 and one second linear member 112 are perpendicular to each other at substantially the center of the chip storage portion 140 . In addition, when viewed from the direction orthogonal to the bottom portion 120, a plurality of the second linear members 112 may be present between the sixth linear members 116 adjacent to each other. It may be located at a non-central location between 116 .

複数の第3線状部材113は、複数の第2線状部材112の上側に位置している。複数の第3線状部材113の各々は、底部120に直交する方向から見たときに、複数の第2線状部材112の各々と直角に交差しつつ、互いに等間隔に離間して並んで延在している。すなわち、複数の第3線状部材113の各々は、底部120に直交する方向から見たときに、複数の第1線状部材111の延在方向と平行に延在している。本実施形態においては、底部120に直交する方向から見たときに、複数の第3線状部材113の各々は、一部の複数の第1線状部材111の各々と重なるように位置している。底部120に平行な方向から見ると、複数の第2線状部材112からなる層が、複数の第1線状部材111からなる層と、複数の第3線状部材113からなる層との間に位置しているため、底部120に直交する方向から見たときに互いに重なり合う第1線状部材111と第3線状部材113との間において、第2線状部材112が存在しない位置には、隙間が形成されている。 The plurality of third linear members 113 are positioned above the plurality of second linear members 112 . Each of the plurality of third linear members 113 crosses each of the plurality of second linear members 112 at right angles when viewed from a direction perpendicular to the bottom portion 120, and is arranged at regular intervals from each other. extended. That is, each of the plurality of third linear members 113 extends parallel to the extending direction of the plurality of first linear members 111 when viewed from the direction perpendicular to the bottom portion 120 . In the present embodiment, each of the plurality of third linear members 113 is positioned so as to overlap each of some of the plurality of first linear members 111 when viewed from the direction perpendicular to the bottom portion 120 . there is When viewed in a direction parallel to the bottom portion 120, the layer composed of the plurality of second linear members 112 is positioned between the layer composed of the plurality of first linear members 111 and the layer composed of the plurality of third linear members 113. Therefore, between the first linear member 111 and the third linear member 113 that overlap each other when viewed from the direction orthogonal to the bottom portion 120, the position where the second linear member 112 does not exist , a gap is formed.

複数の第4線状部材114は、複数の第3線状部材113の上側に位置している。複数の第4線状部材114の各々は、底部120に直交する方向から見たときに、複数の第3線状部材113の各々と直角に交差しつつ、互いに等間隔に離間して並んで延在している。すなわち、複数の第4線状部材114の各々は、底部120に直交する方向から見たときに、複数の第2線状部材112の延在方向と平行に延在している。本実施形態においては、底部120に直交する方向から見たときに、複数の第4線状部材114の各々は、一部複数の第2線状部材112の各々と重なるように位置している。底部120に平行な方向から見ると、複数の第3線状部材113からなる層が、複数の第2線状部材112からなる層と、複数の第4線状部材114からなる層との間に位置しているため、底部120に直交する方向から見たときに互いに重なり合う第2線状部材112と第4線状部材114との間において、第3線状部材113が存在しない位置には、隙間が形成されている。 The plurality of fourth linear members 114 are positioned above the plurality of third linear members 113 . When viewed from the direction orthogonal to the bottom portion 120, each of the plurality of fourth linear members 114 crosses each of the plurality of third linear members 113 at right angles, and is spaced apart from each other at regular intervals. extended. That is, each of the plurality of fourth linear members 114 extends parallel to the extending direction of the plurality of second linear members 112 when viewed from the direction perpendicular to the bottom portion 120 . In the present embodiment, each of the plurality of fourth linear members 114 is positioned so as to partially overlap each of the plurality of second linear members 112 when viewed from the direction orthogonal to the bottom portion 120. . When viewed in a direction parallel to the bottom portion 120, the layer composed of the plurality of third linear members 113 is positioned between the layer composed of the plurality of second linear members 112 and the layer composed of the plurality of fourth linear members 114. Therefore, between the second linear member 112 and the fourth linear member 114 that overlap each other when viewed from the direction orthogonal to the bottom portion 120, the position where the third linear member 113 does not exist , a gap is formed.

複数の第5線状部材115は、複数の第4線状部材114の上側に位置している。複数の第5線状部材115は、底部120に直交する方向から見たときに、複数の第3線状部材113と1対1で対応して重なるように位置している。複数の第6線状部材116は、複数の第5線状部材115の上側に位置している。複数の第6線状部材116は、底部120に直交する方向から見たときに、複数の第4線状部材114と1対1で対応して重なるように位置している。複数の第7線状部材117は、複数の第6線状部材116の上側に位置している。複数の第7線状部材117は、底部120に直交する方向から見たときに、複数の第5線状部材115と1対1で対応して重なるように位置している。 The plurality of fifth linear members 115 are positioned above the plurality of fourth linear members 114 . The plurality of fifth linear members 115 are positioned so as to overlap the plurality of third linear members 113 in one-to-one correspondence when viewed from the direction orthogonal to the bottom portion 120 . The plurality of sixth linear members 116 are positioned above the plurality of fifth linear members 115 . The plurality of sixth linear members 116 are positioned so as to overlap the plurality of fourth linear members 114 in one-to-one correspondence when viewed from the direction orthogonal to the bottom portion 120 . The plurality of seventh linear members 117 are positioned above the plurality of sixth linear members 116 . The plurality of seventh linear members 117 are positioned so as to overlap the plurality of fifth linear members 115 in one-to-one correspondence when viewed from the direction perpendicular to the bottom portion 120 .

本実施形態に係るチップ状電子部品用治具100は、複数の線状部材110として、複数の第7線状部材117の上側にさらに追加の線状部材を備えていてもよい。このとき、追加の線状部材は、上述した第5線状部材115、第6線状部材116および第7線状部材117の説明で示した規則性に従って積層すればよい。 The chip-shaped electronic component jig 100 according to the present embodiment may further include additional linear members above the plurality of seventh linear members 117 as the plurality of linear members 110 . At this time, the additional linear members may be laminated according to the regularity shown in the explanation of the fifth linear member 115, the sixth linear member 116 and the seventh linear member 117 described above.

このように、本実施形態に係るチップ状電子部品用治具100においては、複数の仮想平面のそれぞれの面上に、直線状の複数の線状部材110が互いに平行に、かつ、離間して配置されることで、複数の線状部材110からなる層が複数形成されている。これらの複数の層は互いに積層されており、これらの複数の層においては、ある層に含まれる線状部材110の各々と、当該層に隣接する層に含まれる線状部材110の各々とが、積層方向から見て互いに交差する。 As described above, in the chip-shaped electronic component jig 100 according to the present embodiment, a plurality of linear linear members 110 are arranged parallel to each other and spaced apart from each other on each of a plurality of virtual planes. By arranging them, a plurality of layers composed of a plurality of linear members 110 are formed. These multiple layers are stacked together, and in these multiple layers, each of the linear members 110 included in a layer and each of the linear members 110 included in the layer adjacent to the layer are , cross each other when viewed from the stacking direction.

図3に示すように、本実施形態において、第3線状部材113同士の離間距離Xの長さは、第4線状部材114同士の離間距離Yの長さと等しい。本実施形態において、上記離間距離Xの長さおよび上記離間距離Yの長さの各々は、たとえば0.1mm以上5.0mm以下である。なお、第3線状部材113同士の離間距離Xと、第4線状部材114同士の離間距離Yとは、互いに異なっていてもよい。 As shown in FIG. 3, in the present embodiment, the distance X between the third linear members 113 is equal to the distance Y between the fourth linear members 114 . In the present embodiment, each of the length of the separation distance X and the length of the separation distance Y is, for example, 0.1 mm or more and 5.0 mm or less. Note that the distance X between the third linear members 113 and the distance Y between the fourth linear members 114 may be different from each other.

図2に示すように、本実施形態において、複数の線状部材110の各々は、延在方向から見たときに略円形状の外形を有している。これらの複数の線状部材の各々は、延在方向から見たときに、矩形状、半円状または矩形状以外の多角形状の外形を有していてもよい。図4に示すように、複数の線状部材110の各々の線径Rは、底部120と平行な方向に並んでいる複数の線状部材110同士においては、互いに同一となっている。複数の線状部材110の各々の線径Rは、底部120と平行な方向に並んでいない線状部材110同士においては、互いに同一となっていてもよいし、互いに異なっていてもよい。本実施形態において、複数の線状部材110の各々の線径Rは、互いに全て同一であり、たとえば0.3mmである。複数の線状部材110のうち底部120から最も離れて位置する線状部材の線径Rは、たとえば0.2mmであってもよい。 As shown in FIG. 2, in this embodiment, each of the plurality of linear members 110 has a substantially circular outer shape when viewed from the extending direction. Each of these linear members may have a rectangular, semicircular, or polygonal shape other than a rectangular shape when viewed from the extending direction. As shown in FIG. 4 , the wire diameter R of each of the plurality of linear members 110 is the same among the plurality of linear members 110 aligned in the direction parallel to the bottom portion 120 . The wire diameter R of each of the plurality of linear members 110 may be the same or different between the linear members 110 that are not aligned in the direction parallel to the bottom portion 120 . In this embodiment, the wire diameters R of the plurality of linear members 110 are all the same, for example, 0.3 mm. The wire diameter R of the linear member located farthest from the bottom portion 120 among the plurality of linear members 110 may be, for example, 0.2 mm.

チップ状電子部品用治具100の全体が板状部材で構成される場合には、底部120の厚さは、たとえば0.2mm以上2.0mm以下であり、側壁部130の高さは、たとえば0.1mm以上8.0mm以下である。 When the chip-shaped electronic component jig 100 is entirely made of a plate member, the thickness of the bottom portion 120 is, for example, 0.2 mm or more and 2.0 mm or less, and the height of the side wall portion 130 is, for example, It is 0.1 mm or more and 8.0 mm or less.

本実施形態において、複数の線状部材110の各々は、たとえば、SiC、ジルコニア、イットリア安定化ジルコニア、アルミナもしくはムライト等のセラミックス、ニッケル、アルミニウム、インコネル(登録商標)もしくはSUSなどの金属、ポリテトラフルオロエチレン(PTFE:polytetrafluoroethylene)、ポリプロピレン(PP:polypropylene)、アクリル樹脂、ABS(Acrylonitrile butadiene styrene)ライク樹脂もしくはその他の耐熱樹脂などの樹脂材料、カーボン、または、金属とセラミックスとからなる複合材料で構成されており、本実施形態においては、セラミックスで構成されている。本実施形態においては、焼結などにより、複数の線状部材110同士が互いに接合されている。複数の線状部材110の各々の表面は、SiC、ジルコニア、イットリア、イットリア安定化ジルコニア、アルミナもしくはムライト等のセラミックス、または、ニッケルなどの金属によってさらにコーティングされていてもよい。なお、チップ状電子部品用治具100の全体が、板状部材で構成されている場合であっても、チップ状電子部品用治具100は、複数の線状部材110を構成し得る上記の材料で構成することができる。 In this embodiment, each of the plurality of linear members 110 is made of, for example, SiC, zirconia, yttria-stabilized zirconia, ceramics such as alumina or mullite, nickel, aluminum, metals such as Inconel (registered trademark) or SUS, polytetra Composed of resin materials such as fluoroethylene (PTFE: polytetrafluoroethylene), polypropylene (PP: polypropylene), acrylic resin, ABS (Acrylonitrile butadiene styrene)-like resin or other heat-resistant resins, carbon, or composite materials consisting of metal and ceramics , and in this embodiment, it is made of ceramics. In this embodiment, the plurality of linear members 110 are joined together by sintering or the like. Each surface of the plurality of linear members 110 may be further coated with ceramics such as SiC, zirconia, yttria, yttria-stabilized zirconia, alumina or mullite, or metal such as nickel. Note that even when the chip-shaped electronic component jig 100 is entirely composed of a plate-shaped member, the chip-shaped electronic component jig 100 can form the plurality of linear members 110 as described above. It can be made up of materials.

次に、複数のチップ収納部140について説明する。図3および図4に示すように、本実施形態において、複数のチップ収納部140の各々の開口端は、互いに隣り合う2つの第6線状部材116と、互いに隣り合う2つの第7線状部材117で構成されている。一方、互いに隣り合う2つのチップ収納部140は、1本の第6線状部材116あるいは1本の第7線状部材117によって区切られている。複数の第3線状部材113から複数の第5線状部材115についても、それぞれの線状部材に対応する層において、1本の線状部材が、互いに隣り合う2つのチップ収納部140を区切っている。 Next, the plurality of chip storage units 140 will be described. As shown in FIGS. 3 and 4, in the present embodiment, the open end of each of the plurality of chip storage portions 140 includes two sixth linear members 116 adjacent to each other and two seventh linear members 116 adjacent to each other. It is composed of a member 117 . On the other hand, two adjacent chip storage portions 140 are separated by one sixth linear member 116 or one seventh linear member 117 . For the plurality of third linear members 113 to the plurality of fifth linear members 115 as well, in the layer corresponding to each linear member, one linear member separates the two chip storage portions 140 adjacent to each other. ing.

本実施形態においては、複数のチップ収納部140を底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部140の各々の開口形状が、矩形状であり、具体的には、正方形状である。本実施形態においては、複数のチップ収納部140を、底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部140の各々の開口形状が、多角形状であってもよい。 In the present embodiment, when the plurality of chip storage portions 140 are viewed from the opposite side of the bottom portion 120 in the direction perpendicular to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 140 is rectangular. , specifically square. In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 140 is polygonal. There may be.

本実施形態において、複数のチップ収納部140の各々の開口の内側面は、複数の線状部材110によって形成される。具体的には、互いに隣り合う2つの第3線状部材113と、互いに隣り合う2つの第4線状部材114と、互いに隣り合う2つの第5線状部材115と、互いに隣り合う2つの第6線状部材116と、互いに隣り合う2つの第7線状部材117とによって形成されている。 In this embodiment, the inner side surface of each opening of the plurality of chip storage portions 140 is formed by the plurality of linear members 110 . Specifically, two third linear members 113 adjacent to each other, two fourth linear members 114 adjacent to each other, two fifth linear members 115 adjacent to each other, and two fifth linear members 115 adjacent to each other It is formed by 6 linear members 116 and two seventh linear members 117 adjacent to each other.

図4に示すように、本実施形態において、複数のチップ収納部140の各々の底面は、第2線状部材112によって構成されている。また、図3に示すように、底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部140の各々の底面の中心において、第1線状部材111と第2線状部材112とが互いに交差している。 As shown in FIG. 4 , in this embodiment, the bottom surface of each of the plurality of chip storage portions 140 is configured by the second linear member 112 . Further, as shown in FIG. 3, when viewed from the side opposite to the bottom portion 120 side in the direction perpendicular to the bottom portion 120, the first linear member 111 and the first linear member 111 The second linear members 112 cross each other.

ここで、本実施形態における複数のチップ収納部140に収納可能なチップ状電子部品10について説明する。図1および図2に示すように、本実施形態における複数のチップ収納部140に収納可能なチップ状電子部品10は、略直方体の形状を有している。チップ状電子部品10は、たとえば積層セラミックコンデンサに用いることができる。 Here, the chip-shaped electronic component 10 that can be stored in the plurality of chip storage portions 140 according to this embodiment will be described. As shown in FIGS. 1 and 2, the chip-shaped electronic component 10 that can be stored in the plurality of chip storage portions 140 in this embodiment has a substantially rectangular parallelepiped shape. Chip-like electronic component 10 can be used, for example, as a multilayer ceramic capacitor.

本実施形態における複数のチップ収納部140に収納可能なチップ状電子部品10は、長手方向と、幅方向と、厚さ方向とを有している。チップ状電子部品10は、底部120と直交する方向とチップ状電子部品10の長手方向とが互いに平行となるように、複数のチップ収納部140の各々に収納される。 The chip-like electronic component 10 that can be stored in the plurality of chip storage portions 140 in this embodiment has a longitudinal direction, a width direction, and a thickness direction. Chip-shaped electronic component 10 is housed in each of chip housing portions 140 such that the direction orthogonal to bottom portion 120 and the longitudinal direction of chip-shaped electronic component 10 are parallel to each other.

図1および図2に示すように、チップ状電子部品10の長手方向の長さL、幅方向の幅W、および、厚さ方向の厚さTの各々の寸法は、L:W:T=2:1:1の関係と同等の関係を有している。当該同等の関係とは、L:W:T=2:1:1の関係に対して、長さL、幅方向の幅W、および、厚さ方向の厚さTの各々の寸法が寸法差5%以内の範囲を含むことを意味している。なお、本実施形態に係るチップ状電子部品用治具100に収納可能なチップ状電子部品は、上記の各寸法関係を有するチップ状電子部品10に限定されるものではない。たとえば、本実施形態に係るチップ状電子部品用治具100には、L:W:T=2:1.25:1.25の関係と同等の関係を有するチップ状電子部品を収納してもよい。 As shown in FIGS. 1 and 2, the length L in the longitudinal direction, the width W in the width direction, and the thickness T in the thickness direction of the chip-shaped electronic component 10 are L:W:T= It has a relationship equivalent to a 2:1:1 relationship. The equivalent relationship means that each dimension of the length L, the width W in the width direction, and the thickness T in the thickness direction is different from the relationship of L:W:T=2:1:1. It is meant to include a range within 5%. Note that the chip-like electronic components that can be accommodated in the chip-like electronic component jig 100 according to the present embodiment are not limited to the chip-like electronic components 10 having the above-described dimensional relationships. For example, the chip-shaped electronic component jig 100 according to the present embodiment may accommodate chip-shaped electronic components having a relationship equivalent to the relationship of L:W:T=2:1.25:1.25. good.

本実施形態に係るチップ状電子部品用治具100に収納可能なチップ状電子部品10の長手方向の長さLは、たとえば0.6mm以上3.8mm以下であり、幅方向の幅Wは、たとえば0.3mm以上3.0mm以下であり、厚さ方向の厚さTは、たとえば0.3mm以上3.0mm以下である。チップ状電子部品10をチップ状電子部品用治具100を用いて焼成する場合には、焼成後のチップ状電子部品10の上記長さL、上記幅W、上記厚さTの各寸法が、たとえば積層セラミックコンデンサの積層体などの電子部品に用いられる際に適切な寸法となるように、焼成前において、チップ状電子部品10に係る各寸法が上記の範囲内で適宜設定される。 The longitudinal length L of the chip-shaped electronic component 10 that can be accommodated in the chip-shaped electronic component jig 100 according to the present embodiment is, for example, 0.6 mm or more and 3.8 mm or less, and the width W in the width direction is For example, it is 0.3 mm or more and 3.0 mm or less, and the thickness T in the thickness direction is, for example, 0.3 mm or more and 3.0 mm or less. When the chip-shaped electronic component 10 is fired using the chip-shaped electronic component jig 100, each dimension of the length L, the width W, and the thickness T of the chip-shaped electronic component 10 after firing is For example, each dimension of the chip-shaped electronic component 10 is appropriately set within the above range before firing so that the chip-like electronic component 10 has appropriate dimensions when used as an electronic component such as a laminated body of a multilayer ceramic capacitor.

本実施形態に係るチップ状電子部品用治具100においては、複数のチップ収納部140の各々の開口の形状に係る各寸法は、本実施形態におけるチップ状電子部品10の長手方向の長さL、幅方向の幅W、および、厚さ方向の厚さTの各々が、上述のL:W:T=2:1:1の関係を有していることを考慮して、設定される。以下、本実施形態における複数のチップ収納部140の各々の開口の形状に係る各寸法について説明する。 In the chip-shaped electronic component jig 100 according to the present embodiment, each dimension related to the shape of each opening of the plurality of chip storage portions 140 is the length L of the chip-shaped electronic component 10 in the present embodiment in the longitudinal direction. , the width W in the width direction, and the thickness T in the thickness direction are set in consideration of the relationship of L:W:T=2:1:1. Hereinafter, each dimension related to the shape of each opening of the plurality of chip storage portions 140 in this embodiment will be described.

図1および図3に示すように、複数のチップ収納部140の各々において、底部120と直交する方向から見たときの複数のチップ収納部140の各々の内接円141の直径Dは、複数のチップ収納部140の各々にチップ状電子部品10が収納されたときに、チップ状電子部品10が、長手方向に沿った軸を中心軸として回転可能となるように、設定される。たとえば、本実施形態において、幅方向の幅Wおよび厚さ方向の厚さTの各々の長さがaである場合、上記内接円141の直径Dは、チップ状電子部品10の幅方向の稜線および厚さ方向の稜線で構成される矩形形状の対角線の長さである(√2)aより大きくなるように設定される(D>(√2)a)。これにより、チップ状電子部品10に対して十分な大きさの複数のチップ収納部140が確保でき、チップ状電子部品10をチップ収納部に挿入するときにかかる時間を短縮できる。なお、上記幅方向の幅Wおよび上記厚さ方向の厚さTが互いに異なる場合においては、上記内接円141の直径Dは、およそ√(W2+T2)より大きくなるように設定される。As shown in FIGS. 1 and 3, in each of the plurality of tip storage portions 140, the diameter D of the inscribed circle 141 of each of the plurality of tip storage portions 140 when viewed from the direction orthogonal to the bottom portion 120 is When the electronic chip component 10 is accommodated in each of the chip accommodation units 140, the electronic chip component 10 is set so as to be rotatable about the axis along the longitudinal direction. For example, in the present embodiment, if the length of each of the width W in the width direction and the thickness T in the thickness direction is a, the diameter D of the inscribed circle 141 is equal to It is set to be larger than (√2)a, which is the length of the diagonal line of the rectangular shape composed of the ridgeline and the ridgeline in the thickness direction (D>(√2)a). As a result, a plurality of chip storage portions 140 having a size sufficient for the chip-shaped electronic component 10 can be secured, and the time required to insert the chip-shaped electronic component 10 into the chip storage portion can be shortened. When the width W in the width direction and the thickness T in the thickness direction are different from each other, the diameter D of the inscribed circle 141 is set to be larger than approximately √(W 2 +T 2 ). .

次に、複数のチップ収納部140の各々においては、底部120と直交する方向から見たときに、1つのチップ収納部140に2つ以上のチップ状電子部品10が入らないようにするために、上記内接円141の直径Dが、2a未満となるように設定される(D<2a)。たとえば、図3に示すように、本実施形態においては、複数のチップ収納部140の開口形状が、1辺の長さをDとする正方形状である。チップ状電子部品10の幅Wおよび厚さTをaとしたときに、Dが2a以上であると、1つのチップ収納部140にチップ状電子部品10が2つ入る可能性がある。よって、上記内接円141の直径Dは、2a未満となるように設定される。 Next, in each of the plurality of chip housings 140, when viewed from the direction perpendicular to the bottom 120, two or more chip-shaped electronic components 10 are prevented from entering one chip housing 140. , the diameter D of the inscribed circle 141 is set to be less than 2a (D<2a). For example, as shown in FIG. 3, in the present embodiment, the shape of the openings of the plurality of chip storage portions 140 is a square having a side length of D. As shown in FIG. When the width W and the thickness T of the chip-like electronic component 10 are a, if D is 2a or more, there is a possibility that two chip-like electronic components 10 can fit in one chip storage portion 140 . Therefore, the diameter D of the inscribed circle 141 is set to be less than 2a.

次に、側壁部130の高さの寸法、すなわち、複数のチップ収納部140の各々の深さZの寸法について説明する。複数のチップ収納部140に各々にチップ状電子部品10を挿入した際に、チップ収納部140に入りきらず、チップ状電子部品用治具100上に余ったチップ状電子部品10は、チップ状電子部品用治具100を傾けて振るい落とす。このため、複数のチップ収納部140の各々の深さZは、チップ収納部140に収納されたチップ状電子部品10を振るい落とすことができ、かつ、余ったチップ状電子部品10を確実に振るい落とすことができるように設定する必要がある。 Next, the dimension of the height of the side wall portion 130, that is, the dimension of the depth Z of each of the plurality of chip storage portions 140 will be described. When the chip-shaped electronic components 10 are inserted into each of the plurality of chip storage portions 140, the chip-shaped electronic components 10 that do not fit into the chip storage portions 140 and remain on the chip-shaped electronic component jig 100 are removed from the chip-shaped electronic components. The component jig 100 is tilted and shaken off. Therefore, the depth Z of each of the plurality of chip storage portions 140 is such that the chip-shaped electronic components 10 stored in the chip storage portions 140 can be shaken off, and the surplus chip-shaped electronic components 10 can be reliably filtered out. It should be set so that it can be dropped.

図2および図4に示すように、複数のチップ収納部140の各々の深さZは、チップ状電子部品10の長さLの寸法が2aであるときに、2aの半分より大きくなるように設定する(a<Z)。このように設定することで、チップ状電子部品10の重心がチップ状電子部品10の長手方向の略中心に位置していれば、チップ収納部140に収納されたチップ状電子部品10の重心は、チップ収納部140内に位置する。これにより、余ったチップ状電子部品10は、チップ状電子部品用治具100を傾けて振るい落とすときに、チップ収納部140に収納されたチップ状電子部品10がチップ収納部140から落ちることを抑制できる。 As shown in FIGS. 2 and 4, the depth Z of each of the plurality of chip storage portions 140 is larger than half of 2a when the dimension of the length L of the chip-shaped electronic component 10 is 2a. Set (a<Z). By setting in this way, if the center of gravity of the electronic chip component 10 is positioned substantially at the center of the longitudinal direction of the electronic chip component 10, the center of gravity of the electronic chip component 10 accommodated in the chip accommodation section 140 is , are located in the chip storage portion 140 . As a result, when the chip-like electronic component jig 100 is tilted and shaken off, the remaining chip-like electronic components 10 stored in the chip-like electronic component 140 are prevented from falling out of the chip-like electronic component 140 . can be suppressed.

さらに、図2および図4に示すように、複数のチップ収納部140の各々の深さZは、チップ状電子部品10の長さLの寸法が2aであるときに、3aより小さくなるように設定する(Z<3a)。これにより、チップ状電子部品10をチップ状電子部品用治具100上にばらまいてチップ収納部140に挿入したときに、チップ収納部140に収納されたチップ状電子部品10の上にチップ状電子部品10がさらに位置しても、この上側のチップ状電子部品10のみをふるい落とすことができる。上側のチップ状電子部品10の重心位置の高さの寸法は、底部120を基準として3aであり、上側のチップ状電子部品10の重心は、チップ収納部140の外側に位置するからである。 Furthermore, as shown in FIGS. 2 and 4, the depth Z of each of the plurality of chip storage portions 140 is smaller than 3a when the dimension of the length L of the chip-shaped electronic component 10 is 2a. Set (Z<3a). As a result, when the chip-like electronic components 10 are scattered on the chip-like electronic component jig 100 and inserted into the chip storing portion 140 , the chip-like electronic components are placed on the chip-like electronic components 10 stored in the chip storing portion 140 . Even if the component 10 is further positioned, only the upper chip-like electronic component 10 can be screened out. This is because the height of the center of gravity of the upper chip-shaped electronic component 10 is 3 a with respect to the bottom portion 120 , and the center of gravity of the upper chip-shaped electronic component 10 is located outside the chip housing portion 140 .

以上より、チップ状電子部品10の長さL方向の寸法が2a、幅W方向および厚さT方向の各々の寸法がaであるとき、DとZとの関係は、上記式(D<2a)と上記式(a<Z)とに基づき、(D/2)<a<Zとなるから、(D/2)<Zとなる。さらに、DとZとの関係は、上記式(D>(√2)a)と上記式(Z<3a)とに基づき、Z<3a<(3√2/2)Dとなるから、Z<(3√2/2)Dとなる。 From the above, when the dimension in the length L direction of the chip-like electronic component 10 is 2a, and each dimension in the width W direction and the thickness T direction is a, the relationship between D and Z is expressed by the above formula (D<2a ) and the above formula (a<Z), (D/2)<a<Z, and therefore (D/2)<Z. Furthermore, the relationship between D and Z is based on the above formula (D>(√2)a) and the above formula (Z<3a), so Z <(3√2/2)D.

以上により、本実施形態においては、複数のチップ収納部140の各々において、底部120と直交する方向から見たときの側壁部130の内接円の直径Dの寸法と、複数のチップ収納部140の各々の深さZの寸法とが、下記式(1)の関係を満たしている。 As described above, in the present embodiment, in each of the plurality of chip storage portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 when viewed from the direction perpendicular to the bottom portion 120, and the dimension of the depth Z of each satisfies the relationship of the following formula (1).

(D/2)<Z<(3√2/2)D ・・・(1)
さらに、複数のチップ収納部140の各々の深さZは、チップ状電子部品10の長さLの寸法が2aであるときに、2aより小さくなるように設定することが好ましい(Z<2a)。すなわち、チップ状電子部品10をチップ収納部140に収納したときに、チップ状電子部品10の一部がチップ収納部140の外側に位置していることが好ましい。これにより、チップ収納部140の中に収納されたチップ状電子部品10を取り出すときに、側壁部130にチップ状電子部品10の複数の角部が引っかかって、これら複数の角部が固定されることで、チップ状電子部品10が側壁部130にロックされることを防ぐことができる。
(D/2)<Z<(3√2/2)D (1)
Furthermore, when the dimension of the length L of the chip-shaped electronic component 10 is 2a, the depth Z of each of the plurality of chip storage portions 140 is preferably set to be smaller than 2a (Z<2a). . That is, it is preferable that a part of the electronic chip component 10 is positioned outside the chip housing portion 140 when the electronic chip component 10 is housed in the chip housing portion 140 . As a result, when the chip-like electronic component 10 stored in the chip storing portion 140 is taken out, the plurality of corners of the chip-like electronic component 10 are caught by the side wall portion 130, and the plurality of corners are fixed. Thus, it is possible to prevent the electronic chip component 10 from being locked by the side wall portion 130 .

よって、深さが(Z<2a)と設定されるときは、DとZとの関係は、当該式(Z<2a)と、上記式(D>(√2)a)とに基づき、Z<2a<(√2)Dとなるから、Z<(√2)Dとなる。 Therefore, when the depth is set to (Z<2a), the relationship between D and Z is based on the above formula (Z<2a) and the above formula (D>(√2)a). Since <2a<(√2)D, Z<(√2)D.

以上により、複数のチップ収納部140の各々において、側壁部130の内接円の直径Dの寸法と、複数のチップ収納部240の各々の深さZの寸法とは、さらに下記式(2)の関係を満たしていることが好ましい。 As described above, in each of the plurality of chip storage portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip storage portions 240 are further determined by the following formula (2): It is preferable that the relationship of

(D/2)<Z<(√2)D ・・・(2)
本実施形態において、上記内接円141の直径Dの寸法は、たとえば0.1mm以上5.0mm以下である。上記深さZは、たとえば0.1mm以上8.0mmである。
(D/2)<Z<(√2)D (2)
In this embodiment, the diameter D of the inscribed circle 141 is, for example, 0.1 mm or more and 5.0 mm or less. The depth Z is, for example, 0.1 mm or more and 8.0 mm.

また、図4に示すように、本実施形態においては、複数の線状部材110の各々の線径Rの寸法が、複数のチップ収納部140の各々の深さZの寸法の1/2未満である。 Further, as shown in FIG. 4, in the present embodiment, the dimension of the wire diameter R of each of the plurality of linear members 110 is less than 1/2 of the dimension of the depth Z of each of the plurality of chip storage portions 140. is.

ここで、複数の線状部材の各々の線径Rの寸法と、複数のチップ収納部の各々の深さZの寸法との関係が、本実施形態に係るチップ状電子部品用治具100と異なる、比較例に係るチップ状電子部品用治具について説明する。 Here, the relationship between the dimension of the wire diameter R of each of the plurality of linear members and the dimension of the depth Z of each of the plurality of chip storage portions is the same as that of the chip-shaped electronic component jig 100 according to the present embodiment. A different jig for chip-shaped electronic components according to a comparative example will be described.

図5は、比較例に係るチップ状電子部品用治具の一部の構成を示す正面図である。図5においては、図4と同一の方向から見た断面視にて図示している。図5に示すように、比較例に係るチップ状電子部品用治具900においては、複数の線状部材の各々の線径Rの寸法が、複数のチップ収納部940の各々の深さZの寸法の1/2である。 FIG. 5 is a front view showing a configuration of part of a jig for chip-shaped electronic components according to a comparative example. FIG. 5 shows a cross-sectional view from the same direction as in FIG. As shown in FIG. 5 , in the chip-shaped electronic component jig 900 according to the comparative example, the dimension of the wire diameter R of each of the plurality of linear members is the size of the depth Z of each of the plurality of chip storage portions 940 . It is 1/2 the size.

このような比較例に係るチップ状電子部品用治具900においては、底部120が、第1線状部材911と、第2線状部材912とで構成されている。側壁部130は、2本の第3線状部材913と、2本の第4線状部材914とで構成されている。 In the chip-shaped electronic component jig 900 according to the comparative example, the bottom portion 120 is composed of the first linear member 911 and the second linear member 912 . The side wall portion 130 is composed of two third linear members 913 and two fourth linear members 914 .

図5に示すように、比較例に係るチップ状電子部品用治具900においては、複数の線状部材の各々の線径Rの寸法が比較的大きい。これにより、複数のチップ収納部940の各々に収納された複数のチップ状電子部品10のうち、互いに隣り合っているチップ状電子部品10同士の間に、他のチップ状電子部品10が入り込んで、第3線状部材913の上側に位置することが可能となっている。 As shown in FIG. 5, in the chip-shaped electronic component jig 900 according to the comparative example, the dimension of the wire diameter R of each of the plurality of linear members is relatively large. As a result, among the plurality of chip-shaped electronic components 10 housed in each of the plurality of chip housing portions 940, another chip-shaped electronic component 10 enters between the chip-shaped electronic components 10 adjacent to each other. , can be positioned above the third linear member 913 .

一方、図2および図4に示すように、本発明の実施形態1に係るチップ状電子部品用治具100においては、複数の線状部材の各々の線径Rの寸法が比較的小さいため、複数のチップ収納部140の各々に収納された複数のチップ状電子部品10のうち、互いに隣り合っているチップ状電子部品10同士の間に、他のチップ状電子部品が入り込むことを抑制することができる。 On the other hand, as shown in FIGS. 2 and 4, in the chip-shaped electronic component jig 100 according to the first embodiment of the present invention, since the wire diameter R of each of the plurality of linear members is relatively small, To suppress other chip-shaped electronic components from entering between adjacent chip-shaped electronic components 10 among the plurality of chip-shaped electronic components 10 housed in each of the plurality of chip housing portions 140. can be done.

本発明の実施形態1に係るチップ状電子部品用治具100は、具体的には、チップ状電子部品焼成用治具である。複数のチップ状電子部品10が収納されたチップ状電子部品用治具100を焼成雰囲気下に配置することで、複数のチップ状電子部品10を焼成することができる。また、本発明の実施形態1に係るチップ状電子部品用治具100は、複数のチップ状電子部品10が収納されたチップ状電子部品用治具100をめっき液につけることで、複数のチップ状電子部品10に、Cu、Ni、Sn、Ag、AuまたはPdなどの金属をめっきすることもできる。さらに、端部にAgなどからなる下地電極が形成された複数のチップ状電子部品10について、このような複数のチップ状電子部品10が収納されたチップ状電子部品用治具100をめっき液に浸すことで、上記下地電極に、めっきすることもできる。 The chip-shaped electronic component jig 100 according to the first embodiment of the present invention is specifically a chip-shaped electronic component firing jig. A plurality of chip-shaped electronic components 10 can be fired by arranging the chip-shaped electronic component jig 100 containing the plurality of chip-shaped electronic components 10 in a firing atmosphere. In addition, the chip-shaped electronic component jig 100 according to the first embodiment of the present invention is configured such that the chip-shaped electronic component jig 100 containing the plurality of chip-shaped electronic components 10 is immersed in a plating solution, thereby forming a plurality of chips. The electronic component 10 can also be plated with metals such as Cu, Ni, Sn, Ag, Au or Pd. Further, for a plurality of chip-shaped electronic components 10 having base electrodes made of Ag or the like formed at their ends, a chip-shaped electronic component jig 100 containing such a plurality of chip-shaped electronic components 10 is placed in a plating solution. It is also possible to plate the underlying electrode by immersion.

上記のように、本発明の実施形態1に係るチップ状電子部品用治具100は、チップ状電子部品を収納する複数のチップ収納部140を備えている。複数のチップ収納部140の各々は、底部120と、側壁部130とを含んでいる。底部120は、チップ状電子部品を支持する。側壁部130は、チップ状電子部品を挿入可能に開口している。複数のチップ収納部140の各々において、底部120と直交する方向から見たときの複数のチップ収納部140の各々の側壁部130の内接円の直径Dの寸法と、複数のチップ収納部140の各々の深さZの寸法とが、下記式(1)の関係を満たしている。 As described above, the chip-shaped electronic component jig 100 according to Embodiment 1 of the present invention includes a plurality of chip storage sections 140 for storing chip-shaped electronic components. Each of the plurality of chip storage portions 140 includes a bottom portion 120 and side wall portions 130 . The bottom part 120 supports chip-like electronic components. The side wall portion 130 is open so that the chip-shaped electronic component can be inserted. In each of the plurality of chip storage portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 of each of the plurality of chip storage portions 140 when viewed from the direction orthogonal to the bottom portion 120, and the dimension of the depth Z of each satisfies the relationship of the following formula (1).

(D/2)<Z<(3√2/2)D ・・・(1)
これにより、複数のチップ収納部140において、1つのチップ収納部140に1つのチップ状電子部品10を容易に挿入することができる。
(D/2)<Z<(3√2/2)D (1)
Accordingly, one chip-shaped electronic component 10 can be easily inserted into one chip storage portion 140 among the plurality of chip storage portions 140 .

本実施形態においては、複数のチップ収納部140の各々において、側壁部130の内接円の直径Dの寸法と、複数のチップ収納部140の各々の深さZの寸法とが、下記式(2)の関係を満たしていることがより好ましい。 In this embodiment, in each of the plurality of chip storage portions 140, the dimension of the diameter D of the inscribed circle of the side wall portion 130 and the dimension of the depth Z of each of the plurality of chip storage portions 140 are determined by the following formula ( It is more preferable that the relationship of 2) is satisfied.

(D/2)<Z<(√2)D ・・・(2)
これにより、複数のチップ収納部140に1つずつ挿入されたチップ状電子部品10を、容易に取り出すことができる。
(D/2)<Z<(√2)D (2)
As a result, the chip-like electronic components 10 inserted one by one into the plurality of chip storage portions 140 can be easily taken out.

本実施形態においては、複数のチップ収納部140を、底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部140の各々の開口形状が、多角形状である。 In the present embodiment, when the plurality of chip storage portions 140 are viewed from the side opposite to the bottom portion 120 side in the direction orthogonal to the bottom portion 120, the opening shape of each of the plurality of chip storage portions 140 is polygonal. be.

これにより、複数のチップ収納部140を整列させやすくなる。ひいては、整列された複数のチップ収納部140の各々にチップ状電子部品10を収納することにより、チップ状電子部品用治具100あたりのチップ状電子部品10の充填率を向上させることができる。 This makes it easier to align the plurality of chip storage units 140 . Furthermore, by storing the electronic chip components 10 in each of the aligned chip storage units 140, the filling rate of the electronic chip components 10 per jig 100 for chip electronic components can be improved.

本実施形態に係るチップ状電子部品用治具100は、直線状の複数の線状部材110が互いに積層されることで構成されている。 A chip-shaped electronic component jig 100 according to the present embodiment is configured by stacking a plurality of linear linear members 110 on each other.

これにより、線状部材110同士の間に形成された隙間においてガスまたは液体が通流可能となるため、チップ収納部140の通気性または液体の通過性を向上させることができる。 As a result, gas or liquid can flow through the gaps formed between the linear members 110, so that the air permeability or liquid permeability of the chip storage section 140 can be improved.

本実施形態においては、複数の線状部材110の各々の線径Rの寸法が、複数のチップ収納部140の各々の深さZの寸法の1/2未満である。 In this embodiment, the dimension of the wire diameter R of each of the plurality of linear members 110 is less than half the dimension of the depth Z of each of the plurality of chip storage portions 140 .

これにより、複数のチップ収納部140の各々に収納されたチップ状電子部品10のうち、互いに隣り合うチップ状電子部品10同士の間に、さらに他のチップ状電子部品10が入り込むことを抑制できる。 As a result, among the chip-shaped electronic components 10 housed in each of the plurality of chip housing portions 140, it is possible to prevent another chip-shaped electronic component 10 from entering between the chip-shaped electronic components 10 adjacent to each other. .

本実施形態に係るチップ状電子部品用治具100は、セラミックスで構成されている。
これにより、チップ状電子部品用治具100が金属で構成されている場合と比較して、チップ状電子部品用治具100の耐熱性を向上させることができる。
The chip-shaped electronic component jig 100 according to the present embodiment is made of ceramics.
As a result, the heat resistance of the chip-shaped electronic component jig 100 can be improved as compared with the case where the chip-shaped electronic component jig 100 is made of metal.

(実施形態2)
以下、本発明の実施形態2に係るチップ状電子部品用治具について説明する。本発明の実施形態2に係るチップ状電子部品用治具においては、複数のチップ収納部の各々の開口形状が主に、本発明の実施形態1に係るチップ状電子部品用治具100と異なる。よって、本発明の実施形態1に係るチップ状電子部品用治具100と同様である構成については説明を繰り返さない。
(Embodiment 2)
A jig for chip-like electronic components according to Embodiment 2 of the present invention will be described below. The chip-shaped electronic component jig according to the second embodiment of the present invention differs from the chip-shaped electronic component jig 100 according to the first embodiment of the present invention mainly in the opening shape of each of the plurality of chip storage portions. . Therefore, the description of the configuration similar to that of jig 100 for chip-like electronic components according to Embodiment 1 of the present invention will not be repeated.

図6は、本発明の実施形態2に係るチップ状電子部品用治具の構成を示す平面図である。図7は、図6に示すチップ状電子部品用治具を矢印VII方向から見た図である。図6においては、図1と同一の方向から見て図示している。なお、図6においては、複数の第1線状部材111および複数の第2線状部材112は図示していない。 FIG. 6 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 2 of the present invention. FIG. 7 is a view of the chip-like electronic component jig shown in FIG. 6 as viewed in the direction of arrow VII. In FIG. 6, it is illustrated when viewed from the same direction as in FIG. Note that FIG. 6 does not show the plurality of first linear members 111 and the plurality of second linear members 112 .

図6および図7に示すように、本発明の実施形態2に係るチップ状電子部品用治具200は、複数の線状部材210で構成されている。具体的には、本実施形態において、底部120は、複数の第1線状部材111と、複数の第2線状部材112とを有している。側壁部130は、複数の環状の第8線状部材218と、複数の環状の第9線状部材219とを有している。 As shown in FIGS. 6 and 7, a chip-like electronic component jig 200 according to Embodiment 2 of the present invention is composed of a plurality of linear members 210. As shown in FIG. Specifically, in this embodiment, the bottom portion 120 has a plurality of first linear members 111 and a plurality of second linear members 112 . Side wall portion 130 has a plurality of annular eighth linear members 218 and a plurality of annular ninth linear members 219 .

図7に示すように、複数の環状の第8線状部材218の各々は、側壁部130において底部120側とは反対側の端部を構成するように位置している。図6に示すように、複数の環状の第8線状部材218の各々は、隣接する第8線状部材218と互いに重なり合っている。複数の環状の第8線状部材218の各々は、底部120に直交する方向において底部120側とは反対側から見たときに、環状の内側部分同士が互いに重なり合わないように、位置している。 As shown in FIG. 7 , each of the plurality of annular eighth linear members 218 is positioned to form an end portion of the side wall portion 130 opposite to the bottom portion 120 side. As shown in FIG. 6 , each of the plurality of annular eighth linear members 218 overlaps the adjacent eighth linear member 218 . Each of the plurality of annular eighth linear members 218 is positioned so that the annular inner portions do not overlap each other when viewed from the side opposite to the bottom portion 120 side in the direction perpendicular to the bottom portion 120 . there is

図7に示すように、複数の環状の第9線状部材219の各々は、底部120に直交する方向から見たときに、複数の環状の第8線状部材218の各々と重なるように位置している。複数の環状の第9線状部材219の各々は、隣接する第9線状部材219と互いに重なり合っている。複数の環状の第9線状部材219の各々は、複数の第2線状部材112の第1線状部材111側とは反対側に位置し、かつ、複数の第8線状部材218より底部120側に位置している。 As shown in FIG. 7 , each of the plurality of ninth annular linear members 219 is positioned so as to overlap each of the plurality of eighth annular linear members 218 when viewed from the direction perpendicular to the bottom portion 120 . are doing. Each of the plurality of annular ninth linear members 219 overlaps with the adjacent ninth linear member 219 . Each of the plurality of annular ninth linear members 219 is located on the opposite side of the plurality of second linear members 112 from the first linear member 111 side, and is located at the bottom of the plurality of eighth linear members 218. It is located on the 120 side.

本発明の実施形態2において、複数のチップ収納部240の各々の深さZの寸法は、底部120に直交する方向において、第2線状部材112の第8線状部材218側の端部から、第8線状部材218の第2線状部材112側とは反対側の端部までの距離の寸法である。 In Embodiment 2 of the present invention, the dimension of the depth Z of each of the plurality of chip storage portions 240 is set to , to the end of the eighth linear member 218 opposite to the second linear member 112 side.

本実施形態に係るチップ状電子部品用治具200は上記のように構成されているため、複数のチップ収納部240の開口は、複数の第8線状部材218の各々の内側部分および複数の第9線状部材219の各々の内側部分で構成されている。 Since the jig 200 for chip-shaped electronic components according to the present embodiment is configured as described above, the openings of the plurality of chip storage portions 240 are the inner portions of each of the plurality of eighth linear members 218 and the plurality of openings of the plurality of eighth linear members 218 . It is composed of the inner portion of each of the ninth linear members 219 .

図6および図7に示すように、本発明の実施形態2に係るチップ状電子部品用治具200においては、底部120に直交する方向において底部120側とは反対側から見たときに、複数の第8線状部材218の各々および複数の第9線状部材219の各々の内側部分は、円形状である。すなわち、複数のチップ収納部240を、底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部240の各々の開口形状が、円形状である。 As shown in FIGS. 6 and 7, in the chip-shaped electronic component jig 200 according to the second embodiment of the present invention, when viewed from the side opposite to the bottom portion 120 side in the direction perpendicular to the bottom portion 120, a plurality of The inner portion of each of the eighth linear members 218 and each of the plurality of ninth linear members 219 has a circular shape. That is, when the plurality of tip storage portions 240 are viewed from the side opposite to the bottom portion 120 side in the direction perpendicular to the bottom portion 120, the opening shape of each of the plurality of tip storage portions 240 is circular.

これにより、底部120と直交する方向において底部120側とは反対側から見たときに、複数のチップ収納部240を密に配置することができる。ひいては、チップ状電子部品用治具200あたりのチップ状電子部品10の充填率を向上させることできる。 As a result, when viewed from the side opposite to the bottom portion 120 in the direction perpendicular to the bottom portion 120, the plurality of chip storage portions 240 can be densely arranged. As a result, the filling rate of the chip-shaped electronic components 10 per chip-shaped electronic component jig 200 can be improved.

また、本実施形態においても、上記式(1)の関係を満たしているため、複数のチップ収納部240において、1つのチップ収納部240に1つのチップ状電子部品10を容易に挿入することができる。 Also in the present embodiment, since the relationship of the above formula (1) is satisfied, one chip-like electronic component 10 can be easily inserted into one chip housing portion 240 among the plurality of chip housing portions 240. can.

なお、本実施形態において、底部120に直交する方向において底部120側とは反対側から見たときの複数のチップ収納部240の各々の内接円241は、底部120に直交する方向において底部120側とは反対側から見たときの複数の第8線状部材218の各々の内側面部または第9線状部材219の各々の内側面部で構成される。 In the present embodiment, the inscribed circle 241 of each of the plurality of chip storage portions 240 when viewed from the side opposite to the bottom portion 120 in the direction orthogonal to the bottom portion 120 is the bottom portion 120 in the direction orthogonal to the bottom portion 120 . When viewed from the side opposite to the side, each inner side surface portion of each of the plurality of eighth linear members 218 or each inner side surface portion of each of the plurality of ninth linear members 219 is configured.

(実施形態3)
以下、本発明の実施形態3に係るチップ状電子部品用治具について説明する。本発明の実施形態3に係るチップ状電子部品用治具においては、複数のチップ収納部の各々の開口寸法に係る特徴が主に、本発明の実施形態1に係るチップ状電子部品用治具100と異なる。よって、本発明の実施形態1に係るチップ状電子部品用治具100と同様である構成については説明を繰り返さない。
(Embodiment 3)
A jig for chip-shaped electronic components according to Embodiment 3 of the present invention will be described below. In the jig for chip-shaped electronic components according to Embodiment 3 of the present invention, the features related to the opening dimensions of each of the plurality of chip storage portions are mainly the jig for chip-shaped electronic components according to Embodiment 1 of the present invention. Different from 100. Therefore, the description of the configuration similar to that of jig 100 for chip-like electronic components according to Embodiment 1 of the present invention will not be repeated.

図8は、本発明の実施形態3に係るチップ状電子部品用治具の構成を示す平面図である。 FIG. 8 is a plan view showing the configuration of a jig for chip-shaped electronic components according to Embodiment 3 of the present invention.

図8に示すように、本発明の実施形態3に係るチップ状電子部品用治具300においては、複数のチップ収納部340の各々が、底部120と直交する方向において、底部120側から、底部120側とは反対側に向かうにしたがって、開口寸法が大きくなっている。 As shown in FIG. 8, in the chip-shaped electronic component jig 300 according to Embodiment 3 of the present invention, each of the plurality of chip storage portions 340 is arranged in a direction orthogonal to the bottom portion 120 from the bottom portion 120 side. The opening dimension increases toward the side opposite to the 120 side.

これにより、チップ状電子部品用治具300を揺動させたときに、複数のチップ収納部340の各々に、チップ状電子部品10を滑り込ませやすくすることができる。 Thus, when the chip-shaped electronic component jig 300 is swung, the chip-shaped electronic component 10 can be easily slid into each of the plurality of chip storage portions 340 .

また、本実施形態においても、上記式(1)の関係を満たしているため、複数のチップ収納部340において、1つのチップ収納部340に1つのチップ状電子部品10を容易に挿入することができる。 Also in this embodiment, since the relationship of the above formula (1) is satisfied, one chip-shaped electronic component 10 can be easily inserted into one chip housing portion 340 among the plurality of chip housing portions 340. can.

なお、本発明の実施形態3において、上記開口寸法とは、底部120に平行な方向において互いに隣り合う線状部材310同士の距離の寸法である。 In addition, in Embodiment 3 of the present invention, the opening dimension is the dimension of the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom portion 120 .

本発明の実施形態3に係るチップ状電子部品用治具300においては、複数の線状部材310の一部について、複数の線状部材310の各々の線径が互いに異なっている。具体的には、複数の線状部材310の線径は、第7線状部材317、第6線状部材316、第5線状部材315、第4線状部材314、第3線状部材313の順に大きくなっている。 In the chip-shaped electronic component jig 300 according to Embodiment 3 of the present invention, the wire diameters of the plurality of linear members 310 are different from each other for some of the plurality of linear members 310 . Specifically, the wire diameters of the plurality of linear members 310 are the seventh linear member 317, the sixth linear member 316, the fifth linear member 315, the fourth linear member 314, and the third linear member 313. is increasing in the order of

複数の線状部材310の各々の線径が上記のように順に大きくなっていることにより、底部120に平行な方向において互いに隣り合う線状部材310同士の距離の寸法は、第7線状部材317、第6線状部材316、第5線状部材315、第4線状部材314、第3線状部材313の順に小さくなっている。 Since the wire diameter of each of the plurality of linear members 310 increases in order as described above, the dimension of the distance between the linear members 310 adjacent to each other in the direction parallel to the bottom portion 120 is equal to that of the seventh linear member 317, sixth linear member 316, fifth linear member 315, fourth linear member 314, and third linear member 313 are smaller in this order.

また、本実施形態においては、内接円141の直径Dは、底部120に直交する方向におけるどの位置においても、常に上記式(1)が満たされるように、設定されている。 In addition, in this embodiment, the diameter D of the inscribed circle 141 is set so that the above formula (1) is always satisfied at any position in the direction perpendicular to the bottom portion 120 .

なお、本発明の各実施形態に係るチップ状電子部品用治具は、上記式(1)を満たさないチップ収納部を含んでいてもよい。上記式(1)を満たさないチップ収納部においては、線状部材同士の間を流れるガスの流れを制御することができる。また、側壁部を構成する線状部材を密に配置してもよい。これにより、チップ状電子部品用治具の強度を高めることができる。さらには、本発明の各実施形態に係るチップ状電子部品用治具は、チップ状電子部品を挿入できない大きさの、単なる隙間を有していてもよい。 Note that the chip-shaped electronic component jig according to each embodiment of the present invention may include a chip storage portion that does not satisfy the above formula (1). In the chip storage portion that does not satisfy the above formula (1), the flow of gas flowing between the linear members can be controlled. Also, the linear members forming the side wall may be densely arranged. Thereby, the strength of the jig for chip-shaped electronic components can be increased. Furthermore, the chip-shaped electronic component jig according to each embodiment of the present invention may have a simple gap of a size that cannot insert the chip-shaped electronic component.

上述した実施形態の説明において、組み合わせ可能な構成を相互に組み合わせてもよい。たとえば、板状部材で構成された底部と、複数の線状部材で構成された側壁部とを組み合わることでチップ状電子部品用治具を構成してもよい。すなわち、底部は、チップ収納部内のチップ状電子部品が抜け落ちることを防止できるものであれば、底部の形状、底部の線状部材に対する相対的な位置は、特に限定されるものではない。線状部材が底部を構成する場合、複数の第1線状部材および複数の第2線状部材の各々の面内における延在方向は、特に限定されない。複数の線状部材は、1つのチップ収納部あたり複数の第1線状部材または複数の第2線状部材が底部を形成するように構成されていてもよい。線状部材の断面形状は、多角形でもよい。チップ状電子部品用治具は、底部を挟んで、底部の両側に前記チップ状電子部品を挿入可能に開口している側壁部を有していてもよい。 In the above description of the embodiments, combinable configurations may be combined with each other. For example, a jig for chip-like electronic components may be configured by combining a bottom portion made up of a plate-like member and a side wall portion made up of a plurality of linear members. That is, the shape of the bottom and the position of the bottom relative to the linear member are not particularly limited as long as the bottom can prevent the chip-like electronic component from falling out of the chip storage portion. When the linear members constitute the bottom portion, the extending direction in the plane of each of the plurality of first linear members and the plurality of second linear members is not particularly limited. The plurality of linear members may be configured such that a plurality of first linear members or a plurality of second linear members form the bottom of one chip storage portion. The cross-sectional shape of the linear member may be polygonal. The jig for chip-shaped electronic components may have side walls that are open on both sides of the bottom so that the chip-shaped electronic components can be inserted.

今回開示された実施形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。 It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include all changes within the meaning and scope equivalent to the scope of the claims.

10 チップ状電子部品、100,200,300,900 チップ状電子部品用治具、110,210,310 線状部材、111,911 第1線状部材、112,912 第2線状部材、113,313,913 第3線状部材、114,314,914 第4線状部材、115,315 第5線状部材、116,316 第6線状部材、117,317 第7線状部材、120 底部、130 側壁部、140,240,340,940 チップ収納部、141,241 内接円、218 第8線状部材、219 第9線状部材。 10 Chip-shaped electronic component 100,200,300,900 Chip-shaped electronic component jig 110,210,310 Linear member 111,911 First linear member 112,912 Second linear member 113, 313,913 Third linear member 114,314,914 Fourth linear member 115,315 Fifth linear member 116,316 Sixth linear member 117,317 Seventh linear member 120 Bottom, 130 side wall portion, 140, 240, 340, 940 chip storage portion, 141, 241 inscribed circle, 218 eighth linear member, 219 ninth linear member.

Claims (6)

チップ状電子部品を収納する複数のチップ収納部を備えるチップ状電子部品用治具であって
前記チップ状電子部品用治具は、直線状の複数の線状部材が互いに積層されることで構成され、かつ、セラミックスで構成されており、
前記複数のチップ収納部の各々は、
前記チップ状電子部品を支持する底部と、
前記チップ状電子部品を挿入可能に開口している側壁部とを含み、
前記複数のチップ収納部の各々において、前記底部と直交する方向から見たときの前記側壁部の内接円の直径Dの寸法と、前記複数のチップ収納部の各々の深さZの寸法とが、下記式(1)の関係を満たす、チップ状電子部品用治具。
(D/2)<Z<(3√2/2)D ・・・(1)
A chip-shaped electronic component jig comprising a plurality of chip storage units for storing chip-shaped electronic components ,
The chip-shaped electronic component jig is configured by stacking a plurality of linear linear members on each other, and is configured of ceramics,
each of the plurality of chip storage units,
a bottom supporting the chip-like electronic component;
a side wall portion that is open so that the chip-like electronic component can be inserted;
In each of the plurality of tip storage portions, the dimension of the diameter D of the inscribed circle of the side wall portion when viewed from the direction orthogonal to the bottom portion, and the dimension of the depth Z of each of the plurality of tip storage portions. is a jig for chip-shaped electronic components that satisfies the relationship of the following formula (1).
(D/2)<Z<(3√2/2)D (1)
前記複数のチップ収納部の各々において、前記側壁部の内接円の直径Dの寸法と、前記複数のチップ収納部の各々の深さZの寸法とが、下記式(2)の関係を満たす、請求項1に記載のチップ状電子部品用治具。
(D/2)<Z<(√2)D ・・・(2)
In each of the plurality of chip storage portions, the dimension of the diameter D of the inscribed circle of the side wall portion and the dimension of the depth Z of each of the plurality of chip storage portions satisfy the following formula (2): A jig for chip-like electronic parts according to claim 1.
(D/2)<Z<(√2)D (2)
前記複数のチップ収納部を、前記底部と直交する方向において底部側とは反対側から見たときに、前記複数のチップ収納部の各々の開口形状が、多角形状である、請求項1または請求項2に記載のチップ状電子部品用治具。 2. An opening shape of each of said plurality of chip storage portions is polygonal when viewed from a side opposite to a bottom portion side in a direction orthogonal to said bottom portion. 3. A jig for chip-like electronic components according to item 2. 前記複数のチップ収納部を、前記底部と直交する方向において底部側とは反対側から見たときに、前記複数のチップ収納部の各々の開口形状が、円形状である、請求項1または請求項2に記載のチップ状電子部品用治具。 2. An opening shape of each of said plurality of tip storage portions is circular when viewed from a side opposite to a bottom portion side in a direction orthogonal to said bottom portion. 3. A jig for chip-like electronic components according to item 2. 前記複数のチップ収納部の各々が、前記底部と直交する方向において、底部側から、底部側とは反対側に向かうにしたがって、開口寸法が大きくなっている、請求項1から請求項4のいずれか1項に記載のチップ状電子部品用治具。 5. Any one of claims 1 to 4, wherein each of the plurality of chip storage portions has an opening dimension that increases from the bottom side toward the side opposite to the bottom side in a direction perpendicular to the bottom. 1. A jig for chip-shaped electronic components according to claim 1. 前記複数の線状部材の各々の線径Rの寸法が、前記複数のチップ収納部の各々の深さZの寸法の1/2未満である、請求項1から請求項5のいずれか1項に記載のチップ状電子部品用治具。 6. The dimension of the wire diameter R of each of the plurality of linear members is less than 1/2 of the dimension of the depth Z of each of the plurality of chip storage portions. The jig for chip-like electronic components according to 1.
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