WO2021020393A1 - 画像表示装置の製造方法および画像表示装置 - Google Patents

画像表示装置の製造方法および画像表示装置 Download PDF

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Publication number
WO2021020393A1
WO2021020393A1 PCT/JP2020/028891 JP2020028891W WO2021020393A1 WO 2021020393 A1 WO2021020393 A1 WO 2021020393A1 JP 2020028891 W JP2020028891 W JP 2020028891W WO 2021020393 A1 WO2021020393 A1 WO 2021020393A1
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Prior art keywords
light emitting
insulating film
layer
semiconductor layer
image display
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PCT/JP2020/028891
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English (en)
French (fr)
Japanese (ja)
Inventor
秋元　肇
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Nichia Corp
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Nichia Corp
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Application filed by Nichia Corp filed Critical Nichia Corp
Priority to CN202080052540.8A priority Critical patent/CN114144881B/zh
Priority to JP2021535358A priority patent/JP7523741B2/ja
Publication of WO2021020393A1 publication Critical patent/WO2021020393A1/ja
Priority to US17/585,963 priority patent/US12211883B2/en
Anticipated expiration legal-status Critical
Priority to US18/988,316 priority patent/US20250120235A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
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    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
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    • H10H20/80—Constructional details
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    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
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    • H10H20/80—Constructional details
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    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H10H20/821—Bodies characterised by their shape, e.g. curved or truncated substrates of the light-emitting regions, e.g. non-planar junctions
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    • H10H20/80—Constructional details
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    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
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    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
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    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
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    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0363—Manufacture or treatment of packages of optical field-shaping means
    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8515—Wavelength conversion means not being in contact with the bodies

Definitions

  • An embodiment of the present invention relates to a method for manufacturing an image display device and an image display device.
  • the appearance of a display device using a micro LED which is a fine light emitting element, is expected.
  • a method of manufacturing a display device using micro LEDs a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced.
  • the number of micro LED elements increases as the image quality becomes higher, such as full high-definition, 4K, 8K, etc.
  • the transfer process requires a huge amount of time. Further, a poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.
  • a technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the electrodes are attached to a circuit board on which a drive circuit is formed (for example, Patent Document 1).
  • One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of a light emitting element and improves the yield.
  • the method for manufacturing an image display device includes a step of preparing a second substrate in which a semiconductor layer including a light emitting layer is grown on a first substrate, and a circuit formed on the translucent substrate.
  • It includes a step of forming a via penetrating the first insulating film and the second insulating film, and a step of electrically connecting the light emitting element and the circuit element via the via.
  • the light emitting element is provided on the portion.
  • the outer circumference of the portion includes the outer circumference of the light emitting element projected on the portion in a plan view.
  • the image display device includes a translucent substrate having a first surface, a circuit element provided on the first surface, and a first wiring electrically connected to the circuit element.
  • a conductive layer including a layer, a first insulating film that covers the circuit element and the first wiring layer on the first surface, and a light-reflecting portion provided on the first insulating film, and the portion.
  • a first light emitting element provided above and electrically connected to the portion, at least a part of the first light emitting element, a second insulating film covering the conductive layer and the first insulating film, and the second insulating film.
  • a second wiring layer provided on the insulating film and electrically connected to a surface of the first light emitting element including a light emitting surface facing the side surface of the first insulating film, the first insulating film, and the above. It includes a first via that penetrates the second insulating film and electrically connects the first wiring layer and the second wiring layer.
  • the outer circumference of the portion includes the outer circumference of the first light emitting element projected on the portion in a plan view.
  • the image display device has a flexible substrate having a first surface, a circuit element provided on the first surface, and a first surface electrically connected to the circuit element.
  • a first light emitting element provided on the portion and electrically connected to the portion, at least a part of the first light emitting element, a second insulating film covering the conductive layer and the first insulating film, and the above.
  • a second wiring layer provided on the second insulating film and electrically connected to a surface of the first light emitting element including a light emitting surface facing the first insulating film, and the first insulating film. And a first via that penetrates the second insulating film and electrically connects the first wiring layer and the second wiring layer.
  • the outer circumference of the portion includes the outer circumference of the first light emitting element projected on the portion in a plan view.
  • the image display device has a translucent substrate having a first surface, a plurality of transistors provided on the first surface, and a third electrically connected to the plurality of transistors.
  • a first conductive type first semiconductor layer provided on the portion and electrically connected to the portion, a light emitting layer provided on the first semiconductor layer, and a light emitting layer provided on the light emitting layer.
  • a plurality of vias that penetrate the first insulating film and the second insulating film and electrically connect the wiring of the first wiring layer and the wiring of the second wiring layer.
  • the outer circumference of the portion includes all the outer circumferences of the first semiconductor layer, the light emitting layer, and the second semiconductor layer projected on the portion in a plan view.
  • a method for manufacturing an image display device that shortens the transfer process of the light emitting element and improves the yield is realized.
  • FIG. 1 is a schematic cross-sectional view illustrating a part of the image display device according to the embodiment.
  • FIG. 1 schematically shows the configuration of the sub-pixel 20 of the image display device of the present embodiment.
  • the pixel 10 constituting the image displayed on the image display device is composed of a plurality of subpixels 20.
  • FIG. 1 represents a cross-sectional view taken along the line AA'of FIG. 4 to be described later, and is a cross-sectional view in which cross-sections in a plurality of planes perpendicular to the XY plane are connected to one. Also in other figures, as shown in FIG.
  • the X-axis and the Y-axis are not shown, and the Z-axis perpendicular to the XY plane is shown. That is, in these figures, the plane perpendicular to the Z axis is the XY plane.
  • the subpixel 20 has a light emitting surface 153S substantially parallel to the XY plane.
  • the light emitting surface 153S mainly emits light in the positive direction of the Z axis orthogonal to the XY plane.
  • the subpixel 20 of the image display device includes a substrate 102, a transistor 103, a first wiring layer 110, a first interlayer insulating film 112, a light emitting element 150, and a second interlayer. It includes an insulating film 156, a conductive layer 130, a plurality of vias 161d and 161k, and a second wiring layer 160.
  • the substrate 102 on which the circuit element including the transistor 103 is formed is a translucent substrate, for example, a glass substrate.
  • the substrate 102 has a first surface 102a, and a thin film transistor (TFT) is formed as a transistor 103 on the first surface 102a.
  • the light emitting element 150 is driven by a TFT formed on a glass substrate.
  • the process of forming a circuit element including a TFT on a large glass substrate has been established for manufacturing liquid crystal panels, organic EL panels, and the like, and has an advantage that existing plants can be used.
  • the subpixel 20 further includes a color filter 180.
  • the color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin film adhesive layer 188.
  • the surface resin layer 170 is provided on the interlayer insulating film 156 and the wiring layer 160.
  • the transistor 103 is formed on the TFT underlayer film 106 formed on the first surface 102a of the substrate 102.
  • the TFT underlayer film 106 is provided for the purpose of ensuring flatness when the transistor 103 is formed and protecting the TFT channel 104 of the transistor 103 from contamination or the like during heat treatment.
  • the TFT underlayer film 106 is, for example, SiO 2 .
  • circuit elements such as other transistors and capacitors are formed on the substrate 102, and the circuit 101 is composed of wiring and the like.
  • the transistor 103 corresponds to the drive transistor 26 shown in FIG. 3, which will be described later, and the selection transistor 24, the capacitor 28, and the like are other circuit elements.
  • the circuit 101 includes a TFT channel 104, an insulating layer 105, an insulating film 108, vias 111s and 111d, and a wiring layer 110.
  • the circuit board 100 may include other components such as the substrate 102, the TFT underlayer film 106, the circuit 101, and the interlayer insulating film 112.
  • Transistor 103 is a p-channel TFT in this example.
  • the transistor 103 includes a TFT channel 104 and a gate 107.
  • the TFT is preferably formed by a Low Temperature Poly Silicon (LTPS) process.
  • the TFT channel 104 is a region of polycrystalline Si formed on the substrate 102, and is polycrystalline and activated by annealing the region formed as amorphous Si by laser irradiation.
  • the TFT formed by the LTPS process has sufficiently high mobility.
  • the TFT channel 104 includes regions 104s, 104i, 104d.
  • the regions 104s, 104i, and 104d are all provided on the TFT underlayer film 106.
  • the area 104i is provided between the areas 104s and 104d.
  • the regions 104s and 104d are doped with p-type impurities such as boron ion (B +) and boron fluoride ion (BF2 +), and are ohmic-connected to the vias 111s and 111d.
  • the gate 107 is provided on the TFT channel 104 via the insulating layer 105.
  • the insulating layer 105 is provided to insulate the TFT channel 104 and the gate 107 and to insulate them from other adjacent circuit elements.
  • a potential lower than the region 104s is applied to the gate 107, a channel is formed in the region 104i, so that the current flowing between the regions 104s and 104d can be controlled.
  • the insulating layer 105 is, for example, SiO 2 .
  • the insulating layer 105 may be a multi-layered insulating layer containing SiO 2 or Si 3 N 4 depending on the covering region.
  • the gate 107 is, for example, polycrystalline Si.
  • the polycrystalline Si film of the gate 107 can generally be formed by a CVD process.
  • the gate 107 and the insulating layer 105 are covered with the insulating film 108.
  • the insulating film 108 is, for example, SiO 2 or Si 3 N 4 or the like.
  • the insulating film 108 functions as a flattening film for forming the wiring layer 110.
  • the insulating film 108 is a multilayer insulating film containing, for example, SiO 2 and Si 3 N 4 and the like.
  • the vias 111s and 111d are provided so as to penetrate the insulating film 108.
  • a first wiring layer (first wiring layer) 110 is formed on the insulating film 108.
  • the first wiring layer 110 includes a plurality of wirings having different potentials, and includes wirings 110s and 110d.
  • the code of the wiring layer shall be displayed at a position next to one wiring included in the wiring layer to be labeled.
  • Vias 111s and 111d are provided between the wirings 110s and 110d and the areas 104s and 104d, respectively, and are electrically connected to each other.
  • the wiring 110s electrically connects the region 104s, which is the source region of the transistor 103, to the power supply line 3 shown in FIG. 3, which will be described later.
  • the wiring 110d is electrically connected to the p-type semiconductor layer 153 on the light emitting surface 153S side of the light emitting element 150 via the via 161d and the wiring 160a.
  • the wiring layer 110 and vias 111s and 111d are formed of, for example, an alloy of Al or Al, a laminated film of Al and Ti, or the like.
  • Al is laminated on a thin film of Ti, and Ti is further laminated on Al.
  • the interlayer insulating film 112 is provided on the insulating film 108 and the wiring layer 110.
  • the interlayer insulating film (first insulating film) 112 is an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass).
  • the interlayer insulating film 112 is provided to realize uniform bonding in wafer bonding.
  • the interlayer insulating film 112 also functions as a protective film that protects the surface of the circuit board 100.
  • the conductive layer 130 is provided on the interlayer insulating film 112.
  • the conductive layer 130 includes a light reflecting plate (part) 130a.
  • the light reflecting plates 130a are provided for each subpixel, and the plurality of light reflecting plates 130a are not connected to each other in the conductive layer 130.
  • the plurality of light reflecting plates 130a are connected to the ground wire via vias 161k and wiring 160k.
  • the conductive layer 130 is made of a material having high conductivity, including the light reflecting plate 130a.
  • the conductive layer 130 and the light reflecting plate 130a include, for example, Ti, Al, an alloy of Ti and Sn, and the like. It may contain noble metals having higher light reflectivity such as Cu and V, or Ag and Pt. Since the light reflection plate 130a is made of such a metal material having high conductivity, the light emitting element 150 and the circuit 101 are electrically connected with low resistance.
  • the outer circumference of the light reflection plate 130a includes the outer circumference when the light emitting element 150 is projected from above the Z axis in the XY plane view, that is, the outer circumference in the XY plane view.
  • the light reflecting plate 130a can reflect the scattering of light downward of the light emitting element 150 toward the light emitting surface 153S side so as not to reach the transistor 103. By blocking the scattered light downward from the light emitting element 150 by the light reflecting plate 130a, the arrival of light at the transistor 103 is suppressed, and malfunction of the transistor 103 can be prevented.
  • the light emitting element 150 includes an n-type semiconductor layer (first semiconductor layer) 151, a light emitting layer 152, and a p-type semiconductor layer (second semiconductor layer) 153.
  • the n-type semiconductor layer 151, the light emitting layer 152, and the p-type semiconductor layer 153 are laminated in this order from the side of the interlayer insulating film 112 toward the side of the light emitting surface 153S.
  • the light emitting element 150 has, for example, a substantially square or rectangular shape in XY plan view, but the corners may be rounded.
  • the light emitting element 150 may have, for example, an elliptical shape or a circular shape in an XY plan view. The degree of freedom in layout is improved by appropriately selecting the shape and arrangement of the light emitting elements in a plan view.
  • the light emitting element 150 for example, a nitride semiconductor such as In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) is preferably used.
  • the light emitting element 150 in one embodiment of the present invention is a so-called blue light emitting diode, and the wavelength of the light emitted by the light emitting element 150 is, for example, about 467 nm ⁇ 20 nm.
  • the wavelength of the light emitted by the light emitting element 150 may be bluish purple emission of about 410 nm ⁇ 20 nm.
  • the wavelength of the light emitted by the light emitting element 150 is not limited to the above-mentioned value, and may be appropriate.
  • the second interlayer insulating film 156 covers the first interlayer insulating film 112, the conductive layer 130, and the light emitting element 150.
  • the interlayer insulating film 156 is formed of, for example, a transparent organic insulating material.
  • a silicon-based resin such as SOG (Spin On Glass), a novolak-type phenol-based resin, or the like is used.
  • the interlayer insulating film 156 may be, for example, an ALD (Atomic-layer-deposition) or a SiO 2 film formed by CVD.
  • the interlayer insulating film 156 protects the light emitting element 150, the conductive layer 130, and the like from the surrounding environment such as dust and humidity by covering them.
  • the interlayer insulating film 156 also has a function of insulating the light emitting element 150, the conductive layer 130, and the like from other conductive materials by covering them.
  • the surface of the interlayer insulating film 156 may be flat enough to form the wiring layer 160 on the interlayer insulating film 156.
  • a via 161k is provided so as to penetrate the second interlayer insulating film 156.
  • One end of the via 161k is connected to the light reflecting plate 130a.
  • the via 161d is provided so as to penetrate the interlayer insulating films 112 and 156. One end of the via 161d is connected to the wiring 110d.
  • the wiring layer 160 is provided on the interlayer insulating film 156.
  • the wiring layer 160 includes wirings 160a and 160k.
  • the wiring 160a is connected to the p-type semiconductor layer 153 via a contact hole opened in the interlayer insulating film 156. That is, the wiring 160a is electrically connected to the p-type semiconductor layer 153 at a part of the surface including the light emitting surface 153S.
  • the surface including the light emitting surface 153S and the light emitting surface 153S are, for example, coplanar.
  • the wiring 160a is connected to the other end of the via 161d. Therefore, the p-type semiconductor layer 153 is electrically connected to the region 104d, which is the drain electrode of the transistor 103, via the wiring 160a, the via 161d, and the wiring 110d.
  • the wiring 160k is connected to the other end of the via 161k.
  • the wiring 160k is connected to the ground wire 4 shown in FIG. 3 which will be described later. Therefore, the n-type semiconductor layer 151 is connected to the ground wire 4 via the light reflection plate 130a, the via 161k, and the wiring 160k.
  • the surface resin layer 170 covers the second interlayer insulating film 156 and the second wiring layer 160.
  • the surface resin layer 170 is a transparent resin, which protects the interlayer insulating film 156 and the wiring layer 160, and provides a flattening surface for adhering the color filter 180.
  • the color filter 180 includes a light-shielding unit 181 and a color conversion unit 182.
  • the color conversion unit 182 is provided directly above the light emitting surface 153S of the light emitting element 150 according to the shape of the light emitting surface 153S.
  • the portion other than the color conversion unit 182 is a light-shielding unit 181.
  • the light-shielding unit 181 is a so-called black matrix, which reduces bleeding due to color mixing of light emitted from the adjacent color conversion unit 182 and makes it possible to display a sharp image.
  • the color conversion unit 182 has one layer or two layers.
  • FIG. 1 shows a two-layer portion. Whether the color conversion unit 182 has one layer or two layers is determined by the color of the light emitted by the subpixel 20, that is, the wavelength.
  • the color conversion unit 182 preferably has two layers, a color conversion layer 183 and a filter layer 184, which will be described later.
  • the emission color of the subpixel 20 is blue, it is preferably one layer.
  • the first layer closer to the light emitting element 150 is the color conversion layer 183
  • the second layer is the filter layer 184. That is, the filter layer 184 is laminated on the color conversion layer 183.
  • the color conversion layer 183 is a layer that converts the wavelength of the light emitted by the light emitting element 150 into a desired wavelength.
  • the light having a wavelength of 467 nm ⁇ 20 nm of the light emitting element 150 is converted into light having a wavelength of, for example, about 630 nm ⁇ 20 nm.
  • the light having a wavelength of 467 nm ⁇ 20 nm of the light emitting element 150 is converted into light having a wavelength of, for example, about 532 nm ⁇ 20 nm.
  • the filter layer 184 blocks the wavelength component of blue light emission remaining without color conversion in the color conversion layer 183.
  • the subpixel 20 may output the light through the color conversion layer 183, or outputs the light as it is without passing through the color conversion layer 183. You may do so.
  • the wavelength of the light emitted by the light emitting element 150 is about 467 nm ⁇ 20 nm
  • the subpixel 20 may output the light without passing through the color conversion layer 183.
  • the wavelength of the light emitted by the light emitting element 150 is 410 nm ⁇ 20 nm, it is preferable to provide one color conversion layer 183 in order to convert the wavelength of the output light to about 467 nm ⁇ 20 nm.
  • the subpixel 20 may have a filter layer 184.
  • the filter layer 184 By providing the filter layer 184 on the blue subpixel 20, minute external light reflection generated on the surface of the light emitting element 150 is suppressed.
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating a part of a modification of the image display device of the present embodiment, respectively.
  • the display of the surface resin layer 170 and the color filter 180 is omitted in order to avoid complication.
  • a surface resin layer 170, a color filter 180, and the like are provided on the second interlayer insulating film 156, 256 and the second wiring layer 160. The same applies to the cases of other embodiments and modifications thereof described later.
  • the subpixels 20a and 20b are different from the case of the first embodiment described above in the connection method between the light emitting element 150a and the wirings 160a1 and 160a2.
  • the same components are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 20a includes a light emitting element 150a and a wiring 160a1.
  • the second interlayer insulating film (second insulating film) 256 is preferably a white resin.
  • the interlayer insulating film 256 which is a white resin, can substantially improve the luminous efficiency of the light emitting element 150a by reflecting the laterally emitted light of the light emitting element 150a and the return light caused by the interface of the color filter 180 and the like. it can.
  • the second interlayer insulating film 256 may be a black resin.
  • the interlayer insulating film 256 as a black resin, scattering of light in the subpixel 20a is suppressed, and stray light is suppressed more effectively.
  • An image display device in which stray light is suppressed can display a sharper image.
  • the second interlayer insulating film 256 has an opening 158.
  • the opening 158 is formed by removing a part of the interlayer insulating film 256 above the light emitting element 150a.
  • the wiring 160a1 extends to the p-type semiconductor layer 153a exposed by the opening 158 and is connected to the p-type semiconductor layer 153a.
  • the wiring 160a1 is connected to the via 161d as in the case of the wiring 160a of FIG. 1, and the p-type semiconductor layer 153a is connected to the drain electrode of the transistor 103 via the wiring 160a1, the via 161d and the wiring 110d. ing.
  • the p-type semiconductor layer 153a has a light emitting surface 153S exposed by the opening 158.
  • the light emitting surface 153S is a surface of the p-type semiconductor layer 153a facing the surface in contact with the light emitting layer 152.
  • the light emitting surface 153S is preferably roughened. When the light emitting surface 153S is a rough surface, the light emitting element 150a can improve the light extraction efficiency.
  • the translucent electrodes 159a and 159k are provided on the wirings 160a and 160k, respectively.
  • the translucent electrode 159a extends to the light emitting surface 153S of the opened p-type semiconductor layer 153a.
  • the translucent electrode 159a is provided over the light emitting surface 153S.
  • the translucent electrode 159a electrically connects the wiring 160a2 and the p-type semiconductor layer 153a.
  • the wiring 160a2 is connected to the via 161d as in the case of the wiring 160a of FIG. It is connected to the drain electrode of.
  • the connection area between the translucent electrode 159a and the p-type semiconductor layer 153a can be increased, and the luminous efficiency can be improved.
  • the connection area between the light emitting surface 153S and the translucent electrode 159a can be increased, and the contact resistance can be reduced.
  • any of the configurations of the subpixels 20, 20a, and 20b shown above can be included.
  • FIG. 3 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 1 of the present embodiment includes a display area 2.
  • Subpixels 20 are arranged in the display area 2.
  • the subpixels 20 are arranged in a grid pattern, for example. For example, n subpixels 20 are arranged along the X axis, and m subpixels 20 are arranged along the Y axis.
  • Pixel 10 includes a plurality of subpixels 20 that emit light of different colors.
  • the subpixel 20R emits red light.
  • the subpixel 20G emits green light.
  • the subpixel 20B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by emitting light of the three types of sub-pixels 20R, 20G, and 20B at desired brightness.
  • One pixel 10 includes three sub-pixels 20R, 20G, 20B, and the sub-pixels 20R, 20G, 20B are linearly arranged on the X-axis, for example, as shown in FIG.
  • subpixels of the same color may be arranged in the same column, or subpixels of different colors may be arranged for each column as in this example.
  • the image display device 1 further includes a power supply line 3 and a ground line 4.
  • the power line 3 and the ground line 4 are arranged in a grid pattern along the array of subpixels 20.
  • the power supply line 3 and the ground line 4 are electrically connected to each subpixel 20, and power is supplied to each subpixel 20 from a DC power source connected between the power terminal 3a and the GND terminal 4a.
  • the power supply terminal 3a and the GND terminal 4a are provided at the ends of the power supply line 3 and the ground line 4, respectively, and are connected to a DC power supply circuit provided outside the display area 2. A positive voltage is supplied to the power supply terminal 3a with reference to the GND terminal 4a.
  • the image display device 1 further has a scanning line 6 and a signal line 8.
  • the scanning line 6 is laid out in a direction parallel to the X axis. That is, the scanning lines 6 are laid out along the array in the row direction of the subpixels 20.
  • the signal line 8 is laid out in a direction parallel to the Y axis. That is, the signal line 8 is laid out along the array of the subpixels 20 in the column direction.
  • the image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7.
  • the row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2.
  • the row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2.
  • the row selection circuit 5 is electrically connected to the subpixels 20 of each column via the scanning line 6 to supply a selection signal to each subpixel 20.
  • the signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display area 2.
  • the signal voltage output circuit 7 is electrically connected to the subpixels 20 of each line via the signal line 8 to supply a signal voltage to each subpixel 20.
  • the subpixel 20 includes a light emitting element 22, a selection transistor 24, a drive transistor 26, and a capacitor 28.
  • the selection transistor 24 may be displayed as T1
  • the drive transistor 26 may be displayed as T2
  • the capacitor 28 may be displayed as Cm.
  • the light emitting element 22 is connected in series with the drive transistor 26.
  • the drive transistor 26 is a p-channel TFT, and an anode electrode connected to the p-type semiconductor layer of the light emitting element 22 is connected to a drain electrode which is a main electrode of the drive transistor 26.
  • the series circuit of the light emitting element 22 and the drive transistor 26 is connected between the power supply line 3 and the ground line 4.
  • the drive transistor 26 corresponds to the transistor 103 in FIG. 1 and the like
  • the light emitting element 22 corresponds to the light emitting elements 150 and 150a in FIG. 1 and the like.
  • the current flowing through the light emitting element 22 is determined by the voltage applied between the gate and the source of the drive transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.
  • the selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode.
  • the gate electrode of the selection transistor 24 is connected to the scanning line 6.
  • a capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.
  • the row selection circuit 5 selects one row from the array of subpixels 20 in the m row and supplies the selection signal to the scanning line 6.
  • the signal voltage output circuit 7 supplies a signal voltage having the required analog voltage value for each subpixel 20 in the selected row.
  • a signal voltage is applied between the gate and source of the drive transistor 26 of the subpixel 20 in the selected row.
  • the signal voltage is held by the capacitor 28.
  • the drive transistor 26 causes a current corresponding to the signal voltage to flow through the light emitting element 22.
  • the light emitting element 22 emits light with a brightness corresponding to the current flowing through the light emitting element 22.
  • the row selection circuit 5 sequentially switches the rows to be selected and supplies the selection signal. That is, the row selection circuit 5 scans the row in which the subpixels 20 are arranged. A current corresponding to the signal voltage flows through the light emitting element 22 of the subpixel 20 that is sequentially scanned to emit light. Each pixel 10 emits light with an emission color and brightness determined by the emission color and brightness emitted by the subpixels 20 of each RGB color, and an image is displayed in the display area 2.
  • FIG. 4 is a schematic plan view illustrating a part of the image display device of the present embodiment.
  • the light emitting element 150 (light emitting element 22 in FIG. 3) and the driving transistor 103 (driving transistor 26 in FIG. 3) are laminated in the Z-axis direction, and vias are provided.
  • the anode electrode of the light emitting element 150 and the drain electrode of the driving transistor 103 are electrically connected by 161d.
  • the cathode electrode of the light emitting element 150 and the ground wire 4 shown in FIG. 3 are electrically connected by the via 161k shown in FIG.
  • the plan view of the I layer is schematically displayed in the upper part of FIG. 4, and the plan view of the II layer is schematically displayed in the lower part.
  • the first layer is referred to as "I” and the second layer is referred to as "II".
  • the I-th layer is a layer on which the light emitting element 150 is formed. That is, in FIG. 1, the first layer shows an element on the positive side of the Z axis with respect to the first interlayer insulating film 112, and the element is a layer from the n-type semiconductor layer 151 to the second wiring layer 160. Is. In FIG. 4, the second interlayer insulating film 156 is not shown.
  • the second layer shows an element on the positive side of the Z axis with respect to the TFT lower layer film 106, and the element is a layer from the transistor 103 to the first interlayer insulating film 112.
  • the substrate 102, the insulating layer 105, the insulating film 108, and the first interlayer insulating film 112 are not shown.
  • FIG. 1 The cross-sectional view of FIG. 1 is an arrow cross-sectional view of the AA'line shown by a broken line of the alternate long and short dash line in each of the I layer and the II layer.
  • the light emitting element 150 is connected to the via 161k shown in FIG. 1 by the light reflecting plate 130a.
  • the via 161k is connected to the wiring 160k via the contact hole 161k1.
  • the light emitting element 150 is connected to the wiring 160a via the contact hole 162a provided in the p-type semiconductor layer 153, and the wiring 160a is connected to the via 161d via the contact hole 161d1.
  • the via 161d penetrating the two interlayer insulating films 112 and 156 is schematically shown by a chain double-dashed line in the figure.
  • the via 161d is connected to the wiring 110d via the contact hole 161d2 provided in the first interlayer insulating film 112.
  • the wiring 110d is connected to the via 111d shown in FIG. 1 via the contact hole 111c1 opened in the insulating film 108, and is connected to the drain electrode of the transistor 103.
  • the light emitting element 150 and the wiring 110d formed in the different layers I and II, respectively, are electrically connected by the via 161d penetrating the interlayer insulating films 112 and 156, and the light emitting element.
  • the 150 and the transistor 103 can be electrically connected.
  • the arrangement of the light reflecting plate 130a and the light emitting element 150 when the light reflecting plate 130a reflects the light scattered downward of the light emitting element 150 toward the light emitting surface 153S will be described with reference to FIG.
  • the light reflecting plate 130a is a square having a length L2 in the X-axis direction and a length W2 in the Y-axis direction in the XY plan view.
  • the light emitting element 150 has a rectangular bottom surface having a length L1 in the X-axis direction and a length W1 in the Y-axis direction in an XY plan view.
  • the length of each part is set so that L2> L1 and W2> W1.
  • the light reflecting plate 130a is provided directly below the light emitting element 150, and the outer circumference of the light reflecting plate 130a includes the outer circumference of the light emitting element 150.
  • the outer circumference of the light reflecting plate 130a may include the outer circumference of the light emitting element 150, and the shape of the light reflecting plate 130a is not limited to a square shape and is an appropriate shape depending on the layout on the circuit board 100 and the like. Can be.
  • the light emitting element 150 emits light upward, and also emits light downward, and includes reflected light, scattered light, and the like at the interface between the interlayer insulating film 112 and the surface resin layer 170. Since the conductive layer 130 includes a light reflecting plate 130a having light reflectivity, the light scattered downward of the light emitting element 150 is reflected upward by the light reflecting plate 130a. Therefore, the ratio of the light emitted from the light emitting element 150 to the light emitting surface 153S side becomes large, and the substantial luminous efficiency of the light emitting element 150 is improved.
  • the light reflection plate 130a in this way, the arrival of light below the light emitting element 150 is suppressed, so that even when the circuit element is arranged in the immediate vicinity of the light emitting element 150, it reaches the circuit element. The influence of light can be reduced.
  • the conductive layer 130 is not limited to the case where it is connected to the ground wire 4 by the light reflection plate 130a, and may be connected to another potential such as the potential of the power supply line 3 depending on the circuit configuration and the circuit layout.
  • 5A to 9B are schematic cross-sectional views illustrating a manufacturing method of the image display device of the present embodiment and a modification thereof.
  • a semiconductor growth substrate (second substrate) 1194 is prepared in the manufacturing method of the image display device 1 of the present embodiment.
  • the semiconductor growth substrate 1194 has a semiconductor layer 1150 grown on the crystal growth substrate (first substrate) 1001.
  • the crystal growth substrate 1001 is, for example, a Si substrate, a sapphire substrate, or the like.
  • a Si substrate is used.
  • the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are laminated on the crystal growth substrate 1001 in this order from the crystal growth substrate 1001 side.
  • a vapor phase growth method (Chemical Vapor Deposition, CVD method) is used, and an organic metal vapor deposition method (Metal Organic Chemical Vapor Deposition, MOCVD method) is preferably used.
  • the semiconductor layer 1150 is, for example, In X Al Y Ga 1-XY N (0 ⁇ X, 0 ⁇ Y, X + Y ⁇ 1) or the like.
  • the circuit board 1100 is prepared.
  • the circuit board (third board) 1100 includes the circuit 101 described with reference to FIG. 1 and the like.
  • a conductive layer 130 is formed on the first interlayer insulating film (first insulating film) 112 of the circuit board 1100.
  • the conductive layer 130 is formed, for example, by sputtering or the like through a mask in which a portion forming the light reflection plate 130a is opened.
  • the semiconductor growth substrate 1194 is turned upside down and bonded to the circuit board 1100 on which the conductive layer 130 is formed. More specifically, the bonded surface of the semiconductor growth substrate 1194 is an exposed surface of the n-type semiconductor layer 1151.
  • the bonded surfaces of the circuit board 1100 are the exposed surface of the interlayer insulating film 112 on which the conductive layer 130 is formed and the surface of the conductive layer 130. These sides face each other and the two are pasted together.
  • a low melting point metal or a low melting point alloy may be used for heat crimping.
  • the low melting point metal is, for example, Sn, In, etc.
  • the low melting point alloy can be, for example, an alloy containing Zn, In, Ga, Sn, Bi, etc. as main components.
  • the bonded surfaces of each substrate are flattened using chemical mechanical polishing (CMP), etc., and then the bonded surfaces are cleaned and adhered in vacuum by plasma treatment. You may let it.
  • CMP chemical mechanical polishing
  • FIGS. 6A-7B show two types of modifications relating to the wafer bonding process.
  • the steps of FIGS. 6A to 6C can be used instead of the steps of FIGS. 5A and 5B.
  • the steps of FIGS. 7A and 7B may be used.
  • the semiconductor layer 1150 is transferred to a support substrate 1190 different from the crystal growth substrate 1001.
  • the semiconductor growth substrate 1294 is prepared.
  • the semiconductor layer 1150 is grown on the crystal growth substrate 1001 in the order of the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 from the side of the crystal growth substrate 1001.
  • laminating the n-type semiconductor layer 1151 on the crystal growth substrate 1001 has an advantage that a large margin in the production process can be obtained and the yield can be easily improved.
  • the support substrate 1190 is adhered to the exposed surface of the p-type semiconductor layer 1153.
  • the support substrate 1190 is made of, for example, Si or quartz.
  • the crystal growth substrate 1001 is removed. For removing the crystal growth substrate 1001, for example, wet etching or laser lift-off is used.
  • the circuit board 1100 is prepared.
  • the semiconductor layer 1150 is bonded to the circuit board 1100 on which the conductive layer 130 is formed via the exposed surface of the n-type semiconductor layer 1151.
  • the support substrate 1190 is removed by laser lift-off or the like.
  • the semiconductor layer 1150 is formed on the buffer layer 1140 after the buffer layer 1140 is provided on the crystal growth substrate 1001.
  • the semiconductor growth substrate 1194a is prepared.
  • the semiconductor layer 1150 is formed on the crystal growth substrate 1001 via the buffer layer 1140.
  • the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are laminated on the crystal growth substrate 1001 in this order from the crystal growth substrate 1001 side.
  • the buffer layer 1140 is formed on one surface of the crystal growth substrate 1001.
  • nitride such as AlN is preferably used.
  • the circuit board 1100 is prepared.
  • the 1194a is inverted upside down and is attached to the circuit board 1100 on which the conductive layer 130 is formed via the exposed surface of the n-type semiconductor layer 1151.
  • the crystal growth substrate 1001 is removed by laser lift-off or the like.
  • the buffer layer 1140 since the buffer layer 1140 remains after the removal of the crystal growth substrate 1001, the buffer layer 1140 is removed in any of the subsequent steps.
  • the removal of the buffer layer 1140 may be performed, for example, after the step of forming the light emitting element 150 or before forming the light emitting element 150. Wet etching or the like is used to remove the buffer layer 1140.
  • the explanation will be continued by returning to the manufacturing process after wafer bonding.
  • the circuit board 1100 on which the conductive layer 130 is formed is bonded to the semiconductor layer 1150 by wafer bonding, the crystal growth substrate 1001 is removed by wet etching, laser lift-off, or the like.
  • the semiconductor layer 1150 is formed into a required shape by etching.
  • etching for molding the light emitting element 150, for example, a dry etching process is used, and preferably anisotropic plasma etching (Reactive Ion Etching, RIE) is used.
  • RIE reactive Ion Etching
  • the second interlayer insulating film 156 is formed by covering the first interlayer insulating film 112, the conductive layer 130, and the light emitting element 150.
  • a contact hole 162a is formed in the second interlayer insulating film 156.
  • a via hole 162k is formed that penetrates the interlayer insulating film 156. Beer holes 162d penetrating the interlayer insulating films 112 and 156 are formed. For example, RIE or the like is used for forming contact holes and via holes.
  • the second interlayer insulating film 156 may cover the light emitting element 150 even if the surface is not flat. When the surface of the second interlayer insulating film 156 is not flat, the depths of the via holes 162k and 162d can be made shallow, so that the size of the opening diameter of each via hole can be reduced and the yield can be improved. be able to.
  • vias 161d, 161k and the like are formed by filling the contact holes 162a and via holes 162d and 162k shown in FIG. 9A with a conductive material. After that, the second wiring layer 160 is formed, and the wirings 160a and 160k are formed. Alternatively, the via holes 162d and 162k may be filled with the conductive material to form the vias 161d and 161k, and at the same time, the second wiring layer 160 may be formed.
  • the interlayer insulating film 156 may be provided with insulating properties by covering the light emitting element 150 and the like.
  • the flatness of the surface of the interlayer insulating film 156 may be such that a second wiring layer 160 can be formed on the interlayer insulating film 156, and the flattening step may not be performed.
  • the number of steps can be reduced, and the thickness of the interlayer insulating film 156 can be reduced except in the place where the light emitting element 150 is formed. is there.
  • the depths of the via holes 162k and 162d can be made shallow. By making the depth of the via hole shallow, it is possible to secure a sufficient opening diameter over the depth at which the via hole is formed, so that it becomes easy to secure an electrical connection by the via. Therefore, it is possible to suppress a decrease in yield due to poor electrical characteristics.
  • 10A and 10B are schematic cross-sectional views illustrating a method of manufacturing a modified example of the image display device of the present embodiment.
  • 10A and 10B show a manufacturing process for forming the subpixel 20a shown in FIG. 2A.
  • the same steps as in the case of the first embodiment are performed until the second interlayer insulating film 256 (156) is formed and the via hole is formed.
  • FIGS. 10A and 10B are executed after the step of FIG. 9A.
  • the second interlayer insulating film 256 is etched to form an opening 158 to expose the light emitting surface 153S of the p-type semiconductor layer 153a.
  • the etching may be wet etching or dry etching. After that, the light emitting surface 153S of the exposed p-type semiconductor layer 153a is roughened in order to improve the luminous efficiency.
  • the wiring layer 160 including the opening 158 is formed, and each wiring 160a1,160k is formed by photolithography.
  • the wiring 160a1 is formed so as to be connected to the surface of the exposed p-type semiconductor layer 153a including the light emitting surface 153S.
  • the subpixel 20a of the modified example is formed.
  • 11A and 11B are schematic cross-sectional views illustrating a method of manufacturing a modified example of the image display device of the present embodiment.
  • 11A and 11B show the manufacturing process for forming the subpixel 20b shown in FIG. 2B.
  • the same steps as in the case of the above-mentioned modified example are obtained until the opening 158 is formed. Therefore, in the following description, it is assumed that the steps of FIGS. 11A and 11B are executed after FIG. 10A.
  • the light emitting surface 153S is roughened.
  • the wiring layer 160 including the wiring 160a2, 160k is formed. The wiring 160a2 is not connected to the surface including the light emitting surface 153S.
  • a translucent conductive film covering the wiring layer 160, the second interlayer insulating film 256, and the light emitting surface 153S is formed.
  • the translucent conductive film an ITO film, a ZnO film, or the like is preferably used.
  • the translucent conductive film includes translucent electrodes 159a and 159k.
  • the translucent electrode 159a is formed on the wiring 160a2 and also on the light emitting surface 153S of the p-type semiconductor layer 153. Therefore, the wiring 160a2 and the p-type semiconductor layer 153 are electrically connected.
  • the translucent electrode 159a is provided so as to cover the entire surface of the exposed light emitting surface 153S and is connected to the light emitting surface 153S.
  • a part of the circuit other than the subpixel 20 is formed in the circuit board 1100.
  • the row selection circuit 5 shown in FIG. 3 is formed in the circuit board 1100 together with the drive transistor, the selection transistor, and the like. That is, the row selection circuit 5 may be incorporated at the same time by the manufacturing process described above.
  • the signal voltage output circuit 7 is incorporated in a semiconductor device manufactured by a manufacturing process capable of high integration by microfabrication.
  • the signal voltage output circuit 7 is mounted on another board together with the CPU and other circuit elements, and is interconnected with the wiring of the circuit board 1100, for example, before incorporating the color filter described later or after incorporating the color filter. Will be done.
  • the circuit board 1100 includes a substrate 102 made of a glass substrate including the circuit 101, and the substrate 102 is substantially square.
  • a circuit 101 for one or more image display devices is formed on the circuit board 1100.
  • the circuit 101 for forming one image display device is divided into a plurality of circuit boards 1100 and formed, and all of the divided circuits are combined to form 1 One image display device may be configured.
  • a semiconductor layer 1150 having substantially the same dimensions as the crystal growth substrate 1001 is formed on the crystal growth substrate 1001.
  • the crystal growth substrate 1001 can be a rectangle having the same dimensions as the rectangular circuit board 1100.
  • the crystal growth substrate is not limited to the same shape as the circuit board 1100 or a similar shape, and may have other shapes.
  • the crystal growth substrate 1001 may have a substantially circular wafer shape having a diameter including the circuit 101 formed on the square circuit board 1100.
  • FIG. 12 is a perspective view illustrating a method of manufacturing the image display device of the present embodiment. As shown in FIG. 12, a plurality of semiconductor growth substrates 1194 may be prepared, and the semiconductor layers 1150 formed on the plurality of crystal growth substrates 1001 may be bonded to one circuit board 1100.
  • a plurality of circuits 101 are arranged, for example, in a grid pattern on one board 102.
  • the circuit 101 includes all the subpixels 20 and the like required for one image display device 1.
  • the circuits 101 arranged adjacent to each other are provided with an interval of about the width of the scribe line. No circuit element or the like is arranged at the end of the circuit 101 or near the end.
  • the end of the semiconductor layer 1150 is formed so as to coincide with the end of the crystal growth substrate 1001. Therefore, by arranging the end portion of the semiconductor growth substrate 1194 so as to coincide with the end portion of the circuit 101 and joining the semiconductor layer 1194, the end portion of the semiconductor layer 1150 after joining can be matched with the end portion of the circuit 101. it can.
  • the crystal quality is likely to deteriorate at the end of the semiconductor layer 1150 and its vicinity. Therefore, by matching the end portion of the semiconductor layer 1150 with the end portion of the circuit 101, a region in the vicinity of the end portion of the semiconductor layer 1150 on the semiconductor growth substrate 1194 where the crystal quality is likely to deteriorate is a display region of the image display device 1. Can be avoided.
  • a plurality of circuit boards 1100 are prepared, and the plurality of circuit boards 1100 are bonded to the semiconductor layer 1150 formed on the crystal growth substrate 1001 of one semiconductor growth substrate 1194. You may.
  • FIG. 13 is a schematic cross-sectional view illustrating the method for manufacturing the image display device of the present embodiment.
  • the structure inside the circuit board 1100, the interlayer insulating film 112, the vias 161d, 161k, the wiring layer 160, and the like are not shown.
  • a part of the color conversion member such as the color filter 180 is displayed.
  • a structure including a conductive layer 130, a light emitting element 150, an interlayer insulating film 156, a surface resin layer 170, and vias whose display is omitted is referred to as a light emitting circuit unit 172.
  • a structure in which the light emitting circuit unit 172 is provided on the circuit board 1100 is referred to as a structure 1192.
  • the color filter (wavelength conversion member) 180 is adhered to the structure 1192 on one surface.
  • the other surface of the color filter 180 is adhered to the glass substrate 186.
  • a transparent thin film adhesive layer 188 is provided on one surface of the color filter 180, and is adhered to the surface of the structure 1192 on the light emitting circuit portion 172 side via the transparent thin film adhesive layer 188.
  • the color filter 180 has color conversion units arranged in the positive direction of the X-axis in the order of red, green, and blue.
  • a red color conversion layer 183R is provided on the first layer
  • a green color conversion layer 183G is provided on the first layer
  • a filter layer 184 is provided on the second layer.
  • Each is provided.
  • a single-layer color conversion layer 183B may be provided, or a filter layer 184 may be provided.
  • a light-shielding unit 181 is provided between the color conversion units.
  • the color filter 180 is attached to the structure 1192 by aligning the positions of the color conversion layers 183R, 183G, and 183B of each color with the positions of the light emitting element 150.
  • 14A to 14D are schematic cross-sectional views showing a modified example of the manufacturing method of the image display device of the present embodiment.
  • 14A-14D show a method of forming a color filter by an inkjet.
  • a structure 1192 having a light emitting circuit unit 172 attached to the circuit board 1100 is prepared.
  • a light-shielding portion 181 is formed on the structure 1192.
  • the light-shielding portion 181 is formed by using, for example, screen printing, photolithography technology, or the like.
  • the phosphor corresponding to the emitted color is ejected from the inkjet nozzle to form the color conversion layer 183.
  • the phosphor colors the region where the light-shielding portion 181 is not formed.
  • a general fluorescent material, a perovskite fluorescent material, or a fluorescent paint using a quantum dot fluorescent material is used.
  • a perovskite phosphor material or a quantum dot phosphor material it is preferable because each emission color can be realized, monochromaticity is high, and color reproducibility can be high.
  • a drying process is performed at an appropriate temperature and time. The thickness of the coating film at the time of coloring is set to be thinner than the thickness of the light-shielding portion 181.
  • the phosphor is not ejected.
  • the thickness of the coating film of the blue phosphor is preferably the light shielding portion 181. It is said to be about the same thickness as.
  • the paint for the filter layer 184 is ejected from the inkjet nozzle.
  • the paint is applied over the coating film of the phosphor.
  • the total thickness of the coating film of the phosphor and the paint is about the same as the thickness of the light-shielding portion 181.
  • the semiconductor layer 1150 including the light emitting layer 1152 for forming the light emitting element 150 is attached to the circuit board 1100 including the circuit element such as the transistor 103 for driving the light emitting element 150. match. After that, the semiconductor layer 1150 is etched to form the light emitting element 150. Therefore, the step of transferring the light emitting element can be remarkably shortened as compared with the case of individually transferring the light emitting element separated into the circuit board 1100.
  • the number of subpixels exceeds 24 million, and in the case of an 8K image quality image display device, the number of subpixels exceeds 99 million. It takes an enormous amount of time to mount such a large number of light emitting elements individually on a circuit board, and it is difficult to realize an image display device using micro LEDs at a realistic cost. Further, if a large number of light emitting elements are individually mounted, the yield is reduced due to poor connection at the time of mounting, and further cost increase is unavoidable.
  • the entire semiconductor layer 1150 is attached to the circuit board 1100 before the semiconductor layer 1150 is fragmented, so that the transfer step is completed in one time. ..
  • the light emitting element is directly formed on the circuit board by etching or the like, the light emitting element and the circuit element in the circuit board 1100 are electrically connected by via formation, so that a uniform connection structure can be realized. , The decrease in yield can be suppressed.
  • the semiconductor layer 1150 is attached to the circuit board 1100 at the wafer level without being fragmented in advance or forming an electrode at a position corresponding to the circuit element, there is no need to perform alignment. Therefore, the pasting process can be easily performed in a short time. Since it is not necessary to align the light emitting element 150 at the time of pasting, the light emitting element 150 can be easily miniaturized, which is suitable for a high-definition display.
  • the TFT formed on the glass substrate can be used as the circuit board 1100, so that the existing flat panel manufacturing process or plant can be used.
  • the sub-pixels 20, 20a, and 20b include a conductive layer 130.
  • the conductive layer 130 includes a light reflecting plate 130a, and the light emitting elements 150 and 150a are provided on the light reflecting plate 130a.
  • the light emitting surfaces 153S of the light emitting elements 150 and 150a are provided on the side facing the interlayer insulating film 112 provided with the light reflecting plate 130a. Therefore, the light scattered downward from the light emitting elements 150 and 150a is reflected by the light reflecting plate 130a and distributed to the light emitting surface 153S side. Therefore, the luminous efficiency of the light emitting elements 150 and 150a is substantially improved.
  • the light reflecting plate 130a can block the scattered light below the light emitting elements 150 and 150a, it suppresses the irradiation of the circuit elements in the vicinity of the light emitting elements 150 and 150a and causes the circuit elements to malfunction. Etc. can be prevented.
  • the light reflecting plate 130a has conductivity and is ohmic-connected to the n-type semiconductor layer 151. Therefore, it can be used for electrical connection with the light emitting elements 150 and 150a, and the wiring on the light emitting surface 153S side can be reduced.
  • FIG. 15 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • FIG. 15 shows a cross section seen from an arrow at a position corresponding to the AA'line in FIG.
  • This embodiment differs from the other embodiments described above in that a plurality of light emitting elements 150-1 and 150-2 are provided on one light reflection plate 130a.
  • the same components as those in the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • a plurality of light emitting elements are provided on the light reflecting plate 130a having conductivity.
  • the plurality of light emitting elements are two light emitting elements 150-1 and 150-2.
  • the light emitting element 150-1 includes an n-type semiconductor layer 151-1, a light emitting layer 152-1 and a p-type semiconductor layer 153-1.
  • the n-type semiconductor layer 151-1, the light emitting layer 152-1 and the p-type semiconductor layer 153-1 are laminated in this order from the side of the interlayer insulating film 112 toward the side of the light emitting surface 153S1.
  • the light emitting element 150-2 includes an n-type semiconductor layer 151-2, a light emitting layer 152-2, and a p-type semiconductor layer 153-2.
  • the n-type semiconductor layer 151-2, the light emitting layer 152-2, and the p-type semiconductor layer 153-2 are also laminated in this order from the side of the interlayer insulating film 112 toward the side of the light emitting surface 153S2.
  • the areas of the two light emitting elements 150-1 and 150-2 in the XY plane view are different.
  • the area in the XY plane view is simply referred to as an area.
  • the area of the light emitting element 150-1 is smaller than the area of the light emitting element 150-2.
  • the area of the light emitting element is set according to the light emitting color of the red, green, and blue subpixels.
  • the areas of the light emitting elements 150-1 and 150-2 are appropriately set according to the visual sensitivity, the conversion efficiency of the color conversion unit 182 of the color filter 180, and the like.
  • the light reflection plate 130a is provided so as to reflect the downward scattered light of the light emitting elements 150-1 and 150-2 toward the light emitting surfaces 153S1 and 153S2 and to block the downward scattering.
  • the outer circumference of the light reflecting plate 130a includes the outer circumferences of the two light emitting elements 150-1 and 150-2 in an XY plan view.
  • the light reflection plate 130a has conductivity.
  • the light reflection plate 130a is ohmicly connected to the n-type semiconductor layer 151-1, 151-2. That is, the n-type semiconductor layers 151-1, 151-2, which are the cathode electrodes of the light emitting elements 150-1 and 150-2, are electrically connected to each other by the light reflection plate 130a.
  • the first interlayer insulating film 112, the conductive layer 130, and the light emitting elements 150-1 and 150-2 are covered with the second interlayer insulating film 256.
  • the second interlayer insulating film 256 has openings 258-1,258-2, and the light emitting surfaces 153S1,153S2 are exposed from openings 258-1,258-2.
  • a via 161k is provided so as to penetrate the interlayer insulating film 256.
  • One end of the via 161k is connected to the light reflecting plate 130a.
  • the other end of the via 161k is connected to the wiring 160k.
  • the wiring 160k is connected to, for example, the ground wire 4 of the circuit shown in FIG. Therefore, the n-type semiconductor layers 151-1, 151-2, which are the cathode electrodes of the light emitting devices 150-1 and 150-2, are electrically connected to the ground wire 4 via the light reflection plate 130a, the via 161k, and the wiring 160k. It is connected.
  • the via 161d is provided so as to penetrate the interlayer insulating films 112 and 256, and the wirings 110d and 160a2-1 are connected via the via 161d.
  • a translucent electrode 159a1 is provided over the light emitting surface 153S1.
  • the translucent electrode 159a1 is also provided on the wiring 160a2-1.
  • the translucent electrode 159a1 is provided between the light emitting surface 153S1 and the wiring 160a2-1, and electrically connects the p-type semiconductor layer 153-1 and the wiring 160a2-1. Therefore, the p-type semiconductor layer 153-1 which is the anode electrode of the light emitting element 150-1 is electrically connected to the drain electrode of the transistor 103 via the translucent electrode 159a1, the wiring 160a2-1, the via 161d and the wiring 110d. It is connected.
  • a translucent electrode 159a2 is provided over the light emitting surface 153S2 of the light emitting element 150-2.
  • the light emitting element 150-2 is a part of the subpixel adjacent to the subpixel by the light emitting element 150-2.
  • the light emitting element 150-2 is electrically connected to a transistor different from the transistor 103 in the same way that the transistor 103 and the light emitting element 150-1 are electrically connected.
  • 16A to 16C are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • the step of bonding the semiconductor layer 1150 and the circuit board 1100 on which the conductive layer 130 is formed is the same as in the case of the other embodiments described above.
  • the steps after the process shown in FIG. 8A will be described.
  • the semiconductor layer 1150 is formed into a required shape by RIE or the like, and light emitting elements 150-1 and 150-2 are formed.
  • the first interlayer insulating film 112, the conductive layer 130, and the light emitting elements 150-1 and 150-2 are covered to form the second interlayer insulating film 256.
  • the via hole 162k is formed so as to penetrate the second interlayer insulating film 256.
  • the via hole 162d is formed so as to penetrate the interlayer insulating films 112 and 256.
  • openings 258-1,258-2 are formed in the interlayer insulating film 156, and the light emitting surfaces 153S1 and 153S2 are exposed.
  • the openings 258-1 and 258-2 may be formed before the via holes 162k and the via holes 162d are formed, or after the via holes 162k and the via holes 162d are formed.
  • the via holes 162d and 162k are filled with the conductive material.
  • the second wiring layer 160 is formed.
  • a translucent electrode 159a1 is formed on the light emitting surface 153S1 and over the wiring 160a2-1, and the p-type semiconductor layer 153-1 and the wiring 160a2-1 are electrically connected.
  • a translucent electrode 159a2 is formed over the light emitting surface 153S2, and the translucent electrode 159a2 is electrically connected to an electrode for another driving transistor different from the transistor 103.
  • a translucent electrode 159k is also formed on the wiring 160k at the same time.
  • a color filter is formed as in the case of other embodiments.
  • the image display device of the present embodiment can be manufactured.
  • This embodiment also has the same effect as that of the other embodiments described above. That is, since the semiconductor layers 1150 are bonded to the circuit board 1100 and then the individual light emitting elements 150-1 and 150-2 are formed by etching, the transfer process of the light emitting elements can be significantly shortened.
  • a plurality of light emitting elements 150-1 and 150-2 are provided on the light reflecting plate 130a of the conductive layer 130, and the n-type semiconductor layer 151- 1,151-2 are electrically connected to each other. Therefore, since the plurality of light emitting elements 150-1 and 150-2 are electrically connected by the light reflecting plate 130a, it is possible to reduce the wiring routing on the light emitting surfaces 153S1 and 153S2 sides and improve the circuit layout efficiency. Can be done.
  • FIG. 17 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • FIG. 17 shows an arrow cross section at a position corresponding to the AA'line in FIG.
  • the configuration of the light emitting element 350 and the configuration of the transistor 203 for driving the light emitting element 350 are different from those of the other embodiments described above.
  • the conductive layer 330 includes the light reflection plate 330a, and the configuration of the light reflection plate 330a is different from that of the other embodiments described above.
  • the same components as those in the other embodiments described above are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.
  • the subpixel 320 of the image display device of the present embodiment includes the transistor 203, the light emitting element 350, and the light reflection plate 330a.
  • Transistor 203 is an n-channel TFT in this example.
  • Transistor 203 includes a TFT channel 204 and a gate 107.
  • the TFT channel 204 is a region of polycrystalline Si formed on the first surface 102a of the substrate 102, and is polycrystalline and activated by annealing the region formed as amorphous Si by laser irradiation. ..
  • the TFT channel 204 includes regions 204s, 204i, 204d.
  • the regions 204s, 204i, and 204d are all provided on the TFT underlayer film 106.
  • the area 204i is provided between the areas 204s and 204d.
  • Regions 204s and 204d are doped with n-type impurities such as P, and are ohmic-connected to vias 111s and 111d.
  • the gate 107 is provided on the TFT channel 204 via the insulating layer 105. When a potential higher than the region 204s is applied to the gate 107, a channel is formed in the region 204i to control the current flowing between the regions 204s and 204d.
  • the structure of the upper part of the transistor 203 and the structure of the wiring layer are the same as those of the other embodiments described above.
  • the light reflection plate 330a is provided on the interlayer insulating film 112.
  • the light emitting element 350 is provided on the light reflecting plate 330a.
  • the light reflecting plate 330a is provided over the interlayer insulating film 112, and light emitting elements for other subpixels such as adjacent subpixels are also provided on the same light reflecting plate 330a.
  • the light reflecting plate 330a is connected to, for example, the power line 3 shown in the circuit of FIG. 18 described later. That is, the anode electrodes of the light emitting element 350 constituting each subpixel 320 of the image display device of the present embodiment are electrically connected to the power supply line 3 via the light reflection plate 330a as common wiring.
  • the conductive layer 330 includes a through hole 331.
  • the through hole 331 is provided in the light reflecting plate 330a, and is provided for each light emitting element 350.
  • the through hole 331 is provided at a position corresponding to the position of the via 161d3 penetrating the interlayer insulating films 112 and 256 in the XY plan view.
  • the through hole 331 has a diameter larger than the diameter of the via 161d3 so that the via 161d3 does not come into contact with the through hole 331.
  • the material of the interlayer insulating film 256 is filled between the through hole 331 through which the via 161d3 is penetrated and the via 161d3.
  • the light emitting element 350 includes a p-type semiconductor layer (first semiconductor layer) 353, a light emitting layer 352, and an n-type semiconductor layer (second semiconductor layer) 351.
  • the p-type semiconductor layer 353, the light emitting layer 352, and the n-type semiconductor layer 351 are laminated in this order from the first interlayer insulating film 112 of the circuit board 100 toward the light emitting surface 351S.
  • the light emitting element 350 has, for example, a substantially square or rectangular shape in XY plan view, but the corners may be rounded.
  • the light emitting element 350 may have, for example, an elliptical shape or a circular shape in an XY plan view. The degree of freedom in layout is improved by appropriately selecting the shape and arrangement of the light emitting elements in a plan view.
  • the light emitting element 350 may be made of the same material as in the other embodiments described above.
  • the light emitting element 350 emits blue light having a wavelength of, for example, 467 nm ⁇ 20 nm or bluish purple light having a wavelength of 410 nm ⁇ 20 nm.
  • the second interlayer insulating film (second insulating film) 256 covers the first interlayer insulating film 112 and the light emitting element 350.
  • the second interlayer insulating film 256 has an opening 358.
  • the opening 358 is formed on the light emitting element 350, and the interlayer insulating film 256 is not provided on the light emitting surface 351S of the light emitting element 350.
  • a white resin is preferably used so that the light emitting element 350 reflects the light emitted and is effectively radiated from the opening 358, but it is different from the case of the modification of the other embodiment described above. Similarly, it may be a black resin.
  • the light emitting surface 351S is a surface of the n-type semiconductor layer 351 facing the surface in contact with the light emitting layer 352.
  • the light emitting surface 351S is roughened.
  • Vias 161d3 are provided so as to penetrate the interlayer insulating films 112 and 256 and the light reflecting plate 330a. One end of the via 161d3 is connected to the wiring 110d.
  • the wiring layer 160 is provided on the interlayer insulating film 256.
  • the wiring layer 160 includes wiring 160k3.
  • One end of the via 161d3 penetrating the second interlayer insulating film 256 is connected to the wiring 110d, and the other end of the via 161d3 is connected to the wiring 160k3.
  • An opening 358 is provided at a position corresponding to the light emitting element 350 of the interlayer insulating film 256.
  • the light emitting surface 351S is exposed from the opening 358.
  • a translucent electrode 159k3 is provided over the exposed light emitting surface 351S.
  • the translucent electrode 159k3 is also provided on the wiring 160k3.
  • the translucent electrode 159k3 is provided between the light emitting surface 351S and the wiring 160k3, and connects the n-type semiconductor layer 351 and the wiring 160k3. Therefore, the n-type semiconductor layer 351 is electrically connected to the region 104d corresponding to the drain electrode of the transistor 203 via the translucent electrode 159k3, the wiring 160k3, the via 161d3, and the wiring 110d.
  • connection may be made directly to the wiring 160k3 without using the translucent electrode 159k3.
  • the second interlayer insulating film may be made of a transparent resin so that the wiring can be connected without forming the opening 358. In these cases, the roughening step may be omitted.
  • FIG. 18 is a schematic block diagram illustrating an image display device according to the present embodiment.
  • the image display device 301 of the present embodiment includes a display area 2, a row selection circuit 305, and a signal voltage output circuit 307.
  • the subpixels 320 are arranged in a grid pattern on the XY plane, as in the case of the other embodiment described above.
  • Pixel 10 includes a plurality of subpixels 320 that emit light of different colors, as in the case of the other embodiments described above.
  • the subpixel 320R emits red light.
  • the subpixel 320G emits green light.
  • the subpixel 320B emits blue light.
  • the emission color and brightness of one pixel 10 are determined by the three types of sub-pixels 320R, 320G, and 320B emitting light with desired brightness.
  • One pixel 10 is composed of three sub-pixels 320R, 320G, 320B, and the sub-pixels 320R, 320G, 320B are linearly arranged on the X-axis, for example, as in this example.
  • subpixels of the same color may be arranged in the same column, or subpixels of different colors may be arranged for each column as in this example.
  • the subpixel 320 includes a light emitting element 322, a selection transistor 324, a drive transistor 326, and a capacitor 328.
  • the selection transistor 324 may be displayed as T1
  • the drive transistor 326 may be displayed as T2
  • the capacitor 328 may be displayed as Cm.
  • the light emitting element 322 is provided on the power supply line 3 side, and the drive transistor 326 connected in series with the light emitting element 322 is provided on the ground line 4 side. That is, the drive transistor 326 is connected to the lower potential side than the light emitting element 322.
  • the drive transistor 326 is an n-channel transistor.
  • a selection transistor 324 is connected between the gate electrode of the drive transistor 326 and the signal line 308.
  • the capacitor 328 is connected between the gate electrode of the drive transistor 326 and the ground wire 4.
  • the row selection circuit 305 and the signal voltage output circuit 307 supply the signal line 308 with a signal voltage having a polarity different from that of the other embodiments described above in order to drive the drive transistor 326 which is an n-channel transistor.
  • the row selection circuit 305 supplies a selection signal to the scanning line 306 so as to sequentially select one row from the array of subpixels 320 in the m row.
  • the signal voltage output circuit 307 supplies a signal voltage having the required analog voltage value for each subpixel 320 in the selected row.
  • the drive transistor 326 of the subpixel 320 in the selected row causes a current corresponding to the signal voltage to flow through the light emitting element 322.
  • the light emitting element 322 emits light with a brightness corresponding to the flowing current.
  • 19A to 21C are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • the semiconductor growth substrate 1294 is used in this embodiment.
  • the semiconductor layer 1150 is grown and laminated on the crystal growth substrate 1001 in the order of the n-type semiconductor layer 1151, the light emitting layer 1152, and the p-type semiconductor layer 1153 from the side of the crystal growth substrate 1001. ..
  • a metal layer 1130 is formed on the exposed surface of the p-type semiconductor layer 1153 facing the surface provided with the light emitting layer 1152.
  • the metal layer 1130 includes, for example, Ti, Al, an alloy of Ti and Sn, and the like. It may contain a noble metal having high light reflectivity such as Cu and V, or Ag and Pt.
  • the metal layer By forming the metal layer on the surface of the p-type semiconductor layer 1153, the p-type semiconductor layer 1153 can be protected by the metal layer 1130, and the semiconductor growth substrate 1294 on which the metal layer 1130 is formed can be easily stored. Produce benefits.
  • a thin film layer using a hole-injectable material at the interface between the p-type semiconductor layer 1153 and the metal layer 1130 it is possible to further reduce the drive voltage of the above-mentioned light emitting element 350. ..
  • a material having hole injection property for example, an ITO film or the like can be preferably used.
  • the exposed surface of the metal layer 1130 provided on the semiconductor growth substrate 1294 and the open surface of the first interlayer insulating film 112 of the circuit board 1100 are bonded together.
  • the semiconductor growth substrate is transferred to the support substrate, the crystal growth substrate 1001 is removed, the metal layer 1130 is formed, and then the semiconductor growth substrate is bonded.
  • the crystal growth substrate 1001 uses a semiconductor growth substrate 1194 in which the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 are grown and laminated in this order from the side of the crystal growth substrate 1001. Be done.
  • the semiconductor growth substrate 1194 has already been described in connection with FIG. 5A.
  • a metal layer 1130 is formed on the exposed surface of the p-type semiconductor layer 1153 of the semiconductor growth substrate 1194.
  • the semiconductor layer 1150 may be grown on the crystal growth substrate 1001 via the buffer layer, as described in the case of the first embodiment.
  • the metal layer may also be provided on the side of the circuit board 1100.
  • 20A and 20B show a case where the metal layer 1120 is also formed on the side of the circuit board 1100. As shown in FIG. 20A, the metal layer 1120 is formed on the interlayer insulating film 112 of the prepared circuit board 1100.
  • the circuit board 1100 on which the metal layer 1120 is formed is bonded to the semiconductor growth substrate 1294 on which the metal layer 1130 is formed.
  • wafer bonding can be performed more easily by using the same metal material in each metal layer or by using an alloy containing the same metal material.
  • the metal layer may be provided on at least one of the semiconductor growth substrate 1294 side and the circuit board 1100 side.
  • the crystal growth substrate 1001 is removed by wet etching, laser lift-off, or the like, and the semiconductor layer 1150 is etched by anisotropic etching or the like to form a light emitting element 350.
  • a through hole 331 is formed in the light reflecting plate 330a at a position corresponding to the wiring 110d.
  • the second interlayer insulating film 256 is formed so as to cover the conductive layer 330, the first interlayer insulating film 112, and the light emitting element 350.
  • via holes 162d3 are formed in the second interlayer insulating film 256.
  • RIE or the like is used to form the via hole 162d3.
  • an opening 358 is formed at a position corresponding to the light emitting element 350 of the interlayer insulating film 256.
  • the light emitting surface 351S exposed by the opening 358 is roughened.
  • the via hole 162d3 is filled with the conductive material. After that, or at the same time as filling the via hole, the second wiring layer 160 is formed, and the wiring 160k3 is formed.
  • a translucent electrode 159k3 is formed on the light emitting surface 351S and the wiring 160k3, and electrically connects the n-type semiconductor layer 351 and the wiring 160k3.
  • the surface resin layer 170 covering the interlayer insulating film 256 and the wiring layer 160 is formed to form a superstructure such as a color filter, and then for each image display device 301. Will be disconnected. In this way, the image display device 301 can be manufactured.
  • the light reflecting plate 330a is not limited to a single case, but is provided in an island shape for each light emitting element 350 or for each of a plurality of light emitting elements 350, and the plurality of light reflecting plates 330a are electrically connected by wiring included in the conductive layer 330. You may try to do it.
  • the light reflecting plate 330a of the conductive layer 330 is connected to the same potential for the light emitting elements 350 corresponding to all the subpixels 320, but for example, different power lines 3, that is, separated from each other. It may be connected to the power supply potential.
  • This embodiment also has the same effect as that of the other embodiments described above. That is, since the semiconductor layer 1150 is bonded to the circuit board 1100 and then the individual light emitting elements 350 are formed by etching, the transfer process of the light emitting elements can be significantly shortened.
  • the conductive layer 330 may include a single light reflecting plate 330a, and a simple pattern including only the through hole 331 can be formed. , Pattern design becomes easy, and the development period of the image display device can be shortened.
  • the n-type semiconductor layer 351 can be roughened more easily by forming the light emitting surface 351S, and the wiring 160k3 is connected to the light emitting surface 351S to form a subpixel having high luminous efficiency. can do.
  • the light emitting surface is roughened, the thicker the semiconductor layer to be roughened, the deeper the etching can be performed and the connection area can be increased. Since the n-type semiconductor layer 351 can easily have a low resistance and can be formed thicker without increasing the resistance value, there is an advantage that it can be etched deeper.
  • FIG. 22 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • FIG. 22 shows a cross section seen from an arrow at a position corresponding to the AA'line shown in FIG.
  • the image display device of this embodiment includes a subpixel 420.
  • Subpixel 420 includes substrate 402.
  • the substrate 402 includes a first surface 402a.
  • Circuit elements such as the transistor 103 are provided on the first surface 402a.
  • the superstructure including the circuit element is formed on the first surface 402a.
  • the substrate 402 has flexibility.
  • the substrate 402 is, for example, a polyimide resin or the like.
  • the interlayer insulating films 112, 156, wiring layers 110, 160, and the like are preferably formed of a material having a certain degree of flexibility depending on the flexibility of the substrate 402.
  • the wiring layer 110 having the longest wiring length has the highest risk of being destroyed during bending. Therefore, it is desirable to adjust various film thicknesses and film qualities so that the neutral surface including a plurality of protective films added to the front surface and the back surface is the position of the wiring layer 110 as needed.
  • the transistor 103 and the light emitting element 150 formed on the substrate 402 are the same as in the case of the first embodiment, and for example, the circuit configuration of FIG. 3 is applied. Configurations including circuit configurations of other embodiments can also be easily applied.
  • FIG. 23A to 23B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the present embodiment.
  • a circuit board (third board) 4100 different from the case of the above-mentioned other embodiments is prepared.
  • the circuit board 4100 includes two layers of boards 102 and 402.
  • the substrate 402 (fourth substrate) is provided on the first surface 102a of the substrate 102, and is formed by, for example, applying and firing a polyimide material.
  • An inorganic film such as SiN x may be further sandwiched between the two layers of substrates 102 and 402.
  • the TFT lower layer film 106, the circuit 101, and the interlayer insulating film 112 are provided on the first surface 402a of the substrate 402.
  • the first surface 402a of the substrate 402 is a surface facing the surface on which the substrate 102 is provided.
  • the semiconductor layer 1150 of the prepared semiconductor growth substrate 1194 is bonded to such a circuit board 4100. After that, as in the case of the other embodiment described above, the light emitting element 150, the interlayer insulating film 156, and the second wiring layer 160 are formed, and a superstructure such as a color filter 180 is further formed. For example, the manufacturing process corresponding to FIGS. 5A to 14D already described is applied.
  • the substrate 102 is removed from the structure in which the superstructure such as the color filter is formed, and a new circuit board 4100a is formed.
  • a new circuit board 4100a is formed for removing the substrate 102.
  • laser lift-off or the like is used for removing the substrate 102.
  • the removal of the substrate 102 is not limited to the above-mentioned time point, and can be performed at another appropriate time point.
  • the substrate 102 may be removed after wafer bonding or before the formation of the color filter. By removing the substrate 102 at an earlier point in time, defects such as cracks and chips in the manufacturing process can be reduced.
  • the substrate 402 Since the substrate 402 has flexibility, it can be bent as an image display device, and can be attached to a curved surface, used for a wearable terminal, or the like without any discomfort.
  • FIG. 24 is a schematic cross-sectional view illustrating a part of the image display device according to the present embodiment.
  • the cross-sectional view of FIG. 24 shows a cross section in a parallel plane of the XZ plane.
  • the image display device includes a subpixel group 520.
  • the subpixel group 520 includes transistors 103-1 and 103-2, a first wiring layer 510, a first interlayer insulating film 112, a conductive layer 530, a semiconductor layer 550, and a second interlayer insulating film 556. And a second wiring layer 560 and vias 561d1, 561d2.
  • the semiconductor layer 550 includes two light emitting surfaces 553S1 and 553S2, and the subpixel group 520 substantially includes two subpixels.
  • the display area is formed by arranging the subpixel group 520 including substantially two subpixels in a grid pattern.
  • Transistors 103-1 and 103-2 are formed on TFT channels 104-1 and 104-2, respectively.
  • the TFT channels 104-1 and 104-2 contain p-shaped doped regions, including a channel region between these regions.
  • An insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gates 107-1 and 107-2 are formed via the insulating layer 105, respectively.
  • Gates 107-1 and 107-2 are gates of transistors 103-1 and 103-2.
  • transistors 103-1 and 103-2 are p-channel TFTs.
  • the insulating film 108 covers the two transistors 103-1 and 103-2.
  • a first wiring layer 510 is formed on the insulating film 108.
  • Vias 111s1 and 111d1 are provided between the p-shaped doped region of the transistor 103-1 and the wiring layer 510.
  • Vias 111s2 and 111d2 are provided between the p-shaped doped region of the transistor 103-2 and the wiring layer 510.
  • the first wiring layer 510 includes wiring 510s, 510d1, 510d2.
  • the wiring 510s is electrically connected to the region corresponding to the source electrode of the transistors 103-1 and 103-2 via the vias 111s1 and 111s2.
  • the wiring 510s is connected to, for example, the power supply line 3 of FIG.
  • the wiring 510d1 is connected to the region corresponding to the drain electrode of the transistor 103-1 via the via 111d1.
  • the wiring 510d2 is connected to the region corresponding to the drain electrode of the transistor 103-2 via the via 111d2.
  • the first interlayer insulating film 112 covers the transistors 103-1 and 103-2 and the wiring layer 510.
  • the semiconductor layer 550 is provided on the interlayer insulating film 112.
  • a single semiconductor layer 550 is provided between two driving transistors 103-1 and 103-2 arranged along the X-axis direction.
  • a conductive layer 530 is formed on the first interlayer insulating film 112.
  • the conductive layer 530 is provided between the semiconductor layer 550 and the first interlayer insulating film 112.
  • the conductive layer 530 includes a light reflecting plate (part) 530a having conductivity and light reflection, and the semiconductor layer 550 is provided on the light reflecting plate 530a.
  • the light reflecting plate 530a is connected to, for example, the ground wire 4 of the circuit of FIG. 3 described above.
  • a single semiconductor layer 550 is provided between two driving transistors 103-1 and 103-2 arranged along the X-axis direction.
  • the semiconductor layer 550 includes an n-type semiconductor layer (first semiconductor layer) 551, a light emitting layer 552, and a p-type semiconductor layer (second semiconductor layer) 553.
  • the semiconductor layer 550 is laminated in the order of the n-type semiconductor layer 551, the light emitting layer 552, and the p-type semiconductor layer 553 from the side of the interlayer insulating film 112 toward the side of the light emitting surfaces 553S1 and 553S2.
  • the light reflection plate 530a is electrically connected to the n-type semiconductor layer 551.
  • the second interlayer insulating film (second insulating film) 556 covers the first interlayer insulating film 112, the conductive layer 530, and the semiconductor layer 550.
  • the interlayer insulating film 556 covers a part of the semiconductor layer 550.
  • the interlayer insulating film 556 covers the surface of the p-type semiconductor layer 553 except for the light emitting surfaces 553S1 and 553S2 of the semiconductor layer 550.
  • the interlayer insulating film 556 covers the side surface of the semiconductor layer 550.
  • the interlayer insulating film 556 is preferably a white resin.
  • the portion of the semiconductor layer 550 that is not covered with the interlayer insulating film 556 is covered by the translucent electrodes 559a1 and 559a2.
  • the translucent electrodes 559a1 and 559a2 are provided on the light emitting surfaces 553S1 and 553S2 of the p-type semiconductor layer 553 exposed from the openings 558-1 and 558-2 of the interlayer insulating film 556, respectively.
  • the translucent electrodes 559a1 and 559a2 are electrically connected to the p-type semiconductor layer 553.
  • the vias 561d1 and 561d2 are provided so as to penetrate the interlayer insulating films 556 and 112. One end of the vias 561d1 and 561d2 is connected to the wirings 510d1 and 510d2, respectively.
  • the second wiring layer 560 is provided on the interlayer insulating film 556.
  • the wiring layer 560 includes wirings 560a1 and 560a2.
  • the via 561d1 is provided between the wiring 510d1 and the wiring 560a1.
  • the via 561d2 is provided between the wiring 510d2 and the wiring 560a2.
  • the other ends of the vias 561d1 and 561d2 are connected to the wirings 560a1 and 560a2, respectively.
  • a translucent electrode 559a1 is provided on the wiring 560a1, and the wiring 560a1 and the translucent electrode 559a1 are electrically connected to each other.
  • the translucent electrode 559a1 is extended to an opening 558-1.
  • the translucent electrode 559a1 is provided over the entire surface of the light emitting surface 553S1 exposed from the opening 558-1, and is electrically connected to the p-type semiconductor layer 553 via the light emitting surface 553S1.
  • a translucent electrode 559a2 is provided on the wiring 560a2, and the wiring 560a2 and the translucent electrode 559a2 are electrically connected to each other.
  • the translucent electrode 559a2 is extended to an opening 558-2.
  • the translucent electrode 559a2 is provided over the entire surface of the light emitting surface 553S2 exposed from the opening 558-2, and is electrically connected to the p-type semiconductor layer 553 via the light emitting surface 553S2.
  • An interlayer insulating film 556 is provided between the openings 558-1 and 558-2.
  • the openings 558-1 and 558-2 are provided between the wirings 560a1 and 560a2.
  • the openings 558-1 and 558-2 are, for example, square or rectangular in XY plan view.
  • the shape is not limited to a square, and may be a polygon such as a circle, an ellipse, or a hexagon.
  • the light emitting surfaces 553S1 and 553S2 are also squares, rectangles, other polygons, circles, etc. in XY plan view.
  • the shapes of the light emitting surfaces 553S1 and 553S2 may be similar to or different from the shapes of the openings 558-1 and 558-2.
  • the translucent electrodes 559a1 and 559a2 are connected to the light emitting surfaces 553S1 and 553S2 exposed from the openings 558-1 and 558-2, respectively.
  • the transistor 103-1 When the transistor 103-1 is turned on, holes are injected into the translucent electrode 559a1 via the wiring 560a1, the via 561d1 and the wiring 510d1.
  • the transistor 103-2 When the transistor 103-2 is turned on, holes are injected into the translucent electrode 559a2 via the wiring 560a2, the via 561d2, and the wiring 510d2.
  • electrons are injected into the n-type semiconductor layer 551 via the light reflection plate 530a connected to the ground wire 4.
  • Transistors 103-1 and 103-2 are driving transistors of adjacent subpixels, and are driven sequentially. Therefore, the holes injected from either one of the two transistors 103-1 and 103-2 are injected into the light emitting layer 552, and the electrons injected from the light reflection plate 530a are injected into the light emitting layer 352 to emit light. .. When the transistor 103-1 is turned on, the light emitting surface 553S1 emits light, and when the transistor 103-2 is turned on, the light emitting surface 553S2 emits light.
  • the light emission in the light emitting layer 552 is localized because the resistance of the p-type semiconductor layer 553 and the n-type semiconductor layer 551 suppresses the drift current flowing in the semiconductor layer 550 in the direction parallel to the XY plane. Because it is done.
  • 25A to 26B are schematic cross-sectional views illustrating the method of manufacturing the image display device of the embodiment.
  • the semiconductor growth substrate 1194a is prepared.
  • the semiconductor growth substrate 1194a is laminated on the crystal growth substrate 1001 via the buffer layer 1140 in the order of the p-type semiconductor layer 1153, the light emitting layer 1152, and the n-type semiconductor layer 1151 from the crystal growth substrate 1001 side.
  • a metal layer 1130 is formed on the exposed surface of the n-type semiconductor layer 1151 of the semiconductor growth substrate 1194a.
  • the semiconductor growth substrate 1194a on which the metal layer 1130 is formed is bonded to the prepared circuit board 5100.
  • transistors 103-1 and 103-2, a wiring layer 510, and an interlayer insulating film 112 are formed on a substrate 102 made of glass. It should be noted that the semiconductor layer 1150 may be grown on the semiconductor growth substrate without providing the buffer layer 1140, as in the case of the first embodiment described above.
  • the formation of the semiconductor growth substrate and the like is the same as the case already described in the case of the other embodiments described above and the modified examples thereof, and detailed description thereof will be omitted.
  • the circuit board 5100 may have a circuit configuration different from that of the other embodiments described above, but is the same as the structure already described in most of the other parts. In the following, only the reference numerals will be replaced and detailed description will be omitted as appropriate.
  • the crystal growth substrate 1001 is removed by wet etching, laser lift-off, or the like.
  • the buffer layer 1140 shown in FIG. 25B is removed, and the semiconductor layer 1150 is etched and formed into the semiconductor layer 550.
  • the semiconductor layer 1150 may be etched with the buffer layer 1140 as it is, and then the buffer layer 1140 may be removed.
  • the metal layer 1130 is also etched to form a conductive layer 530 including a light reflecting plate 530a.
  • the outer circumference of the light reflection plate 530a is formed so as to include the outer circumference of the semiconductor layer 1150 in XY plan view.
  • a second interlayer insulating film 556 is formed on the first interlayer insulating film 112 and the semiconductor layer 550. Vias 561d1 and 561d2 are formed on the interlayer insulating film 556. Further, the wiring layer 560 is formed, and the wirings 560a1, 560a2 and the like are formed.
  • openings 558-1 and 558-2 are formed between the wirings 560a1 and 560a2.
  • the light emitting surfaces 553S1 and 553S2 of the p-shaped semiconductor layer exposed by the openings 558-1 and 558-2 are roughened, respectively.
  • the translucent electrodes 559a1 and 559a2 are formed.
  • the sub-pixel group 520 having the semiconductor layer 550 sharing the two light emitting surfaces 553S1 and 553S2 is formed.
  • two light emitting surfaces 553S1 and 553S2 are provided on one semiconductor layer 550, but the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are one semiconductor. It can also be provided on layer 550. As an example, one row or two rows of subpixels may be realized by a single semiconductor layer 550. As a result, as will be described later, it is possible to reduce the recombination current that does not contribute to light emission per light emitting surface and increase the effect of realizing a finer light emitting element.
  • FIG. 27 is a schematic cross-sectional view illustrating a part of the image display device according to the modified example of the present embodiment.
  • This modification is different from the case of the fifth embodiment described above in that two p-type semiconductor layers 5553a1 and 5553a2 are provided on the light emitting layer 552. In other respects, it is the same as in the fifth embodiment.
  • the image display device of this modification includes a sub-pixel group 520a.
  • the subpixel group 520a includes a semiconductor layer 550a.
  • the semiconductor layer 550a includes an n-type semiconductor layer 551, a light emitting layer 552, and p-type semiconductor layers 5553a1,5553a2.
  • the n-type semiconductor layer 551, the light emitting layer 552, and the p-type semiconductor layer 5553a1,5553a2 are laminated in this order from the interlayer insulating film 112 toward the light emitting surface 5553S1,5553S2.
  • the p-type semiconductor layers 5553a1 and 5553a2 are arranged on the light emitting layer 552 at intervals along the X-axis direction.
  • An interlayer insulating film 556 is provided between the p-type semiconductor layers 5553a1 and 5553a2, and the p-type semiconductor layers 5553a1 and 5553a2 are separated by an interlayer insulating film 556.
  • the p-type semiconductor layers 5553a1 and 5553a2 have substantially the same shape in XY plan view, and the shape is substantially square or rectangular, and may be another polygonal shape, circular shape, or the like.
  • the p-type semiconductor layers 5553a1 and 5553a2 have light emitting surfaces 5553S1 and 5553S2, respectively.
  • the light emitting surfaces 5553S1 and 5553S2 are the surfaces of the p-type semiconductor layers 5553a1 and 5553a2 exposed by the openings 558-1 and 558-2, respectively.
  • the shapes of the light emitting surfaces 5553S1 and 5553S2 in the XY plan view have substantially the same shape as the shape of the light emitting surface in the case of the fifth embodiment, and have a shape such as a square.
  • the shape of the light emitting surfaces 5553S1 and 5553S2 is not limited to the square as in this embodiment, and may be a polygon such as a circle, an ellipse, or a hexagon.
  • the shapes of the light emitting surfaces 5553S1 and 5553S2 may be similar to or different from the shapes of the openings 558-1 and 558-2.
  • a translucent electrode 559a1 is provided on the light emitting surface 5553S1.
  • a translucent electrode 559a2 is also provided on the light emitting surface 5553S2.
  • the p-type semiconductor layer 5553a1 is connected to the wiring 560a1 via the translucent electrode 559a1 connected to the light emitting surface 5553S1.
  • the p-type semiconductor layer 5553a2 is connected to the wiring 560a2 via the translucent electrode 559a2 connected to the light emitting surface 5553S2.
  • 28A and 28B are schematic cross-sectional views illustrating a method of manufacturing an image display device of this modified example.
  • the same steps as those described in FIGS. 25A to 25B in the case of the fifth embodiment are adopted until the semiconductor layer 1150 is formed. The subsequent steps will be described below.
  • the buffer layer 1140, the n-type semiconductor layer 1151, the light emitting layer 1152 and the p-type semiconductor layer 1153 are etched to form the light emitting layer 552 and the n-type semiconductor layer 551, and then the light emitting layer 552 and the n-type semiconductor layer 551 are formed. Further, two p-type semiconductor layers 5553a1 and 5553a2 are formed by etching. The buffer layer 1140 may be removed after forming the p-type semiconductor layers 5553a1 and 5553a2.
  • the etching of the p-type semiconductor layers 5553a1 and 5553a2 is stopped when the light emitting layer 552 is reached.
  • the etching of the p-type semiconductor layers 5553a1 and 5553a2 may be advanced to a deeper position.
  • etching for forming the p-type semiconductor layers 5553a1 and 5553a2 may be performed until the depth in the light emitting layer 552 or the n-type semiconductor layer 551 is reached.
  • the light emitting surfaces 5553S1,5553S2 of the p-type semiconductor layer should be 1 ⁇ m or more inside from the end of the etched p-type semiconductor layer 5553a1,5553a2. Is desirable.
  • the recombination current can be suppressed by separating the position of the end portion of the p-type semiconductor layer 5553a1,5553a2 formed by etching from the light emitting surface 5553S1,5553S2.
  • the interlayer insulating film 112 and the interlayer insulating film 556 covering the semiconductor layer 550a are formed, and then vias 561d1 and 561d2 are formed. Further, the wiring layer 560 is formed, and the wirings 560a1, 560a2 and the like are formed.
  • the openings 558-1 and 558-2 are formed in the interlayer insulating film 556, respectively.
  • the light emitting surfaces 5553S1 and 5553S2 of the p-shaped semiconductor layer exposed by the openings 558-1 and 558-2 are roughened, respectively. After that, the translucent electrodes 559a1 and 559a2 are formed.
  • the sub-pixel group 520a having two light emitting surfaces 5553S1 and 5553S2 is formed.
  • the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces are provided on one semiconductor layer 550a. May be good.
  • FIG. 29 is a graph illustrating the characteristics of the pixel LED element.
  • the vertical axis of FIG. 29 represents the luminous efficiency [%].
  • the horizontal axis represents the current density of the current flowing through the pixel LED element as a relative value.
  • the luminous efficiency of the pixel LED element increases substantially constant or monotonously.
  • the luminous efficiency decreases monotonically. That is, the pixel LED element has an appropriate current density that maximizes the luminous efficiency.
  • the light emitting elements 150, 150a, 150-1, 150-2, 350 are all layers of the semiconductor layer 1150 including the light emitting layers 152, 152-1, 152-2, 352. Is formed by separating them individually by etching or the like. At this time, the joint surface between the light emitting layers 152, 152-1, 152-2, 352 and the n-type semiconductor layer 151, 151-1, 151-2, 351 is exposed at the end. Similarly, the joint surface between the light emitting layers 152, 152-1, 152-2, 352 and the p-type semiconductor layers 153, 153a, 153-1, 153-2, 353 is exposed at the end.
  • the ends are formed in all directions for each light emitting element, so that recombination may occur at a total of eight ends.
  • the semiconductor layers 550 and 550a having two light emitting surfaces have four ends. Since the region between the openings 558-1 and 558-2 has few electrons and holes injected and hardly contributes to light emission, it can be considered that the number of ends contributing to light emission is six. As described above, in the present embodiment, the number of end portions of the semiconductor layer is substantially reduced to reduce recombination that does not contribute to light emission, and the reduction in recombination current makes it possible to reduce the drive current. To.
  • the distance between the light emitting surfaces 553S1 and 553S2 in the subpixel group 520 of the fifth embodiment is used. Becomes shorter. In this case, if the p-type semiconductor layer 553 is shared, a part of the electrons injected to the side of the adjacent light emitting surface may be diverted, and the light emitting surface on the non-driven side may emit a small amount of light. ..
  • the p-type semiconductor layers 5553a1 and 5553a2 are separated for each of the light emitting surfaces 5553S1 and 5553S2, it is possible to reduce the occurrence of slight light emission on the light emitting surface on the non-driven side.
  • the semiconductor layer including the light emitting layer is formed by laminating the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer in this order from the side of the interlayer insulating film 112, and roughens the exposed surface of the p-type semiconductor layer. It is preferable from the viewpoint of surface-forming and improving luminous efficiency.
  • the stacking order of the n-type semiconductor layer and the p-type semiconductor layer may be changed, and the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer may be laminated in this order.
  • the stacking order of the light emitting elements can be changed and applied by the above-mentioned appropriate manufacturing procedure.
  • the light emitting device of the first embodiment can be laminated in the order of the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer from the first interlayer insulating film 112 toward the light emitting surface.
  • the light emitting device of the third embodiment can be laminated in the order of the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer from the first interlayer insulating film 112 toward the light emitting surface.
  • the image display device described above can be an image display module having an appropriate number of pixels, for example, a computer display, a television, a portable terminal such as a smartphone, a car navigation system, or the like.
  • FIG. 30 is a block diagram illustrating an image display device according to the present embodiment.
  • FIG. 30 shows the main parts of the configuration of a computer display.
  • the image display device 601 includes an image display module 602.
  • the image display module 602 is, for example, an image display device having the configuration in the case of the first embodiment described above.
  • the image display module 602 includes a display area 2 in which the subpixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7.
  • the image display device 601 may include the configuration according to any one of the second to fifth embodiments.
  • the image display device 601 further includes a controller 670.
  • the controller 670 inputs control signals separated and generated by an interface circuit (not shown) to control the drive and drive order of each subpixel with respect to the row selection circuit 5 and the signal voltage output circuit 7.
  • FIG. 31 is a block diagram illustrating an image display device of this modified example.
  • FIG. 31 shows the configuration of a high-definition flat-screen television.
  • the image display device 701 includes an image display module 702.
  • the image display module 702 is, for example, an image display device 1 having the configuration of the first embodiment described above.
  • the image display device 701 includes a controller 770 and a frame memory 780.
  • the controller 770 controls the drive order of each subpixel in the display area 2 based on the control signal supplied by the bus 740.
  • the frame memory 780 stores display data for one frame and is used for processing such as smooth moving image reproduction.
  • the image display device 701 has an I / O circuit 710.
  • the I / O circuit 710 provides an interface circuit or the like for connecting to an external terminal or device.
  • the I / O circuit 710 includes, for example, a USB interface for connecting an external hard disk device or the like, an audio interface, or the like.
  • the image display device 701 has a receiving unit 720 and a signal processing unit 730.
  • An antenna 722 is connected to the receiving unit 720, and a necessary signal is separated and generated from the radio wave received by the antenna 722.
  • the signal processing unit 730 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc., and the signal separated and generated by the receiving unit 720 is converted into image data, audio data, etc. by the signal processing unit 730. Separated and generated.
  • an image display device provided with an image display module having an appropriate screen size and resolution can be a mobile information terminal such as a smartphone or a car navigation system.
  • the image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, and may be a modified example thereof or the case of another embodiment.
  • FIG. 32 is a perspective view schematically illustrating an image display device of the first to fifth embodiments and modified examples thereof.
  • a light emitting circuit unit 172 having a large number of subpixels 20 is provided on the substrate 102.
  • the conductive layer 130 shown in FIG. 13 includes a light reflecting plate 130a.
  • the light reflection plate 130a is provided on each of the subpixels 20 on the substrate 102.
  • a color filter 180 is provided on the light emitting circuit unit 172.
  • the structure including the circuit board 100, the light emitting circuit unit 172, and the color filter 180 is referred to as an image display module 602, 702 and is incorporated in the image display devices 601, 701.
  • 1,201,601,701 image display device 2 display area, 3 power supply line, 4 ground line, 5,205 line selection circuit, 6,206 scanning line, 7,207 signal voltage output circuit, 8,208 signal line, 10 pixels, 20, 20a, 20b subpixels, 22,222 light emitting elements, 24,224 selection transistors, 26,226 drive transistors, 28,228 capacitors, 100 circuit boards, 101 circuits, 103,203,203-1,203 -2 Transistor, 104, 204, 204-1, 204-2 TFT channel, 105 insulation layer, 107, 107-1, 107-2 gate, 108 insulation film, 110 first wiring layer, 112 first interlayer insulation Film, 150,250 light emitting element, 156,256,556 second interlayer insulating film, 159,159a,159k,459k translucent electrode, 180 color filter, 560 wiring layer, 520,520a subpixel group, 1001 crystal growth Substories, 1100, 4100, 4100a, 5100 Circuit boards, 1140 buffer layers, 1150 semiconductor layers, 1190 support boards,

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022185976A1 (ja) * 2021-03-05 2022-09-09 ソニーセミコンダクタソリューションズ株式会社 発光装置及び発光装置の製造方法
CN116806351A (zh) * 2021-03-30 2023-09-26 日亚化学工业株式会社 图像显示装置的制造方法和图像显示装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116897383A (zh) * 2021-03-30 2023-10-17 日亚化学工业株式会社 图像显示装置的制造方法和图像显示装置
CN115000098B (zh) * 2022-07-29 2023-01-17 惠科股份有限公司 显示面板及制备方法
CN115425047B (zh) * 2022-08-26 2025-09-23 湖北长江新型显示产业创新中心有限公司 一种显示面板和显示装置
WO2024193798A1 (en) * 2023-03-17 2024-09-26 Ams-Osram International Gmbh METHOD FOR PROCESSING AN ARRANGEMENT HAVING µLEDS AND ARRANGEMENT

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242645A (ja) * 2006-03-03 2007-09-20 Rohm Co Ltd 窒化物半導体発光素子及びその製造方法
JP2008134594A (ja) * 2006-11-27 2008-06-12 Lg Phillips Lcd Co Ltd フレキシブル表示装置及びその製造方法
JP2014160736A (ja) * 2013-02-19 2014-09-04 Toshiba Corp 半導体発光装置及び発光装置
JP2018026442A (ja) * 2016-08-09 2018-02-15 旭化成株式会社 発光素子パッケージおよび発光素子パッケージの製造方法
WO2018132070A1 (en) * 2017-01-13 2018-07-19 Massachusetts Institute Of Technology A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display
WO2018175338A1 (en) * 2017-03-20 2018-09-27 Hong Kong Beida Jade Bird Display Limited Making semiconductor devices by stacking strata of micro leds
JP2018205456A (ja) * 2017-06-01 2018-12-27 株式会社ブイ・テクノロジー フルカラーｌｅｄ表示パネル

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002141492A (ja) 2000-10-31 2002-05-17 Canon Inc 発光ダイオードディスプレイパネル及びその製造方法
JP3681992B2 (ja) 2001-06-13 2005-08-10 日本電信電話株式会社 半導体集積回路の製造方法
TWI479660B (zh) * 2006-08-31 2015-04-01 半導體能源研究所股份有限公司 薄膜電晶體，其製造方法，及半導體裝置
JP2008147608A (ja) 2006-10-27 2008-06-26 Canon Inc Ｌｅｄアレイの製造方法とｌｅｄアレイ、及びｌｅｄプリンタ
JP4827698B2 (ja) 2006-10-27 2011-11-30 キヤノン株式会社 発光素子の形成方法
CN101515621B (zh) * 2009-02-19 2011-03-30 旭丽电子(广州)有限公司 发光二极管芯片、制法及封装方法
US8933433B2 (en) * 2012-07-30 2015-01-13 LuxVue Technology Corporation Method and structure for receiving a micro device
JP2016139560A (ja) 2015-01-28 2016-08-04 株式会社ジャパンディスプレイ 表示装置
WO2017094461A1 (ja) * 2015-12-01 2017-06-08 シャープ株式会社 画像形成素子
KR102591388B1 (ko) * 2016-01-18 2023-10-19 엘지전자 주식회사 반도체 발광 소자를 이용한 디스플레이 장치
EP3913680B1 (fr) * 2016-05-13 2025-07-23 Commissariat à l'Energie Atomique et aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique comportant une pluralité de diodes au nitrure de gallium
US10121710B2 (en) * 2016-06-14 2018-11-06 Innolux Corporation Methods for manufacturing a display device
KR102772357B1 (ko) 2016-12-20 2025-02-21 엘지디스플레이 주식회사 발광 다이오드 칩 및 이를 포함하는 발광 다이오드 디스플레이 장치
TWI632673B (zh) * 2017-07-11 2018-08-11 錼創科技股份有限公司 微型發光元件與顯示裝置
KR102454083B1 (ko) 2017-08-30 2022-10-12 엘지디스플레이 주식회사 마이크로-led 표시장치 및 그 제조방법
WO2019049360A1 (ja) 2017-09-11 2019-03-14 凸版印刷株式会社 表示装置及び表示装置基板
TW201913329A (zh) * 2017-09-12 2019-04-01 日商凸版印刷股份有限公司 顯示裝置及顯示裝置基板
CN109887950A (zh) * 2019-04-19 2019-06-14 京东方科技集团股份有限公司 显示基板、led器件、显示面板、显示装置及制作方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007242645A (ja) * 2006-03-03 2007-09-20 Rohm Co Ltd 窒化物半導体発光素子及びその製造方法
JP2008134594A (ja) * 2006-11-27 2008-06-12 Lg Phillips Lcd Co Ltd フレキシブル表示装置及びその製造方法
JP2014160736A (ja) * 2013-02-19 2014-09-04 Toshiba Corp 半導体発光装置及び発光装置
JP2018026442A (ja) * 2016-08-09 2018-02-15 旭化成株式会社 発光素子パッケージおよび発光素子パッケージの製造方法
WO2018132070A1 (en) * 2017-01-13 2018-07-19 Massachusetts Institute Of Technology A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display
WO2018175338A1 (en) * 2017-03-20 2018-09-27 Hong Kong Beida Jade Bird Display Limited Making semiconductor devices by stacking strata of micro leds
JP2018205456A (ja) * 2017-06-01 2018-12-27 株式会社ブイ・テクノロジー フルカラーｌｅｄ表示パネル

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022185976A1 (ja) * 2021-03-05 2022-09-09 ソニーセミコンダクタソリューションズ株式会社 発光装置及び発光装置の製造方法
CN116806351A (zh) * 2021-03-30 2023-09-26 日亚化学工业株式会社 图像显示装置的制造方法和图像显示装置

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