WO2021017601A1 - 横向扩散金属氧化物半导体器件及其制造方法 - Google Patents

横向扩散金属氧化物半导体器件及其制造方法 Download PDF

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WO2021017601A1
WO2021017601A1 PCT/CN2020/092889 CN2020092889W WO2021017601A1 WO 2021017601 A1 WO2021017601 A1 WO 2021017601A1 CN 2020092889 W CN2020092889 W CN 2020092889W WO 2021017601 A1 WO2021017601 A1 WO 2021017601A1
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trench
field plate
dielectric structure
plate dielectric
substrate
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PCT/CN2020/092889
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English (en)
French (fr)
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马春霞
林峰
许超奇
孙贵鹏
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无锡华润上华科技有限公司
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Publication of WO2021017601A1 publication Critical patent/WO2021017601A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L29/66409—Unipolar field-effect transistors
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Definitions

  • This application relates to the field of semiconductor devices, in particular to a method for manufacturing a laterally diffused metal oxide semiconductor device, and also to a laterally diffused metal oxide semiconductor device.
  • LDMOS laterally diffused metal oxide semiconductor
  • Traditional LDMOS devices use LOCOS (Silicon Local Oxidation Isolation) process or STI (Shallow Trench Isolation) process to produce field oxygen on the drift region.
  • LOCOS Silicon Local Oxidation Isolation
  • STI Shallow Trench Isolation
  • the polysilicon gate extends to the field oxygen in the drift region and acts as a field plate.
  • the field oxygen and the polysilicon gate field plate together play the role of RESURF (reduction of surface electric field), which increases the breakdown voltage of the device.
  • RESURF reduction of surface electric field
  • the length of the device drift region is greater than or equal to 0.6 microns, and the source-drain current path is longer when the device is turned on, and the device on-resistance is large; the device size of the STI shallow trench structure can continue to shrink, but The source-drain current flows along the edge of the STI under the silicon substrate when it is turned on, and the current path is long, and the problem of current congestion occurs at the junction of the STI and the silicon substrate and at the corner of the STI, and the on-resistance of the device is relatively large.
  • a new method for manufacturing a laterally diffused metal oxide semiconductor device and a new laterally diffused metal oxide semiconductor device are provided.
  • a method for manufacturing a laterally diffused metal oxide semiconductor device including:
  • a field plate dielectric structure is formed, and the isolation structure in the central area of the trench is removed by etching, thereby exposing the opening in the middle area of the trench.
  • the remaining isolation structure includes isolation structures covering both sides of the trench as the field plate dielectric structure ;
  • a drain region is formed, and a drain region is formed in the substrate.
  • One end of the drain region is provided at a position of the substrate close to the top edge of the trench and extends diagonally downward to the substrate structure at the bottom of the trench.
  • the drain region is at least partially covered by the field plate dielectric structure;
  • a gate is formed, and a gate is formed on the surface of the field plate dielectric structure, and the gate extends along the field plate dielectric structure down to the substrate surface at the bottom of the opening.
  • a laterally diffused metal oxide semiconductor device including:
  • the drain region one end of which is provided at a position of the substrate near the top edge of the trench, and extends diagonally downward to the substrate structure at the bottom of the trench;
  • the field plate dielectric structure covers both sides of the trench and covers at least part of the drain region at the bottom of the trench;
  • the source region is arranged in the substrate at the middle position of the bottom of the trench.
  • the gate is arranged on the surface of the field plate dielectric structure and extends downward from the field plate dielectric structure to the substrate surface at the bottom of the trench.
  • FIG. 1 is a flowchart of a method for manufacturing a laterally diffused metal oxide semiconductor device in an embodiment
  • Figure 2 is a flow chart of forming a trench in an embodiment
  • 3a is a cross-sectional view of a laterally diffused metal oxide semiconductor device before forming a trench in an embodiment
  • 3b is a cross-sectional view of a laterally diffused metal oxide semiconductor device after forming a trench in an embodiment
  • FIG. 4 is a cross-sectional view of a laterally diffused metal oxide semiconductor device after an isolation structure is formed in an embodiment
  • FIG. 5 is a cross-sectional view of a laterally diffused metal oxide semiconductor device after forming a gate in an embodiment.
  • the present application provides a method for manufacturing a laterally diffused metal oxide semiconductor device, including:
  • the surface of the substrate is provided with grooves, as shown in FIG. 2.
  • the step of opening a groove on the surface of the substrate 100 includes:
  • a nitride protective layer 104 is deposited on the isolation oxide layer 102, and then photoresist coating is performed, and exposure and development are performed to form a photolithography layer 106.
  • the part that is not protected by the photolithography layer after exposure and development is etched to remove the nitride, oxide and part of the substrate to form a trench 108 and remove the photolithography layer 106.
  • the bottom edge to the top edge of the trench 108 is a slope structure with a slope 109.
  • An isolation structure is formed in the trench; as shown in FIG. 4, in one of the embodiments, the step of forming an isolation structure in the trench includes:
  • trench oxide such as silicon dioxide
  • the trench oxide is planarized, for example, by chemical mechanical polishing.
  • the trench oxide is formed by a high density plasma chemical vapor deposition process.
  • Stripping removes the nitride protective layer on the surface of the substrate.
  • the isolation oxide layer on the surface of the substrate is stripped to form an isolation structure.
  • the isolation structure in the central region of the trench is removed by photolithography and etching, thereby forming an opening exposing the central region of the trench.
  • the remaining isolation structure includes isolation structures covering both sides of the trench as the field plate dielectric Structure 110.
  • the upper surface of the field plate dielectric structure 110 and the substrate 100 are on the same plane. In the actual process, according to different requirements for breakdown voltage, the upper surface of the field plate dielectric structure 110 with different widths is reserved.
  • the original isolation structure in the etching trench is used to obtain the field plate dielectric structure, which reduces the complexity of process integration.
  • the field plate dielectric structure 110 has an inclined inclined surface 111.
  • the angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, so that the potential line distribution at both ends of the drift region is more uniform, and the smoothness of the gate is improved.
  • the concentration of current under the field plate dielectric structure is reduced, and the current characteristics of the device are further improved.
  • the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
  • the thickness of the field plate dielectric structure is greater than or equal to 380 nanometers and less than or equal to 420 nanometers, and the breakdown voltage of the device is greater than 100 volts.
  • the drain region 112 of the device is formed in the substrate 100 by photolithography and implantation. One end of the drain region 112 is located on the substrate 100 near the top edge of the trench, and extends diagonally downward to the bottom of the trench. In the substrate structure, the drain region 112 is at least partially covered by the field plate dielectric structure 110.
  • the length of the drain region 112 in the trench is set according to different requirements for the breakdown voltage of the device.
  • the drain region 112 is implanted with N-type impurities, and the concentration and depth of the implanted impurities are set according to the specific characteristic requirements of the interval.
  • the source region 114 is formed in the substrate 100 in the middle of the opening through a photolithography and injection process. When the device is turned on, current flows from the source region 114 to the drain region 112, and the current path is close to a straight line, which greatly reduces the on-resistance of the device.
  • a gate 116 is formed on the surface of the field plate dielectric structure 110, and the gate 116 extends down the field plate dielectric structure 110 to the substrate surface at the bottom of the opening to reduce the surface electric field of the device.
  • the gate covers the field plate
  • the size of the dielectric structure and the drain region will affect the on-resistance and breakdown voltage of the device. Different device parameters can be obtained by choosing different gate covering field plate dielectric structure and the size of the drain region.
  • the gate is a polysilicon gate.
  • the thickness of the gate is 2000 angstroms.
  • the step of forming a gate oxide layer is further included, and the gate oxide layer extends down the field plate dielectric structure to the substrate surface at the bottom of the opening.
  • the thickness of the gate oxide layer is 13 nanometers, and the gate voltage of the device at this time is 5 volts.
  • the formation of the gate further includes the steps of forming contact holes, through holes, metal plugs, and metal interconnections.
  • the isolation structure in the central region of the trench is removed by etching, thereby forming an opening exposing the central region of the trench, and forming isolation structures covering both sides of the trench as the field plate dielectric Structure; set one end of the drain region on the substrate near the top edge of the trench, and extend diagonally downward to the substrate structure at the bottom of the trench, forming a source region in the substrate at the middle of the opening, A gate is formed on the surface of the field plate dielectric structure, and the gate extends down the field plate dielectric structure to the surface of the substrate at the bottom of the opening.
  • the field plate dielectric structure is formed by etching the isolation structure in the trench , Compatible with the traditional shallow trench isolation process, no additional field plate formation steps are added, the source and drain current path is along the bottom of the trench when the device is turned on, and the current path is close to a straight line, effectively shortening the source area when the device is turned on There is no current congestion problem between the current path and the drain region, and the on-resistance of the device is reduced.
  • the present application also provides a laterally diffused metal oxide semiconductor device, including:
  • the substrate 100 is provided with grooves on the surface of the substrate 100;
  • the drain region 112 is provided at one end of the substrate 100 near the top edge of the trench, and extends diagonally downward to the substrate structure at the bottom of the trench;
  • the field plate dielectric structure 110 covers at least part of the drain region 112 on both sides of the trench and at the bottom of the trench;
  • the source region 114 is disposed in the substrate 100 at the middle position of the bottom of the trench.
  • the gate 116 is disposed on the surface of the field plate dielectric structure 110 and extends downward from the field plate dielectric structure 116 to the substrate surface at the bottom of the trench.
  • the bottom edge to the top edge of the trench has a slope structure with a slope 109.
  • the field plate dielectric structure 110 has an inclined inclined surface 111.
  • the angle between the inclined surface of the field plate dielectric structure and the horizontal plane is greater than or equal to 30 degrees and less than or equal to 40 degrees, so that the potential line distribution at both ends of the drift region is more uniform, and the smoothness of the gate is improved.
  • the current concentration under the field plate dielectric structure is reduced, and the current characteristics of the device are further improved.
  • the thickness of the field plate dielectric structure is less than or equal to 420 nanometers.
  • the thickness of the field plate dielectric structure is greater than or equal to 380 nanometers and less than or equal to 420 nanometers, and the breakdown voltage of the device is greater than 100 volts.
  • the laterally diffused metal oxide semiconductor device further includes a gate oxide that extends down the field plate dielectric structure to the substrate surface at the bottom of the opening.
  • the laterally diffused metal oxide semiconductor device further includes a contact hole, a through hole, a metal plug, and a metal interconnection layer.
  • the above-mentioned laterally diffused metal oxide semiconductor device includes a substrate with a trench on the surface; a drain region, one end of which is provided at a position of the substrate near the top edge of the trench, and extends diagonally down to the substrate structure at the bottom of the trench.
  • the field plate dielectric structure covering at least part of the drain region on both sides of the trench and the bottom of the trench; the source region, located in the substrate at the middle of the bottom of the trench; the gate, located in the field plate dielectric structure And extend downwards from the field plate dielectric structure to the substrate surface at the bottom of the trench.
  • the device By arranging the gate and field plate dielectric structure in the trench, and the drain region and source region in the substrate, the device is compatible with the traditional shallow trench isolation process without adding additional field plate formation steps, When the device is turned on, the source-drain current path is along the bottom of the trench, and the current path is close to a straight line, effectively shortening the current path between the source region and the drain region when the device is turned on, and there is no current congestion problem, while reducing the device On resistance.

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Abstract

本申请涉及一种横向扩散金属氧化物半导体器件及其制造方法。该方法包括：获取表面开设有沟槽(108)的衬底(100)；形成隔离结构；在沟槽(108)的两侧形成场极板介质结构(110)，在衬底(100)中形成漏极区(112)，漏极区(112)至少部分被场极板介质结构(110)覆盖；在沟槽(108)中部位置的衬底(100)中形成源极区(114)；在场极板介质结构(110)的表面形成栅极(116)，栅极(116)沿场极板介质结构(110)向下延伸至开口底部的衬底表面。

Description

横向扩散金属氧化物半导体器件及其制造方法
相关申请的交叉引用
本申请要求于2019年08月01日提交中国专利局、申请号为2019107065989、发明名称为“横向扩散金属氧化物半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体器件领域，特别是涉及一种横向扩散金属氧化物半导体器件的制造方法，还涉及一种横向扩散金属氧化物半导体器件。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
LDMOS(横向扩散金属氧化物半导体)两个关键的评价参数为器件的击穿电压与导通电阻。传统的LDMOS器件采用LOCOS(硅局部氧化隔离)工艺或STI(浅槽隔离)工艺在漂移区上制作场氧，多晶硅栅扩展到漂移区的场氧上面，充当场极板，漂移区上制作的场氧与多晶硅栅场极板共同起到RESURF(降低表面电场)的作用，增大了器件的击穿电压。LOCOS工艺受到鸟嘴尺寸的限制，器件漂移区的长度大于等于0.6微米，而且器件导通时源漏电流路径较长，器件导通电阻较大；STI浅槽结构的器件尺寸可以继续缩小，但是导通时源漏电流沿着硅衬底下STI边缘流动，电流路径较长，并且在STI与硅衬底交界处及STI拐角处会出现电流拥挤的问题，器件导通电阻较大。
发明内容
根据本申请的各种实施例，提供一种新的横向扩散金属氧化物半导体器件的制造方法和一种新的横向扩散金属氧化物半导体器件。
一种横向扩散金属氧化物半导体器件的制造方法,包括：
获取衬底，所述衬底的表面开设有沟槽；
形成隔离结构，在沟槽中形成隔离结构；
形成场极板介质结构，通过刻蚀去除沟槽中心区域的隔离结构，从而露出沟槽中间区域的开口，剩余的隔离结构包括覆盖所述沟槽的两侧的隔离结构作为场极板介质结构；
形成漏极区，在衬底中形成漏极区，所述漏极区的一端设于衬底靠近沟槽顶部边缘的位置，并斜向下延伸至沟槽底部的衬底结构中，所述漏极区至少部分被所述场极板介质结构覆盖；
形成源极区，在开口中部位置的衬底中形成源极区；以及
形成栅极，在场极板介质结构的表面形成栅极，所述栅极沿场极板介质结构向下延伸至开口底部的衬底表面。
一种横向扩散金属氧化物半导体器件，包括：
衬底，表面开设有沟槽；
漏极区，一端设于衬底靠近沟槽顶部边缘的位置，并斜向下延伸至沟槽底部的衬底结构中；
场极板介质结构，覆盖沟槽两侧，及覆盖沟槽底部的至少部分漏极区；
源极区，设置于沟槽底部的中部位置的衬底中；以及
栅极，设于场极板介质结构的表面并向下延伸出场极板介质结构至所述沟槽底部的衬底表面。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中横向扩散金属氧化物半导体器件的制造方法的流程图；
图2为一实施例中形成沟槽的流程图；
图3a为一实施例中形成沟槽前横向扩散金属氧化物半导体器件的剖面图；
图3b为一实施例中形成沟槽后横向扩散金属氧化物半导体器件的剖面图；
图4为一实施例中形成隔离结构后的横向扩散金属氧化物半导体器件的剖面图；
图5为一实施例中形成栅极后的横向扩散金属氧化物半导体器件的剖面图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。 附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
如图1、图5所示，本申请提供一种横向扩散金属氧化物半导体器件的制造方法,包括：
S102，获取衬底。
所述衬底的表面开设有沟槽，如图2，在其中一个实施例中，衬底100表面开设沟槽的步骤包括：
S202，形成隔离氧化层。
S204，形成氮化物保护层。
如图3a，在隔离氧化层102上沉积氮化物保护层104，然后进行光刻胶涂覆，并进行曝光显影形成光刻层106。
S206，形成沟槽。
如图3a，图3b，对曝光显影后无光刻层保护的部分进行刻蚀，去除氮化物、氧化物和部分衬底，形成沟槽108，去除光刻层106。
其中，沟槽108的底部边缘至顶部边缘为具有斜面109的斜坡结构。
S104,形成隔离结构。
在沟槽中形成隔离结构；如图4所示，在其中一个实施例中，在沟槽中形成隔离结构的步骤包括：
S302，沉积形成沟槽氧化物。
首先，沉积沟槽氧化物，例如二氧化硅，填满沟槽。然后，对沟槽氧化物进行平坦化，例如采用化学机械抛光的方式。在其中一个实施例中，沟槽 氧化物是通过高密度等离子体化学气相淀积工艺形成的。
S304，刻蚀去除氮化物保护层。
剥离去除衬底表面的氮化物保护层。
S306，刻蚀去除隔离氧化层。
剥离去除衬底表面的隔离氧化层，形成隔离结构。
S106,形成场极板介质结构。
如图5所示，通过光刻、刻蚀去除沟槽中心区域的隔离结构，从而形成露出沟槽中间区域的开口，剩余的隔离结构包括覆盖沟槽的两侧的隔离结构作为场极板介质结构110。
场极板介质结构110的上表面与衬底100在同一平面上，在实际工艺中，根据对击穿电压的不同需求，保留不同宽度的场极板介质结构110上表面。
本申请利用刻蚀沟槽中原有的隔离结构得到场极板介质结构，降低了工艺集成的复杂度。
如图5所示，在其中一个实施例中，场极板介质结构110具有倾斜的倾斜表面111。
在其中一个实施例中，场极板介质结构的倾斜表面与水平面的夹角大于等于30度且小于等于40度，使得漂移区两端的电势线分布更加均匀，同时改善了栅极的平缓程度，降低了场极板介质结构下电流的集中程度，进一步改善了器件的电流特性，场极板介质结构的厚度小于等于420纳米。
在其中一个实施例中，场极板介质结构的厚度大于等于380纳米且小于等于420纳米，器件的击穿电压大于100伏特。
S108，形成漏极区。
通过光刻、注入工艺在衬底100中形成器件的漏极区112，所述漏极区 112的一端设于衬底100靠近沟槽顶部边缘的位置，并斜向下延伸至沟槽底部的衬底结构中，漏极区112至少部分被场极板介质结构110覆盖。
在实际工艺中，根据对器件击穿电压的不同需求，设置漏极区112在沟槽中的长度。在一个实施例中，漏极区112注入N型杂质，注入杂质的浓度、深度根据区间的具体特性要求来设置。
S110，形成源极区。
通过光刻、注入工艺在在开口中部位置的衬底100中形成源极区114。器件导通时，电流从源极区114流向漏极区112，电流路径接近为直线，极大的降低了器件的导通电阻。
S112，形成栅极。
在场极板介质结构110的表面形成栅极116，所述栅极116沿场极板介质结构110向下延伸至开口底部的衬底表面，用于降低器件的表面电场，栅极覆盖场极板介质结构及漏极区的尺寸会影响器件的导通电阻和击穿电压，选取不同的栅极覆盖场极板介质结构及漏极区尺寸可以得到不同的器件参数。
在一个实施例中，栅极为多晶硅栅极。
在其中一个实施例中，栅极的厚度为2000埃。
在其中一个实施例中，形成栅极之前还包括步骤形成栅氧层，所述栅氧层沿场极板介质结构向下延伸至开口底部的衬底表面。
在一个实施例中，栅氧层的厚度为13纳米，此时器件的栅压为5伏特。
在其中一个实施例中，形成栅极之后还包括形成接触孔、通孔、金属塞、金属互连的步骤。
上述横向扩散金属氧化物半导体器件的制造方法，通过刻蚀去除沟槽中心区域的隔离结构，从而形成露出沟槽中间区域的开口，形成覆盖在沟槽的 两侧的隔离结构作为场极板介质结构；将漏极区的一端设于衬底靠近沟槽顶部边缘的位置，并斜向下延伸至所述沟槽底部的衬底结构中，在开口中部位置的衬底中形成源极区，在场极板介质结构的表面形成栅极，所述栅极沿场极板介质结构向下延伸至开口底部的衬底表面，场极板介质结构是通过刻蚀沟槽中的隔离结构而形成的，与传统的浅槽隔离工艺兼容，不增加额外的场极板形成步骤，器件导通时源漏电流路径沿着沟槽的底部，电流路径接近直线，有效缩短了器件导通时源极区和漏极区之间的电流路径，而且不存在电流拥挤问题，同时降低器件导通电阻。
如图5所示，在其中一个实施例中，本申请还提供一种横向扩散金属氧化物半导体器件，包括：
衬底100，衬底100表面开设有沟槽；
漏极区112，一端设于衬底100靠近沟槽顶部边缘的位置，并斜向下延伸至沟槽底部的衬底结构中；
场极板介质结构110，覆盖沟槽两侧及沟槽底部的至少部分漏极区112；
源极区114，设置于沟槽底部的中部位置的衬底100中；以及
栅极116，设于场极板介质结构110的表面并向下延伸出场极板介质结构116至所述沟槽底部的衬底表面。
在其中一个实施例中，沟槽的底部边缘至顶部边缘为具有斜面109的斜坡结构。
如图5所示，在其中一个实施例中，场极板介质结构110具有倾斜的倾斜表面111。
在其中一个实施例中，场极板介质结构的倾斜表面与水平面的夹角大于等于30度且小于等于40度，使得漂移区两端的电势线分布更加均匀，同时 改善了栅极的平缓程度，降低了场极板介质结构下电流的集中程度，进一步改善了器件的电流特性，所述场极板介质结构的厚度小于等于420纳米。
在其中一个实施例中，场极板介质结构的厚度大于等于380纳米且小于等于420纳米，器件的击穿电压大于100伏特。
在其中一个实施例中，横向扩散金属氧化物半导体器件还包括栅氧，所述栅氧沿场极板介质结构向下延伸至开口底部的衬底表面。
在其中一个实施例中，横向扩散金属氧化物半导体器件还包括接触孔、通孔、金属塞、金属互连层。
上述横向扩散金属氧化物半导体器件，包括衬底，表面开设有沟槽；漏极区，一端设于衬底靠近沟槽顶部边缘的位置，并斜向下延伸至沟槽底部的衬底结构中；场极板介质结构，覆盖沟槽两侧及沟槽底部的至少部分漏极区；源极区，设置于沟槽底部的中部位置的衬底中；栅极，设于场极板介质结构的表面并向下延伸出场极板介质结构至沟槽底部的衬底表面。通过将栅极、场极板介质结构设置于沟槽内，漏极区、源极区设置于衬底中，该器件与传统的浅槽隔离工艺兼容，不增加额外的场极板形成步骤，器件导通时源漏电流路径沿着沟槽的底部，电流路径接近直线，有效缩短了器件导通时源极区和漏极区之间的电流路径，而且不存在电流拥挤问题，同时降低器件导通电阻。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本 领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种横向扩散金属氧化物半导体器件的制造方法，包括：
    获取衬底，所述衬底的表面开设有沟槽；
    形成隔离结构，在所述沟槽中形成隔离结构；
    形成场极板介质结构，通过刻蚀去除所述沟槽中心区域的隔离结构，从而露出沟槽中间区域的开口，剩余的隔离结构包括覆盖所述沟槽的两侧的隔离结构作为场极板介质结构；
    形成漏极区，在所述衬底中形成漏极区，所述漏极区的一端设于所述衬底靠近沟槽顶部边缘的位置，并斜向下延伸至所述沟槽底部的衬底结构中，所述漏极区至少部分被所述场极板介质结构覆盖；
    形成源极区，在所述开口中部位置的衬底中形成源极区；以及
    形成栅极，在所述场极板介质结构的表面形成栅极，所述栅极沿所述场极板介质结构向下延伸至所述开口底部的衬底表面。
  2. 根据权利要求1所述的制造方法，其中所述场极板介质结构具有倾斜的倾斜表面。
  3. 根据权利要求2所述的制造方法，其中所述场极板介质结构的倾斜表面与水平面的夹角大于等于30度且小于等于40度，所述场极板介质结构的厚度小于等于420纳米。
  4. 根据权利要求1所述的制造方法，其中所述衬底表面开设第一沟槽的步骤包括：
    形成隔离氧化层；
    形成氮化物保护层，沉积形成氮化物保护层；以及
    形成沟槽，光刻、刻蚀形成所述沟槽；
    其中所述沟槽的底部边缘至顶部边缘为斜坡结构。
  5. 根据权利要求4所述的制造方法，其中在所述沟槽中形成隔离结构的步骤包括：
    沉积形成沟槽氧化物；
    刻蚀去除所述氮化物保护层；以及
    刻蚀去除所述隔离氧化层。
  6. 根据权利要求5所述的制造方法，其中所述沟槽氧化物是通过高密度等离子体化学气相淀积工艺形成的。
  7. 根据权利要求5所述的制造方法，其中所述刻蚀去除所述氮化物保护层之前还包括对沟槽氧化物进行平坦化的步骤。
  8. 根据权利要求1所述的制造方法，其中在所述场极板介质结构的表面形成栅极之前还包括形成栅氧层的步骤，所述栅氧层沿场极板介质结构向下延伸至开口底部的衬底表面。
  9. 根据权利要求2所述的制造方法，其中所述场极板介质结构的厚度大于等于380纳米且小于等于420纳米，所述栅极的厚度为2000埃。
  10. 一种横向扩散金属氧化物半导体器件，包括：
    衬底，表面开设有沟槽；
    漏极区，一端设于所述衬底靠近所述沟槽的顶部边缘的位置，并斜向下延伸至所述沟槽底部的衬底结构中；
    场极板介质结构，覆盖所述沟槽两侧，及覆盖所述沟槽底部的至少部分漏极区；
    源极区，设置于所述沟槽底部的中部位置的衬底中；以及
    栅极，设于所述场极板介质结构的表面并向下延伸至所述沟槽底部的衬 底表面。
  11. 根据权利要求10所述的器件，其中所述沟槽的底部边缘至顶部边缘为斜坡结构。
  12. 根据权利要求10所述的器件，其中所述场极板介质结构具有倾斜的倾斜表面。
  13. 根据权利要求12所述的器件，其中所述场极板介质结构的倾斜表面与水平面的夹角大于等于30度且小于等于40度，所述场极板介质结构的厚度小于等于420纳米。
  14. 根据权利要求10所述的器件，其中所述器件还包括栅氧，所述栅氧沿场极板介质结构向下延伸至所述沟槽底部的衬底表面。
  15. 根据权利要求12所述的器件，其中所述场极板介质结构的厚度大于等于380纳米且小于等于420纳米，所述栅极的厚度为2000埃。
PCT/CN2020/092889 2019-08-01 2020-05-28 横向扩散金属氧化物半导体器件及其制造方法 WO2021017601A1 (zh)

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