Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
  • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
  • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
  • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/117—Shapes of semiconductor bodies
  • H10D62/118—Nanostructure semiconductor bodies
  • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
  • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS
  • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
  • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
  • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
  • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Definitions

• the present application relates to semiconductors, and more specifically, to techniques for forming semiconductor structures.
• Embodiments of the invention provide techniques for forming both direct print and self-aligned double patterning nanosheets using a same mask.
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning.
• the second width is less than the first width.
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask covering (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning.
• the second width is less than the first width.
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask exposing (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning.
• the second width is less than the first width.
• a semiconductor structure comprises a substrate and a nanosheet stack disposed over the substrate, the nanosheet stack comprising alternating layers of a sacrificial material and a channel material, the layers of channel material providing nanosheet channels for one or more nanosheet field-effect transistors.
• the semiconductor structure also comprises a hard mask stack disposed over the nanosheet stack, and a patterning layer disposed over the hard mask stack.
• the semiconductor structure further comprises a lithographic mask disposed over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using self-aligned double patterning.
• the second width is less than the first width.
• FIG. 1 depicts a side cross-sectional view of a semiconductor layer stack, according to an embodiment of the invention.
• FIG. 2 depicts a side cross-sectional view of the FIG. 1 structure following patterning of a lithographic mask, according to an embodiment of the invention.
• FIG. 3 depicts a side cross-sectional view of the FIG. 2 structure following etching of exposed portions of the patterning layer and removal of the lithographic mask, according to an embodiment of the invention.
• FIG. 4 depicts a side cross-sectional view of the FIG. 3 structure following formation of a spacer material, according to an embodiment of the invention.
• FIG. 5 depicts a side cross-sectional view of the FIG. 4 structure following etch-back of the spacer material, according to an embodiment of the invention.
• FIG. 6 depicts a side cross-sectional view of the FIG. 5 structure following patterning of a block mask and removal of the exposed patterning mandrel, according to an embodiment of the invention.
• FIG. 7 depicts a side cross-sectional view of the FIG. 6 structure following removal of the block mask, according to an embodiment of the invention.
• FIG. 8 depicts a side cross-sectional view of the FIG. 7 structure following patterning of an additional block mask and removal of exposed portions of the spacer material, according to an embodiment of the invention.
• FIG. 9 depicts a side cross-sectional view of the FIG. 8 structure following removal of the additional block mask, according to an embodiment of the invention.
• FIG. 10 depicts a side cross-sectional view of the FIG. 9 structure following etching of the top hard mask layer, according to an embodiment of the invention.
• FIG. 11 depicts a side cross-sectional view of the FIG. 10 structure following removal of the remaining patterning mandrels, according to an embodiment of the invention.
• FIG. 12 depicts a side cross-sectional view of the FIG. 11 structure following etching of the remaining spacer material and the top-most remaining hard mask layer, according to an embodiment of the invention.
• FIG. 13 depicts a side cross-sectional view of the FIG. 12 structure following etching of the last hard mask layer, according to an embodiment of the invention.
• FIG. 14 depicts a side cross-sectional view of the FIG. 13 structure following open of the padding layer and etching of exposed portions of the nanosheet stack and a portion of the substrate, according to an embodiment of the invention.
• FIG. 15 depicts a side cross-sectional view of the FIG. 1 structure following patterning of a lithographic mask, according to an embodiment of the invention.
• FIG. 16 depicts a side cross-sectional view of the FIG. 15 structure following removal of exposed portions of the patterning layer and removal of the lithographic mask, according to an embodiment of the invention.
• FIG. 17 depicts a side cross-sectional view of the FIG. 16 structure following fill and etch-back of an oxide material, according to an embodiment of the invention.
• FIG. 18 depicts a side cross-sectional view of the FIG. 17 structure following patterning of a block mask to expose a portion of the oxide material, according to an embodiment of the invention.
• FIG. 19 depicts a side cross-sectional view of the FIG. 18 structure following removal of the exposed portion of the oxide material and following removal of the block mask, according to an embodiment of the invention.
• FIG. 20 depicts a side cross-sectional view of the FIG. 19 structure following deposition and etch-back of a spacer, according to an embodiment of the invention.
• FIG. 21 depicts a side cross-sectional view of the FIG. 20 structure following removal of a remaining portion of the patterning layer, according to an embodiment of the invention.
• FIG. 22 depicts a side cross-sectional view of the FIG. 21 structure following open of the top hard mask layer, according to an embodiment of the invention.
• FIG. 23 depicts a side cross-sectional view of the FIG. 22 structure following etching of exposed portions of the nanosheet stack and a portion of the substrate, according to an embodiment of the invention.
• a FET is a transistor having a source, a gate, and a drain, and having action that depends on the flow of majority carriers along a channel that runs past the gate between the source and drain. Current through the channel between the source and drain may be controlled by a transverse electric field under the gate. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (such as the distance between the source and drain).
• Multi-gate FETs are promising candidates to scale down complementary metal-oxide-semiconductor (CMOS) FET technology. Flowever, the smaller dimensions associated with multi-gate FETs (as compared to single-gate FETs) necessitate greater control over performance issues such as short channel effects, punch-through, metal-oxide semiconductor (MOS) leakage current, and the parasitic resistance that is present in a multi-gate FET.
• CMOS complementary metal-oxide-semiconductor
• CMOS devices were typically substantially planar along the surface of the semiconductor substrate, with the exception of the FET gate disposed over the top of the channel.
• FinFETs utilize a vertical channel structure, increasing the surface area of the channel exposed to the gate.
• the gate can more effectively control the channel, as the gate extends over more than one side or surface of the channel.
• the gate encloses three surfaces of the three-dimensional channel, rather than being disposed over just the top surface of a traditional planar channel.
• Nanosheets and nanowires are viable options for scaling to 7nm and beyond.
• a general process flow for formation of a nanosheet stack involves removing sacrificial layers, which may be formed of silicon germanium (SiGe), between sheets of channel material, which may be formed of silicon (Si).
• Process options for nanosheet printing may rely on a direct print with a single mask, or a direct print and self-aligned double patterning (SADP) with two mask processing solutions.
• SADP self-aligned double patterning
• the variability that is created with a direct print process may not be sufficient for device operation.
• SADP may be needed.
• Nanosheet stacks provide various advantages in enabling the use of varying device widths.
• Multiple mask solutions e.g., for direct print and SADP
• OL overlay
• Such OL degradation may be due in part to split levels that cause downstream impacts (e.g., in parasitic capacitance) for various device features (e.g., gate and source/drain overlays, etc.).
• SRAM is a type of memory device that offers high speed, low power consumption and simple operation. Unlike dynamic random-access memory (DRAM), SRAM does not need to regularly refresh stored data and has a straightforward design. SRAM cells may be formed using varying numbers of transistors.
• a 6T SRAM cell is widely used as a primary memory in microprocessor circuits.
• a 6T SRAM cell may include a first n-type FET device (nFET) connected to a first bit line node (BL), a first output node (Q), and a word line node (WL).
• nFET n-type FET device
• a second nFET device of the 6T SRAM cell is connected to the Q node, a ground node (e.g., VSS), and a second output node (Q 1 ).
• a first p-type FET device (pFET) is connected to the Q node, the Q' node, and a voltage source or supply node (e.g., VDD).
• a second pFET device is connected to the VDD node, the Q node and the Q' node.
• a third nFET device is connected to the VSS node, the Q node, and the Q' node.
• a fourth nFET device is connected to a second bit line node (BLB), the WL node and the Q' node.
• the first and fourth nFET devices are pass-gate (PG) transistors of the 6T SRAM cell
• the second and third nFET devices are the pull down (PD) transistors of the 6T SRAM cell
• the first and second pFET devices are the pull-up (PU) transistors of the 6T SRAM cell.
• nanosheet widths may be larger for nFET devices of the 6T SRAM cell than for the pFET devices of the 6T SRAM cell. It should be appreciated, however, that this is not a requirement and that embodiments are not limited to forming smaller nanosheet widths for pFET than nFET devices. Further, the techniques described herein are not limited to use with forming SRAM structures, but instead are more generally applicable for forming nanosheet FETs where different nanosheet widths are desired. [0040] Illustrative processes for forming nanosheets of different widths using both direct print and SADP using a same mask will now be described in further detail with respect to FIGS. 1-23.
• FIG. 1 shows a side cross-sectional view 100 of a semiconductor layer stack, including a substrate 102, a nanosheet stack including alternating layers 104 and 106 of a sacrificial material and a channel material, a padding layer 108, hard mask layers 110, 112 and 114, and a patterning layer 116.
• the substrate 102 may be a semiconductor structure formed of bulk silicon (Si), although other suitable materials may be used, such as various silicon-containing materials.
• silicon-containing materials suitable for the substrate 102 include, but are not limited to, Si, silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), polysilicon, epitaxial silicon, amorphous silicon, and multi-layers thereof.
• the substrate 102 may be silicon-on-insulator (SOI) wafer.
• SOI silicon-on-insulator
• a SOI wafer includes a SOI layer separated from a substrate by a buried insulator.
• Suitable substrate materials include, but are not limited to, Si, strained Si, silicon carbide (SiC), Ge, SiGe, SiGeC, Si alloys, Ge alloys, GaAs, indium arsenide (InAs), indium phosphide (InP), or any combination thereof.
• Suitable dielectric materials for the buried insulator include, but are not limited to, an oxide material such as silicon dioxide (S1O2). When the buried insulator is an oxide, the buried insulator may also be referred to as a buried oxide or BOX.
• the substrate 102 may have a width or horizontal thickness (in direction X-X') that varies as desired (e.g., based on the number of device structures to be formed).
• the substrate 102 may have a height or vertical thickness (in direction Y-Y') ranging from 300 micrometers (m ⁇ ti) to 1000mhi.
• Nanosheet stacks including the alternating layers of a sacrificial material 104 and a channel material 106 are formed over the substrate 102. While FIG. 1 shows an example where there are three sacrificial layers 104 and three channel layers 106 in the nanosheet stack, it should be appreciated that nanosheet stacks may include more or fewer than three sets of alternating layers of the sacrificial material and the channel material.
• the sacrificial layers 104 may be formed of any suitable material that may be etched selective to the channel material 106. If the channel layers 106 are Si, the sacrificial layers 104 may be SiGe. If the channel layers 106 are indium gallium arsenide (InGaAs), the sacrificial layers 104 may be indium aluminum arsenide (InAIAs). Various other combinations of lll-V materials may be used. The material of the sacrificial layers 104 is one that can be removed selective to the material of the channel layers 106. The sacrificial layers 104 and channel layers 106 may each have a thickness in the range of 4nm to 15nm. The nanosheet stack of sacrificial layers 104 and channel layers 106 may be epitaxially grown over the substrate 102.
• the padding layer 108 is formed over the nanosheet stack as illustrated (e.g., such as using chemical vapor deposition (CVD), physical vapor deposition (PVD) or another suitable oxide deposition process).
• the padding layer 108 may be formed of an oxide such as silicon dioxide (S1O2).
• the padding layer 108 may have a height or vertical thickness (in direction Y-Y') in the range of 1 nm to 10nm.
• Hard mask layers 110, 112 and 114 are formed over the padding layer 108.
• the hard mask layers 110 and 114 are a nitride material such as silicon nitride (SiN) while the hard mask layer 112 is an oxide material such as S1O2.
• the hard mask layers 110, 112 and 114 collectively provide a nitride- oxide-nitride (NON) hard mask.
• the hard mask layers 110, 112 and 114 may be formed using high density plasma (HDP) CVD (HDPCVD), plasma-enhanced CVD (PECVD), CVD, etc.
• the hard mask layer 110 may have a height or vertical thickness (in direction Y-Y') in the range of 10nm to 50nm.
• the hard mask layer 112 may have a height or vertical thickness (in direction Y-Y') in the range of 10nm to 50nm.
• the hard mask layer 114 may have a height or vertical thickness (in direction Y-Y') in the range of 10nm to 50nm.
• the patterning layer 116 is formed over the hard mask layer 114.
• the patterning layer 116 may be formed of amorphous silicon (a-Si) or another suitable material such as amorphous carbon (a-C).
• the patterning layer 116 may be formed using any suitable deposition process, such as CVD, PVD, etc.
• the patterning layer 116 may have a height or vertical thickness (in direction Y-Y') in the range of 10nm to 200nm.
• FIG. 2 shows a side cross-sectional view 200 of the FIG. 1 structure followed by lithography and etching to form a lithographic mask with portions 118-1, 118-2 and 118-3 (collectively, lithographic mask 118) over the patterning layer 116 as illustrated.
• the lithographic mask 118 may be formed of photoresist.
• the lithographic mask 118 may have a height or vertical thickness (in direction Y-Y') in the range of 20nm to 1000nm.
• the width or horizontal thickness (in direction X-X') of the lithographic mask portions 118-1 and 118-3 may be in the range of 5nm to 2000nm.
• the lithographic mask portions 118-1 and 118-3 provide direct print control of the width of nanosheets for underlying device structures after the processing described below.
• the lithographic mask portions 118-1 and 118-3 may be used to control the device width for underlying n-type FETs (nFETs) formed from the underlying nanosheet stack.
• the width or horizontal thickness (in direction X-X') of the lithographic mask portion 118-2 may be in the range of 5nm to 200nm.
• the lithographic mask portion 118-2 provides SADP control of the width of nanosheets for underlying device structures after the processing described below.
• the lithographic mask portion 118- 2 may be used to control the device width for underlying p-type FETs (pFETs) formed from the underlying nanosheet stack.
• the number and sizing of the portions of the lithographic mask 118 in FIG. 2 is used to form a particular arrangement of nanosheet FETs from the underlying nanosheet stack (e.g., a pair of nFET devices using direct print with the lithographic mask portions 118-1 and 118-3, and a pair of pFET devices using SADP with the lithographic mask portion 118-2). It should be appreciated that various other combinations of varying width nanosheet FETs may be formed using different numbers and sizes of mask layers.
• FIG. 3 shows a side cross-sectional view 300 of the FIG. 2 structure following etching potions of the patterning layer 116 that are exposed by the lithographic mask 118 (e.g., using a-Si reactive-ion etching (RIE)).
• RIE reactive-ion etching
• the lithographic mask 118 is then removed. As a result, mandrels 116-1 , 116-2 and 116-3 of the patterning layer 116 remain.
• FIG. 4 shows a side cross-sectional view 400 of the FIG. 3 structure following formation of a spacer material 120.
• the spacer material 120 may be formed using atomic layer deposition (ALD) or another suitable process.
• the spacer material 120 may be formed of an oxide, such as a metal oxide, S1O2, etc.
• the spacer material 120 may have a uniform thickness in the range of 5nm to 60nm.
• the spacer material 120 thickness controls the size of the FETs (e.g., pFETs) formed from the underlying nanosheet stack as described in further detail below.
• FIG. 5 shows a side cross-sectional view 500 of the FIG. 4 structure following etch-back of the spacer material 120, resulting in sidewall spacers 120' on sidewalls of the patterning mandrels 116-1 , 116-2 and 116-3.
• FIG. 6 shows a side cross-sectional view 600 of the FIG. 5 structure following patterning of a block mask including portions 122-1 and 122-2 (collectively, block mask 122) to cover the patterning mandrels 116-1 and 116-3, along with the spacer material 120' surrounding sidewalls of the pattering mandrels 116-1 and 116-3 as illustrated.
• This step may be referred to as a "pFET open” step where the spacer material 120' exposed by the block mask 122 is used to form pFET devices from the underlying nanosheet stack (e.g., using SADP).
• the block mask 122 may be formed of a suitable organic planarization layer (OPL) material, using spin-on coating or other suitable processing.
• OPL organic planarization layer
• the height or vertical thickness (in direction Y-Y') of the block mask 122 may be in the range of 100nm to 1000nm.
• FIG. 6 further illustrates the structure following removal of the exposed patterning mandrel 116-2, such as using reactive-ion etching (RIE).
• RIE reactive-ion etching
• FIG. 7 shows a side cross-sectional view 700 of the FIG. 6 structure following removal of the block mask 122.
• the block mask 122 may be removed using dry ashing, a wet clean, etc.
• FIG. 8 shows a side cross-sectional view 800 following patterning of another block mask 124 to cover the spacer material 120' surrounding the removed patterning mandrel 116-2, exposing the patterning mandrels 116- 1 and 116-3 as well as the spacer material 120' on sidewalls of the patterning mandrels 116-1 and 116-3.
• the block mask 124 may be formed of similar materials, with similar processing, and with similar sizing (in direction Y- Y') as the block mask 122.
• This step may be referred to as an "nFET open” step where the patterning mandrels 116-1 and 116-2 are used for direct printing nFET devices from the underlying nanosheet stack.
• FIG. 8 further shows removal of the spacer material 120' surrounding sidewalls of the patterning mandrels 116-1 and 116-3.
• FIG. 9 shows a side cross-sectional view 900 of the FIG. 8 structure following removal of the block mask 124.
• the block mask 124 may be removed using processing similar to that described above with respect to removal of the block mask 122.
• FIG. 10 shows a side cross-sectional view 1000 of the FIG. 9 structure following etching of the hard mask layer 114 that is exposed by the remaining patterning mandrels 116-1 and 116-3 and the remaining spacer sidewalls 120'.
• the hard mask layer 114 may be etched using RIE or other suitable processing. As a result, the hard mask layer 114' remains only below the patterning mandrels 116-1 and 116-3 and the remaining sidewall spacers 120'.
• FIG. 11 shows a side cross-sectional view 1100 of the FIG. 10 structure following removal of the patterning mandrels 116-1 and 116-3.
• the patterning mandrels 116-1 and 116-3 may be removed using processing similar to that described above with respect to removal of the patterning mandrel 116-2.
• FIG. 12 shows a side cross-sectional view 1200 of the FIG. 11 structure following etching of the remaining sidewall spacers 120' and the hard mask layer 112, such that the hard mask layer 112' remains only under the hard mask layer 114'.
• both the hard mask layer 112 and the sidewall spacers 120' may be formed of an oxide and may be removed using RIE or other suitable processing.
• FIG. 13 shows a side cross-sectional view 1300 of the FIG. 12 structure following etching of the hard mask layer 110, exposing the padding layer 108 as shown, such that the hard mask layer 110' remains only under the hard mask layer 112'.
• the hard mask layer 110 may be etched using processing similar to that described above with respect to etching of the hard mask layer 114. This step also removes the remaining hard mask layer 114', which, as described above, may be formed of the same material (e.g., a nitride) as the hard mask layer 110.
• FIG. 14 shows a side cross-sectional view 1400 of the FIG. 13 structure following open of the padding layer 108 and etching of the exposed portions of the nanosheet stack into a portion of the substrate 102.
• the padding layer 108 which may be formed of an oxide, may be opened using processing similar to that described above with respect to etching of the hard mask layer 112. This step also removes the remaining hard mask layer 112
• the sacrificial layers 104 and channel layers 106 of the nanosheet stack, along with the substrate 102, may be etched using RIE or another suitable process, such that portions 104', 106' and 102' of such layers remain as shown.
• the etching of the substrate 102 to form substrate 102' results in formation of fins 103-1 through 103-4 over the substrate 102' below the remaining portions of the sacrificial layers 104' and channel layers 106' of the nanosheet stack.
• the fins 103-1 and 103-4 may be used to form nFET nanosheet transistors, while the fins 103-2 and 103-3 are used to form pFET nanosheet transistors.
• the use of direct printing of the fins 103-1 and 103-4 and the use of SADP of the fins 103-2 and 103-3 requires only a single lithographic mask for primarily defining the placement of features, thereby reducing the OL penalty reduction or degradation that would otherwise impact gate and source/drain patterning (e.g., affecting parasitic capacitances of the resulting structures).
• such techniques permit the formation of devices with different nanosheet widths enabling further scaling of various devices (e.g., including SRAM structures).
• FIGS. 15-23 illustrate another process for using both direct print and SADP for forming nanosheet devices of different widths from the FIG. 1 structure. Whereas FIGS. 2-14 depict a "positive” tone process for forming the FIG. 14 structure, FIGS. 15-23 depicts a "negative” tone process for forming the FIG. 23 structure.
• FIG. 15 shows a side cross-sectional view 1500 of the FIG. 1 structure following patterning of lithographic mask 1518, which may be formed of similar materials, with similar processing and with similar sizing (in direction Y-Y') as that described above with respect to lithographic mask 118.
• the lithographic mask 118 provides positive tone for defining where the underlying patterning layer 116 would remain (e.g., patterning mandrels 116-1 , 116-2 and 116-3)
• the lithographic mask 1518 provides negative tone for defining where the underlying patterning layer 116 will remain following further processing described below.
• FIG. 16 shows a side cross-sectional view 1600 of the FIG. 15 structure following removal of exposed portions of the patterning layer 116 (e.g., using processing similar to that described above with respect to FIG. 3), resulting in patterning mandrels 1516 as shown.
• the lithographic mask 1518 is then removed, using processing similar to that described above with respect to removal of the lithographic mask 118.
• FIG. 17 shows a side cross-sectional view 1700 of the FIG. 16 structure following fill and etch-back of an oxide material 1517.
• the oxide material 1517 may be formed using spin-on coating, deposition fill or another suitable process to overfill the spaces formed by removal or etching of the exposed portions of the patterning layer 116 (e.g., to fill the spaces between the patterning mandrels 1516).
• the etch-back is used to planarize the oxide material 1517 to match a top surface of the patterning mandrels 1516.
• the oxide material 1517 may comprise silicon oxide (SiO x ), a metal oxide, etc.
• FIG. 18 shows a side cross-sectional view 1800 of the FIG. 17 structure following patterning of a block mask 1519 that exposes a portion of the oxide material 1517 in the middle of the structure (e.g., where pFET devices will be formed from the underlying nanosheet stack as described above).
• the block mask 1519 may be formed of materials similar to that of block masks 122 and 124, using similar processing and with similar sizing (in direction Y-Y').
• FIG. 19 shows a side cross-sectional view 1900 of the FIG. 18 structure following removal of the exposed portion of the oxide layer 1517 such that oxide layer 1517' remains.
• the block mask 1519 is then removed, using processing similar to that described above with respect to removal of block masks 122 and 124.
• FIG. 20 shows a side cross-sectional view 2000 of the FIG. 19 structure, following deposition and etch- back of a spacer material 1520.
• the spacer material 1520 may be formed of similar materials and with similar sizing as that described above with respect to spacer material 120.
• FIG. 21 shows a side cross-sectional view 2100 of the FIG. 20 structure following removal of the patterning mandrels 1516, using processing similar to that described above with respect to removal of patterning layer 116 and patterning mandrels 116-1, 116-2 and 116-3.
• FIG. 22 shows a side cross-sectional view 2200 of the FIG. 21 structure following open of the hard mask layers 114, 112 and 110 exposed by the remaining oxide layer 1517' and spacer material 1520.
• the exposed portions of the hard mask layers 114, 112 and 110 may be removed using processing similar to that described above with respect to etching these layers in conjunction with FIGS. 9-13.
• the padding layer 108 is also opened using processing similar to that described above.
• the FIG. 22 structure includes remaining portions 1508, 1510 and 1512 of the padding layer 108, hard mask layer 110 and hard mask layer 112, respectively.
• FIG. 23 shows a side cross-sectional view 2300 of the FIG. 22 structure following etching of exposed portions of the nanosheet stack into a portion of the substrate 102, such that portions 1506, 1504 and 1502 remain of the channel layers 106, sacrificial layers 104 and substrate 102, respectively.
• the sacrificial layers 104 and channel layers 106 of the nanosheet stack, along with the substrate 102, may be etched using processing similar to that described above with respect to FIG. 14. [0077] Similar to the FIG.
• the fins 1503-1 and 1503-4 may be used to form nFET nanosheet transistors, while the fins 1503-2 and 1503-3 are used to form pFET nanosheet transistors.
• the use of direct printing of the fins 1503-1 and 1503-4 and the use of SADP of the fins 1503-2 and 1503-3 requires only a single lithographic mask for primarily defining the placement of features, thereby reducing the OL penalty reduction or degradation that would otherwise impact gate and source/drain patterning (e.g., affecting parasitic capacitances of the resulting structures).
• such techniques permit the formation of devices with different nanosheet widths enabling further scaling of various devices (e.g., including SRAM structures).
• the structures shown in FIGS. 14 and 23 may be subject to various additional processing to form nanosheet FETs. This may include, for example, formation of shallow trench isolation (STI) regions surrounding the fins 103/1503, formation and pattering of dummy gate structures, epitaxial growth of source/drain regions, formation of inner spacers, removal of the sacrificial layers to form gate structures using a replacement metal gate (RMG) process, formation of contacts to the gate structures and source/drain regions, etc.
• STI shallow trench isolation
• RMG replacement metal gate
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet FETs.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using SADP.
• the second width is less than the first width.
• the lithographic mask in some embodiments, is patterned over the patterning layer such that the lithographic material covers the one or more first regions and the one or more second regions.
• the lithographic mask in other embodiments, is patterned over the patterning layer such that lithographic material exposes the one or more first regions and the one or more second regions.
• the hard mask stack may comprise a padding oxide layer and a NON hard mask stack over the padding oxide layer.
• the patterning layer may comprise a-Si.
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet FETs.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask covering (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using SADP.
• the second width is less than the first width.
• the method may further comprise etching portions of the patterning layer exposed by the lithographic mask to form a plurality of patterning mandrels, and removing the lithographic mask.
• the method may further comprise depositing a spacer material over the plurality of patterning mandrels and portions of a top surface of the hard mask stack exposed by etching of the portions of the patterning layer exposed by the lithographic mask, and etching-back the spacer material to remove the spacer material from top surfaces of the plurality of patterning mandrels and to remove the spacer material from portions of the top surface of the hard mask layer, leaving sidewalls spacers surrounding the plurality of patterning mandrels.
• the method may further comprise forming a first block mask covering at least a first subset of the plurality of patterning mandrels and the sidewall spacers surrounding the first subset of the plurality of patterning mandrels and exposing at least a second subset of the plurality of patterning mandrels and the sidewall spacers surrounding the second subset of the plurality of patterning mandrels.
• the first subset of the plurality of patterning mandrels provide for direct printing of the one or more fins of the first width and the second subset of the plurality of patterning mandrels provide SADP for setting the spacing between the two or more fins of the second width.
• the method may further comprise removing the second subset of the plurality of patterning mandrels leaving the sidewall spacers surrounding the second subset of the plurality of patterning mandrels, and removing the first block mask.
• the method may further comprise forming a second block mask covering the sidewall spacers surrounding the second subset of the plurality of patterning mandrels and exposing the first subset of the plurality of patterning mandrels and the sidewall spacers surrounding the first subset of the plurality of patterning mandrels.
• the method may further comprise removing the sidewall spacers surrounding the first subset of the plurality of patterning mandrels exposed by the second block mask, and removing the second block mask.
• a method of forming a semiconductor structure comprises forming a nanosheet stack comprising alternating layers of a sacrificial material and a channel material over a substrate, the layers of channel material providing nanosheet channels for one or more nanosheet FETs.
• the method also comprises forming a hard mask stack over the nanosheet stack, and forming a patterning layer over the hard mask stack.
• the method further comprises patterning a lithographic mask over the patterning layer, the lithographic mask exposing (i) one or more first regions of a top surface of the patterning layer for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions of the top surface of the patterning layer for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using SADP.
• the second width is less than the first width.
• the method may further comprise etching portions of the patterning layer exposed by the lithographic mask to form a plurality of patterning mandrels, and removing the lithographic mask.
• the method may further comprise depositing an oxide material over portions of a top surface of the hard mask stack exposed by etching of the portions of the patterning layer exposed by the lithographic mask, and etching-back the oxide material to form a plurality of oxide mandrels over the top surface of the hard mask stack between the plurality of patterning mandrels.
• the method may further comprise forming a block mask covering at least a first subset of the plurality of oxide mandrels and exposing at least a second subset of the plurality of oxide mandrels.
• the first subset of the plurality of oxide mandrels provide for direct printing of the one or more fins of the first width and the second subset of the plurality of oxide mandrels provide SADP for setting the spacing between the two or more fins of the second width.
• the method may further comprise removing the second subset of the plurality of oxide mandrels, and removing the block mask.
• the method may further comprise forming a spacer material over portions of the top surface of the hard mask stack exposed by the removal of the second subset of the plurality of oxide mandrels and over top surfaces of the first subset of the plurality of oxide mandrels and the plurality of patterning mandrels, and etching back the spacer material to form sidewall spacers adjacent sidewalls of the plurality of patterning mandrels exposed by removal of the second subset of the plurality of oxide mandrels.
• the method may further comprise removing the plurality of patterning mandrels, and etching the hard mask stack, the nanosheet stack and at least a portion of the substrate to form the one or more fins of the first width below the first subset of the plurality of oxide mandrels and to form the one or more fins of the second width below the sidewall spacers.
• a semiconductor structure comprises a substrate and a nanosheet stack disposed over the substrate, the nanosheet stack comprising alternating layers of a sacrificial material and a channel material, the layers of channel material providing nanosheet channels for one or more nanosheet FETs.
• the semiconductor structure also comprises a hard mask stack disposed over the nanosheet stack, and a patterning layer disposed over the hard mask stack.
• the semiconductor structure further comprise a lithographic mask disposed over the patterning layer, the lithographic mask defining (i) one or more first regions for direct printing of one or more fins of a first width in the nanosheet stack and the substrate and (ii) one or more second regions for setting the spacing between two or more fins of a second width in the nanosheet stack and the substrate using SADP.
• the second width is less than the first width.
• the lithographic mask in some embodiments, covers the one or more first regions and the one or more second regions.
• the lithographic mask in other embodiments, exposes the one or more first regions and the one or more second regions.
• the nanosheet stacks over the one or more fins of the first width may provide channels for nFETs and the nanosheet stacks disposed over the one or more fins of the second width may provide channels for pFETs.
• Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc.
• portable communications devices e.g., cell and smart phones
• solid-state media storage devices e.g., solid-state media storage devices
• functional circuitry e.g., solid-state media storage devices
• Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
• CMOSs complementary metal-oxide-semiconductors
• MOSFETs metal-oxide-semiconductor field-effect transistors
• FinFETs fin field-effect transistors
• the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
• the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
• the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
• the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
• the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

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