JP7515564B2 - ナノシートの直接印刷および自己整合ダブル・パターニング - Google Patents

ナノシートの直接印刷および自己整合ダブル・パターニング Download PDF

Info

Publication number
JP7515564B2
JP7515564B2 JP2022500956A JP2022500956A JP7515564B2 JP 7515564 B2 JP7515564 B2 JP 7515564B2 JP 2022500956 A JP2022500956 A JP 2022500956A JP 2022500956 A JP2022500956 A JP 2022500956A JP 7515564 B2 JP7515564 B2 JP 7515564B2
Authority
JP
Japan
Prior art keywords
patterning
mandrels
subset
mask
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022500956A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022541409A5 (https=
JP2022541409A (ja
Inventor
シーグ、スチュアート
デヘネ、ダニエル、ジェームス
ミラー、エリック
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JP2022541409A publication Critical patent/JP2022541409A/ja
Publication of JP2022541409A5 publication Critical patent/JP2022541409A5/ja
Application granted granted Critical
Publication of JP7515564B2 publication Critical patent/JP7515564B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/014—Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/853—Complementary IGFETs, e.g. CMOS comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Thin Film Transistor (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2022500956A 2019-07-17 2020-07-03 ナノシートの直接印刷および自己整合ダブル・パターニング Active JP7515564B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/514,235 US11257681B2 (en) 2019-07-17 2019-07-17 Using a same mask for direct print and self-aligned double patterning of nanosheets
US16/514,235 2019-07-17
PCT/IB2020/056290 WO2021009606A1 (en) 2019-07-17 2020-07-03 Direct print and self-aligned double patterning of nanosheets

Publications (3)

Publication Number Publication Date
JP2022541409A JP2022541409A (ja) 2022-09-26
JP2022541409A5 JP2022541409A5 (https=) 2022-12-13
JP7515564B2 true JP7515564B2 (ja) 2024-07-12

Family

ID=74210237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022500956A Active JP7515564B2 (ja) 2019-07-17 2020-07-03 ナノシートの直接印刷および自己整合ダブル・パターニング

Country Status (6)

Country Link
US (2) US11257681B2 (https=)
JP (1) JP7515564B2 (https=)
CN (1) CN114175211B (https=)
DE (1) DE112020002857T5 (https=)
GB (1) GB2600338B (https=)
WO (1) WO2021009606A1 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11462614B2 (en) * 2019-08-30 2022-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing
US11152358B2 (en) 2019-10-01 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Vertical structure for semiconductor device
US11824116B2 (en) 2019-12-18 2023-11-21 Intel Corporation Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact
US11881402B2 (en) * 2020-09-30 2024-01-23 Applied Materials, Inc. Self aligned multiple patterning
US12176212B2 (en) * 2021-08-30 2024-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Mandrel structures and methods of fabricating the same in semiconductor devices
US12255099B2 (en) * 2021-10-28 2025-03-18 Samsung Electronics Co., Ltd. Methods of forming fin-on-nanosheet transistor stacks
CN117438376B (zh) * 2023-12-20 2024-03-05 华中科技大学 一种基于二维材料的互补性场效应晶体管及制备方法
CN118119182B (zh) * 2024-03-06 2025-09-05 北京超弦存储器研究院 一种垂直超薄沟道dram单元器件的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013536577A (ja) 2010-08-02 2013-09-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 集積フィンベースの電界効果トランジスタ（ＦｉｎＦＥＴ）およびその製造方法
US20160020109A1 (en) 2014-07-16 2016-01-21 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US20180082906A1 (en) 2016-09-20 2018-03-22 Qualcomm Incorporated NOVEL SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm
US20190172755A1 (en) 2017-12-04 2019-06-06 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (cfet) device

Family Cites Families (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7893492B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
US8216902B2 (en) 2009-08-06 2012-07-10 International Business Machines Corporation Nanomesh SRAM cell
US8110466B2 (en) * 2009-10-27 2012-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cross OD FinFET patterning
KR101871748B1 (ko) * 2011-12-06 2018-06-28 삼성전자주식회사 반도체 소자의 패턴 형성 방법
US9048260B2 (en) * 2011-12-31 2015-06-02 Intel Corporation Method of forming a semiconductor device with tall fins and using hard mask etch stops
US8735296B2 (en) * 2012-07-18 2014-05-27 International Business Machines Corporation Method of simultaneously forming multiple structures having different critical dimensions using sidewall transfer
US9318330B2 (en) * 2012-12-27 2016-04-19 Renesas Electronics Corporation Patterning process method for semiconductor devices
US9166023B2 (en) 2013-08-09 2015-10-20 Stmicroelectronics, Inc. Bulk finFET semiconductor-on-nothing integration
US9406522B2 (en) * 2014-07-24 2016-08-02 Applied Materials, Inc. Single platform, multiple cycle spacer deposition and etch
US9202920B1 (en) 2014-07-31 2015-12-01 Stmicroelectronics, Inc. Methods for forming vertical and sharp junctions in finFET structures
US9472506B2 (en) 2015-02-25 2016-10-18 International Business Machines Corporation Registration mark formation during sidewall image transfer process
KR102170701B1 (ko) * 2015-04-15 2020-10-27 삼성전자주식회사 반도체 장치 제조 방법
US9287135B1 (en) 2015-05-26 2016-03-15 International Business Machines Corporation Sidewall image transfer process for fin patterning
US9722052B2 (en) * 2015-10-27 2017-08-01 International Business Machines Corporation Fin cut without residual fin defects
US9871099B2 (en) 2015-11-09 2018-01-16 International Business Machines Corporation Nanosheet isolation for bulk CMOS non-planar devices
US9722022B2 (en) 2015-12-28 2017-08-01 International Business Machines Corporation Sidewall image transfer nanosheet
US9490335B1 (en) 2015-12-30 2016-11-08 International Business Machines Corporation Extra gate device for nanosheet
US9589958B1 (en) * 2016-01-22 2017-03-07 International Business Machines Corporation Pitch scalable active area patterning structure and process for multi-channel finFET technologies
US9679771B1 (en) * 2016-03-07 2017-06-13 Peking University Shenzhen Graduate School Fabrication and design methods using selective etching and dual-material self-aligned multiple patterning processes to reduce the cut-hole patterning yield loss
US9799514B1 (en) * 2016-04-07 2017-10-24 Globalfoundries Inc. Protecting, oxidizing, and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines
US9859174B1 (en) * 2016-06-24 2018-01-02 International Business Machines Corporation Sidewall image transfer structures
US10014389B2 (en) * 2016-07-26 2018-07-03 Globalfoundries Inc. Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures
US10032877B2 (en) * 2016-08-02 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET and method of forming same
US10002762B2 (en) * 2016-09-09 2018-06-19 International Business Machines Corporation Multi-angled deposition and masking for custom spacer trim and selected spacer removal
US9786545B1 (en) * 2016-09-21 2017-10-10 Globalfoundries Inc. Method of forming ANA regions in an integrated circuit
US10069015B2 (en) 2016-09-26 2018-09-04 International Business Machines Corporation Width adjustment of stacked nanowires
US9837403B1 (en) * 2016-09-27 2017-12-05 International Business Machines Corporation Asymmetrical vertical transistor
US10032632B2 (en) * 2016-10-04 2018-07-24 International Business Machines Corporation Selective gas etching for self-aligned pattern transfer
US10128239B2 (en) * 2016-10-17 2018-11-13 International Business Machines Corporation Preserving channel strain in fin cuts
US9923055B1 (en) * 2016-10-31 2018-03-20 International Business Machines Corporation Inner spacer for nanosheet transistors
US10439059B2 (en) * 2016-12-20 2019-10-08 Massachusetts Institute Of Technology High-linearity transistors
US10043746B1 (en) 2017-02-06 2018-08-07 International Business Machines Corporation Fabrication of vertical fuses from vertical fins
US10002939B1 (en) 2017-02-16 2018-06-19 International Business Machines Corporation Nanosheet transistors having thin and thick gate dielectric material
US10707208B2 (en) * 2017-02-27 2020-07-07 International Business Machines Corporation Fabrication of fin field effect transistors utilizing different fin channel materials while maintaining consistent fin widths
US10043900B1 (en) * 2017-03-20 2018-08-07 International Business Machines Corporation Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths
US9847391B1 (en) 2017-04-05 2017-12-19 Globalfoundries Inc. Stacked nanosheet field-effect transistor with diode isolation
US10340141B2 (en) * 2017-04-28 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning method for semiconductor device and structures resulting therefrom
US10692769B2 (en) * 2017-08-29 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd Fin critical dimension loading optimization
US10755969B2 (en) * 2018-01-01 2020-08-25 International Business Machines Corporation Multi-patterning techniques for fabricating an array of metal lines with different widths
TWI651837B (zh) * 2018-02-21 2019-02-21 Powerchip Technology Corporation 積體電路結構及其製造方法
US10566445B2 (en) * 2018-04-03 2020-02-18 International Business Machines Corporation Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates
US11201152B2 (en) * 2018-04-20 2021-12-14 Globalfoundries Inc. Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor
US10304744B1 (en) * 2018-05-15 2019-05-28 International Business Machines Corporation Inverse tone direct print EUV lithography enabled by selective material deposition
US10361129B1 (en) * 2018-05-18 2019-07-23 International Business Machines Corporation Self-aligned double patterning formed fincut
US10672668B2 (en) * 2018-05-30 2020-06-02 International Business Machines Corporation Dual width finned semiconductor structure
US20200066520A1 (en) * 2018-08-22 2020-02-27 International Business Machines Corporation Alternating hard mask for tight-pitch fin formation
US10957798B2 (en) * 2019-02-06 2021-03-23 International Business Machines Corporation Nanosheet transistors with transverse strained channel regions
US10903369B2 (en) * 2019-02-27 2021-01-26 International Business Machines Corporation Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
US10916630B2 (en) * 2019-04-29 2021-02-09 International Business Machines Corporation Nanosheet devices with improved electrostatic integrity
US11527446B2 (en) * 2019-05-13 2022-12-13 International Business Machines Corporation Transistor having strain-inducing anchors and a strain-enhancing suspended channel
US10879379B2 (en) * 2019-05-30 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-gate device and related methods
US10978573B2 (en) * 2019-07-08 2021-04-13 International Business Machines Corporation Spacer-confined epitaxial growth
US11342231B2 (en) * 2019-09-17 2022-05-24 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit device with low threshold voltage
US11094781B2 (en) * 2019-11-01 2021-08-17 International Business Machines Corporation Nanosheet structures having vertically oriented and horizontally stacked nanosheets
US11152464B1 (en) * 2020-03-27 2021-10-19 International Business Machines Corporation Self-aligned isolation for nanosheet transistor
US11251287B2 (en) * 2020-04-14 2022-02-15 International Business Machines Corporation Self-aligned uniform bottom spacers for VTFETS
US11164960B1 (en) * 2020-04-28 2021-11-02 International Business Machines Corporation Transistor having in-situ doped nanosheets with gradient doped channel regions
US12324236B2 (en) * 2021-11-09 2025-06-03 International Business Machines Corporation Bottom contact for stacked GAA FET
US12444653B2 (en) * 2021-12-08 2025-10-14 International Business Machines Corporation Buried power rail at tight cell-to-cell space
US20230282722A1 (en) * 2022-03-04 2023-09-07 International Business Machines Corporation Co-integration of source-drain trench metal cut and gate-contact-over active device for advanced transistor architectures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013536577A (ja) 2010-08-02 2013-09-19 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 集積フィンベースの電界効果トランジスタ（ＦｉｎＦＥＴ）およびその製造方法
US20160020109A1 (en) 2014-07-16 2016-01-21 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US20180082906A1 (en) 2016-09-20 2018-03-22 Qualcomm Incorporated NOVEL SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20nm
JP2019530229A (ja) 2016-09-20 2019-10-17 クアルコム，インコーポレイテッド ２０ｎｍ未満のフィンピッチのための新規の自己整合４重パターニングプロセス
US20190172755A1 (en) 2017-12-04 2019-06-06 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (cfet) device
JP2021513749A (ja) 2017-12-04 2021-05-27 東京エレクトロン株式会社 相補型電界効果トランジスタ（ｃｆｅｔ）デバイスにおいて複数のチャネル材料を組み込む方法

Also Published As

Publication number Publication date
US20210020446A1 (en) 2021-01-21
WO2021009606A1 (en) 2021-01-21
GB2600338B (en) 2023-08-09
US12080559B2 (en) 2024-09-03
JP2022541409A (ja) 2022-09-26
US20220102153A1 (en) 2022-03-31
DE112020002857T5 (de) 2022-02-24
GB2600338A (en) 2022-04-27
CN114175211B (zh) 2025-05-20
GB202201027D0 (en) 2022-03-16
US11257681B2 (en) 2022-02-22
CN114175211A (zh) 2022-03-11

Similar Documents

Publication Publication Date Title
JP7515564B2 (ja) ナノシートの直接印刷および自己整合ダブル・パターニング
CN114097093B (zh) 具有不对称切割布局的自对准栅极隔离
US10177150B2 (en) Semiconductor device and method of fabricating the same
US10381262B2 (en) Fabrication of vertical transport fin field effect transistors with a self-aligned separator and an isolation region with an air gap
TWI782150B (zh) 場效應電晶體、系統晶片以及製造其的方法
TWI565077B (zh) 具有頸部半導體本體的半導體裝置及形成具有變化寬度的半導體本體的方法
US20110248326A1 (en) Structure and method to integrate embedded dram with finfet
US9472572B2 (en) Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins
US12302604B2 (en) Multi-gate device and related methods
US12356660B2 (en) Multi-gate device and related methods
TWI923032B (zh) 用於具有中間介電隔離層的互補式場效電晶體的改善的材料及方法
CN118800728A (zh) 半导体装置及其制造方法
CN120982230A (zh) 用于具有中间介电隔离层的互补式场效晶体管的改善的材料及方法
TW202517035A (zh) 用於具有中間介電隔離層的互補式場效電晶體的改善的材料及方法

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20220518

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20221122

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20221223

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20231214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20231226

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240326

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240618

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240702

R150 Certificate of patent or registration of utility model

Ref document number: 7515564

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150